MB15E05SRPFT-G-BND-ERE1;中文规格书,Datasheet资料

DS04-21377-1EFUJITSU SEMICONDUCTORDATA SHEETASSPSingle Serial InputPLL Frequency Synthesizer On-chip 2.0 GHz PrescalerMB15E05SRs DESCRIPTIONThe Fujitsu MB15E05SR is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2.0 GHz prescaler. The 2.0 GHz prescaler has a dual modulus division ratio of 64/65 or 128/129 enabling pulse swallowing operation.The supply voltage range is between 2.7 V and 5.0 V . A refined charge pump supplies well-balanced output currents of 1.0 mA and 4.0 mA. The charge pump current is selectable by serial data.The phase noise of MB15E05SR was drastically improved comparing wuth the former single PLL, MB15E05SL.The data format of serial data and the pin assignments except for φP , φR and OSCout pins are same as the former one, so it is easy to replace the former one.MB15E05SR is ideally suited for the base station of GSM (Global System for Mobile Communications) and PCS.s FEATURES•High frequency operation: 2.0 GHz Max•Low power supply voltage: V CC = 2.7 V to 5.0 V•Ultra Low power supply current:I CC = 7.0 mA T yp (V CC = Vp = 3.75 V , T a = +25°C, in locking state)•Direct power saving function:Power supply current in power saving modeT yp 0.1 µA (V CC = Vp = 3.75 V , T a = +25°C)(Continued)s PACKAGESMB15E05SR2(Continued)•Dual modulus prescaler: 64/65 or 128/129•Serial input 14-bit programmable reference divider: R = 3 to 16,383•Serial input programmable divider consisting of:- Binary 7-bit swallow counter: 0 to 127- Binary 11-bit programmable counter: 3 to 2,047•Software selectable charge pump current•On-chip phase control for phase comparator•Built-in digital locking detector circuit to detect PLL locking and unlocking.•Operating temperature: T a = –40 °C to +85 °Cs PIN ASSIGNMENTSMB15E05SR3s PIN DESCRIPTIONSPin no.Pin name I/O DescriptionsTSSOP BCC 116OSC IN I Programmable reference divider input. Connection to a TCXO.21N.C.–No connection.32V P –Power supply voltage input for the charge pump.43V CC –Power supply voltage input.54D O O Charge pump output.Phase of the charge pump can be selected via programming of the FC bit.65GND –Ground.76Xfin I Prescaler complementary input, which should be grounded via a capacitor.87fin I Prescaler input.Connection to an external VCO should be done via AC coupling.98Clock I Clock input for the 19-bit shift register.Data is shifted into the shift register on the rising edge of the clock.(Open is prohibited.)109Data I Serial data input using binary code.The last bit of the data is a control bit. (Open is prohibited.)1110LEILoad enable signal input. (Open is prohibited.)When LE is set high, the data in the shift register is transferred to a latch according to the control bit in the serial data.1211PS I Power saving mode control. This pin must be set at “L” at Power-ON.(Open is prohibited.)PS = “H”; Normal modePS = “L”; Power saving mode 1312N.C.–No connection.1413LD/fout O Lock detect signal output (LD)/phase comparator monitoring output (fout).The output signal is selected via programming of the LDS bit.LDS = “H”; outputs fout (fr/fp monitoring output)LDS = “L”; outputs LD (“H” at locking, “L” at unlocking.)1514N.C.–No connection.1615N.C.–No connection.MB15E05SR4s BLOCK DIAGRAMMB15E05SR5s ABSOLUTE MAXIMUM RATINGSWARNING:Semiconductor devices can be permanently damaged by application of stress (voltage, current,temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.s RECOMMENDED OPERATING CONDITIONSWARNING:The recommended operating conditions are required in order to ensure the normal operation of thesemiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges.Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure.No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.ParameterSymbol ConditionRating Unit RemarkMin Max Power supply voltage V CC ––0.5 5.5V V P –V CC 6.0V Input voltage V I ––0.5V CC +0.5V Output voltage V O Except DoGND V CC V V O Do GND V P V Storage temperatureTstg––55+125°CParameterSymbol ValueUnit RemarkMin Typ Max Power supply voltage V CC 2.7 3.75 5.0V V P V CC – 5.5V Input voltageV I GND –V CC V Operating temperatureTa–40–+85°CMB15E05SR6s ELECTRICAL CHARACTERISTICS(V CC = 2.7 V to 5.0 V, T a = –40 °C to +85 °C)*1: Conditions; fosc = 13 MHz, Vosc = 1.2 V PP, T a = +25°C, in locking state.*2: V CC = V P = 3.75 V, fosc = 13 MHz, Vosc = 1.2 V PP, T a = +25°C, in power saving mode*3: AC coupling. 1000 pF capacitor is connected under the condition of min. operating frequency.*4: The symbol “–” (minus) means direction of current flow.*5: V CC = V P = 3.75 V, T a = +25°C (||I3| – |I4||) / [(|I3| + |I4|) /2] × 100(%)(Continued) Parameter Symbol ConditionValueUnitMin Typ MaxPower supply current*1I CC fin = 2000 MHz, V CC = V P = 3.75 V–7.0–mA Power saving current I PS PS = “L”–0.1*220µA Operating frequencyfin f IN–300–2000MHzOSC IN fosc–3–40MHz Input sensitivityfin*3Pfin50 Ω system(Refer to the measurementcircuit.)–15–+2dBm OSC IN*3V OSC–0.5–V CC Vp-p“H” level input voltage Data,Clock,LE, PSV IH–V CC × 0.7––V “L” level input voltage V IL–––V CC × 0.3“H” level input current Data,Clock,LE, PSI IH*4––1.0–+1.0µA “L” level input current I IL*4––1.0–+1.0“H” level input currentOSC INI IH–0–+100µA “L” level input current I IL*4––100–0“H” level output voltageLD/foutV OH V CC = V P = 3.75 V, I OH = –1 mA V CC – 0.4––V “L” level output voltage V OL V CC = V P = 3.75 V, I OL = 1 mA––0.4“H” level output voltageDoV DOH V CC = V P = 3.75 V, I DOH = –0.5 mA V P – 0.4––V “L” level output voltage V DOL V CC = V P = 3.75 V, I DOL = 0.5 mA––0.4High impedance cutoffcurrent Do I OFFV CC = V P = 3.75 V,V OFF = 0.5 V to V P – 0.5 V–– 2.5nA“H” level output currentLD/foutI OH V CC = V P = 3.75 V–––1.0mA “L” level output current I OL V CC = V P = 3.75 V 1.0––“H” level output currentDoI DOH*4V CC = 3.75 V,V P = 3.75 V,V DO = V P/2,Ta = +25°CCS bit = “1”––4.0–mACS bit = “0”––1.0–“L” level output current I DOLCS bit = “1”– 4.0–CS bit = “0”– 1.0–Charge pump currentrateI DOL/I DOH I DOMT*5V DO = V P/2–5–%vs V DO I DOVD*60.5 V ≤ V DO≤ V P – 0.7 V–10–%vs Ta I DOTA*7– 40°C ≤ Ta ≤ +85°C, V DO = V P/2–3–%MB15E05SR(Continued)*6: V CC = V P = 3.75 V, T a = +25°C [(||I2| – |I1||) /2] / [(|I1| + |I2|) /2] × 100(%) (Applied to each I DOL, I DOH)*7: V CC = V P = 3.75 V, V DO = V P/2 (||I DO(+85°C)| – |I DO(–40°C)| |/2) / (|I DO(+85°C)| + |I DO(–40°C)| /2) × 100(%) (Applied to each I DOL, I DOH)7MB15E05SR8s FUNCTIONAL DESCRIPTION1.Pulse Swallow FunctionThe divide ratio can be calculated using the following equation:f VCO = [(P× N) + A] × f OSC÷ R (A < N)f VCO:Output frequency of external voltage controlled oscillator (VCO)N:Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)A:Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127)f OSC:Output frequency of the reference frequency oscillatorR:Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)P:Preset divide ratio of modulus prescaler (64 or 128)2.Serial Data InputSerial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference divider and the programmable divider separately.Binary serial data is entered through the Data pin.One bit of data is shifted into the shift register on the rising edge of the Clock. When the LE signal pin is taken high, stored data is latched according to the control bit data as follows:Table 1. Control Bit(1) Shift Register ConfigurationControl bit (CNT)Destination of serial dataH For the programmable reference dividerL For the programmable divider12345678910111213141516171819 CNT R1R2R3R4R5R6R7R8R9R10R11R12R13R14SW FC LDS CS Programmable Reference CounterMSBData FlowCNT: Control bit[T able 1]R1 to R14: Divide ratio setting bit for the programmable reference counter (3 to 16,383)[T able 2]SW: Divide ratio setting bit for the prescaler (64/65 or 128/129)[T able 5]FC: Phase control bit for the phase comparator[T able 8]LDS: LD/f OUT signal select bit[T able 7]CS: Charge pump current select bit[T able 6]Note: Start data input with MSB first.LSBMB15E05SR9Table 2. Binary 14-bit Programmable Reference Counter Data SettingNote : Divide ratio less than 3 is prohibited.Table 3. Binary 11-bit Programmable Counter Data SettingNote : Divide ratio less than 3 is prohibited.Divide ratio(R)R14R13R12R11R10R9R8R7R6R5R4R3R2R1300000000000011400000000000100⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅1638311111111111111Divide ratio(N)N11N10N9N8N7N6N5N4N3N2N1300000000011400000000100⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅20471111111111112345678910111213141516171819CNTA1A2A3A4A5A6A7N1N2N3N4N5N6N7N8N9N10N11Programmable Counter LSB MSBData Flow CNT : Control bit[T able 1]N1 to N11: Divide ratio setting bits for the programmable counter (3 to 2,047)[T able 3]A1 to A7: Divide ratio setting bits for the swallow counter (0 to 127)[T able 4]Note: Data input with MSB first.MB15E05SR10Table 4. Binary 7-bit Swallow Counter Data SettingTable 5. Prescaler Data SettingTable 6. Charge Pump Current SettingTable 7. LD/fout Output Select Data Setting(2) Relation between the FC Input and Phase CharacteristicsThe FC bit changes the phase characteristics of the phase comparator. The internal charge pump output level (D O) is reversed according to the FC bit. Also, the monitor pin (fout) output is controlled by the FC bit. The relationship between the FC bit and D O is shown below.Table 8. FC Bit Data Setting (LDS = “1”)*: High impedanceDivide ratio(A)A7A6A5A4A3A2A10000000010000001⋅⋅⋅⋅⋅⋅⋅⋅1271111111SW Prescaler divide ratio164/650128/129CS Current value1±4.0 mA0±1.0 mALDS LD/fout output signal1fout signal0LD signalFC = 1FC = 0D O LD/fout D O LD/foutfr > f P Hfout = frLfout = fpfr < f P L Hfr = f P Z*Z*分销商库存信息: FUJITSUMB15E05SRPFT-G-BND-ERE1。