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zl30109中文资料_数据手册_IC数据表

1Features•Supports Telcordia GR-1244-CORE Stratum 4 and Stratum 4E•Supports ITU-T G.823 and G.824 for 2048kbit/s and 1544kbit/s interfaces•Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces •Simple hardware control interface•Accepts two input references and synchronizes to any combination of 2kHz, 8kHz, 1.544MHz,2.048MHz, 8.192MHz, 16.384MHz or 19.44MHz inputs•Provides a range of clock outputs: 1.544MHz, 2.048MHz, 16.384MHz, 19.44MHz and either 4.096MHz and 8.192MHz or 32.768MHz and 65.536MHz•Hitless reference switching between anycombination of valid input reference frequencies •Provides 5 styles of 8kHz framing pulses and a 2kHz multi-frame pulse•Holdover frequency accuracy of 1.5 x 10-7•Lock, Holdover and selectable Out of Range indication•Selectable loop filter bandwidth of 1.8Hz or 922Hz•Less than 24 ps rms intrinsic jitter on the19.44MHz output clock, compliant with OC-3 and STM-1 jitter specifications•Less than 0.6ns pp intrinsic jitter on all output clocks•External master clock source: clock oscillator or crystalApplications•Synchronization and timing control for DSLAM, Gateway and PBX systems that require Stratum 4/4E timing•Line Card synchronization for SDH/PDH applications•Clock and frame pulse source for ST-BUS, GCI and other time division multiplex (TDM) busesNovember 2005ZL30109DS1/E1 System Synchronizer with19.44MHz OutputData SheetFigure 1 - Functional Block DiagramReference MonitorMode ControlVirtual ReferenceIEEE 1149.1aFeedbackTIE Corrector EnableState MachineFrequency Select MUXTIE Corrector CircuitMODE_SEL1:0TCK REF1RSTREF_SELTIE_CLROSCo OSCi Master ClockTDOREF0TDI TMS TRSTHOLDOVER BW_SEL HMS LOCK REF_FAIL0REF_FAIL1DPLLOUT_SELMUXOOR_SEL C2oE1SynthesizerDS1SynthesizerSONET/SDH SynthesizerC4/C65o C8/C32o C16o F4/F65o F8/F32o C1.5o C19o F2koF16o Ordering InformationZL30109QDG 64 Pin TQFP Trays, Bake & Drypack ZL30109QDG164 pin TQFP*Trays, Bake & Drypack*Pb Free Matte Tin -40°C to +85°CZL30109Data Sheet DescriptionThe ZL30109 DS1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for multi-trunk DS1 and E1 transmission equipment. The 19.44MHz output makes the ZL30109 also suitable for SDH line card applications.The ZL30109 generates a 19.44MHz clock and ST-BUS and TDM bus clocks and framing signals that are phase locked to one of two input references. It helps ensure system reliability by monitoring its references for accuracy and stability and by maintaining stable output clocks during reference switching operations and during short periods when a reference is unavailable.The ZL30109 is intended to be the central timing and synchronization resource for network equipment that complies with Telcordia, ETSI, ITU-T and ANSI network specifications.ZL30109Data SheetTable of Contents1.0 Change Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52.0 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62.1 Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62.2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103.1 Reference Select Multiplexer (MUX). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103.2 Reference Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103.3 Time Interval Error (TIE) Corrector Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133.4 Digital Phase Lock Loop (DPLL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163.5 Frequency Synthesizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173.6 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173.7 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174.0 Control and Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174.1 Out of Range Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174.2 Loop Filter Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184.3 Output Clock and Frame Pulse Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184.4 Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184.4.1 Freerun Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184.4.2 Holdover Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194.4.3 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194.5 Reference Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205.0 Measures of Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215.1 Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215.2 Jitter Generation (Intrinsic Jitter). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215.3 Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215.4 Jitter Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215.5 Frequency Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225.6 Holdover Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225.7 Pull-in Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225.8 Lock Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225.9 Phase Slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225.10 Time Interval Error (TIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225.11 Maximum Time Interval Error (MTIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225.12 Phase Continuity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225.13 Lock Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226.0 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236.1 Power Supply Decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236.2 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236.2.1 Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236.2.2 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246.3 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246.4 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257.0 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267.1 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267.2 Performance Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33ZL30109Data SheetList of FiguresFigure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Pin Connections (64 pin TQFP, please see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3 - Reference Monitor Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 4 - Behaviour of the Dis/Re-qualify Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5 - DS1 Mode Out-of-Range Limits (OOR_SEL=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6 - E1 Mode Out-of-Range Limits (OOR_SEL=1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 7 - Timing Diagram of Hitless Reference Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 8 - Timing Diagram of Hitless Mode Switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 9 - DPLL Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 10 - Mode Switching in Normal Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 11 - Reference Switching in Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 12 - Clock Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 13 - Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 14 - Power-Up Reset Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 15 - Timing Parameter Measurement Voltage Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 16 - Input to Output Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 17 - Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 18 - SONET/SDH Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32ZL30109Data Sheet1.0 Change SummaryChanges from July 2005 Issue to November 2005 Issue. Page, section, figure and table numbers refer to this current issue.Changes from November 2004 Issue to July 2005 Issue. Page, section, figure and table numbers refer to this current issue.Page Item Change1Features Added description for hitless reference switching.23Section 6.1Removed power supply decoupling circuit and includedreference to synchronizer power supply decoupling application note.Page Item Change8RST pin Specified clock and frame pulse outputs forced to high impedance.10REF0 pinSpecified seven possible reference input frequencies.27Table “DC Electrical Characteristics*“Corrected Schmitt trigger levels.33Table “Performance Characteristics* - Functional“Gave more detail on Lock Time conditions.ZL30109Data Sheet2.0 Physical Description2.1 Pin ConnectionsFigure 2 - Pin Connections (64 pin TQFP, please see Note 1)Note 1: The ZL30109 uses the TQFP shown in the package outline designated with the suffix QD, the ZL30109does not use the e-Pad TQFP .ZL3010934363840424446486462605856525054161412108642OSCo NC GND OUT_SEL C1.5o MODE_SEL1V DD AV DD IC NC RSTNC AGNDF4/F65o V DD REF1NC ICC 8/C 32o F 2k o C 2o A G N DA V D DC 19o F 8/F 32o C 4/C 65o REF_SEL1820222426303228C 16o F16o TIE_CLR OOR_SELICOSCi A V D DA V D DA V D DA V C O R EA G N D A G N D A G N D NC NC IC ICMODE_SEL0NC BW_SELREF0V C O R EL O C K H M ST R S T G N DT D O T M S H O L D O V E R I C T C K T D I V C O R EA V C O R EG N D R E F _F A I L 0R E F _F A I L 1ZL30109Data Sheet2.2 Pin DescriptionPin DescriptionPin # Name Description1GND Ground. 0 V.2V CORE Positive Supply Voltage. +1.8 V DC nominal.3LOCK Lock Indicator (Output). This output goes to a logic high when the PLL is frequencylocked to the selected input reference.4HOLDOVER Holdover (Output). This output goes to a logic high whenever the PLL goes intoholdover mode.5REF_FAIL0Reference 0 Failure Indicator (Output). A logic high at this pin indicates that the REF0 reference frequency has exceeded the out-of-range limit set by the OOR_SEL pin or thatit is exhibiting abrupt phase or frequency changes.6IC Internal bonding Connection. Leave unconnected.7REF_FAIL1Reference 1 Failure Indicator (Output). A logic high at this pin indicates that the REF1 reference frequency has exceeded the out-of-range limit set by the OOR_SEL pin or thatit is exhibiting abrupt phase or frequency changes.8TDO Test Serial Data Out (Output). JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG scan is not enabled.9TMS Test Mode Select (Input). JTAG signal that controls the state transitions of the TAPcontroller. This pin is internally pulled up to V DD. If this pin is not used then it should beleft unconnected.10TRST Test Reset (Input). Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin should be pulsed low on power-up to ensure thatthe device is in the normal functional state. This pin is internally pulled up to V DD. Ifthis pin is not used then it should be connected to GND.11TCK Test Clock (Input): Provides the clock to the JTAG test logic. If this pin is not used then it should be pulled down to GND.12V CORE Positive Supply Voltage. +1.8 V DC nominal.13GND Ground. 0 V.14AV CORE Positive Analog Supply Voltage. +1.8 V DC nominal.15TDI Test Serial Data In (Input). JTAG serial test instructions and data are shifted in on this pin. This pin is internally pulled up to V DD. If this pin is not used then it should be leftunconnected.16HMS Hitless Mode Switching (Input). The HMS circuit controls phase accumulation during the transition from Holdover or Freerun mode to Normal mode on the same reference. Alogic low at this pin will cause the ZL30109 to maintain the delay stored in the TIEcorrector circuit when it transitions from Holdover or Freerun mode to Normal mode. Alogic high on this pin will cause the ZL30109 to measure a new delay for its TIE correctorcircuit thereby minimizing the output phase movement when it transitions from Holdoveror Freerun mode to Normal mode.17MODE_SEL0Mode Select 0 (Input). This input combined with MODE_SEL1 determines the mode(Normal, Holdover or Freerun) of operation, see Table4 on page18.18MODE_SEL1Mode Select 1 (Input). See MODE_SEL0 pin description.ZL30109Data Sheet Pin Description (continued)Pin # Name Description19RST Reset (Input). A logic low at this input resets the device. On power up, the RST pin must be held low for a minimum of 300ns after the power supply pins have reachedthe minimum supply voltage. When the RST pin goes high, the device will transitioninto a Reset state for 3ms. In the Reset state all clock and frame pulse outputs will beforced into high impedance.20OSCo Oscillator Master Clock (Output). For crystal operation, a 20MHz crystal is connected from this pin to OSCi. This output is not suitable for driving other devices. For clockoscillator operation, this pin must be left unconnected.21OSCi Oscillator Master Clock (Input). For crystal operation, a 20MHz crystal is connected from this pin to OSCo. For clock oscillator operation, this pin must be connected to aclock source.22IC Internal Connection. Leave unconnected.23GND Ground. 0V.24NC No internal bonding Connection. Leave unconnected.25V DD Positive Supply Voltage. +3.3 V DC nominal.26OUT_SEL Output Selection (Input).This input selects the signals on the combined output clock and frame pulse pins, see Table3 on page18.27IC Internal Connection. Connect this pin to ground.28IC Internal Connection. Connect this pin to ground.29AV DD Positive Analog Supply Voltage. +3.3 V DC nominal.30NC No internal bonding Connection. Leave unconnected.31NC No internal bonding Connection. Leave unconnected.32C1.5o Clock 1.544MHz (Output). This output is used in DS1 applications.This clock output pad includes a Schmitt input which serves as a PLL feedback path;proper transmission-line termination should be applied to maintain reflections belowSchmitt trigger levels.33AGND Analog Ground. 0 V34AGND Analog Ground. 0 V35AV CORE Positive Analog Supply Voltage. +1.8 V DC nominal.36AV DD Positive Analog Supply Voltage. +3.3 V DC nominal.37AV DD Positive Analog Supply Voltage. +3.3 V DC nominal.38F2ko Multi Frame Pulse (Output). This is a 2kHz 51ns active high framing pulse, whichmarks the beginning of a multi frame.This clock output pad includes a Schmitt input which serves as a PLL feedback path;proper transmission-line termination should be applied to maintain reflections belowSchmitt trigger levels.ZL30109Data Sheet Pin Description (continued)Pin # Name Description39C19o Clock 19.44MHz (Output). This output is used in SONET/SDH applications.This clock output pad includes a Schmitt input which serves as a PLL feedback path;proper transmission-line termination should be applied to maintain reflections belowSchmitt trigger levels.40AGND Analog Ground.0V41AGND Analog Ground.0V42C4/C65o Clock 4.096MHz or 65.536MHz (Output). This output is used for ST-BUS operation at2.048Mbps, 4.096Mbps or 65.536MHz (ST-BUS 65.536Mbps). The output frequency isselected via the OUT_SEL pin.43C8/C32o Clock 8.192MHz or 32.768MHz (Output). This output is used for ST-BUS and GCIoperation at 8.192Mbps or for operation with a 32.768MHz clock. The output frequencyis selected via the OUT_SEL pin.44AV DD Positive Analog Supply Voltage. +3.3 V DC nominal.45AV DD Positive Analog Supply Voltage. +3.3 V DC nominal.46C2o Clock 2.048MHz (Output). This output is used for standard E1 interface timing and for ST-BUS operation at 2.048Mbps.This clock output pad includes a Schmitt input which serves as a PLL feedback path;proper transmission-line termination should be applied to maintain reflections belowSchmitt trigger levels.47C16o Clock 16.384MHz (Output). This output is used for ST-BUS operation with a16.384MHz clock.This clock output pad includes a Schmitt input which serves as a PLL feedback path;proper transmission-line termination should be applied to maintain reflections belowSchmitt trigger levels.48F8/F32o Frame Pulse (Output). This is an 8kHz 122ns active high framing pulse (OUT_SEL=0) or it is an 8kHz 31ns active high framing pulse (OUT_SEL=1), which marks thebeginning of a frame.This clock output pad includes a Schmitt input which serves as a PLL feedback path;proper transmission-line termination should be applied to maintain reflections belowSchmitt trigger levels.49F4/F65o Frame Pulse ST-BUS 2.048Mbps or ST-BUS at 65.536MHz clock (Output). Thisoutput is an 8kHz 244ns active low framing pulse (OUT_SEL=0), which marks thebeginning of an ST-BUS frame. This is typically used for ST-BUS operation at2.048Mbps and 4.096Mbps. Or this output is an 8kHz 15ns active low framing pulse(OUT_SEL=1), typically used for ST-BUS operation with a clock rate of 65.536MHz.50F16o Frame Pulse ST-BUS 8.192Mbps (Output). This is an 8kHz 61ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUSoperation at 8.192Mbps.51AGND Analog Ground.0V52IC Internal Connection. Connect this pin to ground.ZL30109Data Sheet Pin Description (continued)Pin # Name Description53REF_SEL Reference Select (Input). This input selects the input reference that is used forsynchronization, see Table5 on page20. This pin is internally pulled down to GND.54NC No internal bonding Connection. Leave unconnected.55REF0Reference (Input). This is one of two (REF0, REF1) input reference sources used forsynchronization. One of seven possible frequencies may be used: 2kHz, 8kHz,1.544MHz,2.048MHz, 8.192MHz, 16.384MHz, or 19.44MHz. This pin is internallypulled down to GND.56NC No internal bonding Connection. Leave unconnected.57REF1Reference (Input). See REF0 pin description.58NC No internal bonding Connection. Leave unconnected.59IC Internal Connection. Connect this pin to ground.60OOR_SEL Out Of Range Selection (Input). This pin selects the out of range reference rejection limits, see Table1 on page17.61V DD Positive Supply Voltage. +3.3 V DC nominal.62NC No internal bonding Connection. Leave unconnected.63TIE_CLR TIE Corrector Circuit Reset (Input). A logic low at this input resets the Time IntervalError (TIE) correction circuit resulting in a realignment of the input phase with the outputphase.64BW_SEL Filter Bandwidth Selection (Input). This pin selects the bandwidth of the DPLL loopfilter, see Table2 on page18. Set continuously high to track jitter on the input referenceclosely or set temporarily high to allow the ZL30109 to quickly lock to the input reference.3.0 Functional DescriptionThe ZL30109 is a DS1/E1 System Synchronizer providing timing (clock) and synchronization (frame) signals to interface circuits for DS1 and E1 Primary Rate Digital Transmission links and OC-3/STM-1 links, as well as a 19.44MHz output for SDH line card applications. Figure 1 is a functional block diagram which is described in the following sections.3.1 Reference Select Multiplexer (MUX)The ZL30109 accepts two simultaneous reference input signals and operates on their rising edges. One of them, the primary reference (REF0) or the secondary reference (REF1) signal can be selected as input to the TIE corrector circuit based on the reference selection (REF_SEL) input.3.2 Reference MonitorThe input references are monitored by two independent reference monitor blocks, one for each reference. The block diagram of a single reference monitor is shown in Figure 3. For each reference clock, the frequency is detected and the clock is continuously monitored for three independent criteria that indicate abnormal behavior of the reference signal, for example; long term drift from its nominal frequency or excessive jitter. To ensure proper operation of the reference monitor circuit, the minimum input pulse width restriction of 15nsec must be observed.ZL30109Data Sheet •Reference Frequency Detector : This detector determines whether the frequency of the reference clock is2kHz, 8kHz, 1.544MHz, 2.048MHz, 8.192MHz, 16.384MHz or 19.44MHz and provides this information to the various monitor circuits and the phase detector circuit of the DPLL.•Precise Frequency Monitor : This circuit determines whether the frequency of the reference clock is within the applicable out-of-range limits selected by the OOR_SEL pin, see Figure 5, Figure 6 and Table 1. It will take the precise frequency monitor up to 10 s to qualify or disqualify the input reference.•Coarse Frequency Monitor (CFM): This circuit monitors the reference frequency over intervals ofapproximately 30 µs to quickly detect large frequency changes.•Single Cycle Monitor (SCM): This detector checks the period of a single clock cycle to detect large phase hits or the complete loss of the clock.Figure 3 - Reference Monitor CircuitExceeding the thresholds of any of the monitors forces the corresponding REF_FAIL pin to go high. The single cycle and coarse frequency failure flags force the DPLL into Holdover mode and feed a timer that disqualifies the reference input signal when the failures are present for more than 2.5s. The single cycle and coarse frequency failures must be absent for 10s to let the timer re-qualify the input reference signal as valid. Multiple failures of less than 2.5s each have an accumulative effect and will disqualify the reference eventually. This is illustrated in Figure 4.Reference Frequency Detector Single Cycle Monitor Precise Frequency MonitorCoarse Frequency Monitor dis/requalify timerREF0 / REF1OR OR REF_DIS= reference disrupted.This is an internal signal.Mode select state machine HOLDOVERREF_DIS REF_FAIL0 / REF_FAIL1ZL30109Data SheetSCM or CFM failurecurrent REFtimer2.5 s10 sREF_FAILHOLDOVERFigure 4 - Behaviour of the Dis/Re-qualify TimerWhen the incoming signal returns to normal (REF_FAIL=0), the DPLL returns to Normal mode with the output signal locked to the input signal. Each of the monitors has a built-in hysteresis to prevent flickering of the REF_FAIL status pin at the threshold boundaries. The precise frequency monitor and the timer do not affect the mode (Holdover/Normal) of the DPLL.Figure 5 - DS1 Mode Out-of-Range Limits (OOR_SEL=0)。

RCP890A03 datasheet

SpecificationForLTCC 3dB Hybrid Coupler Model Name : RCP890A03RN2 Technologies co., Ltd.RN2 Technologies co., Ltd.284-2, Galgot-ri, Jinwe-myeon, Pyeongtaek-si, Kyunggi-do, KOREA Phone : (+82) 31 - 376 - 5400FAX : (+82) 31 - 376 - 9151 Distributor:Shenzhen Jushou electronics Co., Ltd.6F,building3,Sege science park, futian shenzhen Tel: 0086-0755-******** Mobile:0086-136******** Email: Fisher@Contact:Mr yu1. Description1-1. Part number: RCP890A031-2. Features- Hybrid Coupler 3dB, 90˚- Surface mount type- Suitable for operation frequency 815~960MHz- RoHS compliance- High stability in temperature and humidity for LTCC base - Low loss for Silver(Ag) conductor- Miniature size and high power capability- Lead-free alloy solderable- Thermal expansion corresponding with common substrate 2. Electrical SpecificationFreq. (MHz) Amplitude Balancemax (dB)Isolationmin (dB)Insertion Lossmax (dB)815-960 ±0.15 -23 -0.15VSWR MaxPhase(degrees)Power CapacityAvg. (Watt)Operating Temp.(℃)1.2 90 ±2.0 200 -55 to +1253. Mechanical Specification 3-1. Outline Dimension3-2. Weight- 1.35 Grams typical4. Port ConfigurationConfiguration Port 1 Port 2 Port 3 Port 4Case 1. Input Isolated Coupling-3dB, 0˚Output-3dB, -90˚Case 2. Isolated Input Output-3dB, 90˚Coupling -3dB, 0˚Case 3. Coupling-3dB, 0˚Output-3dB, 90˚Input IsolatedCase 4.Output-3dB, 90˚Coupling-3dB, 0˚Isolated Input * Once Port 1 is determined, the other three ports are defined automatically.5. Schematic DrawingPort1P inP cou P out P isoPort3 Port4Port26. Typical Performance Data (25℃)Return Loss [dB]Freq. [MHz]Coupling[dB]Out [dB] IL [dB]Amp.Bal.[dB]Phase[degree]S11 S22 S33 S44815 -3.12 -3.07 -0.09 ±0.02 -90.22 -26.15 -27.56 -26.33 -25.85 820 -3.11 -3.08 -0.08 ±0.02 -90.19 -26.37 -27.85 -26.56 -26.07 830 -3.11 -3.10 -0.09 ±0.00 -90.21 -26.85 -28.42 -27.07 -26.52 840 -3.09 -3.11 -0.09 ±0.01 -90.27 -27.34 -29.01 -27.61 -26.97 850 -3.09 -3.13 -0.10 ±0.02 -90.36 -27.92 -29.68 -28.18 -27.47 860 -3.08 -3.13 -0.09 ±0.03 -90.31 -28.50 -30.34 -28.82 -27.99 870 -3.07 -3.13 -0.09 ±0.03 -90.36 -29.12 -31.06 -29.44 -28.53 880 -3.06 -3.14 -0.09 ±0.04 -90.39 -29.81 -31.71 -30.12 -29.12 890 -3.07 -3.16 -0.11 ±0.05 -90.38 -30.50 -32.40 -30.84 -29.72 900 -3.06 -3.14 -0.09 ±0.04 -90.39 -31.22 -32.98 -31.48 -30.27 910 -3.06 -3.14 -0.09 ±0.04 -90.43 -31.95 -33.45 -32.22 -30.88 920 -3.06 -3.16 -0.10 ±0.05 -90.46 -32.69 -33.70 -32.94 -31.45 930 -3.06 -3.15 -0.09 ±0.04 -90.54 -33.41 -33.71 -33.55 -31.92 940 -3.07 -3.14 -0.10 ±0.04 -90.48 -34.05 -33.48 -34.03 -32.38 950 -3.07 -3.13 -0.09 ±0.03 -90.51 -34.53 -33.00 -34.41 -32.73 960 -3.08 -3.14 -0.10 ±0.03 -90.55 -34.72 -32.38 -34.50 -32.89* Data with PCB and Connector Loss ( 0.89 GHz = 0.03dB )7. Operation Temperature Curve (a)RCP650A03 Return Loss(Port1)M a g n i t u d e [d B ]Frequency[MHz]RCP890A03 Return Loss(Port2)M a g n i t u d e [d B ]Frequency[MHz]70080090010001100RCP890A03 Return Loss(Port3)M a g n i t u d e [d B ]Frequency[MHz]70080090010001100RCP890A03 Return Loss(Port4)M a g n i t u d e [d B ]Frequency[MHz]8. Operation Temperature Curve (b)70080090010001100RCP890A03 Coupling & Transmission LossM a g n i t u d e [d B ]Frequency[MHz]70080090010001100RCP890A03 Insertion LossM a g n i t u d e [d B ]Frequency[MHz]70080090010001100RCP890A03 IsolationM a g n i t u d e [d B ]Frequency[MHz]70080090010001100RCP890A03 Phase BalanceP h a s e [d e g ]Frequency[MHz]9. Test Method- Refer to ‘Case 1’ of ‘4. Port Configuration’ on page 4 - Have the network analyzer calibrated properly.- Measure the data of Coupling through port 1 to port 3. (S31) - Measure the data of Transmission through port 1 to port 4. (S41) - Measure the data of Isolation through port 1 to port 2. (S21)- Calculate the Insertion Loss and Amplitude Balance of coupler on the below power method formula.in out P cou : Power of Coupling Port P iso : Power of Isolated Port10. Measurement board layout11. Recommended PCB layout and Solder mask pattern12. Reflow profilePeakSoakingUpPre-HeatingRamp℃ T1:160±5℃ T2:180±5℃ T4:260±5℃ T3:230±5℃Temp.[]Time [sec] t1:60±5sec t2:100±15sec t3:30±5sec t4:60±10sec13. Using note for LTCC CouplersI.Be careful when transportingA.Excessive stress or shock may make products broken or cracked due to the nature ofceramics structure.B.The products cracked or damaged on terminals may have their property changed.II.Be careful during storageA.Store the products in the temperature of -55 ~ 125℃B.Keep the humidity at 45 ~ 75% around the products.C.Prevent corrosive gas (Cl2, NH3, SO X, NO X, etc.) from contacting the products.D.It is recommended to use the products within 6 months of receipt. If the period exceeds6 months, solderability may need to be verified.III.Be careful when solderingA.All the ground terminals, IN and OUT pad of coupler should be soldered on the groundplane of the PCB.B.Products may be cracked or broken by uneven forces from a claw or suction device.C.Mechanical stress by any other devices may damage products when positioning them onPCB.D. A dropped product is recommended not to be used.E.Soldering must be carried out by the condition of specification sheet.F.Any couplers which are de-soldered from PCB should not be used again.14. Packaging15. Environmental ReliabilityITEM PROCEDURE REQUIREMENTS/RESULTTemperature Cycle (Thermal Shock)1. One cycle : 30 minutesStep 1 : 125 ± 5 for 15 minutesStep 2 : -55 ± 5 for 15 minutes2. Time to approach low or high temperature: 10 seconds3. Number of Cycles : 100 cycles4. Keep normal temperature for 1 hour.1. Meet the electrical Specification after testSolderability1. Solder : 230 ± 5°C for 5± 1 sec. 1. More than 85% of the I/Oelectrode pad shall be covered with solder.Heat Resistance 1. Temperature : 100 ± 2 °C 2. Duration : 96 ± 2 hours 1. Meet the electrical Specification after testLow Temp. Resistance1. Temperature : -55 ± 5 °C2. Duration : 24 ± 2 hours 1. Meet the electrical Specification after testVibration Resistance1. Frequency: 5~ 15MHz2. Acceleration : 10g3. Sweep Time: 0.1 oct/min, 15min/axis4. Axis : X, Y and Z direction 1. No appearance damage 2. Meet the electrical Specification after testHumidity Resistance1. One Cycle :Step1:increase Temperature -25~65°C for 2hours with humidity 85%Step2:Maintain for 4 hour after increasing Humidity 90% to 95%Step3: Decrease Temperature 65°C to 25°C 2. Number of Cycles : 103. Maintain for 3hour after decreasing temperature -10°C 1. Meet the electrical Specification after testDrop Shock 1. Dropped onto hard wood from height of 50 cm for 5 times; each x, y and z direction except I/O direction.1. No appearance damage2. Meet the electrical Specification after test16. RoHS test result-RN2 Technologies warrants and represents as follows.。

APX803D-29SRG-7;APX803D-29SAG-7;中文规格书,Datasheet资料

DescriptionThe APX803/D is used for microprocessor (µP) supervisory circuits to monitor the power supplies in µP and digital systems. They provide excellent circuit reliability and low cost by eliminating external components and adjustments when used with +5V, +3.3V, +3.0V powered circuits.These circuits perform a single function: they assert a reset signal on power up and whenever the V CC supply voltage declines below a preset threshold, keeping it asserted for a fixed period of time after V CC has risen above the reset threshold. For the APX803D this period is a minimum of 1ms while for other APX803 variants it is at least 140ms. The reset comparator is designed to ignore fast transients on V CC, and the outputs are guaranteed to be in the correct logic state for V CC down to 1V.The APX803 is available with different reset thresholds suitable for operation with a variety of supply voltages, however the APX803D is available with a 2.93V threshold voltage.The APX803/D have an open collector active low RESET output and compliment Diodes APX809/10 which have push-pull output stages.. Low supply current makes the APX803/D ideal for use in portable equipment. The APX803/D are available in two pin out variants of the 3-pin SOT23 package. Pin Assignments( Top View )GNDV CC RESETSOT23( Top View )GNDV CC RESETSOT23RFeatures• Precision Monitoring of +2.5V, +3V, +3.3V, and +5V Power-Supply Voltages• Fully Specified Over Temperature• Open-drain RESET Active Low• Power-On/power supply glitch Reset Pulse • APX803D 2ms (Typ)• APX803 200ms (Typ)• 30µA Supply Current (Typ.)• Guaranteed Reset Valid to VCC = +1V• No External Components• SOT23 and SOT23R: Available in “Green” Molding Compound (No Br, Sb)• Lead Free Finish/ RoHS Compliant (Note 1) Applications• Computers• Controllers• Intelligent Instruments• Critical µP and µC Power Monitoring • Portable/Battery Powered EquipmentNotes: 1. EU Directive 2002/95/EC (RoHS). All applicable RoHS exemptions applied. Please visit our website atTypical Application CircuitC INPin DescriptionsFunctional Block DiagramRESETV CCAbsolute Maximum RatingsRecommended Operating ConditionsElectrical Characteristics (T A = 25°C)°3. Final datasheet limits to be determined by characterization and correlation.Typical Performance CharacteristicsFigure 1Figure 2Figure 3Figure 4Typical Performance Characteristics (Continued)Figure 7 Figure 8Figure 9 Figure 10Timing DiagramRESETVccFunctional DescriptionMicroprocessors (µPs) and microcontrollers (µC) have a reset input to ensure that it starts up in a known state. The APX803/D drive the µP’s reset input to prevent code-execution errors during power-up, power-down, or brownout conditions. They assert a reset signal whenever the V CC supply voltage declines below a preset threshold and keep it asserted for a fixed period of time after V CC has risen above the reset threshold. For the APX803D this period is a minimum of 1ms while for other APX803 variants it is at least 140ms. The APX803/D have an open-drain output stage.Ensuring a Valid Reset OutputDown to V CC = 0RESET is guaranteed to be a logic low for V CC > 1V. Once V CC exceeds the reset threshold, an internal timer keeps RESET low for the reset timeout period; after this interval, RESET goes high. If a brownout condition occurs (V CC dips below the RESET reset threshold), RESET goes low. Any time V CC goes below the reset threshold, the internal timer resets to zero, and RESET goes low. The internal timer starts after V CC returns above the reset threshold, and RESET remains low for the reset timeout period.When V CC falls below 1V, the APX803/D RESET output no longer sinks current — it becomes an open circuit. Therefore, high-impedance CMOS logic inputs connected to RESET can drift to undetermined voltages. This presents no problem in most applications since most µP and other circuitry is inoperative with V CC below 1V.Interfacing to µP with Bidirectional Reset Pins Since the RESET output on the APX803/D is open drain, this device interfaces easily with μP/µC that have bidirectional reset pins, such as the Motorola 68HC11. Connecting the μP supervisor’s RESET output directly to the microcontroller’s (μC’s) RESET pin with a single pull-up resistor allows either device to assert reset.Supervising and monitoring Multiple Supplies Generally, the pull-up resistor connected to the APX803/D will connect to the supply voltage that is being monitored at the IC’s V CC pin. However, some systems may use the APX803/D open-drain output to level-shift from the monitored supply to reset the µP powered by a different supply voltage or monitor multiple supplies that will be fed into 1 µC/µP reset input.Ordering InformationAPX 8 03 - XX XX G - 7VoltagePackagePacking7 : Tape & ReelOutput typeGreen G : GreenSA : SOT2346:4.6344:4.3840:4.0031:3.0829:2.9326:2.6323:2.2503 : Active-Low, Open DrainSR : SOT23RAPX 8 03 D - 29 XX G - 7VoltagePackagePacking7 : Tape & ReelOutput typeGreen G : GreenSA : SOT2303 : Active-Low, Open DrainSR : SOT23R29:2.93DevicePackage CodePackaging (Note 4) 7” Tape and ReelQuantity Part Number Suffix APX803-XXSAG-7 SA SOT23 3000/Tape & Reel -7 APX803-XXSRG-7 SR SOT23R 3000/Tape & Reel -7 APX803D-29SAG-7 SA SOT23 3000/Tape & Reel -7 APX803D-29SRG-7SRSOT23R3000/Tape & Reel -7Notes: 4. Pad layout as shown on Diodes Inc. suggested pad layout document AP02001, which can be found on our website at /datasheets/ap02001.pdf.Marking Information(1) SOT23 and SOT23R( Top View )XX : Identification codeW : Week : A~Z : 1~26 week;X : A~Z : GreenY : Year 0~9a~z : 27~52 week; z represents 52 and 53 weekDevice Package Identification Code APX803-46SA SOT23 V3 APX803-44SA SOT23V4 APX803-40SA SOT23V5 APX803-31SA SOT23V6 APX803-29SA SOT23V7 APX803-26SA SOT23V8 APX803-23SA SOT23V9 APX803-46SR SOT23R S3 APX803-44SR SOT23R S4 APX803-40SR SOT23R S5 APX803-31SR SOT23R S6 APX803-29SR SOT23R S7 APX803-26SR SOT23R S8 APX803-23SR SOT23R S9 APX803D-29SA SOT23VN APX803D-29SR SOT23R SNPackage Outline Dimensions (All Dimensions in mm)(1) Package Type: SOT23 and SOT23RNotes: 5. Package outline dimensions as shown on Diodes Inc. package outline dimensions document AP02002, which can be found on our website at /datasheets/ap02002.pdf分销商库存信息:DIODESAPX803D-29SRG-7APX803D-29SAG-7。

IPB09N03_DataSheet

IPB09N03_DataSheetOrdering Code MarkingIPI09N03LA, IPP09N03LAParameterSymbol ConditionsUnitmin.typ.max.Thermal characteristicsThermal resistance, junction - case R thJC -- 2.4K/WSMD version, device on PCBR thJAminimal footprint --626 cm 2 cooling area 4)--40Electrical characteristics, at T j =25 °C, unless otherwise specified Static characteristicsDrain-source breakdown voltage V (BR)DSS V GS =0 V, I D =1 mA 25--VGate threshold voltage V GS(th)V DS =V GS , I D =20 µA 1.2 1.62Zero gate voltage drain currentI DSSV DS =25 V, V GS =0 V, T j =25 °C-0.11µA V DS =25 V, V GS =0 V, T j =125 °C-10100Gate-source leakage current I GSS V GS =20 V, V DS =0 V -10100nA Drain-source on-state resistanceR DS(on)V GS =4.5 V, I D =30 A -12.415.5m ?V GS =4.5 V, I D =30 A, SMD version -12.115.1V GS =10 V, I D =30 A -7.79.2V GS =10 V, I D =30 A, SMD version -7.48.9Gate resistance R G -1-?Transconductanceg fs|V DS |>2|I D |R DS(on)max , I D =30 A2142-S 4)Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm 2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air.Values 1)Current is limited by bondwire; with an R thJC =2.4 K/W the chip is able to carry 64 A.2) See figure 33) T j,max =150 °C and duty cycle D <0.25 for V GS <-5 VIPI09N03LA, IPP09N03LA Parameter Symbol Conditions Unitmin.typ.max. Dynamic characteristicsInput capacitance C iss-12401649pF Output capacitance C oss-530704 Reverse transfer capacitance C rss-81122Turn-on delay time t d(on)-913ns Rise time t r-88132Turn-off delay time t d(off)-2233Fall time t f- 4.26Gate Charge Characteristics5)Gate to source charge Q gs- 4.4 5.8nC Gate charge at threshold Q g(th)- 2.0 2.6Gate to drain charge Q gd- 3.1 4.7 Switching charge Q sw- 5.57.9Gate charge total Q g-1014Gate plateau voltage V plateau- 3.5-VGate charge total, sync. FET Q g(sync)V DS=0.1 V,V GS=0 to 5 V-912nCOutput charge Q oss V DD=15 V, V GS=0 V-1115 Reverse DiodeDiode continous forward current I S--50A Diode pulse current I S,pulse--350Diode forward voltage V SD V GS=0 V, I F=50 A,T j=25 °C-0.98 1.2VReverse recovery charge Q rr V R=15 V, I F=I S,d i F/d t=400 A/µs--10nC5) See figure 16 for gate charge parameter definition T C=25 °CValuesV GS=0 V, V DS=15 V,f=1 MHzV DD=15 V, V GS=10 V,I D=25 A, R G=2.7 ?V DD=15 V, I D=25 A,V GS=0 to 5 VIPI09N03LA, IPP09N03LA Package OutlineP-TO263-3-2: OutlineFootprint PackagingIPI09N03LA, IPP09N03LA P-TO262-3-1: OutlineP-TO220-3-1: OutlinePackagingIPI09N03LA, IPP09N03LA Published byInfineon Technologies AGBereich KommunikationSt.-Martin-Stra?e 53D-81541 MünchenInfineon Technologies AG 1999All Rights Reserved.Attention please!The information herein is given to describe certain components and shall not be considered aswarranted characteristics.Terms of delivery and rights to technical change reserved.We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts started herein.Infineon Technologies is an approved CECC manufacturer.InformationFor further information on technology, delivery terms and conditions and prices, please contact your nearest Infineon Technologies office in Germany or our Infineon Technologies representatives worldwide (see address list).WarningsDue to technical requirements, components may contain dangerous substances.For information on the types in question, please contact your nearest Infineon Technologies office. Infineon Technologies' components may only be used in life-support devices or systems with the expressed written approval of Infineon Technologies if a failure of such components can reasonablybe expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implantedin the human body, or to support and/or maintain and sustain and/or protect human life. If they fail,it is reasonable to assume that the health of the user or other persons may be endangered.。

UD4803技术稳定datasheet

RatingSymbol Parameter N-Ch P-Ch Units V DS Drain-Source Voltage 40 -40 V V GS Gate-Sou r ce Voltage±20 ±20 V I D @T C =25℃ Continuous Drain Current, V GS @ 10V 1 23 -20 A I D @T C =100℃Continuous Drain Current, V GS @ 10V 118 -16 A I DM Pulsed Drain Current 246 -40 A EAS Single Pulse Avalanche Energy 328 66 mJ I AS Avalanche Current 17.8-27.2 A P D @T C =25℃Total Power Dissipation 425 31.3 W T STG Storage Temperature Range -55 to 150 -55 to 150 ℃ T JOperating Junction Temperature Range-55 to 150-55 to 150℃Symbol ParameterTyp.Max.UnitR θJA Thermal Resistance Junction-Ambient 1 --- 62 ℃/W R θJCThermal Resistance Junction-Case 1 --- 5 ℃/WBVDSS RDSON ID40V 26m Ω 23A -40V 40m Ω -20AThe UD4803 is the highest performance trench N-ch and P-ch MOSFETs with extreme high cell density , which provide excellent RDSON and gate charge for most of the synchronous buck converter applications . The UD4803 meet the RoHS and Green Product requirement 100% EAS guaranteed with full function reliability approved. zAdvanced high cell density Trench technology zSuper Low Gate Charge zExcellent CdV/dt effect decline z100% EAS Guaranteed z Green Device Available Featuresz High Frequency Point-of-Load Synchronous Buck Converter for MB/NB/UMPC/VGA z Networking DC-DC Power System z CCFL Back-light InverterTO252 Pin ConfigurationProduct SummerySymbol ParameterConditionsMin.Typ.Max.UnitBV DSSDrain-Source Breakdown VoltageV GS =0V , I D =250uA 40 --- --- V△BV DSS /△T J BVDSS Temperature Coefficient Reference to 25℃ , I D =1mA--- 0.034 --- V/℃V GS =10V , I D =12A --- 22 26R DS(ON)Static Drain-Source On-Resistance 2V GS =4.5V , I D =10A --- 28 35m ΩV GS(th) Gate Threshold Voltage 1.0 1.5 2.5 V △V GS(th) V GS(th) Temperature Coefficient V GS =V DS , I D =250uA --- -4.56 --- mV/℃V DS =32V , V GS =0V , T J =25℃ --- --- 1 I DSS Drain-Source Leakage Current V DS =32V , V GS =0V , T J =55℃ --- --- 5 uA I GSSGate-Source Leakage CurrentV GS =±20V , V DS =0V --- --- ±100nA gfs Forward Transconductance V DS =5V , I D =12A --- 8 --- S R g Gate Resistance V DS =0V , V GS =0V , f=1MHz --- 2.6 5.2 ΩQ gTotal Gate Charge (4.5V)---5.5---Q gs Gate-Source Charge --- 1.25 --- Q gd Gate-Drain Charge V DS =20V , V GS =4.5V , I D =12A--- 2.5 --- nC T d(on) Turn-On Delay Time --- 8.9 --- T r Rise Time--- 2.2 --- T d(off) Turn-Off Delay Time --- 41 --- T f Fall Time V DD =20V , V GS =10V , R G =3.3Ω I D =1A--- 2.7 --- nsC iss Input Capacitance --- 593 --- C oss Output Capacitance --- 76 --- C rss Reverse Transfer CapacitanceV DS =15V , V GS =0V , f=1MHz --- 56 ---pFSymbol ParameterConditionsMin.Typ.Max.UnitEASSingle Pulse Avalanche Energy 5V DD =25V , L=0.1mH , I AS =10A9 --- --- mJSymbol Parameter Conditions Min. Typ. Max.UnitI S Continuous Source Current 1,6 --- --- 23 AI SM Pulsed Source Current 2,6V G =V D =0V , Force Current --- --- 46 A V SD Diode Forward Voltage 2V GS =0V , I S =1A , T J =25℃ --- --- 1.2 VNote :1.The data tested by surface mounted on a 1 inch 2 FR-4 board with 2OZ copper.2.The data tested by pulsed , pulse width ≦ 300us , duty cycle ≦ 2%3.The EAS data shows Max. rating . The test condition is V DD =25V,V GS =10V,L=0.1mH,I AS =17.8A4.The power dissipation is limited by 150℃ junction temperature5.The Min. value is 100% EAS tested guarantee.6.The data is theoretically the same as I D and I DM , in real applications , should be limited by total power dissipation.Symbol ParameterConditionsMin.Typ.Max.UnitBV DSSDrain-Source Breakdown VoltageV GS =0V , I D =-250uA -40 --- --- V△BV DSS /△T J BV DSS Temperature Coefficient Reference to 25℃ , I D =-1mA--- -0.012 --- V/℃V GS =-10V , I D =-8A --- 32 40R DS(ON)Static Drain-Source On-Resistance 2V GS =-4.5V , I D =-4A ---52 65 m ΩV GS(th) Gate Threshold Voltage -1.0 -1.6 -2.5 V △V GS(th) V GS(th) Temperature Coefficient V GS =V DS , I D =-250uA --- 4.32 --- mV/℃V DS =-32V , V GS =0V , T J =25℃ --- --- 1 I DSS Drain-Source Leakage Current V DS =-32V , V GS =0V , T J =55℃ --- --- 5 uA I GSSGate-Source Leakage CurrentV GS =±20V , V DS =0V --- --- ±100nA gfs Forward Transconductance V DS =-5V , I D =-8A --- 12.6 --- SR g Gate Resistance V DS =0V , V GS =0V , f=1MHz --- 13 16 ΩQ gTotal Gate Charge (-4.5V)---9---Q gs Gate-Source Charge --- 2.54 --- Q gd Gate-Drain Charge V DS =-20V , V GS =-4.5V , I D =-12A--- 3.1 --- nC T d(on) Turn-On Delay Time --- 19.2 ---T r Rise Time --- 12.8 ---T d(off) Turn-Off Delay Time --- 48.6 --- T f Fall Time V DD =-15V , V GS =-10V , R G =3.3Ω, I D =-1A --- 4.6 --- nsC iss Input Capacitance --- 1004 ---C oss Output Capacitance --- 108 --- C rss Reverse Transfer CapacitanceV DS =-15V , V GS =0V , f=1MHz --- 80 ---pFSymbol ParameterConditionsMin.Typ.Max.UnitEASSingle Pulse Avalanche Energy 5V DD =-25V , L=0.1mH , I AS =-15A20 --- --- mJSymbol ParameterConditionsMin.Typ.Max.UnitI S Continuous Source Current 1,6 --- --- -20 AI SM Pulsed Source Current 2,6V G =V D =0V , Force Current --- --- -40 A V SDDiode Forward Voltage 2V GS =0V , I S =-1A , T J =25℃--- --- -1 VNote : 1.The data tested by surface mounted on a 1 inch 2FR-4 board with 2OZ copper. 2.The data tested by pulsed , pulse width ≦ 300us , duty cycle ≦ 2%3.The EAS data shows Max. rating . The test condition is V DD =-25V,V GS =-10V,L=0.1mH,I AS =-27.2A4.The power dissipation is limited by 150℃ junction temperature5.The Min. value is 100% EAS tested guarantee.6.The data is theoretically the same as I D and I DM , in real applications , should be limited by total power dissipation.1212101DSGS12T J ,Junction Temperature ( ℃)T J , Junction Temperature (℃)。

Datasheet MLX90614 中文数据手册 rev008

标准上，MLX90614 是按照目标物体发射率 1 进行校准的。客户可根据其目标物体的发射率进行修改，可修改范围为 0.1 至 1.0，修改后，客户也不需要用黑体进行校准。
10-位 PWM 输出模式是连续输出所测物体温度的标准配置，测量物体的温度范围为-20…120 °C，分辨率为 0.14 °C。PWM 通过修改 EEPROM 内 2 个单元的值，实际上可以根据需求调整至任何温度范围，而这对出厂校准结果并无影响。
传感器的测量结果均出厂校准化，数据接口为数字式的 PWM 和 SMBus(System Management Bus) 输出。
作为标准，PWM 为 10 位，且配置为-20˚C 至 120 ˚C 内，分辨率为 0.14 ˚C 的连续输出。
传感器出厂默认，上电复位时为 SMBus 通信。
3901090614 Rev 008
PWM 引脚也可配置为热继电器(输入是 To)，这样可以实现简单且性价比高的恒温控制器或温度报警(冰点/沸点)应用，其中的温度临界值是用户可编程的。在 SMBus 系统里，这个功能可以作为处理器的中断信号，以此触发读取主线上从动器的值，并确定精度条件。
传感器有两种供电电压选择：5V 或 3V(电池供电)。其中，5V 也可简便的从更高供电电压(例如 8 至 16V)上通过外接元件调制。(具体请参考“应用信息”)
MLX90614 connection to SMBus
图 1: 典型应用电路
2 概述
MLX90614 是一款用于非接触式的红外温度传感器，集成了红外探测热电堆芯片与信号处理专用集成芯片，全部封装在 TO-39。
低噪声放大器、17 位 ADC 和强大的 DSP 处理单元的全集成，使传感器实现了高精度，高分辨率的测量。

6639S-1-103;6639S-1-102;6639S-1-104;6639S-1-202;6639S-1-203;中文规格书,Datasheet资料

22.23 (.875) DIA.
3.18 (.125)
6639
11.25 .38 (.443 .015)
1.57 (.062)
Байду номын сангаас
22.23 (.875) DIA.
.51 (.020) REF
19.81 (.780) DIA.
12.70 .79 (.500 .031)
10.317+.000/-.051 (.4062+.000/-.002)
DIA.
6.342+.000/-.008
(.2497+.0000/-.0003) DIA. SHAFT .25
45 5 (.010) CHAMFER 1.19 1.60
SLOT (.047) X (.063)
Mechanical Characteristics1
Mechanical Angle ..........................................................Continuous, Stops (340 ° +8 °, -0 °) available Torque (Starting & Running)2 ...................................................................0.40 N-cm (0.5 oz.-in.) max.
Sea Level......................................... 750 VAC minimum .....................750 VAC minimum Power Rating (Voltage Limited By Power Dissipation or 300 VAC, Whichever is Less)

CN803-809-810规格书

如韵电子CONSONANCE极低功耗微处理器复位电路 CN803/809/CN810概述CN803/809/810系列电路是用来监测电源电压或电池电压的微处理器复位电路。

本系列电路不需要外围器件，从而提高了系统的可靠性，降低了系统的成本。

本系列电路在被监测的电源电压低于预先设置的复位阈值时，输出有效的复位信号；当电源电压上升到复位阈值以上时，在至少140毫秒的时间内复位信号还将维持有效。

CN809/810提供CMOS复位输出，CN803提供漏极开路输出。

CN803和CN809的复位输出为低有效，CN810的复位输出为高有效。

在设计上保证短时间的电源突降不会影响复位输出。

在整个温度范围内，当电源电压低至1.15V时仍能保证可靠输出。

本系列器件采用3管脚的SOT23封装。

应用●计算机●微控制器●智能仪表●便携式或电池供电的设备特点●精确的复位阈值：±2.5%●提供两种复位输出：-CMOS输出(CN809/CN810)-漏极开路输出(CN803)●最小140ms的复位脉冲宽度●低工作电流：3V时典型值3.2µA●复位信号在电源电压低至1.15V时仍能维持可靠输出●对短时间电源突降的过滤功能●工作温度范围：－40°C to +85°C●采用SOT23-3封装管脚排列图GNDRESETVCCSOT23-3括号里的内容只针对CN810深圳市国兴顺电子有限公司郑海鑫 139****1192ＱＱ５１４７８９８０７●●器件功能一览表器件型号复位阈值复位电平高有效或低有效输出类型打印标记CN809L 4.63V 低 CMOS AAAA CN810L 4.63V 高 CMOS AGAA CN809M 4.38V 低 CMOS ABAA CN810M 4.38V 高 CMOS AHAA CN809J 4.00V 低 CMOSCWAA CN809T 3.08V 低 CMOS ACAA CN810T 3.08V 高 CMOS AJAA CN809S 2.93V 低 CMOS ADAA CN810S 2.93V 高 CMOS AKAA CN809R 2.63V 低 CMOS AFAA CN810R 2.63V 高 CMOS ALAA CN803S 2.93V 低漏极开路 ABC CN803R 2.63V低漏极开路 ABD功能框图D图1 功能框图管脚描述管脚序号符号功能描述1 GND 地(CN809)CMOS 复位输出（CN809）。

MLX90393_Datasheet_rev001

Part No. Temperature Code Package Code Silicon Version Option Code Packing Format MLX90393 S (-20°C to 85°C) LQ (QFN16 3x3mm) ABA 011 RE (Reel)1. ScopeThis document serves as a specification for a 3-axis magnetometer targeting low-power applications. The IC is based on the Hall-effect and the patented Triaxis® technology from Melexis. The output signals (raw X, Y, Z Magnetic data and Temperature data) will be provided through the I2C fast mode protocol, or via half-duplex SPI (3- or 4-wire). There is an on-board non-volatile memory to store calibration data on-chip.Figure 1: High-level Block DiagramV DDV SS2.Absolute Maximum RatingsThe MLX90393 can withstand the conditions described in the table below for short periods of time; they do not constitute conditions for normal operation.Parameter Remark Min Nom Max Unit V DD_MAX Analog Supply Voltage Limits -0.3 4 VV DD_IO_MAX Digital IO Supply Limits -0.3 min(4, V DD+0.3) V T STORAGE Storage (idle) temperature range -50 125 °C ESD HBM According to AEC-Q100-002 2.5 kV ESD CDM According to AEC-Q100-011-B (QFN) 750 V3.Thermal SpecificationThe MLX90393 has an on-board temperature sensor which measures the temperature of the MLX90393 sensor. The temperature can be read out via the communication protocol in a digital format.Parameter Remark Min Nom Max Unit T RES Temperature sensor resolution 45.2 LSB/°C T25Temperature sensor output at 25°C 46244 LSB16u T LIN Temperature Linearity(1)+/-3 °CT OPERATING Operating temperature range -20 25 85 °C(1)The linearity is defined as the best fit curve through the digital temperature outputs over the entiretemperature range. It includes ADC non-linearity effects.4.Electrical SpecificationThe specifications are applicable at 25degC, unless specified otherwise, and for the complete supply voltage range.(1)Standby current corresponds to the current consumed in the digital, where not the main oscillator isrunning which is used for analog sequencing, but only the low-power oscillator. This standby current is present in Burst mode; whenever the ASIC is counting down to start a new conversion.(2)Idle current is the current that is drawn by the ASIC in the IDLE mode, where it can only receive newcommands on the communication bus, but all other blocks are disabled. The analog (excluding the power-on-reset block) is disconnected, only the digital IO part allows clocking of a few vital gates.5.Timing SpecificationThe specifications are applicable at 25degC, unless specified otherwise, and for the complete supply voltage range.(1)This conversion time is defined as the time to acquire a single axis of the magnetic flux density.When measuring multiple axes, they are obtained through time-multiplexing, i.e. X(t), Y(t+T CONVM) and Z(t+2*T CONVM). The conversion time is programmable through parameters OSR and DIG_FILT for magnetic conversion time and OSR2 for temperature conversion time. The conversion sequence is always TXYZ, the opposite of the ZYXT argument of the command set.(2)The time T INTERVAL is defined as the time between the end of one set of measurements (anycombination of TXYZ) and the start of the following same set of measurements in BURST and WOC mode. As a result of this, the maximum output data rate is not only a function of T INTERVAL but equals 1/(T CONV_BURSTWOC + T INTERVAL).(3)6.Magnetic SpecificationThe specifications are applicable at 25degC, unless specified otherwise, and for the complete supply voltage range.(1)The offset thermal drift is defined as the deviation at 0Gauss from the output with respect to theoutput at 25°C when sweeping the temperature. The highest gradient (µT/°C) typically occurs at 85°C. The spec value is based on characterization on limited sample size at GAIN_SEL=0x7 and RES_XYZ=0x00.(2)The total axis sensitivity is programmable to support different applications, but has no AutomaticGain control on-chip as do the other angular position sensors from Melexis. The highest gain corresponds to at least the minimum +/-4.8mT magnetic measurement range and the magnetic resolution defined by SENS ii.(3)The sensitivity thermal drift is expressed as a band around the sensitivity at 25°C. It is applicable onwafer level trimming, but can be influenced by packaging (overmolding).,RES Z} X YFigure 2: XY axis RMS noise versus conversion time, expressed in mGauss for GAIN_SEL = 0x7Figure 3: Z axis RMS noise versus conversion time, expressed in mGauss for GAIN_SEL = 0x77.Functional SpecificationThe MLX90393 can operate in 3 modes:∙Burst mode: The ASIC will have a programmable data rate at which it willoperate. This data rate implies auto-wakeup and sequencing of the ASIC,flagging that data is ready on a dedicated pin (INT/DRDY). The maximumdata rate corresponds to continuous burst mode, and is a function of thechosen measurement axes. For non-continuous burst modes, the timeduring which the ASIC has a counter running but is not doing an actualconversion is called the Standby mode (STBY).∙Single Measure mode: The master will ask for data via the correspondingprotocol (I2C or SPI), waking up the ASIC to make a single conversion,immediately followed by an automatic return to sleep mode (IDLE) until thenext polling of the master. This polling can also be done by strobing the TRGpin instead, which has the same effect as sending a protocol command for asingle measurement.∙Wake-Up on Change: This mode is similar to the burst mode in the sensethat the device will be auto-sequencing, with the difference that themeasured component(s) is/are compared with a reference and in case thedifference is bigger than a user-defined threshold, the DRDY signal is set onthe designated pin. The user can select which axes and/or temperature fallunder this cyclic check, and which thresholds are allowed.The user can change the operating mode at all time through a specific command on the bus. The device waits in IDLE mode after power-up, but with a proper user command any mode can be set after power-up. Changing to Burst or WOC mode, coming from Single Measure mode, is always accompanied by a measurement first. The top-level state diagram indicating the different modes and some relevant timing is shown below in Figure 4. In the Measure state, the MDATA flag will define which components will be measured (ZYXT). The order of conversion is defined as TXYZ and can not be modified by the user, only the combination of axes is a degree of freedom.Arrows indicated in grey are the direct result of an Exit command. The main difference between STANDBY and WOC_IDLE is that in STANDBY mode, all analog circuitry is ready to make a conversion, but this is accompanied by a larger current consumption than IDLE mode. For burst mode this extra current consumption is justified because the emphasis is more on accurate timing intervals, avoiding the delay of T STBY before conversion and supporting an efficient continuous burst mode without standby overhead.It is the user’s responsibi lity to read back the measured data, the MLX90393 acts as a pure slave. Even in burst mode and WOC mode when the MLX90393 is auto-sequencing, the master will be responsible for collecting the acquired sensor data.TIMEm*T CONVM + T CONVTT ACTIVET STBYT PORFigure 4: Top-level state diagram with indication of timings7.1 Burst modeWhen the sensor is operating in burst mode, it will make conversions at specific time intervals. The programmability of the user is the following:∙ Burst speed (T INTERVAL ) through parameter BURST_DATA_RATE ∙ Conversion time (T CONV ) through parameters OSR, OSR2 and DIG_FILT∙ Axes/Temperature (MDATA) through parameter BURST_SEL or via the command argument (ZYXT)Whenever the MLX90393 has made the selected conversions (based on MDATA), the DRDY signal will be set (active H) on the INT and/or INT/TRG pin to indicate that the data is ready for readback. It will remain high until the master has sent the command to read out at least one of the converted quantities (ZYXT). Should the master have failed to read out any of them by the time the sensor has made a new conversion, the INT/DRDY pin will be strobed low for 10us, and the next rising edge will indicate a new set of data is ready.7.2 Single Measurement modeWhenever the sensor is set to this mode (or after startup) the MLX90393 goes to the IDLE state where it awaits a command from the master to perform a certain acquisition. The duration of the acquisition will be the concatenation of the T STBY, T ACTIVE, m*T CONVM(with m # of axes) and T CONVT. The conversion time will effectively be programmable by the user (see burst mode), but is equally a function of the required axes/temperature to be measured.Upon reception of such a polling command from the master, the sensor will make the necessary acquisitions, and set the DRDY signal high to flag that the measurement has been performed and the master can read out the data on the bus at his convenience. The INT/DRDY will be cleared either when:∙The master has issued a command to read out at least one of the measured components∙The master issues an Exit (EX) command to cancel the measurement∙The chip is reset, after POR (Power-on reset) or Reset command (RT)7.3Wake-Up on Change modeThe Wake-Up on Change (WOC) functionality can be set by the master with as main purpose to only receive an interrupt when a certain threshold is crossed. The WOC mode will always compare a new burst value with a reference value in order to assess if the difference between both exceeds a user-defined threshold. The reference value is defined as one of the following:∙The first measurement of WOC mode is stored as reference value once, as a result of a measurement. This measurement at “t=0” is then the basis for comparison or,∙The reference for acquisition(t) is always acquisition(t-1), in such a way that the INT signal will only be set if the derivative of any component exceeds a threshold.∙The in-application programmability is the same as for burst mode, but now the thresholds for setting the interrupt are also programmable by the user, as well as the reference, if the latter is data(t=0) or data(t-1).8.Digital SpecificationThe supported protocols are I2C and SPI. The SENB/CS pin is used to define the protocol to be used:∙/CS = 0 for SPI, addressing the MLX90393 slave in SPI mode (3- and 4-wire), but releasing this line in between commands (no permanent addressing allowed)∙/CS = 1 for I2C, addressing the MLX90393 slave when the correct address is transmitted over the bus (permanently kept high)To make sure the activity on the SPI bus can not be accidentally interpreted as I2C protocol, programming bits are available in the memory of the MLX90393 to force the communication mode. It concerns the COMM_MODE[1:0] bits with the following effect:8.1Command ListThe MLX90393 only listens to a specific set of commands. Apart from the Reset command, all commands generate a status byte that can be read out. The table below indicates the 10 different commands that are (conditionally) accepted by the MLX90393. The MLX90393 will always acknowledge a command in I2C, even if the command is not a valid command. Interpreting the associated status byte is the method for verification of command acceptance.The argument for the volatile memory access commands (RR/WR) «abc» should be set to 0x0h, in order to get normal read-out and write of the memory.The argument in all mode-starting commands (SB/SW/SM) is a nibble specifying the conversions to be performed by the sensor in the following order «zyxt». For example, if only Y axis and temperature are to be measured in Single Measurement mode the correct command to be transmitted is 0x35h. The sequence of measurement execution on-chip is inverted to «TXYZ», so T will be measured before X, followed by Y and finally Z. By issuing an all-zero «zyxt» nibble, the BURST_SEL value from RAM will be used instead of the empty argument of the command.8.2Status ByteThe status byte is the first byte transmitted by the MLX90393 in response to a command issued by the master. It is composed of a fixed combination of informative bits:∙MODE bitsthese bits define in which mode the MLX90393 is currently set. Whenever a mode transition command is rejected, the first status byte after this command will have the expected mode bit cleared, which serves as an indication that the command has been rejected, next to the ERROR bit. The SM_MODE flag can be the result of an SM command or from raising the TRG pin when TRG mode is enabled in the volatile memory of the MLX90393.∙ERROR bitthis bit is set in case a command has been rejected or in case an uncorrectable error is detected in the memory, a so called ECC_ERROR. A single error in the memory can be corrected (see SED bit), two errors can be detected and will generate the ECC_ERROR. In such a case all commands but the RT (Reset) command will be rejected. The error bit is equally set when the master is reading back data while the DRDY flag is low.∙SED bitthe single error detection bit simply flags that a bit error in the non-volatile memory has been corrected. It is purely informative and has no impact on the operation of the MLX90393.∙RS bitwhenever the MLX90393 gets out of a reset situation –both hard and soft reset –the RS flag is set to highlight this situation to the master in the first status byte that is read out. As soon as the first status byte is read, the flag is cleared until the next reset occurs.D[1:0] bitsthese bits only have a meaning after the RR and RM commands, when data is expected as a response from the MLX90393. The number of response bytes correspond to 2*D[1:0] + 2, so the expected byte counts are either 2, 4, 6 or 8. For commands where no response is expected, the content of D[1:0] should be ignored.8.3SPI CommunicationThe MLX90393 can handle SPI communication at a bitrate of 10Mhz. The SPI communication is implemented in a half-duplex way, showing high similarities with I2C communication, but addressing through the \CS (Chip Select) pin instead of through bus arbitration. The half-duplex nature is at the basis of the supported 3-wire SPI operation. SPI mode 3 is implemented: CPHA=1 (data changed on leading edge and captured on trailing edge, and CPOL=1 (high level is inactive state). The Chip Select line is active-low.The communication is also bundled in bytes, equally MSB first and MSByte first. A command can of course consist of more than 1 byte (refer to Chapter 8.1) as can the response be from the MLX90393 in the form of multiple bytes after the status byte (not shown in Figure 5)COMMAND[7:0]SCL MOSI 1234567812345678MISO/CS STATUS_BYTE[7:0]X (4-wire SPI) or Z (3-wire SPI)Z (3 & 4-wire SPI)ADDNADDFigure 5: SPI communication example8.4 I 2C CommuncationI 2C AddressThe I 2C address is made up of some hard-coded bits and a memory written value as follows:I2C_ADDR[6:0] = {EE_I2C_ADDR[4:0],A 1,A 0} with A i the user-selectable active-high value of the input pads of the MLX90393, referred to the V DD supply system and EE_I2C_ADDR[4:0] default programmed to 03h, but user accessible for overwrite.I 2C PrincipleThe MLX90393 supports I 2C communication in both Standard Mode and Fast Mode. Bytes are transmitted MSB first, and in order to reconstruct words, the bytes need to be concatenated MSByte first. The general principle of communication is always the same:∙ Initiating the communication is always done by the Master (Start condition S)∙ Addressing the Slave (MLX90393) followed by a cleared bit to indicate the Master intends to writesomething to the specific addressed Slave ∙ Acknowledging by the Slave if the transmitted address corresponds to the Slave’s I 2C address. If thelatter isn’t the case, any further activity on the bus except a Sr (Start Repeat) and P (Stop) condition will be ignored by the MLX90393 ∙ Sending a Command Byte by the Master, as depicted in Figure 6. The Slave will always acknowledgethis, even if it is an unrecognized command. A command such as WR and RR consist of more than 1 byte, which can then be transmitted sequentially over the I 2C bus. Referring to Figure 6 the COMMAND byte should then be a sequence of C OMMAND byte1, byte2, etc… ∙ Issuing a Start Repeat (Sr) condition by the Master in order to restart the addressing phase∙Addressing the Slave (MLX90393) followed by a set bit to indicate the Master intends to read something from the specific addressed Slave∙Acknowledging by the Slave if the transmitted address corresponds to the Slave’s I2C address. If the latter isn’t the case, any further activity on the bus except a Sr (Start Repeat) and P (Stop) condition will be ignored by the MLX90393∙Transmitting the Status Byte by the Slave, who is in control of the bus. Following the RR and RM commands the sensor returns additional data bytes after the status byte.∙Acknowledging by the Master if the data is well received∙Generating a Stop condition (P) by the masterThe Master controlled bus activity is shown in blue, the Slave controlled bus activity is shown in orange. In case a command is longer than a single byte (see Table 6), the bytes are transmitted sequentially before generating the Start Repeat (Sr) condition.I2C_ADDR[6:0]W ACKSCOMMAND[7:0]ACKI2C_ADDR[6:0]R ACK Sr STATUS_BYTE[7:0]ACKSCL SDA SCL SDA 123456789123456789123456789P 123456789Figure 6: Default I2C communication example with status byte readbackThe same applies to the Slave responses: following RR and RM commands, the Slave response is more than just the Status Byte. There as well, the data is partitioned in bytes that are transmitted sequentially by the slave. It is the Master’s responsibility to issue enough clocking p ulses to read back all the data. Finding out how many bytes is possible by decoding the Status Byte information, see Section Status Byte.Finally the master is also free to not read back the status byte when issuing a command. In doing so, he loses the ability to see if the command was received properly by the MLX90393. Moreover, the first SM command issued by the master after power-up or reset should have the status byte read back in order to get valid measurement data back.9. Memory MapThe MLX90393 has 1kbit of non-volatile memory, and the same amount of volatile memory. Each memory consists out of 64 addresses containing 16 bit words. The non-volatile memory has automatic 2-bit error detection and 1-bit error correction capabilities per address. The handling of such corrections & detections is explained in Section Status Byte. The memory is split in 2 areas:∙ Customer area [address 0x00h to 0x1Fh] ∙ Melexis area [address 0x20h to 0x3Fh]The RR and WR commands impact the volatile memory only, there no direct access possible to the non-volatile memory. The customer area of the volatile memory is bidirectionally accessible to the customer; the Melexis area is write-protected. Only modifications in the blue area are allowed with the WR command. The adjustments in the customer area can be stored in the permanent non-volatile memory with the STORE command HS, which copies the entire volatile memory including the Melexis area to the non-volatile one. With the HR command the non-volatile memory content can be recalled to the volatile memory, which can restore any modifications due to prior WR commands. The HR step is performed automatically at start-up of the ASIC, either through cold reset or warm reset with the RT command. The above is graphically shown in Figure 7.Figure 7: The memories of the MLX90393, their areas and the impacting commands.The customer area houses 3 types of data:∙Analog configuration bits∙Digital configuration bits∙Informative (free) bitsThe latter can be filled with customer content freely, and covers the address span from (and including) 0x0Ah to 0x1Fh, a total of 352 bits. The memory mapping of volatile and non-volatile memory on address level is identical. The volatile memory map is given in Figure 8.Figure 8: Customer area memory map.The non-volatile memory can only be written (HS store command) if pin VDD is supplied with 3.3V minimum, otherwise the write sequence can not be performed in a reliable way. Additionally, this HS command was designed to be used as one-time calibration, but not as multi write-cycle memory within the application. In case memory is written within the application, the number of write cycles should be kept to a minimum. There is no limit to the write cycles in the volatile memory (WR write command).9.1Parameter DescriptionThe meaning of each customer accessible parameter is explained in this section. The customer area of both the volatile and the non-volatile memory can be written through standard SPI and I2C communication, within the application. No external high-voltages are needed to perform such operations, nor access to dedicated pins that need to be grounded in the application.ANA_RESERVED_LOW : Reserved IO trimming bitsBIST : Enabled the on-chip coil, applying a Z-field [Built-In Self Test]Z_SERIES : Enable all plates for Z-measurementGAIN_SEL[2:0] : Analog chain gain setting, factor 5 between min and max code HALLCONF[3:0] : Hall plate spinning rate adjustmentTRIG_INT_SEL : Puts TRIG_INT pin in TRIG mode when cleared, INT mode otherwise COMM_MODE[1:0] : Allow only SPI [10b], only I2C [11b] or both [0Xb] according to CS pin WOC_DIFF : Sets the Wake-up On Change based on Δ{sample(t),sample(t-1)} EXT_TRIG : Allows external trigger inputs when set, if TRIG_INT_SEL = 0 TCMP_EN : Enables on-chip sensitivity drift compensationBURST_SEL[3:0] : Defines the MDATA in burst mode if SB command argument = 0 BURST_DATARATE[6:0] : Defines T INTERVAL as BURST_DATA_RATE * 20msOSR2[1:0] : Temperature sensor ADC oversampling ratioRES_XYZ[5:0] : Selects the desired 16-bit output value from the 19-bit ADCDIG_FILT[1:0] : Digital filter applicable to ADCOSR[1:0] : Magnetic sensor ADC oversampling ratioSENS_TC_HT[7:0] : Sensitivity drift compensation factor for T < T REFSENS_TC_LT[7:0] : Sensitivity drift compensation factor for T > T REFOFFSET_i[15:0] : Constant offset correction, independent for i = X, Y, ZWOi_THRESHOLD[15:0] : Wake-up On Change threshold, independent for i = X, Y, Z and T10.Packaging Specification10.1QFN packageThe MLX90393 shall be delivered in a QFN package as shown below in Figure 9.XZYFigure 9: Package Outline DrawingThe sensing elements – Hall plates with the patented IMC technology – are located in the center of the die, which on its turn is located in the center of the package. The pinout (in name and function) is given in Table 7 below.11.Standard information regarding manufacturability of Melexisproducts with different soldering processesOur products are classified and qualified regarding soldering technology, solderability and moisture sensitivity level according to following test methods:Reflow Soldering SMD’s (Surface Mount Devices)IPC/JEDEC J-STD-020Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices (classification reflow profiles according to table 5-2)∙EIA/JEDEC JESD22-A113Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing (reflow profiles according to table 2)Wave Soldering SMD’s (Surface Mount D evices) and THD’s (Through Hole Devices)∙EN60749-20Resistance of plastic- encapsulated SMD’s to combined effect of moisture and soldering heat∙EIA/JEDEC JESD22-B106 and EN60749-15Resistance to soldering temperature for through-hole mounted devicesIron Soldering THD’s (Through Hole Devices)∙EN60749-15Resistance to soldering temperature for through-hole mounted devicesSolderability SMD’s (Surface Mount D evices) and THD’s (Through Hole Devices)∙EIA/JEDEC JESD22-B102 and EN60749-21SolderabilityFor all soldering technologies deviating from above mentioned standard conditions (regarding peak temperature, temperature gradient, temperature profile etc) additional classification and qualification tests have to be agreed upon with Melexis. The application of Wave Soldering for SMD’s is allowed only after consulting Melexis regarding assurance of adhesive strength between device and board.Melexis recommends reviewing on our web site the General Guidelines soldering recommendation (/Quality_soldering.aspx) as well as trim&form recommendations (/Assets/Trim-and-form-recommendations-5565.aspx).Melexis is contributing to global environmental conservation by promoting lead free solutions. For more information on qualifications of RoHS compliant products (RoHS = European directive on the Restriction Of the use of certain Hazardous Substances) please visit the quality page on our website: /quality.aspx12.ESD PrecautionsElectronic semiconductor products are sensitive to Electro Static Discharge (ESD). Always observe Electro Static Discharge control procedures whenever handling semiconductor products.13.Recommended Application Diagram13.1I2CA1A0 I2C Address13.2SPI14.Table of Contents1.Scope (1)2.Absolute Maximum Ratings (2)3.Thermal Specification (2)4.Electrical Specification (2)5.Timing Specification (3)6.Magnetic Specification (6)7.Functional Specification (9)7.1Burst mode (11)7.2Single Measurement mode (12)7.3Wake-Up on Change mode (12)8.Digital Specification (13)8.1Command List (13)8.2Status Byte (14)8.3SPI Communication (15)8.4I2C Communcation (16)I2C Address (16)I2C Principle (16)9.Memory Map (19)9.1Parameter Description (20)10.Packaging Specification (22)10.1QFN package (22)11.Standard information regarding manufacturability of Melexis products with different soldering processes (23)12.ESD Precautions (24)13.Recommended Application Diagram (25)13.1I2C (25)13.2SPI (25)。

AMP connector

MTA,CST-100II,SL-156and AMP Economy Power(EP)Connectors2©1977,1978,1979,1980,1983,1986,1988,1992,1993,1994,1995,1999,2000,2001,2002,2003and2005byTyco Electronics Corporation.All International Rights Reserved.AMP,AMP-O-LECTRIC,AMP-O-MATIC,AMPOMATOR,CERTI-CRIMP,PRO-CRIMPER,MADISON CABLE andTYCO are trademarks.TEFLON is a trademark of E.I.DuPontDe Nemours and Company.Other products,logos,and companynames mentioned herein may betrademarks of their respective owners.Introduction and Table of Contents.................................................2,3Connector Selection Guide (3).050[1.27]Centerline ConnectorsMTA-50IDC Connectors and Headers............................................4-10Introduction and Wire-to-Board Mateability Guide (4)IDC Connector Kits(Feed-Thru and Closed End)Ribbon Cable.......................................................5,6Discrete Wire........................................................7,8Through-Hole Header AssembliesVertical and Right-Angle (9)Surface Mount Header AssembliesVertical and Right-Angle (10).100[2.54]Centerline ConnectorsMTA-100IDC Connectors and Headers..........................................11-31Introduction (11)Wire-to-Board Mateability Guide.........................................12,13Connectors—UL94V-2and UL94V-0Closed End with and without Polarizing Tab.............................14,15Feed-Thru with and without Polarizing Tab..............................14,15LED Closed End and Feed-Thru—UL94V-2.............................14,15Accessories.........................................................16,17Posted Connectors Mateability Guide....................................18,19MTA-100Posted Connectors(Wire-to-Wire)UL94V-2Closed End (20)Feed-Thru (20)Headers—UL94V-0Flat—Straight and Right-Angle Posts (21)Narrow Flat—Straight and Right-Angle Posts (22)Polarized—Straight and Right-Angle Posts (23)Friction Lock—Straight and Right-Angle Posts (24)Headers with Retention Peg—Straight Posts (25)High Profile Headers—Right-Angle Posts (26)Polarized—High Temperature,Straight and Right-Angle Posts (27)Friction Lock—High Temperature,Straight and Right-Angle Posts (28)Polarized—Surface Mount,Straight (29)Friction Lock—Surface Mount,Straight (29)Shrouded—Straight and Right-Angle Posts (30)CST-100II Crimp Contacts,Housings and Shrouded Headers.........................31,32.156[3.96]Centerline ConnectorsMTA-156IDC Connectors and Headers..........................................33-57Introduction (33)Wire-to-Board Mateability Guide.........................................34,35Connectors—UL94V-2and UL94V-0Closed End with Locking Ramp,with and without Polarizing Tabs...........36,37Closed End without Locking Ramp,with and without Polarizing Tabs.........36,37Feed-Thru with Locking Ramp,with and without Polarizing Tabs.............38,39Feed-Thru without Locking Ramp,with and without Polarizing Tabs...........38,39Accessories.........................................................40-42Posted Connectors Mateability Guide....................................43,44MTA-156Posted Connectors(Wire-to-Wire)—UL94V-2Closed End (45)Feed-Thru (45)MTA-156Headers—UL94V-0Flat—Straight Posts (46)Flat—Right-Angle Posts (47)Friction Lock—Straight Posts (48)Friction Lock—Right-Angle Posts (49)Polarized Lock—Straight Posts (50)Polarized Lock—Right-Angle Posts (51)Friction Lock—High Temperature,Straight Posts (52)Shrouded—Straight and Right-Angle Posts (53)MTA-156Quad Connectors—UL94V-0.........................................54,55Closed End with Locking Ramp (55)Feed-Thru with Locking Ramp (55)IDCMTA-50IDCMTA-100CrimpCST-100IIIDCMTA-156Catalog82056Dimensions are in inches and Dimensions are shown for USA:1-800-522-6752South America:55-11-2103-6000 Revised6-08millimeters unless otherwise reference purposes only.Canada:1-905-470-4425Hong Kong:852-2735-1628 specified.Values in brackets Specifications subject Mexico:52-55-1106-0800Japan:81-44-844-8013 are metric equivalents.to change. C.America:57-1-254-4444UK:44-208-420-83413MTA-156Card Edge .......................................................56,57Connectors —UL94V-0Closed End with and without Mounting Ears ................................56Feed-Thru with and without Mounting Ears .................................56Accessories ............................................................57SL-156Crimp Connectors and Headers .........................................58-62Wire-to-Board Mateability Guide ............................................58Wire-to-Board Crimp Contacts and Keying Plugs ...............................59Wire-to-Board Housings —UL94V-0.........................................60Housings with Through Board Latch —UL94V-2...............................61Housings and Contacts for Large Insulation Diameter (LID)Wire ..................62AMP Economy Power (EP)Connector System .......................................63-69.156[3.96]Centerline ConnectorsIntroduction ............................................................63Crimp Contacts .........................................................64Plug Housings,Low-Profile ................................................64Low-Profile Headers —Straight and Right-Angle Posts ..........................65Low-Profile Headers,High Temp.—Straight and Right-Angle Posts ...............66.200[5.08]Centerline ConnectorsPlug Housings and Straight and Right-Angle Post Headers ......................67.312[7.92]Centerline ConnectorsLow-Profile Headers —Straight Posts .......................................68Single Connectors1-Position Plug Housing and High-Profile Header —Straight Post .................69MTA Wire Selection and Ribbon Cable Preparation ......................................70IDC Ribbon Cable ...........................................................71-74MTA Wire Termination Flowchart ...................................................75MTA Application Tooling .......................................................76-79Part Number Index ...........................................................80-82Global Contacts (83)Need more information?Call T echnical Support at the numbers listed below.T echnical Support is staffed with specialists well versed in Tyco Electronics products.They can provide you with:I Technical support I CatalogsI Technical Documents I Product SamplesI Authorized Distributor LocationsCrimpSL-156CrimpAMP EP ConnectorsCatalog 82056Dimensions are in inches and Dimensions are shown for USA:1-800-522-6752South America:55-11-2103-6000Revised 6-08millimeters unless otherwise reference purposes only.Canada:1-905-470-4425Hong Kong:852-2735-1628specified.Values in brackets Specifications subject Mexico:52-55-1106-0800Japan:are metric equivalents.to change.C.America:57-1-254-4444UK:44-208-420-83414M T A -50.050[1.27]Component Recognized Underwriters Inc.to US and Standards,File No.E28476(Connectors and Headers)File No.E53793(Ribbon Cable)The MTA-50IDC Connector System is a wire-to-printed cir-cuit board system with con-tacts in a staggered,single row on .050[1.27]centerline.The design features wire feed-through capability for daisy-chain applications.Insulation displacement contacts are used to terminate a wide range of conductor sizes.Ribbon cable can also be ter-minated when the appropriate receptacle assembly and strain relief cover are used.Header assemblies for board mount applications include right-angle (horizontal)and vertical mount products.These are available inthrough-hole and surface mount configurations.Typical uses of the MTA-50IDC connectors would be in the Appliance,Commercial and Home Equipment and Security products industries.See thefollowing pages for related products:I Ribbon Cable (reels),.050[1.27]centerline (p.71)I Application T ooling (p.76)I Cable Assemblies (p.74)Performance DataVoltage Rating —30VAC Current Rating —1amp max.Low-Level Resistance —30milliohmsDielectric Withstanding Voltage —500VACInsulation Resistance —1,000megohmsOperating Temperature —–55°C to +105°C for connector only;cable rating may be lowerTechnical DocumentsApplication Specification —114-13072MTA-50Connectors Product Specifications —108-2113MTA-50Connectors 100-4703MADISON CABLE CableSpecification (28AWG,7/36Tinned copper,PVC insulation)100-6257MADISON CABLE CableSpecification (28AWG,7/36Tinned copper,TPO insulation)These matrixes have been prepared to assist you in defining the correct mating halves for the MTA-50header and connector kit combina-tion.Where a “Y”is indicated the combination is a valid mating pair.Note:T yco Electronics does NOT rec-ommend intermating connectors and headers with different contact plat-ings.C o n n e c t o r K i t sHeaders C o n n e c t o r K i t sMatrix for .000030[0.00076]Gold Plated Part NumbersC o n n e c t o r K i t sMatrix for .000015[0.00038]Gold Plated Part NumbersMatrix for Tin Plated Part Numbers HeadersHeadersMTA-50IDC Connector Kit /Header Mateability GuideCatalog 82056Dimensions are in inches and Dimensions are shown for USA:1-800-522-6752South America:55-11-2103-6000Revised 6-08millimeters unless otherwise reference purposes only.Canada:1-905-470-4425Hong Kong:852-2735-1628specified.Values in brackets Specifications subject Mexico:52-55-1106-0800Japan:are metric equivalents.to change.C.America:57-1-254-4444UK:44-208-420-83415MTA-50.050[1.27]Connector Kits —Ribbon CableFeed-Thru andClosed End ConnectorsMaterial and FinishHousing —UL 94V-2rated,thermo-plasticContacts —Phosphor bronze;.000100[0.00254]min.tin in wiretermination area,over.000050[0.00127]min.nickel;choice on mating end:.000100[0.00254]min.tin or .000030[0.00076]gold or .000015[0.00038]gold,over .000050[0.00127]min.nickelColor Coding by Wire Size for UL94V-0Connectors26AWG —Blue 28AWG —Green 30AWG —BrownFor Strain Relief Covers see page 6.For mating Headers see pages 9and 10.For Mateability Guide,see matrixes on page4..050[1.27].035[0.89]]Ref.Position 1.150[3.81]Notes:1.To determine connector overall length (dim.A),multiply .050x the number of circuits and add .082.Example:.050x 10circuitsequals 0.50+.082=.582[14.78].2.Strain relief covers shown on page 6are required and sold as part of the Connector Kit.3.Stranded UL Style 1061or equiv-alent wire is recommended.4.Unless otherwise stated all toler-ances (except plating)to be ±.005[±0.13].5.Consult Product Drawing for RoHS Compliant information.Note:Tin-plated connectors and headers in even position sizes from 2–12and 18are stocked parts;all other position sizes and products with gold-plated contacts are Make T o Order.Receptacle Assemblies —Ribbon CableCatalog 82056Dimensions are in inches and Dimensions are shown for USA:1-800-522-6752South America:55-11-2103-6000Revised 6-08millimeters unless otherwise reference purposes only.Canada:1-905-470-4425Hong Kong:852-2735-1628specified.Values in brackets Specifications subject Mexico:52-55-1106-0800Japan:are metric equivalents.to change.C.America:57-1-254-4444UK:44-208-420-83416M T A -50.050[1.27].090[2.29]4Plcs.AStrain ReliefCoversMaterial and FinishStrain Relief Cover —UL 94V-0rated,thermoplastic,blackClosed EndFeed-Thru and Closed EndDim.A No.of CircuitsDim.161718.2606.60.3107.87.3609.14Closed End[3.12AFeed-ThruFeed-ThruConnector Kits —Ribbon Cable (Continued)Catalog 82056Dimensions are in inches and Dimensions are shown for USA:1-800-522-6752South America:55-11-2103-6000Revised 6-08millimeters unless otherwise reference purposes only.Canada:1-905-470-4425Hong Kong:852-2735-1628specified.Values in brackets Specifications subject Mexico:52-55-1106-0800Japan:are metric equivalents.to change.C.America:57-1-254-4444UK:44-208-420-83417MTA-50.050[1.27]Connector Kits —Discrete WireFeed-Thru andClosed End ConnectorsMaterial and FinishHousing —UL 94V-2rated,thermo-plasticContacts —Phosphor bronze;.000100[0.00254]min.tin in wiretermination area,over.000050[0.00127]min.nickel;choice on mating end:.000100[0.00254]min.tin or .000030[0.00076]gold or .000015[0.00038]gold,over .000050[0.00127]min.nickelColor Coding by Wire Size for UL94V-0Connectors26AWG —Blue 28AWG —Green 30AWG —BrownFor Strain Relief Covers see page 8.For mating Headers see pages 9and 10.For Mateability Guide,see matrixes on page4..050[1.27].035[0.89]]Ref.Position 1.150[3.81].006 0.15]Notes:1.To determine connector overall length (dim.A),multiply .050x the number of circuits and add .082.Example:.050x 10circuitsequals 0.50+.082=.582[14.78].2.Strain relief covers shown on page 8are required and sold as partofthe Connector Kit.3.Stranded UL Style 1061or equiv-alent wire is recommended.4.Unless otherwise stated all toler-ances (except plating)to be ±.005[±0.13].5.Consult Product Drawing for RoHS Compliant information.Note:Tin-plated connectors and headers in even position sizes from 2–12and 18are stocked parts;all other position sizes and products with gold-plated contacts are Make T o Order.Receptacle Assemblies —Discrete WireCatalog 82056Dimensions are in inches and Dimensions are shown for USA:1-800-522-6752South America:55-11-2103-6000Revised 6-08millimeters unless otherwise reference purposes only.Canada:1-905-470-4425Hong Kong:852-2735-1628specified.Values in brackets Specifications subject Mexico:52-55-1106-0800Japan:are metric equivalents.to change.C.America:57-1-254-4444UK:44-208-420-83418M T A -50.050[1.27]Strain Relief CoversMaterial and FinishStrain Relief Cover —UL 94V-0rated,thermoplastic,blackClosed EndDim.A No.of CircuitsDim.161718.2606.60.3107.87.3609.14Feed-Thru and Closed EndFeed-Thru.090[2.29]4Plcs.AClosed End.123 [3.12AFeed-ThruConnector Kits —Discrete Wire (Continued)Catalog 82056Dimensions are in inches and Dimensions are shown for USA:1-800-522-6752South America:55-11-2103-6000Revised 6-08millimeters unless otherwise reference purposes only.Canada:1-905-470-4425Hong Kong:852-2735-1628specified.Values in brackets Specifications subject Mexico:52-55-1106-0800Japan:are metric equivalents.to change.C.America:57-1-254-4444UK:44-208-420-83419MTA-50.050[1.27]Right-AngleA.125[3.18].016 [0.41].050[1.27]Ref.Ref.Ref.Circuit #1.180 [4.57][5.59±0.08].035[0.89]Ref.VerticalMaterial and FinishHousing —UL 94V-0rated,thermo-plastic,blackContacts —Brass,.000100[0.00254]min.tin over.000050[0.00127]min.nickel on solder legs;choice on mating end:.000100[0.00254]min.tin or .000030[0.00076]gold or .000015[0.00038]gold,over .000050[0.00127]min.nickel#1ABase Part NumbersThrough-Hole Header No.of Part Nos.PostsStandard UL 94V-0,Tin Plated14451202–28Standard UL 94V-0.000030[0.00076]Gold Plated14451252–28Standard UL 94V-0.000015[0.00038]Gold Plated14451232–28Note:To determine header overalllength (dim.A),multiply .050x the number of circuits and add .150.Example:.050x 6circuits equals .300+.150=.450[11.43]..100[2.54].035[0.89].210[5.33].050[1.27].250*[6.35].031±.002[0.78±0.05Circuit #1Typ.Recommended Mounting Hole Size andPattern for .062[1.57]Thick PC BoardDim.shown,refer to Product Drawing for Dimensions and RoHS Compliant information.Base Part NumbersThrough-Hole Header Part Nos.Standard UL 94V-0,1445169Standard UL 94V-0.000030[0.00076]Gold 1445171Standard UL 94V-0.000015[0.00038]Gold 1445170For mating Connector Kits see pages 5through 8.For mateability options,see matrixes on page 4.Note:Tin-plated connectors and headers in even position sizes from 2–12and 18are stocked parts;all other position sizes and products with gold-plated contacts are Make T o Order.Through-Hole Header Assemblies Catalog 82056Dimensions are in inches and Dimensions are shown for USA:1-800-522-6752South America:55-11-2103-6000Revised 6-08millimeters unless otherwise reference purposes only.Canada:1-905-470-4425Hong Kong:852-2735-1628specified.Values in brackets Specifications subject Mexico:52-55-1106-0800Japan: are metric equivalents.to change.C.America:57-1-254-4444UK:44-208-420-834110M T A -50.050[1.27]Right-AngleVerticalMaterial and FinishHousing —UL 94V-0rated,thermo-plastic,blackContacts —Brass,.000100[0.00254]min.tin over.000050[0.00127]min.nickel on solder pads;choice on mating end:.000100[0.00254]min.tin or .000030[0.00076]gold or .000015[0.00038]gold,over .000050[0.00127]min.nickelBoardlock —Phosphor bronze,tin plated .000100[0.000254]min.over .000050[0.00127]min.nickel.035[0.89]Ref.Circuit #1A.249[6.32].003 0.08]Ref.For mating Connector Kits see pages 5through 8.For mateability options,see matrixes on page 4.Note:To determine header overalllength (dim.A),multiply .050x the number of circuits and add .150.Example:.050x 6circuits equals .300+.150=.450[11.43]..162[4.11]*6-circuit Dim.shown,refer to Product Drawing for actualPCB Dimensions and RoHS Compliant information..050[1.27]Circuit #1Typ..028 ±.001 [0.71 ±0.03].075±.001 [1.91±0.03] ].145±.003 [3.68±0.08].574*for use with .010[0.25] Thick StencilTyp.Base Part NumbersSurface Mount Header No.of Part Nos.PostsStandard UL 94V-0,Tin Plated14451722–28Standard UL 94V-0.000030[0.00076]Gold Plated14451742–28Standard UL 94V-0.000015[0.00038]Gold Plated14451732–28Base Part NumbersSurface Mount Header No.of Part Nos.PostsStandard UL 94V-0,Tin Plated14451212–28Standard UL 94V-0.000030[0.00076]Gold Plated14451262–28Standard UL 94V-0.000015[0.00038]Gold Plated14451242–28Note:All SMT product is pre-packaged in standard tape and reel format..162[4.11].574*[14.58][2.54].100[2.54]*6-circuit Dim.shown,refer to Product Drawing for actualPCB Dimensions and RoHS Compliant information..050[1.27]Circuit #1Typ..100[2.54]Typ.Typ.Typ..028±.001[0.71±0.03].065±.001 [1.65±0.03].070±[1.78±[3.68Recommended PC Board Layout for use with .010 [0.25] Thick StencilA.050[1.27].035[0.89]Ref.Ref.Circuit #1.270 [6.86][5.59±0.08]Ref.Note:Tin-plated connectors and headers in even position sizes from 2–12and 18are stocked parts;all other position sizes and products with gold-plated contacts are Make T o Order.Surface Mount Header AssembliesCatalog 82056Dimensions are in inches and Dimensions are shown for USA:1-800-522-6752South America:55-11-2103-6000Revised 6-08millimeters unless otherwise reference purposes only.Canada:1-905-470-4425Hong Kong:852-2735-1628specified.Values in brackets Specifications subject Mexico:52-55-1106-0800Japan:are metric equivalents.to change.C.America:57-1-254-4444UK:44-208-420-834111MTA-100.100[2.54]Technical DocumentsProduct Specification108-1050MTA-100Connectors Application Specifications 114-1019MTA-100Connectors 114-1031MTA-100Ribbon CableAssemblyMT A-100connectorsaccept discrete and ribbon cable wire sizes ranging from 22–28AWG [0.4–0.08mm 2]with maximum insulation outside diameter of .060[1.52]for terminat-ing single wire and .050[1.27]for mass termination of wires.Tin plated solid,fusedstranded,or stranded (7strands)wire with PVC insulation can be used on 22–28AWG [0.4–0.9mm 2]MTA-100connectors and 19stranded wire on22–24AWG [0.4–0.2mm 2]MTA-100connectors.OnlyPerformance Data*Voltage Rating —250vac Current Rating —5amp max.Low-Level Resistance —6m ⍀max.initialDielectric Withstanding Voltage —750vac/1min.Insulation Resistance —5000M ⍀min.initialOperating Temperature —Ϫ55ЊC to ϩ105ЊCNote:Refer to page 70for approved wire listings.one wire to be terminated into an IDC contact slot.The wire-to-post connector housing material is flame retardant thermoplastic,either UL94V-2or UL94V-0rated.A full line of .100[2.54]centerline headers com-pletes the system.Headers are available with straight or right-angle posts,in flat,polarized or friction lock styles.Headers are avail-able in 2through 28positions.Shrouded headers are available in 2through 14positions.*Refer to the Product Specification for additional electrical,mechanical and environmental performance tests and requirements.Catalog 82056Dimensions are in inches and Dimensions are shown for USA:1-800-522-6752South America:55-11-2103-6000Revised 6-08millimeters unless otherwise reference purposes only.Canada:1-905-470-4425Hong Kong:852-2735-1628specified.Values in brackets Specifications subject Mexico:52-55-1106-0800Japan:are metric equivalents.to change.C.America:57-1-254-4444UK:44-208-420-834112M T A -100.100[2.54]This matrix has been prepared to assist you,our customer,in defining the correct mating halves for the MT A-100header and connector combination.Where a “Y”is indicated the combination is a valid mating pair.Where an “N”is indicated the combination is not acceptable for mating.*Select contact plating to match header plating.HeadersC o n n e c t o r sMatrix for Tin Plated Part NumbersCatalog 82056Dimensions are in inches and Dimensions are shown for USA:1-800-522-6752South America:55-11-2103-6000Revised 6-08millimeters unless otherwise reference purposes only.Canada:1-905-470-4425Hong Kong:852-2735-1628specified.Values in brackets Specifications subject Mexico:52-55-1106-0800Japan:are metric equivalents.to change. C.America:57-1-254-4444UK:44-208-420-834113MTA-100.100[2.54]HeadersC o n n e c t o r sThis matrix has been prepared to assist you,our customer,in defining the correct mating halves for the MT A-100header and connector combination.Where a “Y”is indicated the combination is a valid mating pair.Where an “N”is indicated the combination is not acceptable for mating.Matrix for .000030[0.00076]Gold Plated Part NumbersHeadersC o n n e c t o r sMatrix for .000015[0.00038]Gold Plated Part Numbers*Select contact plating to match header plating.Catalog 82056Dimensions are in inches and Dimensions are shown for USA:1-800-522-6752South America:55-11-2103-6000Revised 6-08millimeters unless otherwise reference purposes only.Canada:1-905-470-4425Hong Kong:852-2735-1628specified.Values in brackets Specifications subject Mexico:52-55-1106-0800Japan:are metric equivalents.to change.C.America:57-1-254-4444UK:44-208-420-834114M T A -100.100[2.54]Material and FinishHousing —UL94V-2rated,nylon,see below for color;or UL94V-0rated,nylon,blackContacts —Phosphor bronze,post tin plated,.000030[0.00076]or .000015[0.00038]post gold-plated over nickelClosed End ConnectorsWithout Polarizing TabsWith Polarizing TabsWithout Polarizing TabsWith Polarizing TabsFeed-Thru ConnectorsColor Coding byWireSize for UL94V-2Connectors28AWG —Green 26AWG —Blue 24AWG —White 22AWG —RedAll wire sizes in UL94V-0—BlackFor mateability options,see matrix on pages 12and 13.For mating half visuals,see pages 20thru 30.Notes:1.Refer to pages 70-74for approved wire listing.2.For strain reliefs and dust covers,see page 16.3.For keying plugs,see page 17.4.Other circuit sizes are available upon request.Minimums may apply.5.Connector circuits can be molded closed for keying purposes.Minimums may apply.6.Where no part numbers appear in the chart,parts can be madeavailable upon request.Minimums may apply.7.T o determine connector overall length (dim.A),multiply .100x the number of circuits.Example:.100x 10circuits equals 1.000inch [25.4mm].Catalog 82056Dimensions are in inches and Dimensions are shown for USA:1-800-522-6752South America:55-11-2103-6000Revised 6-08millimeters unless otherwise reference purposes only.Canada:1-905-470-4425Hong Kong:852-2735-1628specified.Values in brackets Specifications subject Mexico:52-55-1106-0800Japan:are metric equivalents.to change.C.America:57-1-254-4444UK:44-208-420-834115MTA-100.100[2.54]Catalog 82056Dimensions are in inches and Dimensions are shown for USA:1-800-522-6752South America:55-11-2103-6000Revised 6-08millimeters unless otherwise reference purposes only.Canada:1-905-470-4425Hong Kong:852-2735-1628specified.Values in brackets Specifications subject Mexico:52-55-1106-0800Japan:are metric equivalents.to change.C.America:57-1-254-4444UK:44-208-420-834116M T A -100.100[2.54]CoversMaterial (RoHS Compliant)Strain Relief Cover —UL94V-2rated,nylon,whiteDust Covers —UL94V-0rated,polyester,whiteClosed End Strain Relief CoversClosed End Dust Coversmay or may not be present.Cover Ordering InformationThe “Base Part Numbers”Chart at right shows the base part number andnumber of circuits available for the described cover.Prefixes and suffixes are determined by the number of circuit positions in the cover.For example,the complete part number for a 10-position closed end strain relief cover would be:Base number 643075plusprefix-and-suffix1-—-0The correct ordering num-ber is1-643075-0Base Part Numbers6430752–286405502–286430772–286406423-28Cover LengthNo.of Dim.Prefix/Circuits A Suffix 2.200-25.083.300-37.624.400-410.165.500-512.76.600-615.247.700-717.788.800-820.329.900-922.8610 1.001--025.411 1.1001--127.9412 1.2001--230.4813 1.3001--333.0214 1.4001--435.56151.5001--538.116 1.6001--640.6417 1.7001--743.1818 1.8001--845.7219 1.9001--948.2620 2.0002--050.821 2.1002--153.34222.2002--255.88No.of Dim.Prefix/Circuits A Suffix No.of Dim.Prefix/Circuits A Suffix No.of Dim.Prefix/Circuits A Suffix 23 2.3002--358.4224 2.4002--460.9625 2.5002--563.526 2.6002--666.0427 2.7002--768.58282.8002--871.12Catalog 82056Dimensions are in inches and Dimensions are shown for USA:1-800-522-6752South America:55-11-2103-6000Revised 6-08millimeters unless otherwise reference purposes only.Canada:1-905-470-4425Hong Kong:852-2735-1628specified.Values in brackets Specifications subject Mexico:52-55-1106-0800Japan:are metric equivalents.to change.C.America:57-1-254-4444UK:44-208-420-834117MTA-100.100[2.54]Replacement IDC ContactsMaterial and FinishPhosphor bronze,post tin plated;.000030[0.00076]or .000015[0.00038]post gold plated over nickelNote:Tyco Electronics does not rec-ommend terminating an MT A contact more than one e replacement contacts when required for field repairs or wire changes.Crimp Snap-In ContactsMaterial and FinishPhosphor bronze,tin platedSpecial applications for crimp snap-in contacts are:1.Double wire per contact 2.Coax or shielded wire3.Mixed wire size in same connectorNote:Only one crimp snap-in contact per connector..125.038Sq.Ref..070.142[3.61]Keying Plug with Carrier Strip (10plugs per strip)Part No.641994-1Material (RoHS Compliant)UL94V-2rated,nylon,natural colorNote:Removal of contact is not necessary when using keying plug.Catalog 82056Dimensions are in inches and Dimensions are shown for USA:1-800-522-6752South America:55-11-2103-6000Revised 6-08millimeters unless otherwise reference purposes only.Canada:1-905-470-4425Hong Kong:852-2735-1628specified.Values in brackets Specifications subject Mexico:52-55-1106-0800Japan: are metric equivalents.to change.C.America:57-1-254-4444UK:44-208-420-8341。

AR8035_datasheet

COMPANY CONFIDENTIAL • 1Data Sheet© 2011–2012 by Atheros Communications, Inc. All rights reserved. Atheros®, Atheros Driven®, Align®, Atheros XR®, Driving the Wireless Future®, Intellon®, No New Wires®, Orion® , PLC4Trucks®, Powerpacket®, Spread Spectrum Carrier®, SSC®, ROCm®, Super A/G®, Super G®, Super N®, The Air is Cleaner at 5-GHz®, Total 802.11®,U-Nav®, Wake on Wireless®, Wireless Future. Unleashed Now.®, and XSPAN®, are registered by Atheros Communications, Inc. Atheros SST™, Signal-SustainTechnology™, Ethos™, Install N Go™, IQUE™, ROCm™, amp™, Simpli-Fi™, There is Here™, U-Map™, U-Tag™, and 5-UP™ are trademarks of Atheros Communications, Inc. The Atheros logo is a registered trademark of Atheros Communications, Inc. All other trademarks are the property of their respective holders. Subject to change withoutMarch 2012Ver. 2.1AR8035 Integrated 10/100/1000 Mbps Ethernet TransceiverGeneral DescriptionThe AR8035 is part of the Arctic family ofdevices - which includes the AR8031, AR8033, and the AR8035. It is Atheros’ 4th generation, single port 10/100/1000 Mbps Tri-speedEthernet PHY. It supports RGMII interface to the MAC.™The AR8035 provides a low power, low BOM (Bill of Materials) cost solution for comprehensive applications including consumer, enterprise, carrier and home networks such as PC, HDTV , Gamingmachines, Blue-ray players, IPTV STB, Media Players, IP Cameras, NAS, Printers, Digital Photo Frames, MoCA/Homeplug(Powerline)/EoC/ adapters and Home Router & Gateways, etc.The AR8035 integrates Atheros latest Green Ethos ® power saving technologies andsignificantly saves power not only during work time, but also during overtime. Atheros Green Ethos ® power savings include ultra-low power in cable unplugged mode or port power down mode, and automatic optimized power saving based on cable length. Furthermore, theAR8035 supports Wake-on-LAN (WoL) feature to be able to help manage and regulate total system power requirements.The AR8035 embeds CDT (Cable Diagnostics Test) technology on-chip which allowscustomers to measure cable length, detect the cable status, and identify remote and local PHY malfunctions, bad or marginal patch cord segments or connectors. Some of the possible problems that can be detected include opens, shorts, cable impedance mismatch, badconnectors, termination mismatch, and a bad transformer.The AR8035 also integrates a voltage regulator on chip. It reduces the termination R/Ccircuitry on both the MAC interface (RGMII) and line side.The AR8035 supports IEEE 802.3az Energy Efficient Ethernet (EEE) standard and Atheros proprietary SmartEEE, which allows legacy MAC/SoC devices without 802.3az support tofunction as the complete 802.3az system. The key features supported by the device are:n 10BASE-Te PHY supports reduced transmitamplitude.n 100BASE-TX and 1000BASE-T use Low Power Idle (LPI) mode to turn off unused analog and digital blocks to save power while data traffic is in idle.Featuresn 10BASE-Te/100BASE-TX/1000 BASE-T IEEE 802.3 compliantn Supports 1000 BASE-T PCS and auto-negotiation with next page supportnSupports RGMII interface to MAC devices with a broad I/O voltage level options including 2.5V , 1.8V and 1.5V , and is compatible with 3.3V I/On RGMII timing modes support internal delay and external delay on Rx pathnError-free operation up to 140 meters of CAT5 cablen Supports Atheros latest Green Ethos ®power saving modes with internal automatic DSP power saving schemen Supports 802.3az (Energy Efficient Ethernet)nFully integrated digital adaptive equalizers, echo cancellers, and near end crosstalk (NEXT) cancellersnSupports Wake-on-LAN (WoL) to detect magic packet and notify the sleeping system to wake upn A robust Cable Discharge Event (CDE) tolerance of ± 6kVnA robust surge protection with ±750V/differential mode and ±4KV/common moden Jumbo Frame support up to 10KB (full duplex)n All digital baseline wander correction n Automatic channel swap (ACS)n Automatic MDI/MDIX crossover n Automatic polarity correctionn IEEE 802.3u compliant Auto-Negotiation n Software programmable LED modesnMultiple Loopback modes for diagnosticsn Cable Diagnostic Test (CDT)n Single power supply: 3.3Vn5mm x 5mm. 40-pin QFN packageAR8035 Functional Block Diagra m2• AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver Atheros Communications, Inc.March 2012COMPANY CONFIDENTIALAtheros Communications, Inc.AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver • 3COMPANY CONFIDENTIAL November 2011Revision HistoryDateRevsion Details Revision2011/3/15First release1.02011/11/25Electrical Characteristicsn Add a note under Recommended Operation Conditions Topside Markingn Add topside marking illustration2.02012/3/1Electrical Characteristicsn Change MDIO tmdelay minimal value to 0 ns; typical value to 4 ns Ordering informationn Remove AR8035-AL1B industrial tray pack ordering2.14• AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver Atheros Communications, Inc.November 2011COMPANY CONFIDENTIALAtheros Communications, Inc.AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver • 5COMPANY CONFIDENTIAL November 2011Table of ContentsGeneral Description ........................................1Features ............................................................1AR8035 Functional Block Diagram ..............2Revision History .............................................3Table of Contents .. (5)1 Pin Descriptions ............................72 Functional Description (13)2.1 Transmit Functions ................................142.2 Receive Functions . (14)2.2.1 D ecoder Modes ...........................142.2.2 Analog to Digital Converter ......142.2.3 Echo Canceller .............................142.2.4 NEXT Canceller ..........................142.2.5 Baseline Wander Canceller .......142.2.6 Digital Adaptive Equalizer .......142.2.7 Auto-Negotiation ........................152.2.8 Smartspeed Function .................152.2.9 Automatic MDI/MDIX Crossover152.2.10 Polarity Correction .....................152.3 Loopback Modes (15)2.3.1 D igital Loopback .........................152.3.2 External Cable Loopback ...........152.3.3 Remote PHY Loopback ..............162.4 Cable Diagnostic Test ............................162.5 LED Interface ..........................................162.6 Power Supplies .......................................182.7 Management Interface ..........................192.8 Atheros Green Ethos® ..........................202.8.1 Low Power Modes ......................202.8.2 Shorter Cable Power Mode .......202.8.3 Hibernation Mode ......................202.9 IEEE 802.3az and Energy Efficient Ethernet 212.9.1 IEEE 802.3az LPI Mode ..............212.10 Atheros SmartEEE ................................222.11 Wake On LAN (WoL) (22)3 Electrical Ch aracteristics (23)3.1 Absolute Maximum Ratings ................233.2 Recommended Operating Conditions 233.3 RGMII Characteristics ...........................243.4 MD IO Characteristics ............................263.5 XTAL/OSC Characteristics ..................273.6 Power Pin Consumption ......................283.7 Typical Power Consumption Parameters293.8 Power-on Sequence, Reset and Clock .303.8.1 Power-on Sequence ....................303.8.2 Reset and Clock Timing . (30)4 Register Descriptions (31)4.1 Register Summary (31)4.1.1 Control .........................................324.1.2 Status ............................................344.1.3 PHY Identifier [18:3] ..................354.1.4 PHY Identifier [19:24] ................354.1.5 Auto-Negotiation Advertisement354.1.6 Link Partner Ability (Base Page) 374.1.7 Auto-Negotiation Expansion ....384.1.8 Next Page Transmit ....................384.1.9 Link Partner Next Page .............394.1.10 1000 BASE-T Control .................394.1.11 1000 BASE-T Status ....................414.1.12 MMD Access Address Register 424.1.13 MMD Access Control Register .424.1.14 Extended Status ..........................434.1.15 Function Control .........................434.1.16 PHY-Specific Status ....................444.1.17 Interrupt Enable ..........................454.1.18 Interrupt Status ...........................464.1.19 Smart Speed .................................474.1.20 Cable Diagnostic Tester Control 474.1.21 LED Control ................................484.1.22 Cable Defect Tester Status .........494.1.23 Debug Port Address Offset .......494.1.24 Debug Port Data .........................494.2 Debug Register Descriptions (50)4.2.1 RGMII RX Clock Delay Control 504.2.2 RGMII TX Clock Delay Control 504.2.3 Hibernation Control and RGMIIGTX Clock Delay Register .........514.2.4 100BASE-TX Test Mode Select .524.2.5 1000BT external loopbackconfigure (52)4.2.6 Rgmii_mode; Test configuration for10BT (53)4.2.7 MMD3 (MDIO Manageable DeviceAddress 3 for PCS) (53)4.2.8 MMD7 (MDIO Manageable DeviceAddress 7 for Auto-Negotiation) 544.3 MDIO Interface Register (54)4.3.1 PCS Control 1 (54)4.3.2 PCS Status 1 (56)4.3.3 EEE Capability (57)4.3.4 EEE Wake Error Counter (57)4.3.5 Wake-on-Lan loc_mac_addr_o .584.3.6 Wake-on-Lan loc_mac_addr_o .584.3.7 Wake-on-Lan loc_mac_addr_o .584.3.8 Rem_phy_lpkb (59)4.3.9 Smart_eee control1 (59)4.3.10 Smart_eee control2 (59)4.3.11 Smart_eee control3 (60)4.3.12 AN status (61)4.3.13 AN XNP transmit1 (61)4.3.14 AN XNP transmit2 (61)4.3.15 EEE advertisement (62)4.3.16 EEE LP advertisement (62)5 Package Dimensions (63)6 Ordering Information (65)7 Top-side Marking (65)6• AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver Atheros Communications, Inc.November 2011COMPANY CONFIDENTIALAtheros Communications, Inc.AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver • 7COMPANY CONFIDENTIAL November 20111.Pin DescriptionsThis section contains a package pinout for the AR8035 QFN 40 pin and a listing of the signal descriptions (see Figure 1-1).The following nomenclature is used for signal names:The following nomenclature is used for signal types described in Table 1-1:Table 1-1.NC No connection to the internal die is made from this pinn At the end of the signal name, indicates active low signals PAt the end of the signal name, indicates the positive side of a differential signalNAt the end of the signal name indicates he negative side of a differential signalTable 1-2.D Open drain IAAnalog input signal I Digital input signalIHInput signals with weak internal pull-up, to prevent signals from floating when left openILInput signals with weak internal pull-down, to prevent signals from floating when left open I/O A digital bidirectional signal OA An analog output signal O A digital output signal P A power or ground signal PD Internal pull-down for input PUInternal pull-up for input8 • AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver Atheros Communications, Inc.November 2011COMPANY CONFIDENTIALFigure 1-1 shows the pinout diagram for the AR8035.NOTE: There is an exposed ground pad on the back side of the package.Figure 1-1. Pinout DiagramAtheros Communications, Inc.AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver • 9COMPANY CONFIDENTIAL November 2011Table 1-3.GTX_CLK 33I, PD RGMII transmit clock, 125 MHz digital. Adding a 22Ω damping resistor is recommended for EMI design near MAC side.RX_CLK 31I/O, PD 125MHz digital, adding a 22Ω damping resistor is recommended for EMI design near PHY side.RX_DV 30I/O, PD RGMII receive data valid RXD029I/O, PD RGMII received data 0RXD128I/O, PD RGMII received data 1RXD226I/O, PD RGMII received data 2RXD325I/O, PD RGMII received data 3TX_EN 32I, PD RGMII transmit enable TXD034I, PD RGMII transmit data 0 TXD135I, PD RGMII transmit data 1TXD236I, PD RGMII transmit data 2 TXD337I, PDRGMII transmit data 3Management Interface and Interrupt MDC 40I, PUManagement data clock referenceMDIO 39I/O, D, PU Management data, 1.5K Ω pull-up to 3.3V/2.5VINT20I/O, D, PD Interrupt Signal to System; default OD-gate, needs an external10K Ω pull-up, active low; can be configured to I/O by register, active high.LED LED_ACT21I/O, PUParallel LED output for 10/100/1000 BASE-T activity, activeblinking. LED active based upon power-on strapping. If pulled up — active low, if pulled down — active highLED_100022I/O, PUParallel LED output for 1000 BASE-T link, LED active based upon power-on strapping. If pulled up — active low, if pulled down — active high10 • AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver Atheros Communications, Inc.November 2011COMPANY CONFIDENTIALLED_10_10024I/O, PUParallel LED output for 10/100 BASE-T link.LED active based upon power-on strapping of LED_1000. If LED_1000 is pulled up, this pin is active low; If LED_1000 is pulled-down, active high. High, external PU 10 MbpsLow, external PU100 MbpsSystem Signal Group/Reference CLK_25M 23O, PD 25 MHz clock output (default). It can be 125, 62.5 or 50 MHz clock outputRSTn 1I System reset, active low. Requires an external pull-up resistor XTLI 5IA Crystal oscillator input. Requires a 27 pF capacitor to GND.Support external 25 MHz, 1.2V swing clock input through this pin.XTLO 4OA Crystal oscillator output; 27 pF to GND RBIAS 7OAExternal 2.37 k Ω 1% to GND to set bias currentPower LX2OA Power inductor pin. Add an external 4.7 µH power inductor between this pin and pin 38.VDDH_REG 8OA 2.5 V regulator output. A 1uF capacitor connected to this pin VDDIO_REG 27OA 1.5V/1.8V regulator output.If RGMII interface voltage level is 2.5V , connect this pin to pin 8 directly.AVDDL 6, 11, 17P 1.1 V analog power input. Connect to Pin 38 through a bead DVDDL 38P 1.1 V digital core power input. Connect to power inductor and 10uF+0.1uF ceramic capacitors to GND VDD333P 3.3 V power for switching regulatorAVDD3314PAnalog 3.3 V power input for PHY, from VDD33 through a bead --Exposed ground pad on back of the chip, tie to groundTable 1-3.SymbolPinTypeDescriptionNOTE: 0=Pull-down, 1=Pull-upNOTE: Power on strapping pins are latched during power-up reset or warm hardware reset.NOTE: Some MAC devices input pins may drive high/low during power-up or reset. So PHY power on strapping status may be affected by the MAC side. In this case an external 10k Ω pull-down or pull-high resistor is needed to ensure a stable expected status.NOTE: When using 2.5V RGMII I/O voltage level, RX_CLK can be pull-up or pull-down.Table 1-4.PHY PinPHY CoreConfiguration Signal DescriptionDefault Internal Weak Pull-up/Pull-downRXD0PHYADDRESS0LED_ACT, RXD[1:0] sets the lower three bits of the physical address. The upper two bits of the physical address are set to the default, “00”0RXD1PHYADDRESS10LED_ACT PHYADDRESS21RX_DV MODE0mode select bit 00RXD2MODE1mode select bit 10LED_1000MODE2mode select bit 21RXD3MODE3mode select bit 30RX_CLK1.8V/1.5VSelect the RGMII/RMII I/O voltage level 1: 1.8V I/O 0: 1.5V I/OTable 1-5.MODE[3:0]Description1100RGMII, PLLOFF, INT;1110RGMII, PLLON, INT;Others ReservedNOTE: PLLOFF means AR8035 can shut down internal PLL in power saving mode; In PLLOFF mode, when the AR8035 enters power saving mode (hibernation), CLK_25m output drops periodically, which saves more power. In PLLON mode, CLK_25M outputs continuously.2.Functional DescriptionThe AR8035 is Atheros's low cost GbE PHY. It is a highly integrated analog front end (AFE) and digital signal transceiver, providing high performance combined with substantial cost reduction. The AR8035 provides physical layer functions for half/full -duplex 10 BASE-Te, 100 BASE-Tx and 1000 BASE-T Ethernet to transmit and receive high-speed data over standard category 5 (CAT5) unshielded twisted pair cable.The AR8035 10/100/1000 PHY is fully 802.3ab compliant, and supports the reduced GigabitMedia-Independent Interface (RGMII) to connect to a Gigabit-capable MAC.The AR8035 transceiver combines echocanceller, near end cross talk (NEXT) canceller, feed-forward equalizer, joint Viterbi, feedback equalizer, and timing recovery, to enhance signal performance in noisy environments.The AR8035 is a part of the Arctic family of devices — which includes the AR8031, the AR8033, and the AR8035. A comparison of these is shown below.Table 2-1 shows a feature comparison across the AR8031, AR8033, and AR8035 family.NOTE: AR8031, AR8033 is pin-to-pin compatibleNOTE: ** 10BASE-Te, 100BASE-TX, 1000BASE-T will be supported NOTE: *** 100BASE-FX, and 1000BASE-X will be supportedTable 2-1. AR8031, AR8033, AR8035 ComparisonFeatureAR8031AR8033AR8035RGMII yes yes yesSGMII yes yes Cu Ethernet **yes yes yes EEE (802.3az)yes yes yes Wake-on-LAN yes yes yesSERDES/Fiber yes ***yes ***1588v2yes Sync-E yes yes Packaging48-pin48-pin40-pin2.1Transmit FunctionsTable 2-2 describes the transmit function encoder modes.2.2Receive Functions2.2.1Decoder ModesTable 2-3 describes the receive function decoder modes.2.2.2Analog to Digital ConverterThe AR8035 device employs an advanced high speed ADC on each receive channel with high resolution, which results in better SNR and lower error rates.2.2.3Echo CancellerA hybrid circuit is used to transmit and receive simultaneously on each pair. A signal reflects back as an echo if the transmitter is not perfectly matched to the line. Other connector or cable imperfections, such as patch panel discontinuity and variations in cable impedance along the twisted pair cable, also result in drastic SNR degradation on the receive signal. The AR8035 device implements a digital echo canceller to adjust for echo and is adaptive to compensate for the varied channel conditions.2.2.4NEXT CancellerThe 1000 BASE-T physical layer uses all four pairs of wires to transmit data. Because the four twisted pairs are bundled together, significant high frequency crosstalk occurs between adjacent pairs in the bundle. The AR8035 device uses three parallel NEXT cancellers on each receive channel to cancel high frequency crosstalk. The AR8035 cancels NEXT by subtracting an estimate of these signals from the equalizer output.2.2.5Baseline Wander CancellerBaseline wander results from Ethernet links that AC-couple to the transceivers and from AC coupling that cannot maintain voltage levels for longer than a short time. As a result, transmitted pulses are distorted, resulting in erroneous sampled values for affected pulses. Baseline wander is more problematic in the 1000 BASE-T environment than in 100 BASE-TX due to the DC baseline shift in the transmit and receive signals. The AR8035 device uses an advanced baseline wander cancellation circuit that continuously monitors and compensates for this effect, minimizing the impact of DC baseline shift on the overall error rate.2.2.6Digital Adaptive EqualizerThe digital adaptive equalizer removes inter-symbol interference at the receiver. The digital adaptive equalizer takes unequalized signals from ADC output and uses a combination of feedforward equalizer (FFE) and decisionTable 2-2. Encoder ModeEncoder Mode Description1000 BASE-T In 1000 BASE-T mode, the AR8035scrambles transmit data bytesfrom the MAC interfaces to 9-bitsymbols and encodes them into4D five-level PAM signals over thefour pairs of CAT5 cable.100 BASE-TX In 100 BASE-TX mode, 4-bit datafrom the MII is 4B/5B serialized,scrambled, and encoded to athree-level MLT3 sequencetransmitted by the PMA.10 BASE-Te In 10 BASE-Te mode, the AR8035transmits and receivesManchester-encoded data.Table 2-3. Decoder ModeDecoder Mode Description1000 BASE-T In 1000 BASE-T mode, the PMArecovers the 4D PAM signals afteraccounting for the cablingconditions such as skew amongthe four pairs, the pair swap order,and the polarity of the pairs. Theresulting code group is decodedinto 8-bit data values. Data streamdelimeters are translatedappropriately and data is outputto the MAC interfaces.100 BASE-TX In 100 BASE-TX mode, the receivedata stream is recovered anddescrambled to align to thesymbol boundaries. The aligneddata is then parallelized and 5B/4B decoded to 4-bit data. Thisoutput runs to the MII receivedata pins after data streamdelimiters have been translated.10 BASE-Te In 10 BASE-Te mode, therecovered 10 BASE-Te signal isdecoded from Manchester thenaligned.feedback equalizer (DFE) for the best-optimized signal-to-noise (SNR) ratio.2.2.7Auto-NegotiationThe AR8035 device supports 10/100/1000 BASE-T Copper auto-negotiation in accordance with IEEE 802.3 clauses 28 and 40. Auto-negotiation provides a mechanism for transferring information between a pair of link partners to choose the best possible mode of operation in terms of speed, duplex modes, and master/slave preference. Auto-negotiation is initiated upon any of the following scenarios: n Power-up resetn Hardware resetn Software resetn Auto-negotiation restartn Transition from power-down to power-up n The link goes downIf auto-negotiation is disabled, a 10 BASE-Te or 100 BASE-TX can be manually selected using the IEEE MII registers.2.2.8Smartspeed FunctionThe Atheros Smartspeed function is an enhanced feature of auto-negotiation that allows the AR8035 device to fall back in speed based on cabling conditions as well as operate over CAT3 cabling (in 10 BASE-T mode) or two-pair CAT5 cabling (in 100 BASE-TX mode). By default, the Smartspeed feature is enabled. Refer to the register “Smart Speed” on page 47, which describes how to set the parameters. Set these register bits to control the Smartspeed feature:n Bit [5]: 1 = Enables Smartspeed (default)n Bits [4:2]: Sets the number of link attempts before adjustingn Bit [1]: Timer to determine the stable link condition2.2.9Automatic MDI/MDIX Crossover During auto-negotiation, the AR8035 device automatically determines and sets the required MDI configuration, eliminating the need for external crossover cable. If the remote device also implements automatic MDI crossover, the crossover algorithm as described in IEEE 802.3 clause 40.4.4 ensures that only one device performs the required crossover.2.2.10Polarity CorrectionIf cabling has been incorrectly wired, theAR8035 automatically corrects polarity errors on the receive pairs in 1000 BASE-T, 100 BASE-TX and 10 BASE-Te modes.2.3Loopback Modes2.3.1Digital LoopbackDigital loopback provides the ability to loop transmitted data back to the receiver using digital circuitry in the AR8035 device. Figure 2-1 shows a block diagram of a digital loopback.n1000M loopback: write register 0x0 = 0x4140 to enable 1000M digital loopback.n100M loopback: write register 0x0 = 0x6100 to enable 100M digital loopback.n10M loopback: write register 0x0 = 0x4100 to enable 10M digital loopback.2.3.2External Cable LoopbackExternal cable loopback loops Tx to Rx through a complete digital and analog path and an external cable, thus testing all the digital data paths and all the analog circuits. Figure 2-2 shows a block diagram of external cable loopback.1.Plug in an external loopback cable (1-3/2-6/4-7/5-8)2.Write debug register 0xB[15] = 0 to disablehibernate (power-saving mode)3.Write debug register 0x11[0] = 1 to enableexternal loopback4.Select wire speed, as follows:Figure 2-1. Digital LoopbackFigure 2-2. External Cable Loopbackn 1000M loopback: write register 0x0 = 0x8140to set 1000M external loopbackn 100M loopback: write register 0x0 = 0xA100 to set 100M external loopbackn 10M loopback: write register 0x0 = 0x0x8100 to set 10M external loopback5.When the cable in 1000M mode is re-plugged, need to write 0x0 = 0x8140 again to make the PHY link.2.3.3Remote PHY LoopbackThe Remote loopback connects the MDI receive path to the MDI transmit path, near the RGMII interface, thus the remote link partner can detect the connectivity in the resulting loop. Figure 2-3, below, shows the path of the remote loopback.Figure 2-3 shows a block diagram of external cable loopback.n Write MMD3 register 0x805A[0]= 1 toenable remote PHY loopback.Please note : The packets from link partner will still appear at RGMII interface when remote loopback is enabled.Also, remote loopback is independent of PHY auto-negotiation.2.4Cable Diagnostic TestThe Cable Diagnostic Test (CDT) feature in the AR8035 device uses Time DomainReflectometry (TDR) to identify remote and local PHY malfunctions, bad/marginal cable or patch cord segments, or connectors. Some of the possible problems that can be diagnosed include opens, shorts, cable impedance mismatch, bad connectors, terminationmismatch, and bad magnetics. The CDT can be performed when there is no link partner or when the link partner is auto-negotiating.1.Set register 0x16[9:8] to select MDI pair under test2.Write register 0x16[0]=1 to enable CDT3.Check register 0x1C[9:8] for fail status4.Check register 0x1C[7:0] to get delta time. The distance between the fail point and PHY is delta time *0.8422.5LED InterfaceThe LED interface can either be controlled by the PHY or controlled manually, independent of the state of the PHY. Three status LEDs are available. These can be used to indicateoperation speed, duplex mode, and link status. The LEDs can be programmed to different status functions from their default value. They can also be controlled directly from the MII register interface.The reference design schematics for the AR8035’s LEDs are shownFigure 2-4 Reference Design Schematic — Active LowFigure 2-5 Reference Design Schematic — Active HighLED_ACT/LED_1000 active states depend on power on strapping mode.Figure 2-3. Remote PHY LoopbackFigure 2-4. Reference Design Schematic —Active LowFigure 2-5. Reference Design Schematic —Active HighWhen strapped high, active low. When strapped low, active high.LED_10_100 depends on LED_1000 power on strapping mode.So LED_10_100 and LED_1000 should have the same LED design.NOTE: Notes: on = active; off = inactiveTable 2-4. LED StatusSymbol10M Link10M Active100M Link100M Active1000M Link1000M ActiveLED_10_100OFF OFF ON ON OFF OFF LED_1000OFF OFF OFF OFF ON ON LED_ACTONBLINKONBLINKONBLINK2.6Power SuppliesThe AR8035 device requires only one external power supply: 3.3 V .Inside the chip there is a 3.3V rail, 2.5V rail, 1.1V rail and a 1.8V/1.5V rail.AR8035 integrates a switch regulator which converts 3.3V to 1.1V at a high-efficiency for core power rail. (It is optional for an external regulator to provide this core voltage). The AR8035 integrates two on chip LDOswhich can support 2.5V; 1.5V/1.8V RGMII I/Ovoltage. Also with 2.5V RGMII I/O voltage configuration AR8035 can work with a 3.3V MAC RGMII interface — because the input can bear 3.3V logic signal, and the output logic VoH and VoL can satisfy the 3.3V LVCMOS/LVTTL requirement. The parameter details are in the Electrical Characteristics chapter.Reference design for 2.5V RGMII voltage level is shown below:Figure 2-6 shows the AR8035 reference design for a 2.5V RGMII voltage level.Reference design for 1.5/1.8V RGMII voltage level is shown below:Figure 2-6. AR8035 reference design for a 2.5V RGMII voltage level。

0190990008;中文规格书,Datasheet资料

This document was generated on 08/10/2012PLEASE CHECK FOR LATEST PART INFORMATIONPart Number:19099-0008Status:ActiveOverview:Ring Tongue - Spade TerminalsDescription:InsulKrimp™ Snap Spade for 18-22 AWG Wire, Stud Size 5 (M3), Mylar Tape CarrierDocuments:Drawing (PDF)Product Specification PS-19902-011 (PDF)Product Specification PS-19902-009 (PDF)RoHS Certificate of Compliance (PDF)Agency CertificationCSA LR18689ULE32244GeneralProduct Family Ring and Spade Terminals Series19099Crimp Quality Equipment Yes Mil-Spec N/AOverviewRing Tongue - Spade Terminals Product Name InsulKrimp™Type Spade Snap UPC800753088771PhysicalBarrel Type Closed Color - Resin Natural Flammability 94V-0InsulationPVC Material - Plating Mating Tin Net Weight0.578/gPackaging Type Adhesive Tape on Reel Stud Size5 (M3)Wire Insulation Diameter 4.40mm max.Wire Size AWG 18, 20, 22Wire Size mm²0.25 - 1.50Material InfoOld Part NumberAA-2704-05XTReference - Drawing NumbersProduct Specification PS-19902-009, PS-19902-011Sales DrawingAACD20502Seriesimage - Reference onlyEU RoHSChina RoHSELV and RoHS Compliant REACH SVHC Not ReviewedLow-Halogen Status Not ReviewedNeed more information on product environmental compliance?Email productcompliance@For a multiple part number RoHS Certificate of Compliance, click herePlease visit the Contact Us section for any non-product compliance questions.Search Parts in this Series 19099SeriesApplication Tooling | FAQTooling specifications and manuals are found by selecting the products below.Crimp Height Specifications are then contained in the Application Tooling Specification document.GlobalDescription Product #Crimp Dies for MTA-100 Tape Applicator used in 3BF Press, MTA-105Tape Applicator used in TM-2000™ Press,and ATP-301 Air Crimping Press for Mylar Tape Mounted Terminals 0192880023Mini-Mac™Applicator0638851300This document was generated on 08/10/2012PLEASE CHECK FOR LATEST PART INFORMATION分销商库存信息: MOLEX 0190990008。

摩托罗拉半导体数据库第3卷产品目录说明书

MDA920-7
Motorola
Motorola Semiconductor Datasheet Library
/MDA920-7-datasheet.html
MDA920A
Motorola
Semiconductor Data Library Volume 3 /MDA920A-datasheet.html 1974
MDA920A1 N/A
Single-Phase Full-Wave Bridge Rectifier
/MDA920A1-datasheet.html
MDA920A2 Motorola
Single-Phase Full-Wave Bridge Rectifier
/MDA920A8-datasheet.html
MDA920A9 Motorola
Single-Phase Full-Wave Bridge Rectifier
/MDA920A9-datasheet.html
MDA920A7 Motorola
Single-Phase Full-Wave Bridge Rectifier
/MDA920A7-datasheet.html
MDA920A8 Motorola
Single-Phase Full-Wave Bridge Rectifier
/MDA920A5-datasheet.html
MDA920A6 Motorola
Single-Phase Full-Wave Bridge Rectifier
/MDA920A6-datasheet.html
/MDA920A2-datasheet.html
MDA920A3 Motorola

DP80390CPU_03中文资料

DP80390CPU is delivered with fully automated testbench and complete set of tests allowing easy package validation at each stage of SoC design flow.
CPU FEATURES
♦ Technical documentation ◊ Installation notes ◊ HDL core specification ◊ Datasheet
♦ Synthesis scripts ♦ Example application ♦ Technical support
◊ IP Core implementation support ◊ 3 months maintenance
元器件交易网
DP80390CPU
Pipelined High Performance 8-bit Microcontroller ver 3.10
OVERVIEW
DP80390CPU is an ultra high performance, speed optimized soft core of a singlechip 8-bit embedded controller dedicated for operation with fast (typically on-chip) and slow (off-chip) memories. The core has been designed with a special concern about performance to power consumption ratio. This ratio is extended by an advanced power management unit PMU.

ANALOG DEVICES AD8039-EP 数据手册

Low Power, 350 MHzVoltage Feedback AmplifierAD8039-EP Rev. 0Information furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, M A 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.FEATURESLow power: 1 mA quiescent current per amplifierHigh speed−3 dB bandwidth (G = +1): 350 MHzSlew rate: 425 V/μsLow costLow noise8 nV/√Hz at 100 kHz600 fA/√Hz at 100 kHzLow input bias current: 750 nA maximumLow distortion−90 dB SFDR at 1 MHz−65 dB SFDR at 5 MHzWide supply range: 3 V to 12 VSmall packaging: 8-lead SOICSupports defense and aerospace applications (AQEC standard) Extended temperature range: −55°C to +105°CControlled manufacturing baselineOne assembly/test siteOne fabrication siteEnhanced product change notificationQualification data available on request APPLICATIONSBattery-powered instrumentationFiltersADC driversLevel shiftingBufferingPhoto multipliersFUNCTIONAL BLOCK DIAGRAMV OUT1–IN1+IN1–V S+V SV OUT2–IN2+IN2AD8039-EP9557-1Figure 1. 8-Lead SOIC_N–610000.1110100–33691215182124FREQUENCY (MHz)GAIN(dB)9557-2Figure 2. Small Signal Frequency Response for Various Gains,V OUT = 500 mV p-p, V S = ±5 VGENERAL DESCRIPTIONThe AD8039-EP dual amplifier is a high speed (350 MHz) voltage feedback amplifier with an exceptionally low quiescent current of 1.0 mA per amplifier typical (1.5 mA maximum). Despite its low power and low cost, the amplifier provides excellent overall performance. Additionally, it offers a high slew rate of 425 V/μs and a low input offset voltage of 3 mV maximum.The Analog Devices, Inc., proprietary XFCB process allows low noise operation (8 nV/√Hz and 600 fA/√Hz) at extremely low quiescent currents. Given its wide supply voltage range (3 V to 12 V), wide bandwidth, and small packaging, the AD8039-EP amplifier is designed to work in a variety of applications where power and space are at a premium. The AD8039-EP amplifier has a wide input common-mode range of 1 V from either rail and swings to within 1 V of each rail on the output. This amplifier is optimized for driving capacitive loads up to 20 pF. If driving larger capacitive loads, a small series resistor is needed to avoid excessive peaking or overshoot.The AD8039-EP amplifier is available in an 8-lead SOIC package and is rated to work over the extended temperature range of−55°C to +105°C.Additional application and technical information can be found in the AD8038/AD8039 data sheet.AD8039-EPRev. 0 | Page 2 of 8TABLE OF CONTENTSFeatures .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications . (3)Absolute Maximum Ratings ............................................................5 Maximum Power Dissipation ......................................................5 Output Short Circuit .....................................................................5 ESD Caution...................................................................................5 Typical Performance Characteristics ..............................................6 Outline Dimensions ..........................................................................7 Ordering Guide .. (7)REVISION HISTORY2/11—Revision 0: Initial VersionAD8039-EPRev. 0 | Page 3 of 8SPECIFICATIONST A = 25°C, V S = ±5 V , R L = 2 kΩ, gain = +1, unless otherwise noted. Table 1.Parameter Test Conditions/Comments M in Typ M ax UnitDY N AMIC PERFORMA N CE−3 dB Bandwidth G = +1, V OUT = 0.5 V p-p, T MIN to T MAX 300 350 MHz G = +2, V OUT = 0.5 V p-p 175 MHz G = +1, V OUT = 2 V p-p 100 MHz Bandwidth for 0.1 dB Flatness G = +2, V OUT = 0.2 V p-p 45 MHz Slew Rate G = +1, V OUT = 2 V step, R L = 2 kΩ 400 425 V/μs T MIN to T MAX 300 325 V/μs Overdrive Recovery Time G = +2, 1 V overdrive 50 ns Settling Time to 0.1% G = +2, V OUT = 2 V step 18 nsN OISE/HARMO N IC PERFORMA N CESFDR Second Harmonic f C = 1 MHz, V OUT = 2 V p-p, R L = 2 kΩ −90 dBc Third Harmonic f C = 1 MHz, V OUT = 2 V p-p, R L = 2 kΩ −92 dBc Second Harmonic f C = 5 MHz, V OUT = 2 V p-p, R L = 2 kΩ −65 dBc Third Harmonic f C = 5 MHz, V OUT = 2 V p-p, R L = 2 kΩ −70 dBc Crosstalk, Output-to-Output f = 5 MHz, G = +2 −70 dB Input Voltage Noise f = 100 kHz 8 nV/√Hz Input Current Noise f = 100 kHz 600 fA/√Hz DC PERFORMA N CE Input Offset Voltage T A = 25°C 0.5 3 mV T MIN to T MAX 4.5 mV Input Offset Voltage Drift 4.5 μV/°C Input Bias Current T A = 25°C 400 750 nA T MIN to T MAX 2.0 μA Input Bias Current Drift 3 nA/°C Input Offset Current ±25 nA Open-Loop Gain V OUT = ±2.5 V 70 dBI N PUT CHARACTERISTICSInput Resistance 10 MΩ Input Capacitance 2 pF Input Common-Mode Voltage Range R L = 1 kΩ ±4 V Common-Mode Rejection Ratio V CM = ±2.5 V, T A = 25°C 61 67 dB V CM = ±2.5 V, T MIN to T MAX 59 dB OUTPUT CHARACTERISTICS DC Output Voltage Swing R L = 2 kΩ, saturated output ±4 V Capacitive Load Drive 30% overshoot, G = +2 20 pF POWER SUPPLY Operating Range 3 12 V Quiescent Current per Amplifier T A = 25°C 1.0 1.5 mA T MIN to T MAX 2.6 mA Power Supply Rejection Ratio −Supply T A = 25°C 71 77 dB T MIN to T MAX 63 dB+Supply T A = 25°C 64 70 dB T MIN to T MAX 63 dBAD8039-EPRev. 0 | Page 4 of 8T A = 25°C, V S = 5 V , R L = 2 kΩ to V S /2, gain = +1, unless otherwise noted. Table 2.Parameter Test Conditions/Comments Min Typ Max UnitDY N AMIC PERFORMA N CE−3 dB Bandwidth G = +1, V OUT = 0.2 V p-p, T MIN to T MAX 275 300 MHz G = +2, V OUT = 0.2 V p-p 150 MHz G = +1, V OUT = 2 V p-p 30 MHz Bandwidth for 0.1 dB Flatness G = +2, V OUT = 0.2 V p-p 45 MHz Slew Rate G = +1, V OUT = 2 V step, R L = 2 kΩ 340 365 V/μs T MIN to T MAX 275 305 V/μs Overdrive Recovery Time G = +2, 1 V overdrive 50 ns Settling Time to 0.1% G = +2, V OUT = 2 V step 18 ns OISE/HARMO N IC PERFORMA N CE SFDR Second Harmonic f C = 1 MHz, V OUT = 2 V p-p, R L = 2 kΩ −82 dBc Third Harmonic f C = 1 MHz, V OUT = 2 V p-p, R L = 2 kΩ −79 dBc Second Harmonic f C = 5 MHz, V OUT = 2 V p-p, R L = 2 kΩ −60 dBc Third Harmonic f C = 5 MHz, V OUT = 2 V p-p, R L = 2 kΩ −67 dBc Crosstalk, Output-to-Output f = 5 MHz, G = +2 −70 dB Input Voltage Noise f = 100 kHz 8 nV/√Hz Input Current Noise f = 100 kHz 600 fA/√Hz DC PERFORMA N CE Input Offset Voltage T A = 25°C 0.8 3 mV T MIN to T MAX 4.5 mV Input Offset Voltage Drift 3 μV/°C Input Bias Current T A = 25°C 400 750 nA T MIN to T MAX 2.0 μA Input Bias Current Drift 3 nA/°C Input Offset Current ±30 nA Open-Loop Gain V OUT = ±2.5 V 70 dB I PUT CHARACTERISTICS Input Resistance 10 MΩ Input Capacitance 2 pF Input Common-Mode Voltage Range R L = 1 kΩ 1.0 to 4.0 V Common-Mode Rejection Ratio V CM = ±1 V, T A = 25°C 59 65 dB V CM = ±1 V, T MIN to T MAX 59 dB OUTPUT CHARACTERISTICS DC Output Voltage Swing R L = 2 kΩ, saturated output 0.9 to 4.1 V Capacitive Load Drive 30% overshoot, G = +2 20 pF POWER SUPPLY Operating Range 3 12 V Quiescent Current per Amplifier T A = 25°C 0.9 1.5 mA Power Supply Rejection Ratio T MIN to T MAX 65 71 dBAD8039-EPRev. 0 | Page 5 of 8ABSOLUTE MAXIMUM RATINGSTable 3.Parameter Rating Supply Voltage 12.6 V Power Dissipation See Figure 3 Common-Mode Input Voltage ±V S Differential Input Voltage ±4 V Storage Temperature Range −65°C to +125°C Operating Temperature Range −55°C to +105°C Lead Temperature (Soldering, 10 sec) 300°CStresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.MAXIMUM POWER DISSIPATIONThe maximum safe power dissipation in the AD8039-EPpackage is limited by the associated rise in junction temperature (T J ) on the die. The plastic encapsulating the die locally reaches the junction temperature. At approximately 150°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8039-EP . Exceeding a junction temperature of 175°C for an extended time can result in changes in the silicon devices, potentially causing failure.The still-air thermal properties of the package and PCB (θJA ), ambient temperature (T A ), and total power dissipated in the package (P D ) determine the junction temperature of the die. The junction temperature can be calculated asT J = T A + (P D × θJA )The power dissipated in the package (P D ) is the sum of the quies-cent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (V S ) multiplied by the quiescent current (I S ). Assuming the load (R L ) is referenced to midsupply, the total drive power is V S /2 × I OUT , some of which is dissipated in the package and some in the load (V OUT × I OUT ). The difference between the total drive power and the load power is the drive power dissipated in the package.P D = quiescent power + (total drive power − load power ) P D = [V S × I S ] + [(V S /2) × (V OUT /R L )] − [V OUT 2/R L ] AMBIENT TEMPERATURE (°C)0–55M A X I M U M P O W E R D I S S I P A T I O N (W )1.0–2553565951251.52.00.509557-0038-LEAD SOIC_NFigure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer BoardRMS output voltages should be considered. If R L is referenced to −V S , as in single-supply operation, then the total drive power is V S × I OUT . If the rms signal levels are indeterminate, consider the worst case, when V OUT = V S /4 for R L to midsupply.P D = (V S × I S ) + (V S /4)2/R LIn single-supply operation with R L referenced to −V S , worst case is V OUT = V S /2.Airflow increases heat dissipation, effectively reducing θJA . In addition, more metal directly in contact with the package leads from metal traces, throughholes, ground, and power planes reduces θJA .Figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 8-lead SOIC_N (125°C/W) on a JEDEC standard 4-layer board. θJA values are approximations.OUTPUT SHORT CIRCUITShorting the output to ground or drawing excessive current from the AD8039-EP will likely cause a catastrophic failure.ESD CAUTIONAD8039-EPRev. 0 | Page 6 of 8TYPICAL PERFORMANCE CHARACTERISTICSV S = ±5 V , C L = 5 pF, R G = R F = 1 kΩ, R L = 2 kΩ, frequency = 1 MHz, T A = −55°C to +105°C, unless otherwise noted.FREQUENCY (MHz)G A I N (d B )–1.0–1.51.00.51.52.00–0.5–2.0–2.5–3.00.1110100100009557-004Figure 4. Small Signal Frequency Response vs. Temperature,Gain = +1, V S = ±5 V, V OUT = 500 mV p-p FREQUENCY (MHz)G A I N (d B )–369123–60.1110100100009557-005Figure 5. Large Signal Frequency Response vs. Temperature,Gain = +2, V S = ±5 V, V OUT = 2 V p-pAD8039-EPRev. 0 | Page 7 of 8CONTROLLING DIMENSIONS ARE IN MILLIMETERS;INCH DIMENSIONS (IN PARENTHESES)ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.COMPLIANT TO JEDEC STANDARDS MS-012-AA012407-AOUTLINE DIMENSIONS0.17(0.0067)0.40(0.0157)0.25(0.0098)0.10(0.0040)COPLANARITY0.10Figure 6. 8-Lead Standard Small Outline Package [SOIC_N]Narrow Body(R-8)Dimensions shown in millimeters and (inches)ORDERING GUIDEModel 1Temperature Range Package DescriptionPackage Option AD8039SRZ-EPR7−55°C to +105°C 8-Lead Standard Small Outline Package [SOIC_N] R-81Z = RoHS Compliant Part.AD8039-EPRev. 0 | Page 8 of 8NOTES©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.D09557-0-2/11(0)。

Agilent U8903A Data Sheet说明书

Agilent U8903A Audio AnalyzerMake an Audible DifferenceData SheetStep up from the HP 8903BThe U8903A is the next-generation replacement for the widely used HP 8903B audio analyzer. Application note ‘Migrating Code from the 8903B to U8903A (5990-4135EN)’ provides compatible equivalent commands, and sample test programs comparing the old R2D2 codes with new U8903A SCPI commands’.Whether listening to mono, stereo or surround, the human ear knows what sounds good.Measuring “how good,” however, can be a challenge. The Agilent U8903A audio analyzer helps you measure and quantify audio performance in applications such as wireless audio, analog components and ICs, and consumer audio.Across the audio spectrum and beyond, this scalable, single-unit solution provides versatile measurement functions, diverse test signals and powerful analysis capabilities. Whatever your application, the U8903A can help you make an audible difference in device performance.CapabilitiesSelect generator, analyzer, graph and sweep modes with one-button access Measure at DC and from 10 Hz to 100 kHzCharacterize signal-to-noise ratio, SINAD, IMD, DFD, THD+N ratio, THD+N level, crosstalk, and more Apply weighting functions, standard filters and custom filtersStimulate your device with high-quality signals and arbitrary waveforms View numerical and graphical displays of measurement resultsConnect to a PC through GPIB, LAN/ LXI - C and USB interfacesThe U8903A audio analyzer combines the functionality of a distortion meter, SINAD meter, frequency counter, AC voltmeter, DC voltmeter and FFT analyzer with a low-distortion audio source. On the bench or in a test system, its accuracy and versatility will help you make an audible difference in your end product.Measure and analyze essential audio parametersWith the U8903A, you can measure below, across and above the audio spectrum with its 10 Hz to 100 kHz frequency range and built-in DC measurements. Its dual input channels let you perform stereo audio, frequency response, wireless and component tests—all at a single-channel price.Easily characterize parameters such as signal-to-noise ratio, SINAD, intermodulation distortion (IMD), different-frequency distortion (DFD), total harmonic distortion (THD+N ratio, THD+N level), crosstalk and more. Additional measurement capabilities include AC level, DC level, frequency count and frequency spectrum (through FFT analysis; see Figure 1).For all measurements, you can apply weighting functions as well as low-pass, high-pass and standard filters (Figure 2). You can also create custom filters using MATLAB® and other applications and upload them through the analyzer’s USB port. Filters and weighting functions can be applied one, two or three at a time.Generate high-quality test signalsThe built-in, dual-channel signal generator lets you stimulate your device with a variety of high-quality signals: sine (–105 dB noise floor), square, rectangular, noise (Gaussian and rectangular), two-tone and multi-tone (up to 60) (Figure 3). To simulate complex and real-world signals, you can also create arbitrary waveforms with up to 16,384 points and a 321.5 kHz sampling rate.The output voltage range is 0 V to 8 Vrms with 1% accuracy. For unbalanced connections, you can select 50 W or 600 W output impedance.Figure 1:Perform FFT analysis with up to 32 Kpointsand a wide selection of informative graphingfunctions.Figure 2:Apply an extensive selection of filters,including a variety of weighting functions.Figure 3:Utilize high-quality test signals that provide low distortion and low noise level.Easily perform manual and automated testsOne-button access makes it easy to select the four main operating modes: analyzer, generator, graph and sweep. The 5.7-inch color display provides numeric readouts as well as graphical views of analog sweeps, FFT spectra and more.For PC-based control on the bench or in a test system, the U8903A includes GPIB, LAN/ LXI – C and and USB interfaces. If your system currently uses an HP 8903B audio analyzer, the application note ‘Migrating Code from the 8903B to U8903A (5990-4135EN)’ describes compatible equivalent commands, andprovides sample test programs comparing the old R2D2 codes with new U8903A SCPI commands’.Figure 4: The new U8903A audio analyzer offers numerous improvements over the widely used HP 8903B.Replace your 8903B and add next-generation capabilitiesFor nearly two decades, the HP 8903B provided unparalleled versatility and performance in audio applications. Today, the U8903A audio analyzer builds on the legacy of the 8903B by offering faster single-point measurements (0.4 sec vs. 3.0 sec) as well as a wider frequency range, expanded performance and greater functionality (Tables 1, 2 and 3). Because the U8903A is based on the latest digital technologies, we also predict greaterinstrument uptime on the bench and in test systems.With the U8903A, you can configuremeasurements faster through its graphical user interface (GUI) and one-button selection of major operating modes. The color screen lets you view dual-parameter displays from one or two channels as well as graphical displays of sweeps, frequency spectra andmore (Figure 4).Frequency range Frequency accuracyU8903ADC and 10 Hz to 100 kHz 5 ppm (0.0005%)HP 8903B20 Hz to 100 kHz 0.004%Table 1: Comparison of frequency range and accuracyAC voltage input range AC accuracyDC voltage input range DC accuracyU8903A0 V to 140 Vrms ± 1%0 to ± 200 V ± 1%HP 8903B0.3 mVrms to 300 Vrms ± 4%4 V to 300 V ± 1%Table 2: Comparison of accuracy and ranges in AC and DC level measurementsFrequency range Residual THD+N (signal distortion)at 80 kHz BWU8903A10 Hz to 100 kHz~ –101 dB (at 1 kHz, 1 Vrms), 20 Hz to 20 kHz HP 8903B20 Hz to 100 kHz –80 dB (or 15 μV), 20 Hz to 20 kHzTable 3: Comparison of range and residual THD+N measurementsTake a closer lookPlug-and-play USB 2.0 connectivityFront panel5.7-inch color displayOne-button access to analyzer, generator and sweep modesQuick buttons for graphical analysis Front-panel output on/offbutton for DUT protectionSoftkeys for easy function selectionDual-channel generator outputs and analyzer inputs with XLR connectorsRear panelGPIB, LAN/ LXI – C and USB interfacesUpgraded rear panelTwo DB-25 connectors for multi-channel connections Six additional input and output channelsDB-25-to-XLR cableThe next release of the U8903A will include multi-channel measurement capabilities designed for the testing of consumer audio products. Total channel count will expand from two to eight with the additional six inputs and outputs accessible through the rear panel of the instrument. For the latest information, please visit /find/audioanalyzer.Address challenging audio applicationsGeneral audio testingThe U8903A provides essential measurement capabilities that enable efficient analysis of audio amplifiers and other devices in the audio chain. For example, the analyzer includes balanced and unbalanced outputs and inputs. It also provides a wide selection of filters and enhances your flexibility by making it easy to upload customized filters. With an array of sweep functions and flexible data display formats for each measurement, you’ll be ready to address a wide range of challenging audio applications.Balanced inputsIn the quest for higher output power, many audio amplifiers use bridged output stages. Such amplifiers can be difficult to characterize because their outputs cannot be grounded. To test these devices, the usual approach has been to use a balanced, calibrated isolation transformer connected to an analyzer with an unbalanced input.The widely used HP 8903B eliminated the need for a transformer, but it was still necessary to float the analyzer input before connecting the bridged device and making measurements. With Agilent U8903A, you simply make a balanced connection with an XLR connector and make measurements—no floating required.Standard and custom filtersA selection of built-in filters simplifies audio measurements by providing weighting networks required by international standards. These include CCIR, CCIR/ARM and CCIT weighting filters; a C message filter; and an ANSI “A” weighting filter. In addition to the standard filters, you can create custom filters using applications such as MATLAB or Agilent VEE and upload the filters through the analyzer’s USB port. The U8903A also includes selectable 15 kHz, 20 kHz and 30 kHz low-pass filters to reject unwanted out-of-band signals and noise.Display scaling and formattingU8903A gives you flexible control over data displays. For example, you can choose volts, millivolts, dBm into 600 ohms (or other resistance values), or watts for AC level measurements, and select percent or dB for distortion measurements.Amplifier testingGenerator outputAudio amplifier AnalyzerinputFigure 5: Use a single button to access the swept measurement mode.Swept measurementsWith its internal audio source and precise digital control, the U8903A can perform automatic swept measurements of frequency response, distortion and signal-to-noise. For example, to check the frequency response of an active filter, only a few steps are required. After connecting the deviceand setting the required source level, simply enter the start and stop frequencies, and then press the “Sweep” key (Figure 5).Transmitter and receiver testingThe U8903A includes several measurement features that simplify the testing of the transceivers used in devices such as car radios, telephones, mobile radios, broadcast radios, FM tuners and television. The U8903A can handle all of these applications when combined with a modulating signal generator for receiver testing and a signal analyzer for transmitter testing (see diagrams).Receiver testingGenerator outputModulated signalSignal generatorTwo-way radioAnalyzer inputTrue-RMS detectionTo accurately characterize signals with high noise content, true-RMS detection is required. The U8903A employs true-RMS detection for all signals with crest factor less than three. In addition, quasi-peak detection (CCIR 468-4) and peak-to-peak detection are also available through softkey selections.Built-in filtersThe U8903A includes a variety of essential filters for transmitter and receiver testing. Its CCITT, CCIR, and C-message weighting filters meet international standards for receiver testing. For transmitter testing, the seven-pole 400 Hz high-pass filter provides better than 40 dB rejection of signals up to 250 Hz, letting you measure transmitter audio distortion to 1% without disabling squelch signals.For even greater flexibility, you can apply custom filters created using applications such as MATLAB and Agilent VEE. Once you’ve uploaded a filter via the U8903A’s USB port, it can be applied to your measurements through a softkey selection. In all, you can apply up to three filters at a time.SINAD measurementsCommonly used to test FM receivers, SINAD measurements must be made repeatedly when checking receiver sensitivity or adjacent-channel selectivity. To smooth out the typically noisy signals that are present during receiver testing, the analyzer’s SINAD mode employs extra filtering circuits. These have been optimized for high speed and excellentrepeatability: The U8903A provides distortion and SINAD measurements with an acquisition time of less than 1.5 seconds and ameasurement rate of greater than two reading per second after locking.Signal-to-noise ratioTo characterize signal quality in AM receivers, the U8903A can automatically make the necessary signal-to-noise ratio measurements. It does this by monitoring the incoming AC signal level while turning its low-distortion source on and off.Transmitter testingModulated signalSpectrum analyzerTwo-way radioCharacteristicsPower Consumption250 VAPower Requirements• 100 V ac to 240 V ac• 47 Hz to 63 HzOperating Environment• Operating temperature from 0 °C to 55 °C• Relative humidity at 30% to 80% RH (noncondensing)• Altitude up to 3000 m• Pollution Degree 2• Installation Category IIStorage Compliance–55 °C to 75 °CSafety ComplianceCertified with:• IEC 61010-1:2001/EN61010-1:2001 (2nd Edition)• Canada: CAN/CSA-C22.2 No. 61010-1-04• USA: Ansi/Ul 61010-1:2004Emc Compliance• IEC 61326-1:2005/EN 61326-1:2006• Canada: ICES-001:2004• Australia/New Zealand: AS/NZS CISPR11:2004Dimensions (W x D x H)426.80 x 405.00 x 141.35 mmWeight< 8.5 kg (without cards)WarrantyOne year for U8903AThree months for standard-shipped accessories (see page 13)SpecificationsThe following specifications are based on performance with a 30 minutes warm-up time and at a temperature from 0 °C to 55 °C unless stated otherwise.Audio generatorGenerated waveformSine, Dual Sine, And Variable Phase FrequencyRangeAccuracyResolutionOutputRange (Balanced)Range (Unbalanced/Common) Amplitude accuracyAmplitude resolution Sine, Dual sine, Variable Phase, Square, Noise (Gaussian and Rectangular), Arbitrary, DC, Multitone, SMPTE IMD (1:1, 4:1, and 10:1), DFD (IEC 60118/IEC 60268)5 Hz to 80 kHz5 ppm0.1 Hz0 V to 16 V rms0 V to 8 V rms± 1%1 μV rms (limited to five digits of resolution)± 0.01 dB ± 0.1 dB~ –95 dB (at 23 °C ± 5°C)0 V to 7.2 V rms (Gaussian), 0 V to 13.16 V rms (Rectangular)0 V to 3.6 V rms (Gaussian), 0 V to 6.58 V rms (Rectangular)–22.6 V to 22.6 V –11.3 V to 11.3 V ± 1.5%Flatness20 Hz to 20 kHz 5 Hz to 80 kHzTHD + N at 1 kHz, 1 V rms , Range (Balanced)Range (Unbalanced/Common)DC OutputRange (Balanced)Range (Unbalanced/Common)Amplitude accuracy~ –101 dB (at 23 °C ± 5 °C)~ –99 dB (from 0 °C to 55 °C)~ –85 dBDC Offset20 Hz to 20 kHz 20 kHz to 80 kHz Audio analyzerXLR BNC DC, AC30 kHz 100 kHz400 mV to 140 V rms < 1 μV [1] to 140 Vrms200 Vp for altitude up to 3000 m 200 k W 100 k W± 0.01 dB [2] (at 23 °C ± 5 °C) ± 0.012 dB [3] (from 0 °C to 55 °C)± 0.1 dB (at 23 °C ± 5°C)± 0.15 dB (from 0 °C to 55 °C)~ –101 dB¡ 70 dB [4] ¡ 40 dB[4]~ –101 dBOverload protection for all ranges, onscreen warning message on the front panelInput Characteristics Connection type Balanced Unbalanced CouplingMeasurement bandwidth Low HighInput rangesMeasurement range Maximum rated input Impedance Balanced Unbalanced Flatness20 Hz to 20 kHz 20 kHz to 100 kHzTHD + N at 1 kHz, 1 V rms , 20 Hz to 20 kHz bandwidth CMRR~ 20 kHz (input range ~ 6.4 V)~ 20 kHz (input range > 6.4 V)Crosstalk20 Hz to 20 kHz Input protection[1] Defined by 24-bit measurement.[2] ± 0.01 dB – 0.001 dB/Hz below 50 Hz.[3] ± 0.012 dB – 0.001 dB/Hz below 50 Hz.[4] When AC coupled, CMRR will deteriorate at low frequencies.0.01 °~ 0.0025% (–92 dB)Triggering Resolution SMPTE IMD Residual IMDGraph mode256, 512, 1024, 2048, 4096, 8192, 16384, 32768Rectangular, Hann, Hamming, Blackman-Harris, Rife-Vincent 1 and 3, Flattop ± 0.1 dB (± 1.2%)Normal, Interpolate, Peak, Absolute Value Displays highest FFT bin between graph pointsSize/Acquisition length WindowAmplitude accuracy (Flattop window)Display mode Time domainFrequency domainAudio filters• 15 kHz low pass • 20 kHz low pass • 30 kHz low pass• User-defined [1]• 20 Hz high pass • 100 Hz high pass • 400 Hz high pass• User-defined[1]• A-Weighting (ANSI-IEC “A” weighted, per IEC Rec 179)• CCIR 1K weighted (CCIR Rec. 468)• CCIR 2K weighted (Dolby 2K)• C-Message (C-Message per IEEE 743)• CCITT (ITU-T Rec. O.41, ITU-T Rec. P.53)• User-defined[1]Low pass filterHigh pass filterWeighting filter[1] User-defined filters can be uploaded through standard I/O connections.Sweep capabilityFrequency Sweep (Sine And Dual Sine Waveforms)[1] This range is applicable for sine wave only.Ordering InformationModel Number U8903A – 200Description2-channel audio analyzerStandard-shipped accessoriesLAN and USB cables, power cord, ProductReference CD-ROM (contains U8903A QuickStart Guide and User Guide), Quick Start Guide,1GB USB Flash Memory device and Certificateof Calibration.Optional accessoriesU8903A - 101Male BNC to Male BNC cable;1.2 mU8903A - 102Male BNC to Male RCA cable; 2mU8903A - 103Male XLR to Female XLR cable; 2mU8903A - 908Rack mount kit – standard 3UU8903A – ABJJapanese User Guide (hardcopy)/find/emailupdates Get the latest information on the products and applications you select.Agilent Email UpdatesRemove all doubtOur repair and calibration services will get your equipment back to you,p e r f o r m i n g l i k e n e w, w h e n promised. You will get full value outof your A gilent equipment through-out its lifetime. Your equipmentwill be serviced by A gilent-trainedtechnicians using the latest factorycalibration procedures, automated repair diagnostics and genuine parts. You will always have the utmost confidence in your measurements. For information regarding self maintenance of this product, please contact your Agilent office.Agilent offers a wide range of additional expert test and measurement services for your equipment, including initial start-up assistance onsite educationand training, as well as design, systemintegration, and project management.For more information on repair andcalibration services, go to:/find/removealldoubt For more information on AgilentTechnologies’ products, applications or services, please contact your local Agilent office. The complete list is available at:/find/contactusAmericas Canada Latin America United States (877) 894 4414305 269 7500(800) 829 4444Asia Pacific Australia China Hong Kong India Japan Korea Malaysia Singapore Taiwan Thailand 1 800 629 485800 810 0189800 938 6931 800 112 9290120 (421) 345080 769 08001 800 888 848180****81000800 047 8661 800 226 /find/audioanalyzerEurope & Middle East Austria BelgiumDenmark Finland FranceGermany Ireland Israel Italy Netherlands Spain Sweden SwitzerlandUnited Kingdom Other European Countries:/find/contactus43(0)136****157132 (0) 2 404 93 4045 70 13 15 15358 (0) 10 855 21000825 010 700**0.125/minute49 (0) 7031 464 63331890 924 204972-3-9288-504/54439 02 92 60 848431 (0) 20 547 211134 (91) 631 33000200-88 22 550800 80 53 5344 (0) 118 9276201Revised: October 1, 2009© Agilent Technologies, Inc. 2009Printed in USA, December 4, 20095990-3831ENProduct specifications and descriptions in this document subject to change without notice.LXI is the LAN-based successor to GPIB, providing faster, more efficient connectivity. Agilent is a founding member of the LXI consortium./find/channelpartners Get the best of both worlds: Agilent’s measurement expertise and product breadth, combined with channelpartner convenience.Agilent Channel Partners。

MB90803资料

元器件交易网
FUJITSU SEMICONDUCTOR DATA SHEET
16-bit Proprietary Microcontroller
CMOS
R
MB90800 Series
MB90803/F804/V800
s DESCRIPTION
The MB90800 series is a general-purpose 16-bit microcontroller that has been developed for high-speed realtime processing required for industrial and office automation equipment and process control, etc. The LCD controller of 48 segment four common is built into. Instruction set has taken over the same AT architecture as in the F2MC*-8L and F2MC 16L, and is further enhanced to support high level languages, extend addressing mode, enhanced divide/multiply instructions with sign and enrichment of bit processing. In addition, long word processing is now available by introducing a 32-bit accumulator. * : F2MC, an abbreviation for FUJITSU Flexible Microcontroller, is a registered trademark of FUJITSU Ltd.

Cree MSC030SDA070K 零恢复硅玻璃晶体管说明书

MSC030SDA070KDatasheet Zero Recovery Silicon Carbide Schottky DiodeFinalApril 2018Contents1Revision History (1)1.1Revision A (1)2Product Overview (2)2.1Features (2)2.2Benefits (2)2.3Applications (2)3Electrical Specifications (3)3.1Absolute Maximum Ratings (3)3.2Electrical Performance (4)3.3Performance Curves (5)4Package Specification (7)4.1Package Outline Drawing (7)1Revision HistoryThe revision history describes the changes that were implemented in the document. The changes arelisted by revision, starting with the most current publication.1.1Revision ARevision A was published in April 2018. It is the first publication of this document.2Product OverviewThis section shows the product overview for the MSC030SDA070K device.2.1FeaturesThe following are key features of the MSC030SDA070K device:Ultra-fast recovery timesSoft recovery characteristicsLow forward voltageLow leakage currentAvalanche energy ratedRoHS compliant2.2BenefitsThe following are benefits of the MSC030SDA070K device:High switching frequencyLow switching lossesLow noise (EMI) switchingHigher reliability systemsIncreased system power density2.3ApplicationsThe MSC030SDA070K device is designed for the following applications: Power Factor Correction (PFC)Anti-parallel diodeSwitch-mode power supplyInverters/convertersMotor controllersFreewheeling diodeSwitch-mode power supplyInverters/convertersSnubber/clamp diode3Electrical SpecificationsThis section shows the electrical specifications for the MSC030SDA070K device.3.1Absolute Maximum RatingsThe following table shows the absolute maximum ratings for the MSC030SDA070K device.All ratings: T= 25 °C unless otherwise specified.CTable 1 • Absolute Maximum RatingsSymbol Parameter Ratings UnitV R Maximum DC reverse voltage700VV RRM Maximum peak repetitive reverse voltage700V RWM Maximum working peak reverse voltage70056AI F Maximum DC forward current(T = 25 °C)C24Maximum DC forward current(T = 135 °C)CMaximum DC forward current19(T = 145 °C)C79I FRM Repetitive peak forward surge current(T = 25 °C, t = 8.3 ms, half sine wave)C pI FSM Non-repetitive forward surge current146(T= 25 °C, t = 8.3 ms, half sine wave)C pP tot Power dissipation167W(T = 25 °C)C72Power dissipation(T = 110 °C)CT , TJ STG Operating junction and storage temperature range–55 to 175°CT L Lead temperature for 10 seconds300100mJE AS Single pulse avalanche energy(starting T = 25 °C, L = 0.22 mH, peak I = 30 A)J LThe following table shows the thermal and mechanical characteristics of the MSC030SDA070K device.Table 2 • Thermal and Mechanical CharacteristicsSymbol Characteristic Typ Max UnitRθJC Junction-to-case thermal resistance0.620.9°C/WW T Package weight0.07oz1.9gTorque Maximum mounting torque10lbf-in1.1N-mThe following table shows the static characteristics of the MSC030SDA070K device.Table 3 • Static CharacteristicsSymbol Characteristic Test Conditions Typ Max UnitV F Forward voltage I = 30 A, T = 25 °CF J 1.5 1.8VI = 30 A, T = 175 °CF J 1.75I RM Reverse leakage current V = 700 V, T = 25 °CR J1200μAV = 700 V, T = 175 °CR J10Q C Total capacitive charge V = 400 V, T = 25 °CR J83nCC J Junction capacitance V = 1 V, T = 25 °C, ƒ = 1 MHzR J1200pFV = 200 V, T = 25 °C, ƒ = 1 MHzR J150V = 400 V, T = 25 °C, ƒ = 1 MHzR J128This section shows the typical performance curves for the MSC030SDA070K device.Figure 1 • Maximum Transient Thermal ImpedanceFigure 2 • Forward Current vs. Forward Voltage Figure 3 • Max. Forward Current vs. Case Temp.Figure 4 • Max. Power Dissipation vs. Case Temp.Figure 5 • Reverse Current vs. Reverse VoltageFigure 4 • Max. Power Dissipation vs. Case Temp.Figure 5 • Reverse Current vs. Reverse VoltageFigure 6 • Total Capacitive Charge vs. Reverse Voltage Figure 7 • Junction Capacitance vs. Reverse Voltage4Package SpecificationThis section outlines the package specification for the MSC030SDA070K device.4.1Package Outline DrawingThis section details the TO-220 package drawing of the MSC030SDA070K device. Dimensions are inmillimeters and (inches).Figure 8 • Package Outline DrawingMicrosemi Corporate HeadquartersOne Enterprise, Aliso Viejo,CA 92656 USAWithin the USA: +1 (800) 713-4113Outside the USA: +1 (949) 380-6100Fax: +1 (949) 215-4996Email:***************************© 2018 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided "as is, where is" and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice.Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing devices; RF solutions; discrete components; enterprise storage and communication solutions; security technologies and scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, California, and has approximately 4,800 employees globally. Learn more at .053-4084。

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♦ Technical documentation ◊ Installation notes ◊ HDL core specification ◊ Datasheet
♦ Synthesis scripts ♦ Example application ♦ Technical support
◊ IP Core implementation support ◊ 3 months maintenance
● Fully synthesizable, static synchronous design with positive edge clocking and no internal tri-states
● Scan test ready
● 2.0 GHz virtual clock frequency in a 0.25u technological process
•
Internal type
Program
Memory
- synchronous - asynchronous
•
Internal Program Memory size
ROM
-
0 - 64kB
•
Internal Program Memory size
RAM
-
0 - 64kB
•
Internal Program fixed size
○ Unlimited number of software watch-points
Internal (direct) Data Memory Special Function Registers (SFRs) External Data Memory
○ Unlimited number of software breakpoints
Memory
பைடு நூலகம்
- true - false
• Interrupts
-
subroutines location
• Power Management Mode
- used - unused
• Stop mode
- used - unused
• DoCD™ debug unit
- used - unused
● 24 times faster multiplication
● 12 times faster addition
● Up to 256 bytes of internal (on-chip) Data Memory
● Up to 8M bytes of linear Program Memory ○ 64 kB of internal (on-chip) Program Memory ○ 8 MB external (off-chip) Program Memory
● De-multiplexed Address/Data bus to allow easy connection to memory
● Dedicated signal for Program Memory writes.
All trademarks mentioned in this document are trademarks of their respective owners.
DP80390CPU
Pipelined High Performance 8-bit Microcontroller ver 4.02
OVERVIEW
DP80390CPU is an ultra high performance, speed optimized soft core of a singlechip 8-bit embedded controller dedicated for operation with fast (typically on-chip) and slow (off-chip) memories. It supports up to 8 MB of linear code and 16 MB of linear data spaces. The core has been designed with a special concern about performance to power consumption ratio. This ratio is extended by an advanced power management unit PMU.
DP80390CPU is delivered with fully automated testbench and complete set of tests allowing easy package validation at each stage of SoC design flow.
CPU FEATURES
PERIPHERALS
● DoCD™ debug unit ○ Processor execution control
Run Halt Step into instruction Skip instruction
○ Read-write all processor contents
Program Counter (PC) Program Memory Internal (direct) Data Memory Special Function Registers (SFRs) External Data Memory
● 100% software compatible with industry standard 80390 & 8051 ○ LARGE mode – 8051 instruction set ○ FLAT mode – 80390 instruction set
● Pipelined RISC architecture enables to execute instructions 10 times faster compared to standard 8051
○ Hardware watch-points activated at a certain
address by any write into memory address by any read from memory address by write into memory a required data address by read from memory a required data
● Interrupt Controller ○ 2 priority levels ○ 2 external interrupt sources
All trademarks mentioned in this document are trademarks of their respective owners.
CONFIGURATION
The following parameters of the DP80390CPU core can be easy adjusted to requirements of dedicated application and technology. Configuration of the core can be prepared by effortless changing appropriate constants in package file. There is no need to change any parts of the code.
● Up to 16M bytes of external (off-chip) Data Memory
● User programmable Program Memory Wait States solution for wide range of memories speed
● User programmable External Data Memory Wait States solution for wide range of memories speed
Program Memory(PC)
○ Automatic adjustment of debug data transfer speed rate between HAD and Silicon
○ JTAG Communication interface
● Power Management Unit ○ Power management mode ○ Switchback feature ○ Stop mode
○ Code execution breakpoints
one real-time PC breakpoint unlimited number of real-time OPCODE breakpoints
○ Hardware execution watch-point
one at Internal (direct) Data Memory one at Special Function Registers (SFRs) one at External Data Memory
DP80390CPU soft core is 100% binarycompatible with the industry standard 80390 & 8051 8-bit microcontroller. There are two configurations of DP80390CPU: Harward where internal data and program buses are separated, and von Neumann with common program and external data bus. DP80390CPU has Pipelined RISC architecture 10 times faster compared to standard architecture and executes 85-200 million instructions per second. This performance can also be exploited to great advantage in low power applications where the core can be clocked over ten times more slowly than the original implementation for no performance penalty.