睿智FPGA开发板用户手册1.5版本最新
晶珩 睿莓 1 用户手册说明书
睿莓1 (REIMEI1) 一款性能优异且极具性价比的单板计算机上海晶珩电子科技有限公司2023-03-18版权声明睿莓1 (REIEMI1) 及其相关知识产权为上海晶珩电子科技有限公司所有。
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目录1产品概述 (6)1.1目标应用 (6)1.2规格参数 (6)1.2.1硬件 (6)1.2.2软件 (7)1.3功能布局 (7)1.4包装清单 (8)1.5订购编码 (9)2快速启动 (9)2.1设备清单 (9)2.2硬件连接 (9)2.3首次启动 (10)2.3.1启动桌面 (10)2.3.2查看系统版本 (10)2.3.3设置时区 (10)2.3.4查看系统分区情况 (10)2.3.5查看存储空间 (10)2.3.6设置Hostname (11)2.3.7关机 (11)2.3.8重启 (11)3接线指南 (11)3.1IPEX-1 (11)3.2POE (12)4软件操作指引 (12)4.1使用SSH连接到设备 (12)4.1.1使能SSH (12)4.1.2SSH工具 (13)4.1.3获取设备IP地址 (13)4.1.4连接到系统 (13)4.2通过调试串口连接到系统 (13)4.3使用APT工具管理软件 (13)4.4X11桌面使用简介 (14)4.4.1启动X11桌面 (14)4.4.2配置系统启动到X11桌面 (14)4.4.3桌面任务栏 (16)4.4.4桌面个性化设置 (17)4.4.5关闭自动息屏功能 (18)4.4.6查看X11桌面系统日志 (19)4.4.7X11桌面截屏 (19)4.4.8播放音频 (19)4.5Weston桌面使用简介 (20)4.5.1Weston桌面启动和关闭 (20)4.5.2配置系统启动到weston桌面 (20)4.5.3Weston桌面系统日志 (21)4.5.4Weston桌面的截屏 (21)4.5.5Weston桌面的录屏 (21)4.5.6播放视频 (22)4.6系统配置 (22)4.6.1网络配置 (22)4.6.2蓝牙配置 (23)4.6.3添加外置存储 (24)4.6.4用户管理 (24)4.7X11桌面高级配置 (25)4.7.1lightdm配置文件 (25)4.7.2配置禁止自动息屏 (25)4.8Weston高级配置 (26)4.8.1Weston配置文件简介 (26)4.8.2Weston桌面定制化 (27)4.8.3添加桌面快捷方式 (28)4.9编译工具链 (28)4.10接口设备文件 (28)4.1140-Pin GPIO编程指南 (29)4.11.1使用libgpiod控制GPIO (29)4.11.2i2c_dev (32)4.11.3spi_dev (32)4.12QT编程指南 (33)4.12.1Qt环境快速应用 (33)4.12.2安装其它的依赖库 (34)4.12.3配置Qt Creator交叉编译环境 (35)4.12.4命令行方式编译Qt Widgets应用程序 (36)4.12.5命令行方式编译Qt Quick(QML)应用程序 (36)4.13Gstreamer (37)4.13.1H264 mkv格式视频解码 (37)4.13.2mp4格式解码 (37)4.14Docker (37)4.14.1Docker的安装 (37)4.14.2Docker的卸载 (38)4.14.3查看Docker (38)4.14.4使用Docker (40)4.15Bootloader配置指南 (40)4.15.1指定配置文件路径 (41)4.15.2修改bootargs参数 (41)4.16使用dtoverlay (42)4.16.1dtoverlay配置说明 (42)4.16.2目前支持的dtoverlay (42)5操作系统安装 (44)5.1镜像下载 (44)5.2系统烧录 (44)5.2.1烧录SD卡 (45)5.2.2烧录eMMC (45)6故障排除 (47)6.1HDMI无显示 (47)6.2开机绿灯常亮设备无法启动 (47)6.3SSH不可用 (47)7FAQ (47)7.1默认用户名密码 (47)7.2是否支持docker服务 (47)7.3是否预安装Linux Header包 (47)8Known Issues (47)9关于我们 (48)9.1关于EDATEC (48)9.2联系方式 (48)1睿莓1是一款具有优异性能、小巧紧凑的,并且极具性价比的单板计算机。
C8051F530A开发板用户指南说明书
Rev. 0.4 11/14Copyright © 2014 by Silicon LaboratoriesC8051F53x/52xEVELOPMENT IT SER S UIDE1. Relevant DevicesThe C8051F530 Development Kit is intended as a development platform for microcontrollers in the C8051F53x/52x MCU family. Code developed on the C8051F530 can be easily ported to the other members of this MCU family.2. Kit ContentsThe C8051F530 Development Kit contains the following items:⏹ C8051F530A Target Board⏹ C8051Fxxx Development Kit Quick-Start Guide ⏹ AC to DC Power Adapter⏹ USB Debug Adapter (USB to Debug Interface)⏹ USB CableThe development kit target board contains two C8051F530 microcontrollers that can communicate through an LIN network. One of the C8051F530 (U2) can also be connected to a CP2102 USB to UART bridge and directly connected to two analog signals and a Voltage Reference Signal Input.3. Hardware Setup Using a USB Debug AdapterThe target board is connected to a PC running the Silicon Laboratories IDE via the USB Debug Adapter as shown in Figure 1.1. Connect the USB Debug Adapter to one of the DEBUG connectors on the target board (HDR1 or HDR2) with the 10-pin ribbon cable. The recommended connection is to the HDR2 (connected to U2) as this microcontroller can be connected to the CP2102 USB to UART bridge.2. Verify that shorting blocks are installed on J13 and J14 to supply power to the target devices.3. Connect one end of the USB cable to the USB connector on the USB Debug Adapter.4. Connect the other end of the USB cable to a USB Port on the PC.5. Connect the ac/dc power adapter to power jack P5 on the target board.D 1D 2H H D 4C8051F53x/52xNotes:e the Reset button in the IDE to reset the target when connected using a USB Debug Adapter.2. Remove power from the target board and the USB Debug Adapter before connecting or disconnecting theribbon cable from the target board. Connecting or disconnecting the cable when the devices have power can damage the device and/or the USB Debug Adapter.4. Software SetupSimplicity Studio greatly reduces development time and complexity with Silicon Labs EFM32 and 8051 MCU products by providing a high-powered IDE, tools for hardware configuration, and links to helpful resources, all in one place.Once Simplicity Studio is installed, the application itself can be used to install additional software and documentation components to aid in the development and evaluation process.Figure 2.Simplicity StudioThe following Simplicity Studio components are required for the C8051F530 Development Kit:⏹ 8051 Products Part Support ⏹ Simplicity Developer PlatformDownload and install Simplicity Studio from /8bit-software or /simplicity-studio .Once installed, run Simplicity Studio by selecting Start →Silicon Labs →Simplicity Studio →Simplicity Studio from the start menu or clicking the Simplicity Studio shortcut on the desktop. Follow the instructions to install the software and click Simplicity IDE to launch the IDE.The first time the project creation wizard runs, the Setup Environment wizard will guide the user through the process of configuring the build tools and SDK selection.C8051F53x/52xIn the Part Selection step of the wizard, select from the list of installed parts only the parts to be used during development. Choosing parts and families in this step affects the displayed or filtered parts in the later device selection menus. Choose the C8051F53x/52x family by checking the C8051F53x/52x check box. Modify the part selection at any time by accessing the Part Management dialog from the Window →Preferences →Simplicity Studio →Part Management menu item.Simplicity Studio can detect if certain toolchains are not activated. If the Licensing Helper is displayed after completing the Setup Environment wizard, follow the instructions to activate the toolchain.4.1. Running BlinkyEach project has its own source files, target configuration, SDK configuration, and build configurations such as the Debug and Release build configurations. The IDE can be used to manage multiple projects in a collection called a workspace. Workspace settings are applied globally to all projects within the workspace. This can include settings,such as key bindings, window preferences, and code style and formatting options. Project actions, such as build and debug, are context-sensitive. For example, the user must select a project in the Project Explorer view in order to build that project.To create a project based on the Blinky example, perform the following steps:1. Click the Software Examples tile from the Simplicity Studio home screen.2. In the Kit drop-down, select C8051F530A Development Kit ; in the Part drop-down, select C8051F530, and in the SDK drop-down, select the desired SDK. Click Next .3. Select Example , and click Next .4. Under C8051F530A Development Kit , select F52x-53x Blinky ; click Next , and click Finish .5. Click on the project in the Project Explorer , and click Build (the hammer icon in the top bar). Alternatively, go to Project →Build Project .6. Click Debug to download the project to the hardware and start a debug session.7. Press the Resume button to start the code running. The LED should blink.8. Press the Suspendbutton to stop the code.9. Press the Reset the devicebutton to reset the target MCU.10. Press the Disconnectbutton to return to the development perspective.4.2. Simplicity Studio HelpSimplicity Studio includes detailed help information and device documentation within the tool. The help containsdescriptions for each dialog window. To view the documentation for a dialog, click the question mark icon in the window:This will open a pane specific to the dialog with additional details.The documentation within the tool can also be viewed by going to Help →Help Contents or Help →Search .C8051F53x/52x4.3. CP210x USB to UART VCP Driver InstallationThe Target Board includes a Silicon Labs CP210x USB-to-UART Bridge Controller. Device drivers for the CP210x need to be installed before the PC software can communicate with the MCU through the UART interface.1. After opening Simplicity Studio for the first time, a dialog will prompt to install the CP210x drivers. Click Yes . The drivers can also be installed at any time by going to Help →Install Drivers →CP210x VCP USB Drivers .2. Accept the license agreement and follow the steps to install the driver on the system. The installer will let you know when your system is up to date. The driver files included in this installation have been certified by Microsoft.3. To complete the installation process, connect the included USB cable between the host computer and the USB connector (P4) on the Target Board. Windows will automatically finish the driver installation. Information windows will pop up from the taskbar to show the installation progress.4. If necessary, the driver files can be uninstalled by selecting Windows Driver Package—Silicon Laboratories...option in the Programs and Features window.4.4. Configuration Wizard 2The Configuration Wizard 2 is a code generation tool for all of the Silicon Laboratories devices. Code is generated through the use of dialog boxes for each of the device's peripherals.Figure 3.Configuration Wizard 2 UtilityThe Configuration Wizard 2 utility helps accelerate development by automatically generating initialization source code to configure and enable the on-chip resources needed by most design projects. In just a few steps, the wizard creates complete startup code for a specific Silicon Laboratories MCU. The program is configurable to provide the output in C or assembly language. For more information, refer to the Configuration Wizard documentation.Documentation and software is available on the kit CD and from the downloads web page: /mcudownloads .C8051F53x/52x 5. Target BoardThe C8051F52xA-53xA Development Kit includes a target board with two C8051F530A devices preinstalled for evaluation and preliminary software development. Numerous input/output (I/O) connections are provided to facilitate prototyping using the target board. Refer to Figure4 for the locations of the various I/O connectors.Table 1. Target Board Part SummaryPart DescriptionP5 Power connector (Accepts input from 7 to 15VDC unregulated power adapter.)PWR Red Power-on LED (D3)TB1 LINconnectorU55V Voltage RegulatorA SideJ2 28-pin Expansion I/O connector for U2HDR2 Debug connector for Debug Adapter Interface(D2)P1.3_A GreenLEDbuttonReset_A ResetbuttonP1.4_A PushR32Potentiometer for P1.2_AJ6, J8Connects R32 (potentiometer) to U2 and +5 VJ13Connects power to U2J11, J12Connects external crystal to U2 pins P0.7_A and P1.0_AJ3 Connects analog channel 1 to U2 P1.6_AJ4 Connects analog channel 2 to U2 P1.7_AJ5 Connects VREFIN to U2 P0.0_AconnectorTB2 AnaloginputHDR4 Connector block for serial port connection, Green LED, and push-buttonU3Silicon Laboratories CP2102 USB-to-UART BridgeP1 USB connector to serial interface (CP2102)USB ACTIVE Red USB Active LED (D4) (CP2102)T2 LINtransceiverU2 C8051F530A “A” SideC8051F53x/52x5.1. Target Board Shorting Blocks: Factory DefaultsThe C8051F530A target board comes from the factory with preinstalled shorting blocks on many headers. Figure 4shows the positions of the factory default shorting blocks.B SideJ1 26-pin Expansion I/O connector for U1HDR1Debug connector for Debug Adapter InterfaceP1.3_B Green LED (D1)Reset_B Reset button P1.4_B Push button J14Connects power to U1J9, J10Connects external crystal to U1 pins P0.7_B and P1.0_B HDR3Green LED and push-button connector blockT1 LIN transceiver U1C8051F530A “B” SideTable 1. Target Board Part SummaryPart DescriptionP1.4_BPWRUSB ACTIVE P1.3_AP1.3_B D2D1D4Pin 1C8051F53x/52x5.2. System Clock SourcesThe C8051F530A device installed on the target board features a calibrated programmable internal oscillator that is enabled as the system clock source on reset. After reset, the internal oscillator operates at a frequency of 191.4kHz (±0.5%) by default but may be configured by software to operate at other frequencies. Therefore, in many applications, an external oscillator is not required. However, if you wish to operate the C8051F530A device at a frequency not available with the internal oscillator, an external crystal may be used. Refer to the C8051F52x/ 52xA/53x/53xA data sheet for more information on configuring the system clock source.The target board is designed to facilitate the installation of external crystals. Install the crystals at the pads marked Y1 or Y2. Install a 10M resistor at R17 or R22, and install capacitors at C29 and C30 or C34 and C35 using values appropriate for the crystals selected. Headers J9, J10, J11, and J12 connect the external crystal pins to the general purpose I/O headers (J1 and J2). If the external crystal is in use, these headers should not be populated. Refer to the C8051F52x/52xA/53x/53xA data sheet for more information on the use of external oscillators.5.3. Switches and LEDsFour switches are provided on the target board.Switch RESET_A is connected to the RESET pin of the C8051F530A A-Side (U2).Switch RESET_B is connected to the RESET pin of the C8051F530A B-Side (U1).Pressing RESET_A or RESET_B puts the attached device into its hardware-reset state.Switches P1.4_A and P1.4_B are connected to the C8051F530A parts (U1 and U2) general purpose I/O (GPIO) pins through headers. Pressing P1.4_A or P1.4_B generates a logic low signal on the port pin of the respective microcontroller.Remove the shorting block from the header to disconnect P1.4_A or P1.4_B from the port pins. The port pin signals are also routed to pins on the J1 and J2 I/O connectors. See Table2 for the port pins and headers corresponding to each switch.Four LEDs are also provided on the target board. The red LED labeled PWR is used to indicate a power connection to the target board. The green LEDs labeled D1 and D2 are connected to the C8051F530A's GPIO pins through headers. Remove the shorting blocks from the headers to disconnect the LEDs from the port pins. The port pin signals are also routed to pins on the J1 and J2 I/O connectors. The red LED labeled USB ACTIVE is used to indicate that the CP2102 USB-to-UART bridge is properly connected to a PC and is ready for communication. See Table2 for the port pins and headers corresponding to each LED.A potentiometer (R32) is provided on the target board. Header J8 connects the potentiometer to +5V, and header J6 connects the potentiometer to the P1.2_A pin of the U2 A-Side C8051F530A microcontroller.Table 2. Target Board I/O DescriptionsDescription I/O HeaderReset_A U2-Reset noneReset_B U1-Reset noneP1.4_A U2-P1.4HDR4[3–4]P1.4_B U1-P1.4HDR3[3–4]Green LED D2U2-P1.3HDR4[1–2]Green LED D1U1-P1.3HDR3[1–2]Red LED D3PWR noneRed LED D4USB ACTIVE nonePotentiometer R32U2-P1.2J6, J8C8051F53x/52x5.4. Expansion I/O Connectors (J1, J2)The two Expansion I/O connectors J1 (26pins) and J2 (28pins) provide access to all signal pins of the C8051F530A devices. Pins for V DD, GND, 5V, Reset, Vbat, LIN, 3.3V, and VREFIN are also available. A small through-hole prototyping area is also provided.All I/O signals routed to connectors J1 and J2 are also routed to through-hole connection points between J1 and J2 and the prototyping area (see Figure4). Each connection point is labeled indicating the signal available at the connection point. Table3 lists the pin descriptions for J1 and J2.Table 3. Pin Descriptions for J1 and J2J1J2Pin #Description Pin #Description Pin #Description Pin #Description 1P0.0_B14P1.5_B1P0.0_A15P1.6_A 2P0.1_B15P1.6_B2P0.1_A16P1.7_A 3P0.2_B16P1.7_B3P0.2_A17+5V4P0.3_B17+5V4P0.3_A18RST/C2CLK_A 5P0.4_B18RST/C2CLK_B5P0.4_A19VBAT 6P0.5_B19VBAT6P0.5_A20LIN7P0.6_B20LIN7P0.6_A21VREFIN 8P0.7_B21NC8P0.7_A22VREGOUT_A 9P1.0_B22VREGOUT_B9P1.0_A23+3.3V 10P1.1_B23NC10P1.1_A24NC11P1.2_B24NC11P1.2_A25NC12P1.3_B25GND12P1.3_A26NC13P1.4_B26GND13P1.4_A27GND14P1.5_A28GND5.5. Target Board DEBUG Interface (HDR1, HDR2)The DEBUG connectors (HDR1 and HDR2) provide access to the DEBUG (C2) pins of the C8051F530A parts. They are used to connect the USB Debug Adapter to the target board for in-circuit debugging and Flash programming. Table4 shows the DEBUG pin definitions.Table 4. DEBUG Connector Pin DescriptionsPin #Description1+3VD(+3.3VDC)2, 3, 9GND (Ground)4C2D5RST (Reset)6P0.67C2CK8Not Connected10USB PowerC8051F53x/52x5.6. USB to Serial Connector (P1, HDR4)A USB-to-Serial bridge interface is provided. A B-type USB connector (P1), a CP2102, and related circuits are provided to facilitate the serial connection between a PC and the U2 A-Side C8051F530A microcontroller on the target board. The RX, TX, CTS, and RTS signals of the UART side of the Bridge (CP2102) may be connected to the microcontroller by installing shorting blocks on HDR4 as shown in Table5.Table 5. UART ConnectionsHDR3Connection Signals5–6P0.4_A to TX_A7–8P0.5_A to RX_A9–10P1.1_A to RTS_A11–12P1.2_A to CTS_AThe BUS-Powered CP2102 uses the 5V provided by the USB interface.5.7. Analog I/O (TB2, J3, J4, J5)The Analog connector block (TB2) and headers J3, J4, and J5 provide Analog inputs to the C8051F530A (U2) as shown in Table6. Headers J3, J4, and J5 connect the inputs from the Analog connector to the microcontroller pins.Table 6. Analog I/O ConnectionsTB2Signal Connection I/O Shorting Block Vrefin External Reference Input or Internal Reference Output P0.0_A J5CH1Analog Input 1P1.6_A_MC J3CH2Analog Input 1P1.7_A_MC J4GND Ground GND—5.8. Power Supply Options (P5, TB1, J13, J14)The target board provides two options of power supply. The first option is to use the provided 9V power supply attached to the P5 connector. The second option is to use an external 12V (7.5V minimum) connected to the TB1 terminal block (pins 1 and 3).Headers J13 and J14 connect the +5V power supply to the VREGIN pins on U1 and U2. These headers can be populated to supply power directly or depopulated to measure the operating current drawn by the corresponding C8051F530A device.C8051F53x/52x5.9. LIN Connectivity (TB1)The C8051F530A Target Board has two C8051F530A devices (U1 and U2) and two LIN transceivers (T1 and T2) to provide LIN connectivity on the target board. These devices can also be interfaced to another LIN bus using the TB1 terminal block.Table 7. LIN ConnectionsTB1Signal Connection+12V Supplies 12V (7.5V minimum) to the target board. This can be connected to the power supply of another LIN bus or any external supply.LIN Connects the 12V LIN bus signal to the T1 and T2 LIN transceivers.GND GroundC8051F53x/52x6. SchematicsF i g u r e 5.C 8051F 530A T a r g e t B o a r d S c h e m a t i c (1 o f 3)C8051F53x/52xF i g u r e 6.C 8051F 530A T a r g e t B o a r d S c h e m a t i c (2 o f 3)C8051F53x/52xF i g u r e 7.C 8051F 530A T a r g e t B o a r d S c h e m a t i c (3 o f 3)C8051F53x/52xD OCUMENT C HANGE L IST Revision 0.2 to Revision 0.3⏹Updated for C8051F530A TB.⏹Added "LIN Connectivity (TB1)‚" on page 10. Revision 0.3 to Revision 0.4⏹Updated "Software Setup‚" on page 2.DisclaimerSilicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Laboratories products are generally not intended for military applications. Silicon Laboratories products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.Trademark InformationSilicon Laboratories Inc., Silicon Laboratories, Silicon Labs, SiLabs and the Silicon Labs logo, CMEMS®, EFM, EFM32, EFR, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZMac®, EZRadio®, EZRadioPRO®, DSPLL®, ISOmodem ®, Precision32®, ProSLIC®, SiPHY®, USBXpress® and others are trademarks or registered trademarks of Silicon Laboratories Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other products or brand names mentioned herein are trademarks of their respective holders.Silicon Laboratories Inc.400 West Cesar Chavez Austin, TX 78701USAIoT Portfolio /IoTSW/HW/simplicityQuality/qualitySupport and Community。
Gowin FPGA 开发板 RISCV 编程 快速应用手册说明书
Gowin FPGA开发板RISCV编程快速应用手册IPUG546-1.1,2022-11-11版权所有© 2022广东高云半导体科技股份有限公司、Gowin以及高云均为广东高云半导体科技股份有限公司注册商标, 本手册中提到的其他任何商标,其所有权利属其拥有者所有。
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版本信息目录目录 (i)图目录 (ii)表目录 (iii)1 前言 (1)1.1 AE250简介 (1)1.2 准备工作 (2)1.3 开发/调试步骤 (3)2 Debug Cable连接说明 (4)3 RDS使用说明 (6)3.1 RDS安装 (6)3.2 新建工程 (6)3.3 导入/导出工程 (8)3.4 下载程序到Flash (10)3.5 片上调试 (13)3.6 RDS内置的串口终端使用方法 (15)4 参考设计 (16)4.1 工程代码 (16)4.2 参考设计 (17)图目录图1-1 AE250结构框图 (1)图1-2开发/调试系统结构框图 (2)图2-1 AICE-MINI+ Debug Cable及其引脚示意图 (4)图3-1新建工程 (7)图3-2 Import/Export a Project (8)图3-3导入工程界面 (9)图3-4导出工程界面 (9)图3-5设置System Reset Vector Default (10)图3-6设置SPI1 Configuration (11)图3-7设置MSPI接口为普通IO (12)图3-8 ae250.sag中bootloader参数设置 (12)图3-9 Debug参数设置界面 (13)图3-10 Debug按钮介绍 (14)图3-11汇编指令代码窗口 (14)图3-12 RDS内置串口终端 (15)表目录表目录表2-1 AICE-MINI+ Debug Cable引脚定义 (4)表3-1 SPI1接口物理约束 (11)1 前言 1.1 AE250简介1前言1.1AE250简介AE250是一个32位RISC-V MCU系统,其主要结构如图1-1所示。
FPGA开发板使用说明书(二版)
目 录第一章综述 (1)核心板介绍EP1C12核心板资源介绍 (1)EP2C35核心板资源介绍 (2)FPGA开发板介绍FPGA开发板资源介绍 (4)第二章 系统模块功能介绍 (7)EP1C12核心板模块说明EP1C12F324C8芯片说明 (9)NOR FLASH模块说明 (10)SRAM模块说明 (11)FPGA接口I/O说明 (12)EP2C35核心板模块说明EP2C35F484C8芯片说明 (19)NOR FLASH模块说明 (20)SRAM模块说明 (21)S D R A M模块说明 (22)NAND FLASH模块说明 (23)FPGA接口I/O说明 (24)核心板使用注意事项 (29)FPGA开发平台模块说明液晶显示模块 (31)RTC实时时钟模块 (33)USB接口模块 (33)音频CODEC接口模块 (34)EEPROM存储模块 (35)数字温度传感器模块 (36)其它功能模块 (37)FPGA开发平台使用注意事项 (38)第三章 软件的安装 (39)QUARTUSII的安装 (39)QUARTUSII的授权 (46)NIOSII IDE的安装 (51)附表一核心板载资源与FPGAEP1C12I/O接口对照表 (55)附表二核心板载资源与FPGAEP2C35I/O接口对照表 (60)附表三EP1C12/ EP2C35与开发板硬件资源I/O接口对照表 (66)第一章综述FPGA开发平台是根据现代电子发展的方向,集EDA和SOPC系统开发为一体的综合性实验开发系统,除了满足高校专、本科生和研究生的SOPC教学实验开发之外,也是电子设计和电子项目开发的理想工具。
整个开发系统由核心板、SOPC开发平台和扩展板构成,根据用户不同的需求配置成不同的开发系统。
系统根据用户不同的设计需求来更换其它不同系列的核心板,如: EP1C12、EP2C20、EP3C25等。
所以,不管从性能上而言,还是从系统灵活性上而言,无论您是初学者,还是资深硬件工程师,它都会成为您的好帮手。
FPGA黑金开发板用户手册
Black Gold 黑金动力II代用户手册v1.0修订历史目录内容介绍:本手册包括以下部分第一部分, 主要器件及特性第二部分, 开关,按键及数码管第三部分, VGA接口Chapter 1 主要器件及特性本手册中描述了”黑金动力”系列开发板的设计原理和使用方法,作为开发板的配套说明材料.这套开发板主要是面向FPGA的初级,中级开发人员,或者对FPGA感兴趣的爱好者,偏向个人用户.这套开发板采用核心板与扩展板分离的方式,简单实用,扩展性好,特别适合爱好者的快速入门和开发人员的产品开发验证,也适合做更深入的IC前端设计.在这套开发板上,一切皆有可能.同时,这套开发板也提供了一个SOPC平台,可以实现嵌入式的软核,如NIOSII,Open RISC等,为嵌入式电子产品的设计开发提供了又一种选择.主要元器件介绍●Altera Cyclone Ⅱ系列 FPGA核心板配置的FPGA芯片是Cyclone Ⅱ系列的EP2C8Q208C更详细可到:/literature/lit-cyc2.jsp下载官方手册●64Mbit的SDRAM核心板同时配备了高达64Mbit的SDRAM,对于运行NIOS的软核提供了有力的保障,这款芯片的时钟频率有143MHz,实验证明,NIOSⅡ可以稳定地运行120MHz,速度还是相当快的.●16Mbit的配置芯片核心板还配备了16Mbit的配置芯片,不仅可以储存配置信息,同时可以实现NIOSⅡ软件程序存储.●20MHz的有源晶振20M的有源晶振为整个系统提供了时钟源泉.●ENC28J60网口芯片实现开发板与以太网之间的通信实验.●USB 2.0高速数据接口采用应用广泛,性能稳定的CH376芯片,实现了开发板USB接口的扩展,便于与计算机进行高速数据通信.●板载128*64的点阵LCD采用ST7565P控制芯片,内置DC/DC电路,可以通过串行,并行进行通信.●实时时钟芯片(RTC)配置DS1302芯片,增加了主电源/后背电源双电源引脚,同时提供了对后背电源进行涓细电流充电的能力.●EEPROM配置24LC04芯片,24LC04是512*8bit的EEPROM,支持IIC接口.●PS/2鼠标,键盘接口标准的鼠标,键盘接口,支持3.3V和5V设备,可以用来验证PS/2接口协议.●9针RS-232串口实现与计算机的数据通信,辅助调试.●VGA接口标准VGA接口,可直接与显示器连接,用于验证VGA时序.●5个独立按键可以与液晶配合,实现完美的人机界面.开发板示意图核心板扩展板-Chapter 2 开关,按键与数码管按键在绝大多数电子电气设备中都存在身影,可以说,如果说显示屏是人与机器之间沟通的窗户的话,按键就是沟通的桥梁,通过按键,可以方便快捷地对机器进行操作控制.在黑金开发板中,我们设置了5个按键,分别为上,下,左,右,确认,用户可以自行设定按键的功能.电源开关电源接口及开关位于核心板左上方,如图其中F1为限流1.1A的F110保险管,在电源的保护上起到了很大的作用按键核心板上的复位电路该复位电路可以实现对开发板的初始化作用,防止程序陷入死循环.扩展板上的按键扩展板上搭配有5个按键,可以满足大多数场合的设计需要,采用低电平闭合电路.按键开关管脚映射表LEDs在核心板上设置了4个LED,可以作为测试使用,电路如图LED管脚映射表数码管在扩展板上并设有6位独立共阳数码管,实验证明数码管在诸多设计开发中起到了不可代替的作用.数码管的电路如图该电路图为第一位数码管的电路,其他的电路与之类似.其中,每个数码管都通过一个9012三极管放大电流,保证其亮度均匀.数码管管脚映射表Chapter 3 点阵型液晶显示器(LCD)在扩展板的右方包括了一块128*64像素的液晶显示器,带有少见的白色背光.常见的LCD模块有LCM(玻璃),背光,PCB板,三种之中LCM(玻璃)模块必不可少,有无背光,有无PCB用户可以根据需要自行选择.点阵的LCD模块按驱动控制器的集成方式分成两种:COB和COG,COG是将驱动控制芯片集成到了玻璃里面,用户只需在电路板上加上无法集成的电阻电容即可实现对LCD的控制;而COB则需要将驱动芯片焊接在LCD模块后面的PCB板上.黑金开发板上提供的LCD使用的是COG液晶,它将驱动控制IC集成到了LCM上,这样就省去了PCB底板,节省了很大的空间.该LCD的驱动芯片为ST7565P,支持三种接口方式,通常采用串行时序方式,接口简单,使用方便.LCD的原理图LCD的管脚映射表LCD参数注意:该LCD的显存存在8(page)*8+1行,即65行,s0-s131列,即132列,与标准的128*64液晶有的差异,该LCD的最后一行(page8的D0)和最后三列(ADC为正常时,s129,s130,s131;ADC为反向时,s0,s1,s2)是不能显示的,而显存上其他数据与LCD上的点一一对应,具体如下图红圈所示显示屏上的每个点都对应控制器片内显示缓存RAM中的一个位,显示屏上的64*128个点分别对应显示RAM的8个Page,每个Page有128 Byte的空间对应,如图所示用户如果要点亮LCD屏幕上的某一个点时,实际上就是对该点所对应的显示RAM区中的某一个位进行置1操作;所以就要确定该点所在的行地址,列地址.由上图可以看出,液晶的行地址实际上就是Page的信息,每个Page应有8行;而列地址表示该点的横坐标,在屏上为从左到右排列,Page中的一个Byte对应的是一列(8行,即8个点),一共128列.可以根据这样的关系在程序中控制LCD屏幕的显示.在LCD上显示字符,不管是中文还是英文,都需要字库的支持,在有些LCD模块中,已经将字库烧写在芯片当中,这样的字库有优点也有缺点.优点是操作简单,而缺点是不灵活,显示效果不好,扩展性差,而且性价比不高.黑金开发板所选用的COG屏幕是不带字库的.Chapter 4 VGA接口VGA(Video Graphics Array)接口,也叫D-Sub接口,是显示卡上输出模拟信号的接口,显卡所处理的信息最终都要输出到显示屏上显示,显卡的输出接口就是电脑与显示屏之间桥梁,它负责向显示器输出相应的图像信号.CRT显示器因为设计制造上的原因,只能接受模拟信号,这就需要显卡能够输入模拟信号,于是就有了VGA接口.虽然液晶显示器可以直接接接收数字信号,但是为了兼容性,大多数液晶显示器也配备了VGA接口模块.VGA是IBM在1987年随PS/2机一起推出的一种视频传输标准,具有分辨率高,显示速率快,颜色丰富等优点,在彩色显示器领域得到了广泛的应用.目前VGA技术的应用还主要基亍VGA显示卡的计算机,笔记本等设备.根据分辨率不同,VGA分为VGA (640x480),SVGA(800x600),XGA(1024x768),SXGA(1280x1024)等.虽然说VGA的标准对于现在的个人计算机市场十分过时,但是VGA仍然是所有制造商所支持的最低标准,例如不管所有厂商的显卡,在不安装自己驱动的情况下,都是支持VGA 标准显示的.VGA接口是一种D型接口(D-SUB),上面共有15个针孔,分成三排,每排五个,如图所示.VGA引脚定义引脚1,2,3分别为红绿蓝三基色模拟电压,为0~0.714V peak-peak(峰-峰值),0V代表无色,0.714V代表满色.一些非标准显示器使用的是 1Vpp的满色电平.HSYNC与VSYNC 分别为行数据同步与帧数据同步,为TTL电平.黑金开发板的扩展板上配备了一个VGA接口,其电路为VGA管脚映射表VGA的时序介绍VGA的时序如图所示,它分为行数据时序和帧数据时序行数据时序为显示一行数据的时序,由上图可看出,显示一行数据需要处理两件事情:第一,产生行同步HSYNC.不难看出HSYNC是一个脉冲信号,该信号周期为:e=a+b+c+d,低电平时间为a.其中a,b,c,d均为时间信号,这些信号根据需要显示的分辨率的不同而不同.第二,产生显示的数据(DATA)信号,此信号为模拟信号,当在显示有效数据(Active Video)内,DATA信号为0~0.714Vpp的模拟电压(R,G,B),根据分辨率的不同,DATA的采样率,点数也不同.帧数据时序与行数据时序类似,是显示一个屏数据的时序.只是这里的基本单位为每行数据,而行数据里面的最基本单位为每个点.下表列出常用分辨率及时间参数Chapter 5 PS/2 鼠标键盘接口PS/2 原是“Personal System 2”的意思,“个人系统2”,是IBM公司在上个世纪80年代推出的一种个人电脑。
智能融合2系列SoC FPGA开发板使用指南说明书
Application Note AC401January 20141© 2014 Microsemi Corporation SmartFusion2 SoC FPGA - SPI Master ProgrammingTable of ContentsPurposeThis application note describes how to use the serial peripheral interface (SPI) Master Programming mode on SmartFusion ®2 system-on-chip (SoC) field programmable gate array (FPGA) Development Kit board DVP-102-000400-001 Rev C.Note:Rev A and Rev B Development Kit Board are not supported.Two software utilities, SPI_Memory.exe and SetMuxes.exe, are described in this document. The SPI_Memory.exe is used to program Atmel ® AT25DF641 and SetMuxes.exe is used to configure the multiplexers on the Development Kit board to either perform SPI Memory Programming or initiate SPI Master Programming.IntroductionSPI Master Programming mode, also known as auto-update or reflash is one of the programming methods available to program SmartFusion2 devices. Refer to the SmartFusion2 Programming User's Guide for more information on the available programming modes. On power-up or resetting the device with FLASH_GOLDEN_N pin asserted (driven low), the SmartFusion2 device configures the dedicated SPI port to operate in Master mode. It also reads the attached external SPI memory device from address zero. Auto programming is executed if a valid programming image is found. Figure 1 shows a high level system design to execute auto programming.Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Development Kit Board Programming Circuit Design Description . . . . . . . . . . . . . . . . . . . . 2Programming the SPI Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Appendix A - SPI Memory Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Appendix B - SetMuxes Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7SmartFusion2 SoC FPGA - SPI Master Programming2Development Kit Board Programming Circuit Design DescriptionThe Development Kit board programming circuitry has an on board FT4232H module from Future Technology Devices International (FTDI). This module is a universal serial bus (USB)-to-serial interface converter. For more information on FT432H module, see FTDI website at /Products/Modules/DevelopmentModules.htm. This module is connected to the M2S dedicated SPI port and the SPI memory device using the multiplexers. The multiplexers can then be configured either manually or through SetMuxes.exe utility described below to program the Atmel SPI memory device or to initiate an auto-programming operation. The Development Kit board is designed in this fashion to program the SPI memory device on board through the FTDI chip. Figure 2 shows how the multiplexers are connected.Figure 1 • Auto Programming (SPI- Master) ModeDevelopment Kit Board Programming Circuit Design Description3Figure 2 • Connection of MultiplexersFigure 3 • Development Kit Board Programming Circuit - Auto Programming ModuleSmartFusion2 SoC FPGA - SPI Master Programming4Note:Some of the FT4232H I/O pins control the enable and select signals of the multiplexers.SetMuxes.exe configures these pins to either perform the SPI memory programming manually or initiate auto-programming.Programming the SPI MasterThe following steps describe how to program the SPI master.1.Set the jumpers on the Development Kit board as:–J43 (Pin 1 - Pin 2)–J55 (Pin 1 - Pin 2)–J70 (Pin 2 - Pin 3)2.Install the FTDI drivers based on the operating system as described in the FTDI driver installationguide available at: /Support/Documents/InstallGuides.htm.3.Copy the following files into a local directory on your PC.–FTCJTAG.dll: Used for interfacing FT2232 to devices using the JTAG protocol.Note:Click the file name to download a ZIP file containing the library.–libMPSSE.dll : This library has been created to aid the implementation of I2C designs using FTDI devices which incorporate the FTDI MPSSE.–SetMuxes.exe: Refer "Appendix B - SetMuxes Utility"for more information.–SPI_Memory.exe: Refer "Appendix A - SPI Memory Utility"for more information.–Click here to download a sample demo project containing both the exe files.4.Copy the programming file (.spi) to a local directory on the PC. Use one of the .spi files included inthis demo package or generate a design and export it through Libero ® System-on-Chip (SoC)software. For more information on how to use Libero software, refer /download/software/liberosoc/default.aspx.5.Open the Command Prompt and navigate to the directory where the files are saved.6.Connect the Development Kit board mini USB (J24) to the PC.7.Power-up the Development Kit board.Figure 4 • Development Kit Board Programming Circuit - FT4232H ModuleProgramming the SPI Master58.In the command prompt, type:SetMuxes MEMThis application sets the multiplexers for the FTDI chip to access the Atmel memory device on the board. Figure 4 shows an example message on successful setting-up of the multiplexers.9.In the command prompt, type:SPI_Memory -aprogram <file name>.spiThis updates the Atmel spi memory device, as shown in Figure 6.10.In the command prompt type the following:SetMuxes REFFigure 5 • SetMuxes MEMFigure 6 • aprogram <file name>.spiSmartFusion2 SoC FPGA - SPI Master Programming6This command sets the multiplexers for the M2S chip to access the Atmel memory device on the board and initiates reflash, as shown in Figure 7. The M2S device functions with a delay of approximately a minute. The functioning is based on the design that you programmed.Note:With this configuration, any subsequent resets to the device or board power cycle initiate thereflash operation again.11.In the command prompt type the following:SetMuxes SPIThis application sets the multiplexers for the FTDI chip to access the M2S device, as shown in Figure 8.List of ChangesThe following table lists critical changes that were made in the current version of the document.Figure 7 • SetMuxes REFFigure 8 • SetMuxes SPIRevisionChanges in Current Version (51900145-2/2.08*)Page Revision 1January 2014Updated the section "Programming the SPI Master"(SAR 53223).4Appendix A - SPI Memory Utility7Appendix A - SPI Memory UtilitySPI_Memory.exe is a standalone command line utility that uses the FTDI chip to program the SPI file into the Atmel AT25DF641 memory device used in the Development Kit board. This supports the following platforms:•Windows XP •Windows Vista •Windows 7Usage: spi_memory [options] <filename> Available options:•-h : show help message •-a<action>: Specify action name as follows:–read_id: Read device ID.–Blank: Checks to see if device is in erased state.–Erase: Erases the entire device.–Program: Programs the content of the file into the device starting at address 0.–Verify: Verifies the content of the device against the file.–Read: Reads the content of the device and saves it in ReadBuffer.bin.Appendix B - SetMuxes UtilitySetMuxes.exe configures the multiplexers on the Development Kit board based on the desired operation.This supports the following platforms:•Windows XP •Windows Vista •Windows 7Usage: SetMuxes [options]MEM: Configures the multiplexers to enable FTDI connection to the SPI memory device on the dedicated SPI port.REF: Configures the multiplexers to connect the M2S device to the SPI memory device and initiate reflash.SPI: Configures the multiplexers to connect the M2S device to FTDI for SPI- Slave programming.51900269-1/01-14© 2013 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security; enterprise and communications; and industrial and alternative energy markets. Products include high-performance, high-reliability analog and RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at .Microsemi Corporate HeadquartersOne Enterprise, Aliso Viejo CA 92656 USAWithin the USA: +1 (949) 380-6100Sales: +1 (949) 380-6136Fax: +1 (949) 215-4996。
FPGA可编程逻辑器件芯片EP4S100G5F45I1中文规格书
Document Revision Historythe Device & Pin Options dialog box in the Quartus II software uses a32-bit CRC circuit to ensure data reliability and is one of the best optionsfor mitigating SEU.You can implement the error detection CRC feature with existing circuitryin Stratix II devices, eliminating the need for external logic. For Stratix IIdevices, CRC is computed by the device during configuration andchecked against an automatically computed CRC during normaloperation. The CRC_ERROR pin reports a soft error when configurationSRAM data is corrupted, triggering device reconfiguration.Custom-Built CircuitryDedicated circuitry is built in the Stratix II devices to perform errordetection automatically. This error detection circuitry in Stratix II devicesconstantly checks for errors in the configuration SRAM cells while thedevice is in user mode. You can monitor one external pin for the error anduse it to trigger a re-configuration cycle. You can select the desired timebetween checks by adjusting a built-in clock divider.Software InterfaceIn the Quartus II software version 4.1 and later, you can turn on theautomated error detection CRC feature in the Device & Pin Optionsdialog box. This dialog box allows you to enable the feature and set theinternal frequency of the CRC between 400kHz to 50MHz. This controlsthe rate that the CRC circuitry verifies the internal configuration SRAMbits in the FPGA device.For more information on CRC, refer to AN 357: Error Detection Using CRCin Altera FPGA Devices.DocumentTable3–7 shows the revision history for this chapter.Revision HistoryTable3–7.Document Revision History (Part 1 of2)Date andDocumentChanges Made Summary of Changes Version—May 2007, v4.2Moved Document Revision History section to the endof the chapter.—Updated the “Temperature Sensing Diode (TSD)”section.Operating ConditionsTable5–10.2.5-V LVDS I/O SpecificationsSymbol Parameter Conditions Minimum Typical Maximum Unit2.375 2.500 2.625V V CCIO I/O supply voltage for left andright I/O banks (1, 2, 5, and6)V ID Input differential voltage100350900mV swing (single-ended)V ICM Input common mode voltage2001,2501,800mVR L = 100 Ω250450mV V OD Output differential voltage(single-ended)R L = 100 Ω 1.125 1.375V V OCM Output common modevoltageR L Receiver differential input90100110Ωdiscrete resistor (external toStratix II devices)Table5–11.3.3-V LVDS I/O SpecificationsSymbol Parameter Conditions Minimum Typical Maximum Unit V CCIO (1)I/O supply voltage for top3.135 3.300 3.465Vand bottom PLL banks (9,10, 11, and 12)100350900mV V ID Input differential voltageswing (single-ended)V ICM Input common mode voltage2001,2501,800mV V OD Output differential voltageR L = 100 Ω250710mV (single-ended)R L = 100 Ω8401,570mV V OCM Output common modevoltage90100110ΩR L Receiver differential inputdiscrete resistor (external toStratix II devices)Note to Table5–11:(1)The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by V CCINT, not V CCIO.The PLL clock output/feedback differential buffers are powered by VCC_PLL_OUT. For differential clockoutput/feedback operation, VCC_PLL_OUT should be connected to 3.3 V.Timing ModelTable5–34.Output Timing Measurement Methodology for Output Pins Notes(1), (2), (3)I/O StandardLoading and TerminationMeasurementPointR S (Ω)R D (Ω)R T (Ω)V CCIO (V)V TT (V)C L (pF)V MEAS (V)LVTTL (4) 3.1350 1.5675 LVCMOS (4) 3.1350 1.5675 2.5 V (4) 2.3750 1.1875 1.8 V (4) 1.71000.855 1.5 V (4) 1.42500.7125 PCI (5) 2.97010 1.485 PCI-X (5) 2.97010 1.485 SSTL-2 Class I2550 2.325 1.1230 1.1625 SSTL-2 Class II2525 2.325 1.1230 1.1625 SSTL-18 Class I2550 1.6600.79000.83 SSTL-18 Class II2525 1.6600.79000.83 1.8-V HSTL Class I5050 1.6600.79000.83 1.8-V HSTL Class II2525 1.6600.79000.83 1.5-V HSTL Class I5050 1.3750.64800.6875 1.5-V HSTL Class II25 1.3750.64800.6875 1.2-V HSTL with OCT50 1.14000.570 Differential SSTL-2 Class I5050 2.325 1.1230 1.1625 Differential SSTL-2 Class II2525 2.325 1.1230 1.1625 Differential SSTL-18 Class I5050 1.6600.79000.83 Differential SSTL-18 Class II2525 1.6600.79000.83 1.5-V Differential HSTL Class I5050 1.3750.64800.6875 1.5-V Differential HSTL Class II25 1.3750.64800.6875 1.8-V Differential HSTL Class I5050 1.6600.79000.83 1.8-V Differential HSTL Class II2525 1.6600.79000.83 LVDS100 2.3250 1.1625 HyperTransport100 2.3250 1.1625 LVPECL100 3.1350 1.5675 Notes to Table5–34:(1)Input measurement point at internal node is 0.5 × V CCINT.(2)Output measuring point for V MEAS at buffer output is 0.5 × V CCIO.(3)Input stimulus edge rate is 0 to V CC in 0.2 ns (internal signal) from the driver preceding the I/O buffer.(4)Less than 50-mV ripple on V CCIO and V CCPD, V CCINT = 1.15 V with less than 30-mV ripple(5)V CCPD = 2.97 V, less than 50-mV ripple on V CCIO and V CCPD, V CCINT = 1.15 V。
FPGA 开发板用户手册
FPGA_Cyclone_I_EP1C3 核心板一、FPGA_Cyclone_EP1C3 核心板特点:1.系统采用双层PCB板设计,高密度走线,完善的电源和时钟设计,性能稳定可靠、结构紧凑美观。
支持FPGA开发,提供引脚信息和预留PLL资源,支持扩展设计;2.该核心板适合于快速产品原型开发、学生各种电子设计大赛、学习FPGA设计技术等,亦可用于系统设计前期快速评估设计方案;3.例程模块化设计,简单明了,上手容易。
亦可作为以后系统的模块选用,加快项目系统搭建速度,实用性强;4.可持续性学习。
该FPGA开发板中FPGA的所有I/O口全部引出来,均可用于扩展。
用户可以根据自己的需要,设计实际电路,然后通过这些I/O连接到FPGA上,完成所需功能;5.性价比高,针对于学生用户定价,让更多的学生加入学习FPGA的行列。
二、FPGA_Cyclone_EP1C3 核心板配置:1. FPGA芯片:EP1C3T144C8 含2,910 Les;59,904bits(13个4Kbit存储块);1 PLL;104 I/O口2. 配置芯片:EPCS1 FPGA串行配置芯片含1 M bit Flash3. I2C存储器电路:24LC16B 16K bit(8 Blocks×256×8 Bit)4. SPI存储器电路:93LC46B 1K bit(64×16 Bit)5. 有源晶振:50 MHz6. 电源芯片:LM1117-3.3V、LM1117-1.5V7. AS、JTAG调试接口8. 核心板尺寸:100mm×79mm套件包括:1. 一块已测试好的FPGA_Cyclone_EP1C3 核心板2. 配套光盘一张(模块例程,PDF格式原理图,相关技术文档,数据手册)可选配 ByteBlaster II 下载线Periphery_For_FPGA外设板Periphery_For_FPGA外设板特点:1. 该外设板是基于FPGA的硬件描述语言和软内核嵌入式系统的SOPC开发平台。
IQ51A使用手册
IQ51A单片机开发板使用手册V1.1产品简介 (4)系统简介 (7)系统资源 (7)实验项目 (8)扩展接口 (9)相关资料 (10)相关配件 (10)快速完整性检查 (10)第二章学习前准备工作 (12)2.1 硬件准备 (12)2.2 软件准备 (15)1.Keilc 的安装 (15)2 Keil C51的使用 (18)3 STC – ISP 的安装 (25)4 下载程序 (26)第三章硬件电路以及原理分析 (28)3.1 单片机理论总结以及DEMO电路分析 (28)3.2 LED原理 (32)3.3 LED数码管电路分析 (32)3.4 4*4矩阵键盘电路分析 (35)矩阵式键盘的按键识别方法确定矩阵式键盘上何键被按下介绍一种“行扫描法”。
行扫描法行扫描法又称为逐行(或列)扫描查询法,是一种最常用的按键识别方法,如上图所示键盘,介绍过程如下。
判断键盘中有无键按下将全部行线Y0-Y3置低电平,然后检测列线的状态。
只要有一列的电平为低,则表示键盘中有键被按下,而且闭合的键位于低电平线与4根行线相交叉的4个按键之中。
若所有列线均为高电平,则键盘中无键按下。
判断闭合键所在的位置在确认有键按下后,即可进入确定具体闭合键的过程。
其方法是:依次将行线置为低电平,即在置某根行线为低电平时,其它线为高电平。
在确定某根行线位置为低电平后,再逐行检测各列线的电平状态。
若某列为低,则该列线与置为低电平的行线交叉处的按键就是闭合的按键。
从而确定被按下的按键是哪个。
3.5 AD原理以及pcf8591电路分析 (39)3.6 DA原理以及电路分析 (40)3.7 8*8的LED阵列原理以及电路分析 (41)3.8 IIC总线原理分析 (41)3.9 EEPROM电路分析 (44)3.10 SRAM电路分析 (45)3.11 LCD原理以及接口电路分析 (46)3.12 蜂鸣器电路以及音乐原理 (47)3.13 继电器电路分析 (48)3.14 实时时钟原理以及电路分析 (49)3.15 单总线协议讲解 (49)3.16 单总线控制DS18B20的电路分析 (52)3.17 串口原理以及电路分析 (53)3.18 单片机下载电路分析 (54)3.19 USB转串口的电路分析 (54)3.20单片机DEMO电路分析 (54)第四章实验以及代码说明 (56)第一步:IO口端口操作 (56)4.1.1 流水灯实验 (56)4.1.2 继电器实现弱电控制强电实验 (58)4.1.3 键盘按下识别 (59)4.1.4 蜂鸣器音乐实验 (59)第二部:做一些简单外围功能的实现,主要还是端口操作 (60)4.2.1 静态数码管实验 (60)4.2.2 动态数码管实验 (60)4.2.3 LED阵列显示实验 (60)4.2.4 矩阵键盘扫描识别 (61)4.2.5 模块化规范编程 (62)4.2.6 IO模拟 iic总线读写EEPROM实验 (63)4.2.7 IO模拟单总线控制DS18b20测温实验 (63)第三步单片机内设以及外设的使用实验 (64)4.3.1 高速串口通信实验 (64)4.3.2中断函数应用1:定时器中断定时刷新数码管 (65)4.3.3 iic总线控制ADC实现模数转换 (66)4.3.4中断实验应用2:外部中断实现AD转换 (66)4.3.5 iic总线控制DAC实现数模转换 (66)4.3.6 高速SRAM读写实验 (66)4.3.7 彩色LCD显示实验 (67)第四步,DSP以及ARM基础的学习 (67)4.4.1 并行DSP通用ADC模数转换实验 (69)4.4.2 SRAM操作实验 (69)4.4.3LCD操作 (69)产品简介开发板图片系统简介STC89C54RD+是一款8位的高性能MCU,采用8051的内核,可以通过串口进行方便的程序烧写。
XILINX_VIRTEX-5
© 2006–2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other trade-marks are the property of their respective owners. PowerPC is a trademark of IBM, Inc. All specifications are subject to change without notice.Virtex-5 Electrical CharacteristicsVirtex™-5 FPGAs are available in -3, -2, -1 speed grades, with -3 having the highest performance.Virtex-5 D C and AC characteristics are specified for both commercial and industrial grades. Except the operating temperature range or unless otherwise noted, all the D C and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1 speed grade industrial device are the same as for a -1 speed grade commercial device). However, only selected speed grades and/or devices might be available in the industrial range.All supply voltage and junction temperature specifications are representative of worst-case conditions. The parame-ters included are common to popular designs and typical applications.This Virtex-5 data sheet, part of an overall set of documen-tation on the Virtex-5 family of FPGAs, is available on the Xilinx website:•Virtex-5 Family Overview •Virtex-5 User Guide•Virtex-5 Configuration Guide•Virtex-5 XtremeDSP™ Design Considerations •Virtex-5 Packaging and Pinout Specification•Virtex-5 RocketIO™ GTP Transceiver User Guide •Virtex-5 Tri-mode Ethernet MAC User Guide•Virtex-5 Integrated Endpoint Block User Guide for PCI Express® Designs•Virtex-5 System Monitor User Guide •Virtex-5 PCB Designer’s GuideAll specifications are subject to change without notice.Virtex-5 DC CharacteristicsVirtex-5 Data Sheet:DC and Switching CharacteristicsDS202 (v3.6) November 5, 2007Advance Product SpecificationTable 1: Absolute Maximum RatingsSymbolDescriptionUnitsV CCINT Internal supply voltage relative to GND –0.5 to 1.1V V CCAUX Auxiliary supply voltage relative to GND –0.5 to 3.0V V CCO Output drivers supply voltage relative to GND –0.5 to 3.75V V BATT Key memory battery backup supply –0.5 to 4.05V V REF Input reference voltage–0.5 to 3.75V V IN (3)3.3V I/O input voltage relative to GND (4) (user and dedicated I/Os)–0.75 to4.05V 2.5V or below I/O input voltage relative to GND (user and dedicated I/Os)–0.75 to V CCO + 0.5V V TSVoltage applied to 3-state 3.3V output (4) (user and dedicated I/Os)–0.75 to 4.05V Voltage applied to 3-state 2.5V or below output (user and dedicated I/Os)–0.75 to V CCO + 0.5V T STG Storage temperature (ambient)–65 to 150°C T SOL Maximum soldering temperature (2)+220°C T JMaximum junction temperature (2)+125°CNotes:1.Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.2.For soldering guidelines and thermal considerations, see UG195: Virtex-5 Packaging and Pinout Specification on the Xilinx website.3. 3.3V I/O absolute maximum limit applied to DC and AC signals.4.For 3.3V I/O operation, refer to UG190: Virtex-5 User Guide, Chapter 6, 3.3V I/O Design Guidelines .Table 2: Recommended Operating ConditionsSymbol Description Temperature Range Min Max UnitsV CCINT Internal supply voltage relative to GND, T J = 0°C to +85°C Commercial0.95 1.05V Internal supply voltage relative to GND, T J = –40°C to +100°C Industrial0.95 1.05VV CCAUX(1)Auxiliary supply voltage relative to GND, T J = 0°C to +85°C Commercial 2.375 2.625V Auxiliary supply voltage relative to GND, T J = –40°C to +100°C Industrial 2.375 2.625VV CCO(2,4,5)Supply voltage relative to GND, T J = 0°C to +85°C Commercial 1.14 3.45V Supply voltage relative to GND, T J = –40°C to +100°C Industrial 1.14 3.45VV IN 3.3V supply voltage relative to GND, T J = 0°C to +85°C Commercial GND – 0.20 3.45V 3.3V supply voltage relative to GND, T J = –40°C to +100°C Industrial GND – 0.20 3.45V 2.5V and below supply voltage relative to GND,T J = 0°C to +85°CCommercial GND – 0.20V CCO+ 0.2V2.5V and below supply voltage relative to GND,T J = –40°C to +100°CIndustrial GND – 0.20V CCO+ 0.2VI IN Maximum current through any pin in a powered or unpoweredbank when forward biasing the clamp diode.Commercial10mAIndustrial10mAV BA TT(3)Battery voltage relative to GND, T J = 0°C to +85°C Commercial 1.0 3.6V Battery voltage relative to GND, T J = –40°C to +100°C Industrial 1.0 3.6VNotes:1.Recommended maximum voltage drop for V CCAUX is 10 mV/ms.2.Configuration data is retained even if V CCO drops to 0V.3.V BATT is required only when using bitstream encryption. If battery is not used, connect V BATT to either ground or V CCAUX.4.Includes V CCO of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V.5.The configuration supply voltage V CC_CONFIG is also known as V CCO_0Table 3: DC Characteristics Over Recommended Operating ConditionsSymbol Description Data Rate Min Typ Max Units V DRINT Data retention V CCINT voltage (below which configuration data might be lost)0.75V V DRI Data retention V CCAUX voltage (below which configuration data might be lost) 2.0VI REF V REF leakage current per pin10µAI L Input or output leakage current per pin (sample-tested)10µAC IN Input capacitance (sample-tested)8pFI RPU(1)Pad pull-up (when selected) @ V IN = 0V, V CCO = 3.3V20150µAPad pull-up (when selected) @ V IN = 0V, V CCO = 2.5V1090µAPad pull-up (when selected) @ V IN = 0V, V CCO = 1.8V545µAPad pull-up (when selected) @ V IN = 0V, V CCO = 1.5V330µAPad pull-up (when selected) @ V IN = 0V, V CCO = 1.2V215µAI RPD(1)Pad pull-down (when selected) @ V IN = 2.5V 5110µA I BATT(2)Battery supply current150nAn Temperature diode ideality factor 1.0002n r Series resistance 5.0ΩNotes:1.Typical values are specified at nominal voltage, 25°C.2.Maximum value specified for worst case process at 25°C.Important NoteTypical values for queiscent supply current are now specified at nominal voltage, 85ºC junction temperatures (T j). Xilinx recommends analyzing static power consumption at T j = 85ºC because the majority of designs operate near the high end of the commercial temperature range. D ata sheets for older products (e.g., Virtex-4 devices) still specify typical quiescent supply current at T j = 25ºC. Queiscent supply current is specified by speed grade for Virtex-5 devices. Use the XPOWER™ Estimator (XPE) spreadsheet tool (download at /power) to calculate static power consumption for conditions other than those specified in Table 4.Table 4: Typical Quiescent Supply CurrentSymbol Description DeviceSpeed and Temperature Grade Units -3 (C)-2 (C & I)-1 (C & I)I CCINTQ Quiescent V CCINT supply current XC5VLX30480480300mAXC5VLX30T507507317mAXC5VLX50651651449mAXC5VLX50T689689475mAXC5VLX8510721072883mAXC5VLX85T11151115866mAXC5VLX110139113911109mAXC5VLX110T144814481154mAXC5VLX220N/A27832278mAXC5VLX220T N/A28442328mAXC5VLX330N/A41933432mAXC5VLX330T N/A42673492mAXC5VSX35T720720554mAXC5VSX50T10921092840mAXC5VSX95T N/A19241475mA I CCOQ Quiescent V CCO supply current XC5VLX30 1.5 1.5 1.5mAXC5VLX30T 1.5 1.5 1.5mAXC5VLX50222mAXC5VLX50T222mAXC5VLX85333mAXC5VLX85T333mAXC5VLX110444mAXC5VLX110T444mAXC5VLX220N/A88mAXC5VLX220T N/A88mAXC5VLX330N/A1212mAXC5VLX330T N/A1212mAXC5VSX35T 1.5 1.5 1.5mAXC5VSX50T222mAXC5VSX95T N/A44mAPower-On Power Supply RequirementsXilinx FPGAs require a certain amount of supply current during power-on to insure proper device initialization. The actual current consumed depends on the power-on ramp rate of the power supply.The power supplies can be can be turned on in any sequence, though the specifications shown in Table 5 are for the recommended power-on sequence of V CCINT , V CCAUX , and V CCO . Xilinx does not specify the current for other power-on sequences.Table 5 shows the minimum current required by Virtex-5devices for proper power-on and configuration.If the current minimums shown in Table 5 are met, the device powers on properly after all three supplies have passed through their power-on reset threshold voltages.The FPGA must be configured after V CCINT is applied.Once initialized and configured, use the XPOWER tools to estimate current drain on these supplies.I CCAUXQQuiescent V CCAUX supply currentXC5VLX30383838mA XC5VLX30T 434343mA XC5VLX50575757mA XC5VLX50T 626262mA XC5VLX85939393mA XC5VLX85T 989898mA XC5VLX110125125125mA XC5VLX110T 130130130mA XC5VLX220N/A 229229mA XC5VLX220T N/A 236236mA XC5VLX330N/A 345345mA XC5VLX330T N/A 353353mA XC5VSX35T 494949mA XC5VSX50T 747474mA XC5VSX95TN/A131131mANotes:1.Typical values are specified at nominal voltage, 85°C junction temperatures (T j ). Industrial(I) grade devices have the same typical values ascommercial (C) grade devices at 85°C, but higher values at 100°C. Use the XPE tool to calculate 100°C values.2.Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating.3.If DCI or differential signaling is used, more accurate quiescent current estimates can be obtained by using the XPOWER Estimator (XPE) orXPOWER Analyzer (XPA) tools.Table 4: Typical Quiescent Supply Current (Continued)SymbolDescriptionDeviceSpeed and Temperature GradeUnits-3 (C)-2 (C & I)-1 (C & I)Table 5: Power-On Current for Virtex-5 DevicesDevice I CCINTMINI CCAUXMINI CCOMINUnits Typ (1)MaxTyp (1)MaxTyp (1)MaxXC5VLX302357650mA XC5VLX30T 2468650mA XC5VLX5032011450mA XC5VLX50T 33612450mA XC5VLX85492186100mA XC5VLX85T515196100mASelectIO™ DC Input and Output LevelsValues for V IL and V IH are recommended input voltages. Values for I OL and I OH are guaranteed over the recom-mended operating conditions at the V OL and V OH test points. Only selected standards are tested. These are cho-sen to ensure that all standards meet their specifications. The selected standards are tested at a minimum V CCO with the respective V OL and V OH voltage levels shown. Other standards are sample tested.XC5VLX110623250100mA XC5VLX110T 651260100mA XC5VLX2201023458150mA XC5VLX220T 1056472150mA XC5VLX3301470690150mA XC5VLX330T 1509706150mA XC5VSX35T 3079850mA XC5VSX50T 47214850mA XC5VSX95T804262100mANotes:1.Typical values are specified at nominal voltage, 25°C.Table 5: Power-On Current for Virtex-5 Devices (Continued)Device I CCINTMINI CCAUXMINI CCOMINUnits Typ (1)MaxTyp (1)MaxTyp (1)MaxTable 6: Power Supply Ramp TimeSymbol DescriptionRamp Time Units V CCINT Internal supply voltage relative to GND 0.20 to 50.0ms V CCO Output drivers supply voltage relative to GND 0.20 to 50.0ms V CCAUXAuxiliary supply voltage relative to GND0.20 to 50.0msTable 7: SelectIO DC Input and Output Levels I/O StandardV ILV IHV OLV OH I OL I OH V, MinV, MaxV, MinV, MaxV, MaxV, MinmAmALVTTL –0.30.8 2.0 3.450.4 2.4Note(3)Note(3)LVCMOS33, LVDCI33–0.30.8 2.0 3.450.4V CCO – 0.4Note(3)Note(3)LVCMOS25, LVDCI25–0.30.7 1.7V CCO + 0.30.4V CCO – 0.4Note(3)Note(3)LVCMOS18, LVDCI18–0.335% V CCO 65% V CCO V CCO + 0.30.45V CCO – 0.45Note(4)Note(4)LVCMOS15, LVDCI15–0.335% V CCO 65% V CCO V CCO + 0.325% V CCO 75% V CCO Note(4)Note(4)LVCMOS12–0.335% V CCO 65% V CCO V CCO + 0.325% V CCO 75% V CCO Note(6)Note(6)PCI33_3(5)–0.230% V CCO 50% V CCO V CCO 10% V CCO 90% V CCO Note(5)Note(5)PCI66_3(5)–0.230% V CCO 50% V CCO V CCO 10% V CCO 90% V CCO Note(5)Note(5)PCI-X (5)–0.235% V CCO50% V CCOV CCO10% V CCO90% V CCONote(5)Note(5)GTLP –0.3V REF – 0.1V REF + 0.1–0.6N/A 36N/A GTL –0.3V REF – 0.05V REF + 0.05–0.4N/A 32N/A HSTL I_12–0.3V REF – 0.1V REF + 0.1V CCO + 0.325% V CCO75% V CCO 6.3 6.3HSTL I (2)–0.3V REF – 0.1V REF + 0.1V CCO + 0.30.4V CCO – 0.48–8HSTL II (2)–0.3V REF – 0.1V REF + 0.1V CCO + 0.30.4V CCO – 0.416–16HSTL III (2)–0.3V REF – 0.1V REF + 0.1V CCO + 0.30.4V CCO – 0.424–8HSTL IV (2)–0.3V REF – 0.1V REF + 0.1V CCO + 0.30.4V CCO – 0.448–8DIFF HSTL I (2)–0.350% V CCO – 0.150% V CCO + 0.1V CCO + 0.3––––DIFF HSTL II (2)–0.350% V CCO – 0.150% V CCO + 0.1V CCO + 0.3––––SSTL2 I –0.3V REF – 0.15V REF + 0.15V CCO + 0.3V TT – 0.61V TT + 0.618.1–8.1SSTL2 II –0.3V REF – 0.15V REF + 0.15V CCO + 0.3V TT – 0.81V TT + 0.8116.2–16.2DIFF SSTL2 I –0.350% V CCO – 0.1550% V CCO + 0.15V CCO + 0.3––––DIFF SSTL2 II –0.350% V CCO – 0.1550% V CCO + 0.15V CCO + 0.3––––SSTL18 I –0.3V REF – 0.125V REF + 0.125V CCO + 0.3V TT – 0.47V TT + 0.47 6.7–6.7SSTL18 II –0.3V REF – 0.125V REF + 0.125V CCO + 0.3V TT – 0.60V TT + 0.6013.4–13.4DIFF SSTL18 I –0.350% V CCO – 0.12550% V CCO + 0.125V CCO + 0.3––––DIFF SSTL18 II–0.350% V CCO – 0.12550% V CCO + 0.125V CCO + 0.3––––Notes:1.Tested according to relevant specifications.2.Applies to both 1.5V and 1.8V HSTL.ing drive strengths of 2, 4, 6, 8, 12, 16, or 24 mA.ing drive strengths of 2, 4, 6, 8, 12, or 16 mA.5.For more information on PCI33_3, PCI66_3, and PCI-X, refer to refer to UG190: Virtex-5 User Guide, Chapter 6, 3.3V I/O Design Guidelines .6.Supported drive strengths of 2, 4, 6, or 8 mA.Table 7: SelectIO DC Input and Output Levels (Continued)I/O StandardV ILV IHV OLV OH I OL I OH V, MinV, MaxV, MinV, MaxV, MaxV, MinmAmAHT DC Specifications (HT_25)LVDS DC Specifications (LVDS_25)Extended LVDS DC Specifications (LVDSEXT_25)Table 8: HT DC Specifications Symbol DC ParameterConditionsMin Typ Max Units V CCO Supply Voltage2.38 2.5 2.63V V OD Differential Output Voltage R T = 100 Ω across Q and Q signals495600715mV Δ V OD Change in V OD Magnitude –1515mV V OCM Output Common Mode Voltage R T = 100 Ω across Q and Q signals 495600715mV Δ V OCM Change in V OCM Magnitude –1515mV V ID Input Differential Voltage 2006001000mV Δ V ID Change in V ID Magnitude –1515mV V ICM Input Common Mode Voltage 440600780mV Δ V ICMChange in V ICM Magnitude–1515mVTable 9: LVDS DC Specifications Symbol DC ParameterConditionsMin Typ Max Units V CCO Supply Voltage2.382.52.63V V OH Output High Voltage for Q and Q R T = 100 Ω across Q and Q signals 1.675V V OL Output Low Voltage for Q and QR T = 100 Ω across Q and Q signals0.825V V ODIFF Differential Output Voltage (Q – Q), Q = High (Q – Q), Q = High R T = 100 Ω across Q and Q signals 247350600mV V OCM Output Common-Mode Voltage R T = 100 Ω across Q and Q signals1.125 1.250 1.375V V IDIFF Differential Input Voltage (Q – Q), Q = High (Q – Q), Q = High 100350600mV V ICMInput Common-Mode Voltage0.31.22.2VTa ble 10: Extended LVDS DC Specifications Symbol DC ParameterConditionsMin Typ Max Units V CCO Supply Voltage2.382.5 2.63V V OH Output High Voltage for Q and Q R T = 100 Ω across Q and Q signals – 1.785V V OL Output Low Voltage for Q and QR T = 100 Ω across Q and Q signals0.715––V V ODIFF Differential Output Voltage (Q – Q), Q = High (Q – Q), Q = High R T = 100 Ω across Q and Q signals 350–820mV V OCM Output Common-Mode Voltage R T = 100 Ω across Q and Q signals 1.125 1.250 1.375V V IDIFF Differential Input Voltage (Q – Q), Q = High (Q – Q), Q = High Common-mode input voltage = 1.25V 100–1000mV V ICMInput Common-Mode VoltageDifferential input voltage = ±350 mV0.31.22.2VLVPECL DC Specifications (LVPECL_25)These values are valid when driving a 100Ω differential load only, i.e., a 100Ω resistor between the two receiver pins. The V OH levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant of lower com-mon-mode ranges. Table 11 summarizes the D C output specifications of LVPECL. For more information on using LVPECL, see UG190: Virtex-5 User Guide, Cha pter 6, SelectIO Resources.Ta ble 11: LVPECL DC SpecificationsSymbol DC Parameter Min Typ Max Units V OH Output High Voltage V CC – 1.025 1.545V CC – 0.88V V OL Output Low Voltage V CC – 1.810.795V CC – 1.62V V ICM Input Common-Mode Voltage0.6 2.2V V IDIFF Differential Input Voltage(1,2)0.100 1.5V Notes:1.Recommended input maximum voltage not to exceed V CCAUX + 0.2V.2.Recommended input minimum voltage not to go below –0.5V.RocketIO GTP Transceiver SpecificationsRocketIO GTP Transceiver DC CharacteristicsTa ble 12: Absolute Maximum RatingsSymbol Description Units MGTAVCCPLL Analog supply voltage for the GTP_DUAL shared PLL relative to GND–0.5 to 1.32V MGTAVTTTX Analog supply voltage for the GTP_DUAL transmitters relative to GND–0.5 to 1.32V MGT AVTTRX Analog supply voltage for the GTP_DUAL receivers relative to GND–0.5 to 1.32V MGTAVCC Analog supply voltage for the GTP_DUAL common circuits relative to GND–0.5 to 1.32V–0.5 to 1.32V MGT AVTTRXC Analog supply voltage for the resistor calibration circuit of the GTP_DUALcolumnNotes:1.Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.Ta ble 13: Recommended Operating Conditions(1)(2)Symbol Description Min Max Units MGT AVCCPLL(1)Analog supply voltage for the GTP_DUAL shared PLL relative to GND 1.14 1.26V MGT AVTTTX(1)Analog supply voltage for the GTP_DUAL transmitters relative to GND 1.14 1.26V MGTAVTTRX(1)Analog supply voltage for the GTP_DUAL receivers relative to GND 1.14 1.26V MGT AVCC(1)Analog supply voltage for the GTP_DUAL common circuits relative to GND0.95 1.05V1.14 1.26V MGTAVTTRXC(1)Analog supply voltage for the resistor calibration circuit of the GTP_DUALcolumnNotes:1.Each voltage listed requires the filter circuit described in UG196: Virtex-5 RocketIO GTP T ransceiver User Guide.2.Voltages are specified for the temperature range of T J = –40°C to +100°C.Ta ble 14: DC Characteristics Over Recommended Operating Conditions(2)Symbol Description Min Typ Max UnitsI MGTAVTTTX GTP_DUAL tile transmitter termination supply current(3)7190mAI MGTAVCCPLL GTP_DUAL tile shared PLL supply current3660mAI MGTAVTTRXC GTP_DUAL tile resistor termination calibration supply current0.10.5mAI MGTAVTTRX GTP_DUAL tile receiver termination supply current(3)0.10.5mAI MGTAVCC GTP_DUAL tile internal analog supply current56110mAR REF Precision reference resistor for internal calibration termination49.55050.5ΩNotes:1.Typical values are specified at nominal voltage, 25°C, with a 3.2 Gb/s line rate.2.I CC numbers are given per GTP_DUAL tile with both GTP devices operating with default settings.3.AC coupled TX/RX link.Ta ble 15: Quiescent Supply CurrentSymbol Description Device Typ(1)Max UnitsI CCINTQ Quiescent internal supply current XC5VLX30T mAXC5VLX50T mAXC5VLX85T mAXC5VLX110T mAXC5VLX220T mAXC5VLX330T mAXC5VSX35T mAXC5VSX50T mAXC5VSX95T mAI VTTTXQ Quiescent transmitter supply current XC5VLX30T mAXC5VLX50T mAXC5VLX85T mAXC5VLX110T mAXC5VLX220T mAXC5VLX330T mAXC5VSX35T mAXC5VSX50T mAXC5VSX95T mA I AVCCPLLQ Quiescent GTP_DUAL PLL supply current XC5VLX30T mAXC5VLX50T mAXC5VLX85T mAXC5VLX110T mAXC5VLX220T mAXC5VLX330T mAXC5VSX35T mAXC5VSX50T mAXC5VSX95T mAI VTTRXCQ Quiescent receiver termination switching supply current XC5VLX30T mAXC5VLX50T mAXC5VLX85T mAXC5VLX110T mAXC5VLX220T mAXC5VLX330T mAXC5VSX35T mAXC5VSX50T mAXC5VSX95T mATa ble 15: Quiescent Supply Current (Continued)Symbol Description Device Typ(1)Max UnitsI TTRXQ Quiescent receiver termination supply current XC5VLX30T mAXC5VLX50T mAXC5VLX85T mAXC5VLX110T mAXC5VLX220T mAXC5VLX330T mAXC5VSX35T mAXC5VSX50T mAXC5VSX95T mAI VCCQ Quiescent internal analog supply current XC5VLX30T mAXC5VLX50T mAXC5VLX85T mAXC5VLX110T mAXC5VLX220T mAXC5VLX330T mAXC5VSX35T mAXC5VSX50T mAXC5VSX95T mA Notes:1.Typical values are specified at nominal voltage, 25°C.2.Given for entire die. Powered and unconfigured.3.Unconnected (if channel is driven to voltage).4.More accurate quiescent current estimates can be obtained by using the XPOWER Estimator (XPE) or XPOWER Analyzer (XPA) tools.RocketIO GTP Transceiver DC Input and Output LevelsTable 16 summarizes the D C output specifications of the Virtex-5 RocketIO GTP Transceivers. Figure 1 shows the single-ended output voltage swing. Figure 2 shows the peak-to-peak differential output voltage. Consult UG196: Virtex-5 RocketIO GTP T ransceiver User Guide for further details.Ta ble 16: GTP Transceiver DC SpecificationsSymbolDC ParameterConditionsMinTyp MaxUnitsDV PPIN Differential peak-to-peak inputvoltageExternal AC coupled ≤ 3.2 Gb/s 1502000mV External AC coupled > 3.2 Gb/s 1802000mV V IN Absolute input voltage DC coupledMGT AVTTRX = 1.2V –4001200mV V CMIN Common mode input voltage DC coupledMGT AVTTRX = 1.2V 800mV DV PPOUT Differential peak-to-peak output voltage (1)TXBUFDIFFCTRL = 000, TX_DIFF_BOOST = ON 1400mV V SEOUT Single-ended output voltage swing (1)TXBUFDIFFCTRL = 000, TX_DIFF_BOOST = ON700mV V CMOUT Common mode output voltage Equation basedMGT AVTTTX = 1.2V 1200 – Amplitude/2mVR IN Differential input resistance 90100120ΩR OUT Differential output resistance 90100120ΩT OSKEW T ransmitter output skew15ps C EXTRecommended external AC coupling capacitor (2)75100200nFNotes:1.The output swing and preemphasis levels are programmable using the attributes discussed in UG196:Virtex-5 RocketIO GTP Transceiver UserGuide and can result in values lower than reported in this table.2.Values outside of this range can be used as appropriate to conform to specific protocols and standards.Figure 1: Single-Ended Output Voltage SwingFigure 2: Peak-to-Peak Differential Output VoltageTable 17 summarizes the DC input specifications of the Virtex-5 RocketIO GTP Transceivers. Figure 3 shows the single-ended input voltage swing. Figure 4 shows thepeak-to-peak differential clock input voltage swing. Consult UG196: Virtex-5 RocketIO GTP Transceiver User Guide for further details.Ta ble 17: RocketIO GTP Clock DC Input Level Specification (1)SymbolDC ParameterConditions MinTypMaxUnitsDV PPIN Differential peak-to-peak input voltage2008002000mV V SEIN Single-ended input voltage 1004001000mVR IN Differential input resistance80105130ΩCEXTRequired external AC coupling capacitor75100200nFNotes:1.V MIN = 0V and V MAX = 1200mVFigure 3: Single-Ended Clock Input Voltage Swing Peak-to-PeakFigure 4: Differential Clock Input Voltage Swing Peak-to-PeakRocketIO GTP Switching CharacteristicsConsult UG196:Virtex-5 RocketIO GTP Transceiver User Guide for further information. Ta ble 18: GTP Transceiver PerformanceSymbol DescriptionSpeed GradeUnits -3-2-1F GTPMAX Maximum GTP transceiver data rate 3.75 3.75 3.2Gb/s F GPLLMAX Maximum PLL frequency 2.0 2.0 2.0GHz F GPLLMIN Minimum PLL frequency 1.0 1.0 1.0GHzTa ble 19: CRC Block Switching CharacteristicsSymbol DescriptionSpeed GradeUnits -3-2-1F CRC CRCCLK maximum frequency320320250MHzTa ble 20: GTP Transceiver Reference Clock Switching CharacteristicsAll Speed GradesUnits Symbol Description Conditions Min Typ MaxF GCLK Reference clock frequency range(1)CLK60350MHzT RCLK Reference clock rise time20% – 80%200400ps T FCLK Reference clock fall time80% – 20%200400ps T DCREF Reference clock duty cycle CLK455055% T GJTT Reference clock total jitter, peak-peak(2)CLK40ps T LOCK Clock recovery frequency acquisitiontimeInitial PLL lock1msT PHASE Clock recovery phase acquisition time Lock to data after PLL hasrelocked to the reference clock.Includes lock to reference time.200µsNotes:1.The clock from the GTP_DUAL differential clock pin pair can be used for all serial bit rates. GREFCLK can be used for serial bit rates up to 1 Gb/s.2.Measured at the package pin.Figure 5: Reference Clock Timing ParametersTa ble 21: GTP User Clock Switching Characteristics(1)Speed GradeUnits Symbol Description Conditions-3-2-1F TXOUT TXOUTCLK maximum frequency375375320MHz F RXREC RXRECCLK maximum frequency375375320MHzT RX RXUSRCLK maximum frequency375375320MHzT RX2RXUSRCLK2 maximum frequency RXDA TAWIDTH = 0350350320MHz RXDA TAWIDTH = 1187.5187.5160MHzT TX TXUSRCLK maximum frequency375375320MHzT TX2TXUSRCLK2 maximum frequency TXDA T AWIDTH = 0350350320MHz TXDA T AWIDTH = 1187.5187.5160MHzNotes:1.Clocking must be implemented as described in UG196: Virtex-5 RocketIO GTP T ransceiver User GuideTa ble 22: GTP Transmitter Switching CharacteristicsSymbol Description Min Typ Max UnitsF GTX Serial data rate range0.1F GTPMAX Gb/sT RTX TX Rise time140ps T FTX TX Fall time120ps T LLSKEW TX lane-to-lane skew(1) 2 + 500 ps UI V TXOOBVDPP Electrical idle amplitude20mV T TXOOBTRANS Electrical idle transition time40ns T J3.75T otal Jitter(2) 3.75 Gb/s0.35UID J3.75Deterministic Jitter(2)0.19UIT J3.2T otal Jitter(2) 3.20 Gb/s0.35UID J3.2Deterministic Jitter(2)0.19UIT J2.5T otal Jitter(2) 2.50 Gb/s0.30UID J2.5Deterministic Jitter(2)0.14UIT J2.0T otal Jitter(2) 2.00 Gb/s0.30UID J2.0Deterministic Jitter(2)0.14UIT J1.25T otal Jitter(2) 1.25 Gb/s0.20UID J1.25Deterministic Jitter(2)0.10UIT J1.00T otal Jitter(2) 1.00 Gb/s0.20UID J1.00Deterministic Jitter(2)0.10UIT J500T otal Jitter(2)500 Mb/s0.10UID J500Deterministic Jitter(2)0.04UIT J100T otal Jitter(2)100 Mb/s0.02UID J100Deterministic Jitter(2)0.01UI Notes:ing same REFCLK input with TXENPMAPHASEALIGN enabled for up to four consecutive GTP_DUAL sites.ing PLL_DIVSEL_FB = 2, INTDATAWIDTH = 1.3.All jitter values are based on a Bit-Error Ratio of 1e–12.Ethernet MAC Switching CharacteristicsConsult UG194:Virtex-5 T ri-mode Ethernet Media Access Controller User Guide for further information.Ta ble 23: GTP Receiver Switching CharacteristicsSymbolDescriptionMin Typ Max Units F GRX Serial data rate RX oversampler not enabled 0.5F GTPMAXGb/s RX oversampler enabled0.10.5Gb/s R XOOBVDPP OOB detect threshold peak-to-peakOOBDETECT_THRESHOLD = 10060105165mV R XSST Receiver spread-spectrum tracking (1)Modulated @ 33 KHz–50000ppm R XRL Run length (CID)Internal AC capacitor bypassed 150UI R XPPMTOLData/REFCLK PPM offset toleranceACDR 2nd -order loop enabled–10001000ppmSJ Jitter ToleranceJT_SJ 3.75Sinusoidal Jitter (2) 3.75 Gb/s 0.30UI JT_SJ 3.2Sinusoidal Jitter (2) 3.20 Gb/s 0.40UI JT_SJ 2.50Sinusoidal Jitter (2) 2.50 Gb/s 0.40UI JT_SJ 2.00Sinusoidal Jitter (2) 2.00 Gb/s 0.40UI JT_SJ 1.00Sinusoidal Jitter (2) 1.00 Gb/s 0.30UI JT_SJ 500Sinusoidal Jitter (2)500 Mb/s 0.30UI JT_SJ 500Sinusoidal Jitter (2)500 Mb/s OS 0.30UI JT_SJ 100Sinusoidal Jitter (2)100 Mb/s OS0.30UISJ Jitter Tolerance with Stressed EyeJT_TJSE 3.2T otal Jitter with Stressed Eye (3)3.20 Gb/s 0.87UI JT_SJSE 3.2Sinusoidal Jitter with Stressed Eye (3)3.20 Gb/s0.30UINotes:ing PLL_RX_DIVSEL_OUT = 1.ing 80 MHz sinusoidal jitter only in the absence of deterministic and random jitter.3.Stimulus signal includes 0.4UI of DJ and 0.17UI of RJ. RX equalizer is enabled.4.All jitter values are based on a Bit Error Ratio of 1e –12.Ta ble 24: Maximum Ethernet MAC PerformanceDescriptionSpeed GradeUnits-3-2-1Ethernet MAC Maximum Performance10/100/1000Mb/s。
fpga使用手册
fpga使用手册
FPGA(Field Programmable Gate Array)是一种可编程逻辑器件,其内部逻辑和布线可以根据用户的需求进行配置。
FPGA具有高度的灵活性和可编程性,可以用于各种数字系统设计,如通信、图像处理、控制等。
在使用FPGA时,首先需要了解FPGA的基本结构和原理。
FPGA由许多逻辑块和布线组成,每个逻辑块可以配置为不同的逻辑门,如AND、OR、XOR等。
布线则用于连接逻辑块,以实现复杂的数字逻辑功能。
在FPGA开发过程中,通常使用硬件描述语言(如Verilog 或VHDL)进行设计。
这些语言可以描述数字系统的行为和结构,然后通过编译器将设计转换为FPGA的配置文件。
在使用FPGA时,还需要注意以下几点:
1.选择合适的FPGA芯片:根据项目需求选择合适的FPGA芯片,包括芯片的逻辑资源、内存大小、I/O端口等。
2.设计合适的硬件架构:根据项目需求设计合适的硬件架构,包括处理器的选择、内存的配置、接口的设计等。
3.优化代码:在编写硬件描述语言时,需要注意代码的优化,以减少资源占用和提高运行速度。
4.调试和测试:在将设计编译为配置文件并下载到FPGA 后,需要进行调试和测试,以确保设计的正确性和可靠性。
总之,使用FPGA需要一定的硬件设计和编程经验,但
通过不断学习和实践,可以逐渐掌握FPGA的使用技巧和方法。
FPGA助学板教材-睿智FPGA开发板硬件详解
FPGA助学板教材-睿智FPGA开发板硬件详解睿智FPGA助学板硬件详解开发板套件硬件是保证实验学习的基础,这部分内容主要针对硬件部分做简单描述,可适当阅读或翻查,特别是涉及到硬件接⼝定义等信息时,了解这部分内容很有必要。
同时,可与光盘附带的硬件原理图⼀并参考使⽤。
1.睿智FPGA助学板硬件1.1 总体介绍图1 助学板硬件实拍图主硬件资源1 .主芯⽚采⽤ALTERA公司最新四代FPGA CycloneIV系列EP4CE6E22C8N;2 .板载EPCS4N/EPCS16⼤容量串⾏配置芯⽚,⽀持JTAG/AS模式;3. 板载64MbitSDRAM,⽀持SOPC,NIOSII开发(很多价低的板不带SDRAM,⽆法⽀持NIOS SOPC开发);4 .板载50MHz有源晶振,提供系统⼯作主时钟;5 .采⽤1117-3.3V稳压芯⽚,提供3.3V电压输出;6 .采⽤1117-1.2V稳压芯⽚,提供FPGA内核电压;7 .采⽤1117-2.5V稳压芯⽚,提供PLL电压;8 .精⼼的去耦设计,采⽤⼤量去耦电容;9. 提供5V直流电源插座;10. 提供⽅⼝USB接⼝电源插座;11. ⼀个系统复位按键Reset,也可做为⽤户输⼊按键;12. ⾃锁按键电源开关;13. LED电源指⽰灯;14. 精⼼设计分配的IO资源,所有IO引出,3个扩展接⼝,通⽤2.54mm间距,任由您⾃⼰扩展;15.JTAG下载接⼝对应下载的⽂件是.SOF,速度快,平常学习推荐使⽤此接⼝;16. AS下载接⼝对应下载的⽂件是.POF,速度较慢,需要固化程序时使⽤。
丰富外设资源1 .板载4个独⽴按键,可做按键控制,数字逻辑基础实验等;2 .板载4位LED发光⼆极管,可做LED控制,数字逻辑基础实验等;3. 板载4位数码管,频率计,秒表;4. 板载4位拨码开关,可做开关控制等实验;5 .设有1X20液晶屏排座,⽀持LCD1602,LCD12864,TFT液晶屏(不包括LCD,需另购);6 .精密可调电阻,调节液晶背光;7 .板载1路蜂鸣器,可做发声及⾳乐实验;8 .PS2接⼝,可做PS/2键盘实验;9 .板载全新原装进⼝温度传感器芯⽚LM75A,可以做温度计实验;10 .RS232串⼝,可做串⼝通讯实验;11 .VGA接⼝,可做显⽰器实验等;12. I2C串⾏EEPROM AT24C08,做IIC总线实验;13 .红外线接收模块;1.2 FPGA的IO分配FPGA的硬件设计与单⽚机,ARM或DSP还是有所不同,MCU的IO通常功能都是固定好的,Datasheet要求某个引脚什么功能,就必须是什么功能。
usb-fpga-开发板使用手册说明书
USB FPGA 开发板使用手册一、开发板简介USB FPGA开发板在设计上充分考虑到实际应用的需要,增强了FPGA扩展能力和处理能力,使之能更好的适合更复杂的应用。
板上扩展了两容量64M字节总线独立的SDRAM存储器,使板卡能更适合于数据计算和数据传输缓存,同时采用CYPRESS公司的USB2.0高速传输芯片,保证了板卡的数据传输能力。
板卡扩展了FPGA的84个端口,足以保证实际的外部连接需要。
同时增加了一片MAX3232电平转换芯片,使之与FPGA连接,可以设计FPGA的串口数据传输通信。
板卡同时支持USB供电和外部供电方式,板载的3.3V电源芯片足够提供3A 的电流,可以为外部板卡提供电源。
板卡的提供大量的实际有价值的程序,并且我们将不断的升级和开发使用与这个板卡的应用程序。
板卡上大容量的SDRAM足以在FPGA上运行NIOSII操作系统。
考虑到FPGA的管脚数量有限,而且已经给FPGA配置了EPSC4,因此未扩展FLASH 存储器。
我们为这个板卡开辟专门的技术交流网页,应用程序将在上面更新。
二、板上主要芯片:USB芯片:CY7C68013A‐56FGPA芯片:EP2C8Q208C8SDRAM芯片两片:MT48LC16M16A2FPGA配置芯片:EPCS4串口收发芯片:MAX3232ESEEEPROM芯片: 24LC643.3V LDO:LM1085‐3.31.2V LDO:LM1117‐1.250MHZ有源晶振三、电路板硬件说明1. 电路板实物图1:FPGA的AS模式下载接口2:FPGA的JTAG模式下载接口3:4个与FPGA管脚相连的LED4:FPGA的配置程序重新加载按键5:MT48LC16M16A2 SDRAM存储器6:CY7C68013A程序存储器EEPROM 24LC647:CY7C68013A芯片8:FPGA EP2C8Q2089: 串口电平转换芯片MAX323210:MT48LC16M16A2 SDRAM存储器11:FPGA 的外部有源时钟12:CY7C68013A 的复位按键13:USB接口14:外部5V电源输入,提供给板子电源(可以不接,由USB接口提供电源输入) 2. 电路板的管脚分配详细的管教分配请看文档 《USBFPGA第四版硬件配置手册.pdf》。
FPGA开发板 使用说明书
目录第一章 综述 (1)其次章 系统模块 (1)第三章 软件的介绍 (10)第四章 USB 电缆的安装与运用 (27)第一章 综述THSOPC-3型FPGA开发板是依据现代电子发展的方向,集EDA和SOPC系统开发为一体的综合性试验开发板,除了满意高校专、本科生和探讨生的SOPC教学试验开发之外,也是电子设计和电子项目开发的志向工具。
一、好用范围:●自主创新应用开发;●单片机与FPGA联合开发;●IC设计硬件仿真;●科研项目硬件验证与开发;●高速高档自主学问产权电子产品开发;●毕业设计平台;●探讨生课题开发;●电子设计竞赛培训;●现代DSP开发应用;●针对各类CPU IP核的片上系统开发;●DSP Biulder系统设计。
二、硬件配置:THSOPC-3型FPGA开发板基于Altera Cyclone II 器件的嵌入式系统开发供应了一个很好的硬件平台,它可以为开发人员供应以下资源:●支持+5V 电源适配器干脆输入或者USB接口供电,5V、3.3V、1.2V混合电压源;●FPGACycloneII FPGA EP2C8,40万门,2个锁相环;●isp单片机AT89S8253。
isp单片机AT89S8253及开发编程工具,MCS51兼容,12KB isp可编程Flash ROM,2KB ispEEPROM,都是10万次烧写周期;2.7-5.5V工作电压;0-24MHz工作时钟;可编程看门狗;增加型SPI串口,9个中断源等。
此单片机可与FPGA联合开发,特别符合实现当今电子设计竞赛项目的功能与指标实现;●EPM3032 CPLD;● 4 Mbits 的EPCS4 配置芯片;●512KB高速SRAM;●20MHz 高精度时钟源(可倍频到300MHz);● 4 个用户自定义按键;●8 个用户自定义开关;●8 个用户自定义LED;● 2 个七段码LED;●标准AS 编程接口和JTAG调试接口;●两个标准2.54mm扩展接口,供用户自由扩展;●RS-232 DB9串行接口;●PS/2键盘接口;●VGA 接口;●4X4键盘;●液晶显示屏20字X4行;●USB-Blaster 编程器,可对FPGA 通过JTAG 口编程、调试、测试;单片机编程ByterBlasreMV 编程器;●光盘:配套子程序库、资料、编程软件、试验指导书。
ARTIX-7 FPGA 核心板 用户手册说明书
ARTIX-7 FPGA核心板用户手册AX7A035BREV 1.1版芯驿电子科技(上海)有限公司目录一、开发板简介 (5)二、FPGA核心板 (8)(一)简介 (8)(二)FPGA (9)(三)有源差分晶振 (11)(四)DDR3 (12)(五)QSPI Flash (15)(六)LED灯 (17)(七)JTAG接口 (17)(八)电源接口 (18)(九)扩展接口 (18)(十)电源 (25)(十一)结构图 (28)三、扩展板 (29)(一)简介 (29)(二)千兆以太网接口 (30)(三)光纤接口 (31)(四)PCIe x4接口 (33)(五)HDMI输出接口 (34)(六)HDMI输入接口 (35)(七)SD卡槽 (37)(八)USB转串口 (38)(九)EEPROM 24LC04 (39)(十)温度传感器 (40)(十一)扩展口 (41)(十二)JTAG接口 (44)(十三)按键 (45)(十四)LED灯 (46)(十五)供电电源 (47)黑金ARTIX-7系列的高端FPGA开发平台(型号:AX7A035B)正式发布了,为了让您对此开发平台可以快速了解,我们编写了此用户手册。
这款ARTIX-7 FPGA开发平台采用核心板加扩展板的模式,方便用户对核心板的二次开发利用。
在底板设计上我们设计了丰富的外围接口,比如一路PCIex2接口,两路光纤模块接口,一路HDMI输出接口,一路HDMI输入接口,一路千兆以太网接口,Uart接口,SD卡接口等等。
满足用户各种PCIe高速数据传输,视频图像处理和工业控制的要求,是一款"全能级“的FPGA开发平台。
为高速视频传输,网络、光纤和PCIe 通信及数据处理的前期验证和后期应用提供了可能。
相信这样的一款产品非常适合从事FPGA开发的学生、工程师等群体。
一、开发板简介在这里,对这款AX7A035B FPGA 开发平台进行简单的功能介绍。
开发板的整个结构,继承了我们一贯的核心板+扩展板的模式来设计的。
MYiRZynqFPGA使用手册
MYiRZynqFPGA使用手册MYiR Zynq FPGA 使用手册版本V1.02015年5月28日版本记录目录目录 (3)简介 (5)第1章HelloWorld (6)1.1 新建Vivado工程 (6)1.2 新建Block Design (7)1.3 设置工程使用Verilog语言 (8)1.4 添加PS的IP核并配置 (9)1.5 生成综合文件 (11)1.6 生成FPGA顶层文件 (12)1.7 综合实现 (12)1.8 导出硬件配置文件 (13)1.9 启动SDK,新建SDK工程 (13)1.10 修改源码 (14)1.11 生成boot.bin启动文件 (15)第2章GPIO操作1 (16)2.1 新建Vivado工程 (16)2.2 添加IP核并配置 (16)2.3 综合实现 (16)2.4 新建SDK工程 (16)2.5 生成boot.bin运行 (16)第3章GPIO操作2 (17)3.1 新建Vivado工程 (17)3.2 添加IP核并配置 (17)3.3 综合 (17)3.4 分配引脚 (18)3.5 实现和生成bitstream (19)3.6 导出硬件配置文件 (19)3.7 SDK新建FSBL工程分配引脚 (20)3.8 SDK新建app工程 (20)3.9 生成boot.bin启动文件 (21)第4章GPIO操作3 (23)4.1 新建Vivado工程 (23)4.2 添加axi gpio ip核 (23)4.3 综合 (25)4.4 分配引脚 (25)4.5 生成boot.bin (26)第5章PL中断 (27)5.1 新建Vivado工程 (27)5.2 添加其他IP核 (27)5.3 综合分配引脚 (31)5.4 生成boot.bin启动文件 (31)附录A 售后服务与技术支持 (33)简介例程使用的软件版本是Vivado Design Suite 2014.4,安装之后会有4个软件,Vivado 2014.4,Xilinx SDK 2014.4,System Generator 2014.4和Vivado HLS 2014.4。
FPGA应用开发实验指导书-学生版本new
FPGA应用与开发实验指导书目录实验一:Quartus软件操作 (4)1.Quartus II 的文本编辑输入法 (4)2.Quartus II 的图形编辑输入法 (16)实验二:简单的组合逻辑电路设计 (20)1.四舍五入判别电路............................................................ 错误!未定义书签。
2.控灯电路............................................................................ 错误!未定义书签。
3.优先权排队电路................................................................ 错误!未定义书签。
实验三:显示译码电路.............................................................. 错误!未定义书签。
1.数字循环显示.................................................................... 错误!未定义书签。
2.字母循环显示电路............................................................ 错误!未定义书签。
实验四:BCD码加法电路........................................................... 错误!未定义书签。
1.二进制码到BCD码的转换 ............................................. 错误!未定义书签。
2.1位BCD加法器 .............................................................. 错误!未定义书签。
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伟欣科技®睿智FPGA 2C5/2C8 开发板用户手册更新日期:2011‐12‐10请关注论坛,最新文档及资料、代码将在论坛发布我们的FPGA开发网官方网站:官方淘宝店: /邮箱:OurFPGA@QQ群:155291300提醒:请您在使用此开发板前,认真阅读此说明书,并将此电子书妥善保管,在开发学习中,可能会经常使用查询!欢迎对FPGA、嵌入式、单片机等感兴趣的朋友登陆网站,参加技术交流,下载技术资料。
在普通会员区,提供了约200多门视频教程下载(截止到2011年8月1日的数量,每周会更新添加,数量还在增加中。
),欢迎您来访!现在立即去体验一下:开发板简介FPGA与EDA技术是目前相当热门的技术,翻遍各大招聘网站电子类招聘信息,类似“精通FPGA技术,熟悉Verilog VHDL语言”等字眼已经为应聘者所熟悉;甚至,有的时候,“熟悉FPGA”就意味着高薪!实际上,FPGA技术已经成为目前电子行业应用最为广泛的技术之一,未来的就业和发展前景相当好!目前有众多朋友热切的期望能学习FPGA知识,FPGA技术实践性极强,拥有一块适合学习需求的FPGA开发板是非常有必要的!睿智FPGA开发板正是为此推出的一套高性价比开发板!此开发板由“伟欣科技®”精心设计开发,采用 Altera公司的CycloneII系列芯片EP2C5Q208C8、EP2C8Q208C8作为核心处理器进行设计,CycloneII系列芯片可以说是目前市场上性价比最高的芯片,比第一代芯片设计上、内部的逻辑资源上都有很大的改进,同时价格也可以被广大用户接受。
睿智FPGA开发板采用核心板与接口板分离的方式,核心板上除FPGA、各类存储器以及用户扩展PACK外,还有按键、LED及电源插座等。
因为有用户扩展PACK,核心板完全可以脱离接口板而单独使用,通过PACK,用于自己的设计或电子设计大赛,扩展性极好。
接口板上集成了最常用和经典外围接口,所有的外设经过精心分配及设计,不需要进行任何跳线设置,实验时非常方便!此外,对于重点外设的关键信号都设置了测试点,方便用户使用逻辑分析仪、示波器、万用表等进行信号测量。
总之,睿智FPGA开发板是完全站在用户的角度精心设计开发,简约不简单!同时,睿智FPGA开发板的配套光盘提供相当丰富的实验代码及各种参考文档。
睿智FPGA开发板用户群体面向广大的高校相关专业学生、电子爱好者、科研单位、企事业单位的开发设计人员,适合于产品原型的快速开发、学生参加各种电子设计大赛、学习 FPGA 技术入门,课程设计以及毕业设计等,亦可用于系统设计前期快速评估设计方案。
特别适合FPGA、NIOSII、SOPC快速入门和产品开发及验证。
第一章 注意事项(必看!)我们认为以下几条是特别重要的提醒事项,将其放在最前面,请认真阅读并牢记! 1.1软件及环境强烈建议使用Windows XP中文版系统使用开发板及安装相关软件!本开发板配套使用的说明文档、代码、程序、文档等信息均在XP中文系统下测试。
使用统一的电脑环境,有利于避免使用其它系统造成的未知错误,也有利于出现问题后,和技术支持人员沟通,利于QQ群学友沟通,利于论坛各学友沟通交流!Altera的软件版本在不断的升级,目前我们推荐使用最新版本QuartusII11.0,此版本软件经作者使用,认为各方面功能均达到最好,并且支持中文注释(此功能对于初学者是很非常方便的),光盘中附带了软件安装包。
Quartus II软件和NIOS 软件的版本必须一致,并安装在同一个目录下面,安装目录不要有中文和空格。
详细情况请参考后面章节的安装说明。
关于QuartusII软件安装破解,在后面有详细步骤说明,请大家耐心阅读,并仔细认真按说明操作,不要想当然,目前发现,很多客户收到开发板,出现问题最多的就是软件的安装和破解,明明手册提供了安装详细说明,可有部分人就是不愿意看,自己在那里瞎捣腾,结果弄得软件装不好,破解了不成功,在那里急得蹦,火急火燎的找技术支持,但又听不进去建议。
在这里强调一下,初学者还是认真的按说明来操作,安装与破解不是技术活,没有任何技术含量,只要按手册上认真操作,一定能成功。
1.2 JTAG及AS的插拔安全开发板带有JTAG和AS下载接口,严禁带电拔插JTAG及AS下载线!带电操作容易对FPGA芯片的内部配置部分电路造成致命损坏,损坏后是无法修复的!请牢记一条:插拔下载线时必须断电!这个与平时大家使用电脑主板插拔内存时差不多。
这里再罗嗦几句:“别说我们没提醒大家,既然提到,请大家严格尊照,这是为了您的利益,不要不当回事,由于误操作导致开发板损坏的,我们不负责维修的”。
平时建议大家使用JTAG下载插口,如图1.1所示,红色框的为JTAG下载口。
AS插口在必要时再使用。
平时不用开发板时,可以不拔下载线,只拔USB与主机接口即可。
图1.1 下载接口JTGA和AS1.3外接电源开发板套装里面附带标准5V/2A电源一条,5V输入,内正外负。
建议使用我们标配电源,如果使用其它电源,请您一定确认输出电压是否为5V,以免由于电压不同造成开发板损坏!核心板和接口板均设有5V电源插口,位置在PCB左上角。
如图1.2所示:使用开发板时,只用随便接一个插口即可。
不必要核心板和接口板都插电源。
因为电源走线内部是相通的。
图1.2 两个5V电源接口1.4核心板与接口板连接核心板与接口板是通过三排接插口相连的,核心板上是双排座,接口板上是双排针。
发货到您手中的开发板,两块PCB板是已经装配好的。
如果不单独使用核心板,那么平时不要将核心板拔下,尽量避免频繁插拔两块板。
即使要插拔时,请尽量小心谨慎些。
取下核心板时,建议一手固定接口板,另一手拿住核心板PCB四周,用适度的力取下,过程中尽量保持核心板的平整度,不时调整四周用力力度。
参考图1.3。
图1.3 取下核心板安装核心板时,注意核心板方向,要将核心板PCB四周边与接口板上白色示意线对齐,并且保证插座和插针一一对应,确认无误后,方可安装。
参考图1.4示意图。
图1.4 安装核心板第二章 硬件资源描述开发板套件硬件是保证实验学习的基础,这部分内容主要针对硬件部分做简单描述,可适当阅读或翻查,特别是涉及到硬件接口定义等信息时,了解这部分内容很有必要。
同时,可与光盘附带的硬件原理图一并参考使用。
2.1睿智FPGA开发板照片图2.1‐2.7为睿智FPGA开发板照片,包括全局、核心板、接口板及细节照片。
图2.1 睿智FPGA开发板照片(一)图2.2 睿智FPGA开发板照片(二)图2.3 睿智FPGA开发板照片(三)图2.4 睿智FPGA开发板照片(四)图2.5睿智FPGA开发板照片(五)图2.6 睿智FPGA开发板照片(六)图2.7 睿智FPGA开发板照片(七)2.2睿智FPGA开发板硬件介绍2.2.1硬件资源图示以下资源图,以EP2C5Q208C8N主芯片为例。
图2.8 开发板硬件资源图示2.2.2核心板资源:•FPGA主芯片采用Altera公司高性价比FPGA:CycloneII系列EP2C5Q208C8N或EP2C8Q208C8N•板载EPCS4N或EPCS16N串行配置芯片,同时支持JTAG和AS模式;•采用64Mbit的SDRAM,足够胜任NIOSII设计;•板载50MHz有源晶振,提供系统工作主时钟;•采用大功率LDO电源管理芯片1085‐3.3V,最大支持3A的3.3V电压输出; •采用1117‐1.2V稳压芯片,提供FPGA内核电压;•精心的去耦设计,采用大量去耦电容,PLL电源采用PI型滤波;•提供双5V直流电源插座,方便核心板单独使用和套装使用;•红色电源指示灯及IN5819高速肖特基二极管,防止电源反接;•自锁按键电源开关;•一个系统复位按键Reset,也可做为用户输入按键;•重配置按键及配置成功指示灯;•所有输入输出口精心设计分配,使用3个扩展接口插座,通用2.54mm间距;•JTAG下载接口,对应下载的文件是SOF文件,速度快,JTAG将程序直接下载到 FPGA 中,但是掉电程序丢失,平时学习推荐使用JTAG方式,最后固化程序的时候再通过AS方式将程序下载到配置芯片中即可;•AS下载接口,对应下载的是POF文件,速度相对较慢,需要重新上电并且拔掉下载线,才能工作,操作相对麻烦,不推荐学习的时候使用。
2.2.3接口板资源:•DC5V接口及红色LED电源指示灯;•板载8个独立按键,可做按键控制,数字逻辑基础实验等;•板载8位LED发光二极管,做数字逻辑基础流水,显示等实验;•板载8位数码管,做动态或静态数码管显示实验,频率计、秒表; •板载4位拨码开关,可做开关控制等实验;•板载1路蜂鸣器,可用作发声及音乐实验;•设有LCD1602液晶屏接口,做字符显示实验(不包括LCD);•设有LCD12864液晶屏接口,做汉字、字符等显示实验(不包括LCD);•RS232串口,可做串口通讯实验;•PS2接口,可做PS/2键盘实验; •温度传感器接口,可以做温度计实验;•TLC549 AD转换器,可以做电压表等实验;•TLC5620 DA转换器,实际作用更大了;•256色VGA接口,可做显示器实验等;•32.768KHz基准晶振;• TL431,可作为2.5V电压基准源,•可调电位器,调节DA值;•I2C串行EEPROMAT24C08,做IIC总线实验;•PCF8563T实时时钟;2.3核心板电路分析2.3.1 FPGA主芯片核心板上的FPGA芯片采用的是CycloneⅡ系列的EP2C5Q208C8N或EP2C8Q208C8N,此芯片资源丰富,价格适中,非常适合FPGA初中级学习使用,它的资源如图2.9所示。
图2.9 EP2C5Q208C8N 芯片资源截图通常,芯片的逻辑单元和RAM 的数量是重要的参考指标,对于EP2C5Q208和EP2C8Q208来说,已经足够初学者使用了。
核心板上FPGA 主芯片的原理图如图2.10所示。
图2.10 EP2C8Q208C8N的4个BANK图2.3.2存储器SDRAM电路核心板选用的SDRAM芯片是HY57V641620FTP为64Mbit容量,地址为A0~A11,SDRAM 的电源部分使用多个104电容进行了滤波处理,保证了芯片工作的电源稳定性。
SDRAM部分原理图如图2.11所示:图2.11 SDRAM原理图2.3.3电源电路电源是保证整个开发系统正常工作最重要的部分。
核心板外部输入5V电源,经过1085‐3.3V稳压后输出3.3V,3.3V主要用于给FPGA所有IO口,核心板存储器电路、串行配置器件、复位电路和LED等供电。
然后3.3V送给1117‐1.2V稳压,提供FPGA的内部核工作,以及锁相环部分电源工作。