verilog设计篮球比赛的定时器
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篮球比赛的定时器（一个时钟1khz）module self_timer(clk,reset,pause,light,data,wx); input clk,reset,pause;
output light;
output[7:0] data;
output wx;
reg light;
reg[7:0] data;
reg wx;
reg clk1hz;
reg[3:0] s0,s1;
reg[2:0] count1;
reg [9:0] count0;
always@(posedge clk or negedge reset)
begin
if(!reset)
count1<=2'd0;
else
if(count1==2'd2)
begin
count1<=2'd0;
wx <= ~wx;
end
else
count1<=count1+1'b1;
end
always@(posedge clk or negedge reset)
begin
if(!reset)
count0<=9'd0;
else
if(count0==9'd50)
begin
count0<=9'd0;
clk1hz <=~clk1hz;
end
else
count0<=count0+1'b1;
end
always@(posedge clk1hz or negedge reset or negedge pause) begin
if(!reset)
begin
s1<=4'd2;
s0<=4'd4;
end
else
if(!pause)
begin
s1<=s1;
s0<=s0;
end
else
if(s0==4'd0&&s1==4'd0)
begin
s1<=4'd0;
s0<=4'd0;
light=1'b1;
end
else
if(s0==4'd0)
begin
s0<=4'd9;
s1<=s1-1'b1;
end
else
s0<=s0-1'b1;
end
always@(wx or s0 or s1)
begin
if(wx==1'b1)
begin
case(s0)
4'b0000:data=~8'hc0;
4'b0001:data=~8'hf9;
4'b0010:data=~8'ha4;
4'b0011:data=~8'hb0;
4'b0100:data=~8'h99;
4'b0101:data=~8'h92;
4'b0110:data=~8'h82;
4'b0111:data=~8'hf8;
4'b1000:data=~8'h80;
4'b1001:data=~8'h90;
default:data=~8'hc0;
endcase
end
else
if(wx==1'b0)
begin
case(s1)
4'b0000:data=~8'hc0;
4'b0001:data=~8'hf9;
4'b0010:data=~8'ha4;
4'b0011:data=~8'hb0;
4'b0100:data=~8'h99;
4'b0101:data=~8'h92;
4'b0110:data=~8'h82;
4'b0111:data=~8'hf8;
4'b1000:data=~8'h80;
4'b1001:data=~8'h90;
default:data=~8'hc0;
endcase
end
end
endmodule
测试模块
`timescale 1ns/100ps
module top;
`define clk_cycle 50
reg clk,reset,pause;
wire light;
wire[7:0] data;
wire wx;
always #`clk_cycle clk=~clk;
initial
begin
clk=0;
reset=1;
pause=1;
#10 reset=0;
#60 reset=1;
#110 pause=0;
#160 pause=1;
end
self_timer m(.reset(reset),.clk(clk),.pause(pause),.light(light),.data(data),.wx(wx)); endmodule
篮球比赛的定时器（两个时钟）
module self_timer(clk,reset,pause,wx,light,data);
input clk,wx,reset,pause;
output light;
output[7:0] data;
reg light;
reg[7:0] data;
reg[3:0] s0,s1;
always@(posedge clk or negedge reset or negedge pause)
begin
if(!reset)
begin
s1<=4'd2;
s0<=4'd4;
end
else
if(!pause)
begin
s1<=s1;
s0<=s0;
end
else
if(s0==4'd0&&s1==4'd0)
begin
s1<=4'd0;
s0<=4'd0;
light=1'b1;
end
else
if(s0==4'd0)
begin
s0<=4'd9;
s1<=s1-1'b1;
end
else
s0<=s0-1'b1;
end
always@(wx or s0 or s1)
begin
if(wx==1'b1)
begin
case(s0)
4'b0000:data=~8'hc0;
4'b0001:data=~8'hf9;
4'b0010:data=~8'ha4;
4'b0011:data=~8'hb0;
4'b0100:data=~8'h99;
4'b0101:data=~8'h92;
4'b0110:data=~8'h82;
4'b0111:data=~8'hf8;
4'b1000:data=~8'h80;
4'b1001:data=~8'h90;
default:data=~8'hc0;
endcase
end
else
if(wx==1'b0)
begin
case(s1)
4'b0000:data=~8'hc0;
4'b0001:data=~8'hf9;
4'b0010:data=~8'ha4;
4'b0011:data=~8'hb0;
4'b0100:data=~8'h99;
4'b0101:data=~8'h92;
4'b0110:data=~8'h82;
4'b0111:data=~8'hf8;
4'b1000:data=~8'h80;
4'b1001:data=~8'h90;
default:data=~8'hc0;
endcase
end
end
endmodule
测试模块：
`timescale 1ns/100ps
module top;
`define clk_cycle 50
reg clk,reset,pause;
wire light;
wire[7:0] data;
always #`clk_cycle clk=~clk;
initial
begin
clk=0;
reset=1;
pause=1;
#10 reset=0;
#60 reset=1;
#110 pause=0;
#160 pause=1;
end
self_timer m(.reset(reset),.clk(clk),.pause(pause),.light(light),.data(data),.wx(wx)); endmodule。