Xilinx 高速AD DA采集

TSW4200 Platform
• Self-contained baseband TX-RX transceiver loop specifically designed for system evaluation and programming development
– DAC3283 DAC EVM with on-board CDCE62005 Clocking solution – ADS62P49 ADC EVM with on-board CDCE72010 Clocking solution
High Speed Analog Speedway: TSW4200 Data Converter Solution
Russell Hoppenstein
HSDC Applications Manager
With Contributions from: Kang Hsia Tommy Neu Wenjing Lu Richard Prentice Cliff Schecht
DAC Interface Adapter Board
ADC Interface Adapter Board
DAC3283
Dual 16-bit, 800MSPS Communications DAC
• Features
– 48-pin QFN package (Smallest 16-bit dual DAC at 800MSPS) – Superior Linearity
• “the frequency at Fred is aliased down, or under-sampled, to be at frequency Fblue at the ADC digital outputs in the spectral domain” • Or better yet, “the ADC can’t tell the difference”
• Power Supply Considerations
– Utilizing DC-DC Converters for Efficient Supplies – Power Supply Noise Reduction Techniques
• DAC Special Features
– Interpolation Filters – Digital Signal Adjustments (QMC) – NCO option
– Key Parameters
• Linearity (IMD3) • Noise Spectral Density • SFDR (Spurious Free Dynamic Range)
– System Specifications
• Adjacent Channel Interference • Spurious Emissions
Sampling Theory
• The Nyquist Rate is the minimum sampling rate required to avoid aliasing
– Nyquist rate is simply twice the highest frequency
“1st Nyquist”
• Applications – Wireless Infrastructure (3G/4G Base Stations) – High Speed Digitizers – Portable Test and Measurement Systems – Radar and Guidance Systems
Bad Aliasing (graphically speaking)
As drawn here, this is 1 modulated carrier with a BW = 45MHz, centered at 100MHz
• Applications
ADS62P49
Low Power, High Performance Dual 14-bit 250MSPS ADC
• Features
– 250MSPS – Fast dual 14-bit ADC – 72.5 dBFS SNR, 84 dBc SFDR at 70MHz IF – Internal gain settings: 1-6 dB in 1 dB steps
– In the example given, the bandwidth of each signal is practically zero – these are discrete tones at 1/9 and 10/9 of Fs – But signals with no bandwidth contain little information and are therefore not usually very useful for communication systems – So let’s look at aliasing with some bandwidth involved….
• • • • ADS5493 ADS62P49 ADS54RF63 ADS5400 16 bit 14 bit 12 bit 12 bit 130 MSPS 250 MSPS 550 MSPS 1000 MSPS
Key System Parameters
• Transmitter Side (DACs)
• Analog Signal Chain Interface - DAC
– Proper Load for Current Sink DACs – Interface Network to Quadrature Modulator – Low Pass Filter Design Techniques
Progression of Data Converters
• Transmit Side
– – – – Progression toward higher complex IF frequencies Support higher signal BW Support DPD solutions (5x RF signal BW) Examples:
– – – – – If Fs is the Sampling Frequency (clock rate) a high frequency Fred = 10/9 * Fs and a low frequency at Fblue = 1/9 * Fs = Fred – Fs Both look like 1/9 * Fs to the ADC Thus one might say,
• DAC5688 • DAC3283 • DAC5682 16 bit 16 bit 16 bit 800 MSPS 800 MSPS 1000 MSPS
• Receive Side
– – – – – Capture higher IF frequencies Support higher signal BW Higher dynamic range to provide better blocker immunity DPD Feedback Examples
• Real World Clocking Solutions
– – – – Clock Jitter impact to Data Converter Performance Jitter Impact as Related to Input Frequency TI High Performance Clocking Solutions Clock Improvement Techniques
• Receiver Side (ADCs)
– Key Parameters
• SNR (Signal to Noise Ratio) • SFDR (Spurious Free Dynamic Range)
– System Specifications
• Sensitivity • Blocker Immunity
Agenda
• Data Converter Introduction
– – – – Industry Progression of Data Converters Key Performance Metrics TSW4200 Platform Introduction Sampling Theory
• Digital Interface Options
– CMOS – Low Speed Interface – Parallel LVDS – Serialized LVDS
• Analog Signal Chain Interface - ADC
– Passive Transformer Interface – Buffer vs. Non-buffered Device – Active Op-Amp Interface
• 95 dBc IMD at 10MHz IF • 77 dBc IMD at 150MHz IF
– – – – – – – –
2x/4x interpolation with phase, gain and offset QMC correction Fs/2 and Fs/4 coarse mixer Low power consumption – 1150mW all features on Single byte wide interleaved DDR LVDS input bus Wireless Infrastructure (3G/4G Base Stations) Software Defined Radios Test and Measurement – ARB Power Amplifier Linearization
example:
Under-sampling (Aliasing)
• We just down-converted a signal from a high frequency to a lower frequency – that sounds useful
– This is called Under-sampling
• This usually requires an analog frequency mixer
• What is not always clear in the definition of the Nyquist Rate is that it refers to the bandwidth of the signal, not the frequency
• 70.2 dBFS SNR, 88 dBc SFDR at 70MHz IF • 66.6 dBFS SNR, 84 dBc SFDR at 200MHz IF
– Small 9x9mm QFN pkg; pin compatible with entire ADS62Pxx family – Low power: 625 mW per channel (LVDS output)
“2nd Nyquist”
“3rd Nyquist”
“4th Nyquist”
“etc……..”
ห้องสมุดไป่ตู้
Fs/2 = 45
‘Nyquist’
67.5
Fs=90M
112.5
135
180
SAMPLE/CLOCK RATE
What is Aliasing?
• Aliasing - two different sinusoids give the same digital samples
• Evaluation Strategy –TSW4200 Platform
– – – – TSW4200 Block Diagram Performance Plots Mix and Match Topology Concept System Modifications with Alternate EVMs