FPGA可编程逻辑器件芯片XC3S250E-4TQ144I中文规格书

PCB Guidelines for DDR3
Strict adherence to all documented DDR3 PCB guidelines is required for successful operation. For more information on PCB guidelines, see the UltraScale Architecture PCB Design and Pin Planning User Guide (UG583) [Ref11].
PCB Guidelines for DDR4
Strict adherence to all documented DDR4 PCB guidelines is required for successful operation. For more information on PCB guidelines, see the UltraScale Architecture PCB Design and Pin Planning User Guide (UG583) [Ref11].
Pin and Bank Rules
DDR3 Pin Rules
bitstream is split into two stages. Specifically, IP cores built by the Memory IP or Memory Interface Generator (MIG) must not use bank 65 I/O. This ensures that IP can remain completely within stage 2, and avoid complications with its embedded I/O and demanding timing constraints.
The rules are for single and multi-rank memory interfaces.
•Address/control means cs_n, ras_n, cas_n, we_n, ba, ck, cke, a, parity (valid for RDIMMs only), and odt. Multi-rank systems have one cs_n, cke, odt, and one ck pair per rank.
•Pins in a byte lane are numbered N0 to N12.
•Byte lanes in a bank are designed by T0, T1, T2, or T3. Nibbles within a byte lane are distinguished by a “U” or “L” designator added to the byte lane designator (T0, T1, T2, or T3). Thus they are T0L, T0U, T1L, T1U, T2L, T2U, T3L, and T3U.
Note:There are two PLLs per bank and a controller uses one PLL in every bank that is being used by the interface.
1.dqs, dq, and dm location.
a.Designs using x8 or x16 components – dqs must be located on a dedicated byte
clock pair in the upper nibble designated with “U” (N6 and N7). dq associated with
a dqs must be in same byte lane on any of the other pins except pins N1 and N12.
b.Designs using x4 components – dqs must be located on the dedicated dqs pair in
the nibble (N0 and N1 in the lower nibble, N6 and N7 in the upper nibble). dq’s
associated with a dqs must be in the same nibble on any of the other pins except pin N12 (upper nibble).
c.dm (if used) must be located on pin N0 in the byte lane with the corresponding dqs.
When dm is disabled, pin N0 can be used for dq and pin N0 must not be used for
address/control signal. Pin N0 must not be used for Address/Control when dm is not used (exception reset# pin).
Note:dm is not supported with x4 devices.
d.dm, if not used, must be pulled low on the PCB. Typical values used for this are equal
to the DQ trace impedance such as 40 or 50Ω. Consult with the memory vendor for their specific recommendation. Unpredictable failures occur if this is not pulled low appropriately.
2.The x4 components must be used in pairs. Odd numbers of x4 components are not
permitted. Both the upper and lower nibbles of a data byte must be occupied by a x4 dq/dqs group.
3.Byte lanes with a dqs are considered to be data byte lanes. Pins N1 and N12 can be used
for address/control in a data byte lane. If the data byte is in the same bank as the remaining address/control pins, see step #4.
4.Address/control can be on any of the 13 pins in the address/control byte lanes. Address/
control must be contained within the same bank.
5.For dual slot configurations of RDIMMs and UDIMMs: cs, odt, cke, and ck port widths
are doubled. For exact mapping of the signals, see the DIMM Configurations.
6.One vrp pin per bank is used and DCI is required for the interfaces. A vrp pin is
required in I/O banks containing inputs as well as in output only banks. It is required in output only banks because address/control signals use SSTL15_DCI/SSTL135_DCI to enable usage of controlled output impedance. DCI cascade is allowed. When DCI
cascade is selected, vrp pin can be used as a normal I/O. All rules for the DCI in the UltraScale™ Architecture SelectIO™ Resources User Guide (UG571) [Ref7] must be
followed.
7.ck pair(s) must be on any PN pair(s) in the Address/Control byte lanes.
8.reset_n can be on any pin as long as general interconnect timing is met and I/O
standard must be SSTL15. Reset to DRAM should be pulled down so it is held low during
power up. When dm is disabled, the reset pin can be allocated to N0th pin of data byte lane or any other free pin of that byte lane as long as other rules are not violated.
9.Banks can be shared between two controllers.
a.Each byte lane is dedicated to a specific controller (except for reset_n).
b.Byte lanes from one controller cannot be placed inside the other. For example, with
controllers A and B, “AABB” is allowed, while “ABAB” is not.
10.All I/O banks used by the memory interface must be in the same column.
11.All I/O banks used by the memory interface must be in the same SLR of the column for
the SSI technology devices.
12.Maximum height of interface is five contiguous banks. The maximum supported
interface is 80-bit wide.
Maximum component limit is nine and this restriction is valid for components only and not for DIMMs.
13.Bank skipping is not allowed.
14.Input clock for the MMCM in the interface must come from a GCIO pair in the I/O
column used for the memory interface. Information on the clock input specifications can be found in the AC and DC Switching Characteristics data sheets (LVDS input
requirements and MMCM requirements should be considered). For more information, see Clocking, page87.
15.There are dedicated V REF pins (not included in the rules above). Either internal or
external V REF is permitted. If an external V REF is not used, the V REF pins must be pulled to ground by a resistor value specified in the UltraScale™ Architecture SelectIO™
Resources User Guide (UG571) [Ref7]. These pins must be connected appropriately for the standard in use.
16.The interface must be contained within the same I/O bank type (High Range or High
Performance). Mixing bank types is not permitted with the exceptions of the reset_n in step 7 and the input clock mentioned in step 12.
17.The par pin is required for DDR3 RDIMMs. For more information on parity errors, see
the Address Parity, page34.
18.The system reset pin (sys_rst_n) must not be allocated to Pins N0 and N6 if the byte
is used for the memory I/Os.。