可编程ASCII 第四章课件

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Net Declarations
s1 0 s2 0 1 X Z
0 X X 0
1
X 1 X 1
X
X X X X
Z
0 1 X Z
s1
wire value
s2
wire net type
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Wire Values and Timing
Multiplexer built by tri-state buffers
4.1.4 A Simple Testbench
Module Wires
Ports
Interconnections
Wire Values and Timing
A Simple A Simple Testbench Testbench
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A Simple Testbench
`timescale 1ns/100ps values in this testbench, they are module TriMuxTest; declared as reg and initialized to 0. reg i0=0, i1=0, s=0; wire y; TriMux MUT (i0, i1, s, y); The initial statement is initial begin a procedural construct #15 i1=1’b1; and uses delay control #15 s=1’b1; statements to delay the #15 s=1’b0; program flow in this #15 i0=1’b1; procedural block. #15 i0=1’b0; #15 $finish; The delay before $finish allows the last input change end to have a chance to affect the endmodule
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4.1
Module Wires
Wires or nets are used for interconnection of substructures together, and interconnection of module ports to appropriate ports of a module’s substructures. By default module ports are wires (net). Wires have delays, can take any of the four values (0, 1, Z and X).
`timescale 1ns/100ps module Anding (input a, b, output y); and (y, a, b); endmodule
Values put into the a and b inputs of Anding are carried through these wires to the inputs of and.
Verilog for a Multiplexer with Tri-state Buffers 16
Wire Values and Timing
Simulation Results of buff1
At time 34 ns, both g1 and g2 conduct. g1 is still conducting because it takes the not gate 5 ns to change the value of sel_ and bufif1 an extra 4 ns to stop g1 from conducting. This causes the value X to appear on y.
A net used for a module port or an internal interconnection can take any of the four Verilog logic values, i.e., 0, 1, Z, and X. Such a value assigned to a net can have a delay, which may be specified by the assignment to the net or as part of its declaration. Multiple simultaneous assignments to a net, or driving a net by multiple sources is legal and the result is defined by the type of the net.
sel
trimux
g0
The symbol of output ports
i0 g1 i1 g2 y
Multiplexer using Tri-state buffers
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4.1.2 Interconnections
Module Wires
Ports
Interconnections Interconnections
Chapter 4 Combinational Circuit Description
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4.1 Module Wires
4.1.1 Ports 4.1.2 Interconnections 4.1.3 Wire values and timing 4.1.4 A simple testbench
A Simple Module
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4.1.3
Wire Values and Timing
Module Wires
Ports
Interconnections
WireValues Wire Values and Timing and Timing
A Simple Testbench
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Wire Values and Timing
Wire Values and Timing
A Simple Testbench
10
Interconnections
The and primitive generates its output, which is carried through the y net to the output of Anding.
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4.5 Behavioral Combinational Descriptions 4.5.1 Simple procedural blocks 4.5.2 Timing control 4.5.3 Intra-assignment delay 4.5.4 Blocking and nonblocking assignments 4.5.5 Procedural if-else 4.5.6 Procedural case statement 4.5.7 Procedural for statement 4.5.8 Procedural while loop 4.5.9 A multilevel description 4.6 Combinational Synthesis 4.6.1 Gate level synthesis 4.6.2 Synthesizing continuous assignments 4.6.3 Behavioral synthesis 4.6.4 Mixed synthesis 4.7 Summary
for the not gate instantiations
not #5 g0 (sel_, sel); bufif1 #4 g1 (y, i0, sel_), g2 (y, i1, sel ); endmodule
Two instances of bufif1 are combined into one gate instantiation construct
Simulation time 45 ns sel becomes 0. At Results of bufif1 Because of the delay Because of this change, after a 4ns of the not gate, this X delay, neither g1 nor g2 conduct, value remains on y for causing a Z (high impedance) to 5 ns. appear on y for a period of 5 ns (inverter17 delay).
4.2 Gate Level Logic
4.2.1 Gate primitives 4.2.2 User defined primitives 4.2.3 Delay formats 4.2.4 Module parameters
4.3 Hierarchical Structures
4.3.1 Simple hierarchies 4.3.2 Vector declarations 4.3.3 Iterative structures 4.3.4 Module path delay
4.4 Describing Expressions with Assign Statements
4.4.1 Bitwise operators 4.4.2 Concatenation operators 4.4.3 Vector operations 4.4.4 Conditional operation 4.4.5 Arithmetic expressions in assignments 4.4.6 Functions in expressions 4.4.7 Bus structures 4.4.8 Net declaration assignment