M21L216128A-10J中文资料

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M21L216128A
128 K x 16 SRAM
HIGH SPEED CMOS SRAM
ORDERING INFORMATION
44-pin 400mil SOJ 44-pin 400mil TSOP (TypeII)
PRODUCT NO.
CE DQ1 - DQ16
WE LB HB
OE VCC GND NC
Description
Address Inputs Chip Enable Input
Data Inputs/Outputs Write Enable Input Lower Byte Enable Input (DQ1 to DQ8) Higher Byte Enable Input (DQ9 to DQ16) Output Enable Input Power Ground No Connection
0V ≤ VIN ≤ VCC Output(s) disable 0V ≤ VOUT ≤ VCC IOH = -4.0 mA
IOL = 8.0 mA
VII
-0.5
0.8
V
1,2
ILI
-10
10
µA
ILO
-5
5
µA
VOH
2.4
V
1
VOL
0.4
V
1
VCC
3.0
3.6
V
1
DESCRIPTION Power Supply Current : Operating TTL Standby
M21L216128A
DQ9
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Elite Semiconduture Memory Technology Inc
Publication Date : Sep. 2000
Revision : 1.0
2/14
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M21L216128A
ABSOLUTE MAXIMUM RATINGS *
36
DQ14
35
DQ13
34
GND
33
VCC
32
DQ12
31
DQ11
30
DQ10
29
DQ9
28
NC
27
A8
26
A9
25
A10
24
A11
23
NC
Elite Semiconduture Memory Technology Inc
Publication Date : Sep. 2000
Revision : 1.0
SYMBOL CI CI/O
MAX 6 8
UNITS NOTES
pF
4
pF
4
Elite Semiconduture Memory Technology Inc
Publication Date : Sep. 2000
Revision : 1.0
3/14
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Pin Descriptions Pin No.
1 - 5, 18 - 22, 24-27, 42 - 44
6 7 - 10, 13 - 16, 29 - 32, 35 - 38
17 39 40
41 11, 33 12, 34 23, 28
Symbol A0 - A16
CMOS Standby
CAPACITANCE
CONDITIONS
MAX SYMBOL
-10 -12 -15
Device selected; CE ≤ VIL; VCC=MAX; f=fMAX ; outputs open
CE ≥ VIH; VCC=MAX; f=fMAX
CE1 ≥ VCC-0.2; VCC = MAX; all other inputs ≤ GND +0.2 or ≥ VCC -0.2; all inputs static ; f=0
GENERAL DESCRIPTION
The M21L216128A is a high speed, low power asynchronous SRAM containing 2,097,152 bits and organized as 131,072 by 16 bits, it is produced by high performance CMOS process.
Acess Time (ns)
M21L216128A-10J 10
M21L216128A-10T
M21L216128A-12J 12
M21L216128A-12T
M21L216128A-15J 15
M21L216128A-15T
PACKING TYPE SOJ TSOP SOJ TSOP SOJ TSOP
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SRAM
FEATURES
T Fast access times : 10, 12, and 15ns T Fast OE access times : 5, 6, and 7ns T Single +3.3V ± 0.3V power supply T Fully static -- no clock or timing strobes necessary T All inputs and outputs are TTL-compatible T Three state outputs T Center power and ground pins for greater noise immunity T Easy memory expansive with CE and OE options T Automatic CE power down T +LJKSHUIRUPDQFH ORZSRZHU FRQVXPSWLRQ &026
tBLZ
0
tBHZ
5
Write Cycle
Write cycle time Chip Enable to end of write
tWC
ICC 190 160 130
ISB1
35 30 25
ISB2
10 10 10
UNITS NOTES
mA
3
mA
mA
DESCRIPTION Input Capacitance Input/Output Capacitance(DQ)
CONDITIONS TA= 25°C ; f=1 MHz
VCC=3.3V
*Stresses greater than those listed under Absolute Maximum. Ratings may permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
This device offers center power and ground pins for improved performance and noise immunity. Static design
eliminates the need for external clocks or timing strobes. For increased system flexibility and eliminating bus contention problems, this device offers chip enable ( CE ), separate byte
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATIONS
(All Temperature Ranges ; VCC = 3.3V ± 0.3V unless otherwise noted)
DESCRIPTION
CONDITIONS
SYMBOL MIN MAX UNITS NOTES
Voltage on VCC Supply Relative to Vss … ……-0.5V to +4.6V VIN …………………………………………..….-0.5V to VCC+1.0V Operating Temperature, Topr ………………….. 0 °C to +70 °C Storage Temperature (plastic) ……………….-55 °C to +125 °C Junction Temperature ……………………………………+125 °C Power Dissipation …..…………………………………….…1.0W Short Circuit Output Current ………………………………50mA
Input High (Logic 1) Voltage
VIH
2.2 VCC+0.5 V
1,2
Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current
Output High Voltage Output Low Voltage Supply Voltage