viper17 application
Acer Aspire V17 Nitro Black Edition VN7-792G-75RU
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User's Guide
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NVIDIA Datacenter GPU Manager 1.7说明书
Release NotesTABLE OF CONTENTS Changelog (iii)Patch Releases (iii)DCGM v1.7.2 (iii)DCGM v1.7 GA (iv)New Features (iv)Improvements (iv)Bug Fixes (iv)Known Issues (v)This version of DCGM (v1.7) requires a minimum R384 driver that can be downloaded from NVIDIA Drivers. On NVSwitch based systems such as DGX-2 or HGX-2, a minimum of R418 driver is required. If using the new profiling metrics capabilities in DCGM, then a minimum of R418 driver is required. It is recommended to install the latest Tesla driver from NVIDIA drivers for use with DCGM.Patch ReleasesDCGM v1.7.2DCGM v1.7.2 released in December 2019.Improvements‣Added support for Quadro RTX 8000 and Quadro RTX 6000.‣Added support for Tesla V100S-PCIE-32GB.‣Make the passive health watches (controlled by dcgmi health) warn for pending page retirements. They used to report a failure, but warn instead as this failure doesn’t prevent the workload from executing.‣Added the ability to pause and resume DCGM profiling metrics so that profiling can be done while monitoring is enabled. This is done via dcgmi profile --pause/--resume.‣Enabled the NVLink Rx+Tx profiling fields (1011-1012).‣Added the dcgmi dmon --nowatch option to allow dcgmi to observe metrics that were already watched by other DCGM clients without affecting the watchfrequency or quota policy.Bug Fixes‣Fixed the DCGM profiling data sometimes appearing under the wrong GPU in pass-through mode. This could occur if the PCI BDF of the GPUs was changed as the GPUs were passed through.‣Fixed the first value returned always being 0 for DCP fields 1001-1012. DCP now records a valid value immediately after the fields are watched.‣Fixed DCP PCIe bandwidth being off by a factor of 2-5x when metrics were multiplexed.DCGM v1.7 GADCGM v1.7.1 released in September 2019.New FeaturesGeneral‣DCGM now supports new profiling metrics at the device-level from GPUs that can be used to understand application behavior. This capability is supported asbeta on Linux x86_64 and POWER (ppc64le) platforms. See the User Guide formore information. Note that automatic multiplexing of metrics is alpha.‣Samples and bindings have been moved to /usr/local/dcgm. ImprovementsGeneral‣DCGM 1.7 requires a minimum glibc version of 2.14. As a result, the installation of DCGM on older Linux distributions such as Red Hat Enterprise Linux (RHEL)6.x or CentOS 6.x may result in an error. See the Supported Platforms section inthe User Guide for the minimum system requirements.‣Added error codes and messages for various DCGM health checks‣Added a new CLI option fail-early to DCGM Diagnostics. This option enables early failure checks for the Targeted Power, Targeted Stress, SM Stress, andDiagnostic tests to check for a failure while the test is running instead at the end of the tests, providing feedback on GPU state quicker to the user‣Updated error reporting to indicate failures in the CUDA tests when running the MemoryBandwidth tests‣DCGM documentation can now be found online at / datacenter/dcgm and packages no longer include documentation.Bug Fixes‣The Memory Bandwidth test threshold for P4 products has been changed to 145GB/s since P4 would fail to reach the threshold of 165GB/s in certain scenarios.‣Fixed an issue with the targeted power test on T4 that would cause incorrect failures in some cases‣Fixed an issue with NVVS to report failures on a per-GPU basis‣Fixed an issue with NVVS to report failures on a per-GPU basis‣dcgmFieldValue_t is no longer supported in DCGM. The return value of thedcgmGetLatestValuesForFields() and dcgmEntityGetLatestValues()APIs is an updated struct dcgmFieldValue_v1, so developers may need toupdate their application to use the new struct when calling these APIs‣On K80s, failures due to throttling are disabled by default. See the Known Issues for more information‣Fixed issues with debug log file (--debugLogFile) and plugin statistics (--statspath) file generation with DCGM Diagnostics‣Fixed output formatting issues with dcgmi diag --verbose‣DCGM installer packages (deb and rpm) are now signed‣Fixed an issue with DCGM Diagnostics where in some cases, fields with the same timestamps are repeated in the statistics cache (available via log files)‣Fixed a limitation with the length of the log file name (specified using debugLogFile). The log file name including path can now support up to 128charactersKnown Issues‣When using profiling metrics with T4 in GPU VM passthrough, DCGM may report memory bandwidth utilization to be 12% higher.‣When using multiplexing of profiling metrics, the PCIe bandwidth numbers returned by DCGM may be incorrect. This issue will be fixed in a later release of the profiling metrics feature.‣On DGX-2/HGX-2 systems, ensure that nv-hostengine and the Fabric Manager service are started before using dcgmproftester for testing the new profilingmetrics. See the Getting Started section in the DCGM User Guide for details oninstallation.‣On K80s, nvidia-smi may report hardware throttling(clocks_throttle_reasons.hw_slowdown = ACTIVE) during DCGMDiagnostics (Level 3). The stressful workload results in power transients thatengage the HW slowdown mechanism to ensure that the Tesla K80 productoperates within the power capping limit for both long term and short termtimescales. For Volta or later Tesla products, this reporting issue has been fixedand the workload transients are no longer flagged as "HW Slowdown". TheNVIDIA driver will accurately detect if the slowdown event is due to thermalthresholds being exceeded or external power brake event. It is recommended that customers ignore this failure mode on Tesla K80 if the GPU temperature is within specification.‣To report NVLINK bandwidth utilization DCGM programs counters in the HW to extract the desired information. It is currently possible for certain othertools a user might run, including nvprof, to change these settings after DCGMmonitoring begins. In such a situation DCGM may subsequently return errorsor invalid values for the NVLINK metrics. There is currently no way withinDCGM to prevent other tools from modifying this shared configuration. Oncethe interfering tool is done a user of DCGM can repair the reporting by runningnvidia-smi nvlink -sc 0bz; nvidia-smi nvlink -sc 1bz.NoticeTHE INFORMATION IN THIS GUIDE AND ALL OTHER INFORMATION CONTAINED IN NVIDIA DOCUMENTATION REFERENCED IN THIS GUIDE IS PROVIDED “AS IS.” NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY, OR OTHERWISE WITH RESPECT TO THE INFORMATION FOR THE PRODUCT, AND EXPRESSL Y DISCLAIMS ALL IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE. Notwithstanding any damages that customer might incur for any reason whatsoever, NVIDIA’s aggregate and cumulative liability towards customer for the product described in this guide shall be limited in accordance with the NVIDIA terms and conditions of sale for the product.THE NVIDIA PRODUCT DESCRIBED IN THIS GUIDE IS NOT FAULT TOLERANT AND IS NOT DESIGNED, MANUFACTURED OR INTENDED FOR USE IN CONNECTION WITH THE DESIGN, CONSTRUCTION, MAINTENANCE, AND/OR OPERATION OF ANY SYSTEM WHERE THE USE OR A FAILURE OF SUCH SYSTEM COULD RESULT IN A SITUATION THAT THREATENS THE SAFETY OF HUMAN LIFE OR SEVERE PHYSICAL HARM OR PROPERTY DAMAGE (INCLUDING, FOR EXAMPLE, USE IN CONNECTION WITH ANY NUCLEAR, AVIONICS, LIFE SUPPORT OR OTHER LIFE CRITICAL APPLICATION). NVIDIA EXPRESSL Y DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY OF FITNESS FOR SUCH HIGH RISK USES. NVIDIA SHALL NOT BE LIABLE TO CUSTOMER OR ANY THIRD PARTY, IN WHOLE OR IN PART, FOR ANY CLAIMS OR DAMAGES ARISING FROM SUCH HIGH RISK USES.NVIDIA makes no representation or warranty that the product described in this guide will be suitable for any specified use without further testing or modification. T esting of all parameters of each product is not necessarily performed by NVIDIA. It is customer’s sole responsibility to ensure the product is suitable and fit for the application planned by customer and to do the necessary testing for the application in order to avoid a default of the application or the product. Weaknesses in customer’s product designs may affect the quality and reliability of the NVIDIA product and may result in additional or different conditions and/ or requirements beyond those contained in this guide. NVIDIA does not accept any liability related to any default, damage, costs or problem which may be based on or attributable to: (i) the use of the NVIDIA product in any manner that is contrary to this guide, or (ii) customer product designs.Other than the right for customer to use the information in this guide with the product, no other license, either expressed or implied, is hereby granted by NVIDIA under this guide. Reproduction of information in this guide is permissible only if reproduction is approved by NVIDIA in writing, is reproduced without alteration, and is accompanied by all associated conditions, limitations, and notices.TrademarksNVIDIA and the NVIDIA logo are trademarks and/or registered trademarks of NVIDIA Corporation in the Unites States and other countries. Other company and product names may be trademarks of the respective companies with which they are associated.Copyright© 2013-2019 NVIDIA Corporation. All rights reserved.。
VIPER53资料
DRAIN
ON/OFF OSCILLATOR
PWM LATCH OVERTEMP. DETECTOR R1 R2 R3 UVLO COMPARATOR VDD 8.4/ 11.5V 0.5V STANDBY COMPARATOR 4V 150/400ns BLANKING PWM COMPARATOR 8V S FF R4 Q R5 0.5V H COMP BLANKING TIME SELECTION 1V
TAPE and REEL VIPer53SP13TR
DIP-8 PowerSO-10™
2/24
元器件交易网
VIPer53DIP / VIPer53SP
ABSOLUTE MAXIMUM RATINGS
Symbol VDS ID VDD VOSC ICOMP ITOVL VESD Tj Tc Tstg Parameter Continuous Drain Source Voltage (Tj=25 ... 125°C) Continuous Drain Current Supply Voltage OSC Input Voltage Range COMP and TOVL Input Current Range Electrostatic Discharge: Machine Model (R=0Ω; C=200pF) Charged Device Model Junction Operating Temperature Case Operating Temperature Storage Temperature (See note 1) (See note 1) Value -0.3 ... 620 Internally limited 0 ... 19 0 ... VDD -2 ... 2 Unit V A V V mA
DS51617A TC1303 DFN调节输出示例板用户指南说明书
TC1303 DFNAdjustable OutputDemo BoardUser’s Guide © 2006 Microchip Technology Inc.DS51617ADS51617A-page ii © 2006 Microchip Technology Inc.Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY , PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE . Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.TrademarksThe Microchip name and logo, the Microchip logo, Accuron, dsPIC, K EE L OQ , micro ID , MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC and SmartShunt areregistered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, , dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,In-Circuit Serial Programming, ICSP , ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, , PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, TotalEndurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.All other trademarks mentioned herein are property of their respective companies.© 2006, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.Printed on recycled paper.Note the following details of the code protection feature on Microchip devices:•Microchip products meet the specification contained in their particular Microchip Data Sheet.•Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.•There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to ourknowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.•Microchip is willing to work with the customer who is concerned about the integrity of their code.•Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PICmicro ® 8-bit MCUs, K EE L OQ ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analogproducts. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.TC1303 DFN ADJUSTABLE OUTPUTDEMO BOARD USER’S GUIDETable of ContentsPreface (1)Introduction (1)Document Layout (1)Conventions Used in this Guide (2)Recommended Reading (2)The Microchip Web Site (3)Customer Support (3)Document Revision History (3)Chapter 1. Product Overview1.1 Introduction (5)1.2 What is the TC1303 DFN Adjustable Output Demo Board? (6)1.3 What the TC1303 DFN Adjustable Output Demo Board Kit includes (6)Chapter 2. Installation and Operation2.1 Introduction (7)2.2 Features (7)2.3 Getting Started (7)Appendix A. Schematic and LayoutsA.1 Introduction (11)A.2 Board – Schematic (12)A.3 Board – Top Silk Screen Layer (13)A.4 Board – Top Metal Layer (14)A.5 Board – Bottom Metal Layer (15)Appendix B. Bill Of Materials (BOM)Worldwide Sales and Service (18)© 2006 Microchip Technology Inc.DS51617A-page iiiTC1303 DFN Adjustable Output Demo Board User’s Guide NOTES:DS51617A-page iv© 2006 Microchip Technology Inc.TC1303 DFN ADJUSTABLE OUTPUTDEMO BOARD USER’S GUIDEPrefaceAll documentation becomes dated, and this manual is no exception. Microchip tools and documentation are constantly evolving to meet customer needs, so some actual dialogsand/or tool descriptions may differ from those in this document. Please refer to our web site () to obtain the latest documentation available.Documents are identified with a “DS” number. This number is located on the bottom of each page, in front of the page number. The numbering convention for the DS number is“DSXXXXXA”, where “XXXXX” is the document number and “A” is the revision level of the document.For the most up-to-date information on development tools, see the MPLAB® IDE on-line help.Select the Help menu, and then Topics to open a list of available on-line help files.INTRODUCTIONThis chapter contains general information that will be useful to know before using theTC1303 DFN Adjustable Output Demo Board . Items discussed in this chapter include:•Document Layout•Conventions Used in this Guide•Recommended Reading•The Microchip Web Site•Customer Support•Document Revision HistoryDOCUMENT LAYOUTThis document describes how to use the TC1303 DFN Adjustable Output Demo Board. The manual layout is as follows:•Chapter 1.“Product Overview” – Important information about the TC1303 DFNAdjustable Output Demo Board .•Chapter 2.“Installation and Operation” – Includes instructions on how to getstarted with this user’s guide and a description of the user’s guide.•Appendix A.“Schematic and Layouts” – Shows the schematic and layoutdiagrams for the TC1303 DFN Adjustable Output Demo Board .•Appendix B.“Bill Of Materials (BOM)” – Lists the parts used to build theTC1303 DFN Adjustable Output Demo Board .© 2006 Microchip Technology Inc.DS51617A-page 1TC1303 DFN Adjustable Output Demo Board User’s GuideDS51617A-page 2© 2006 Microchip Technology Inc.CONVENTIONS USED IN THIS GUIDEThis manual uses the following documentation conventions:RECOMMENDED READINGThis user's guide describes how to use TC1303 DFN Adjustable Output Demo Board. The following Microchip documents are available and recommended as supplemental reference resources.TC1303A/TC1303B/TC1303C Data Sheet, "500mA Synchronous Buck Regulator, + 300mA LDO with Power-Good Output" (DS21949)This data sheet provides detailed information regarding the TC1303 product family.DOCUMENTATION CONVENTIONSDescriptionRepresentsExamplesArial font:Italic characters Referenced books MPLAB ® IDE User’s Guide Emphasized text ...is the only compiler...Initial capsA window the Output window A dialogthe Settings dialogA menu selectionselect Enable Programmer QuotesA field name in a window or dialog“Save project before build”Underlined, italic text with right angle bracket A menu pathFile>SaveBold characters A dialog button Click OKA tabClick the Power tab ‘b nnnnA binary number where n is a digit‘b00100, ‘b10Text in angle brackets < > A key on the keyboard Press <Enter>, <F1>Courier font:Plain CourierSample source code #define START Filenames autoexec.bat File paths c:\mcc18\hKeywords_asm, _endasm, static Command-line options -Opa+, -Opa-Bit values0, 1Italic Courier A variable argumentfile .o , where file can be any valid filename0x nnnnA hexadecimal number where n is a hexadecimal digit 0xFFFF , 0x007A Square brackets [ ]Optional arguments mcc18 [options] file[options]Curly brackets and pipe character: { | }Choice of mutually exclusive arguments; an OR selection errorlevel {0|1}Ellipses...Replaces repeated text var_name [,var_name...]Represents code supplied by user void main (void){ ...}PrefaceTHE MICROCHIP WEB SITEMicrochip provides online support via our web site at . This website is used as a means to make files and information easily available to customers.Accessible by using your favorite Internet browser, the web site contains the followinginformation:•Product Support – Data sheets and errata, application notes and sampleprograms, design resources, user’s guides and hardware support documents,latest software releases and archived software•General Technical Support – Frequently Asked Questions (FAQs), technicalsupport requests, online discussion groups, Microchip consultant programmember listing•Business of Microchip – Product selector and ordering guides, latest Microchippress releases, listing of seminars and events, listings of Microchip sales offices,distributors and factory representativesCUSTOMER SUPPORTUsers of Microchip products can receive assistance through several channels:•Distributor or Representative•Local Sales Office•Field Application Engineer (FAE)•Technical Support•Development Systems Information LineCustomers should contact their distributor, representative or field application engineerfor support. Local sales offices are also available to help customers. A listing of salesoffices and locations is included in the back of this document.Technical support is available through the web site at: In addition, there is a Development Systems Information Line which lists the latestversions of Microchip's development systems software products. This line also pro-vides information on how customers can receive currently available upgrade kits.The Development Systems Information Line numbers are:1-800-755-2345 – United States and most of Canada1-480-792-7302 – Other International LocationsDOCUMENT REVISION HISTORYRevision A (July 2006)•Initial Release of this Document.© 2006 Microchip Technology Inc.DS51617A-page 3TC1303 DFN Adjustable Output Demo Board User’s Guide NOTES:DS51617A-page 4© 2006 Microchip Technology Inc.TC1303 DFN ADJUSTABLE OUTPUTDEMO BOARD USER’S GUIDE© 2006 Microchip Technology Inc.DS51617A-page 5Chapter 1. Product Overview1.1INTRODUCTIONStep-down-converter choices include a variety of linear and switching regulators. The TC1303C Adjustable Output Regulator provides a unique combination of a 500mA synchronous buck regulator and 300mA Low-Dropout Regulator (LDO) with a Power-Good (PG) monitor to provide a highly integrated solution of dual supply applications for devices like Cellular Phones, Portable Computers, USB-Powered Devices, Hand Held instruments, etc. The device provides a very cost-effective solution with minimal board space because of the high-frequency operation of the buckconverter, which reduces the size requirements of the external inductor and capacitor, the minimal external component requirement by the LDO and the small DFN (dual flat no leads) package size.The 500mA synchronous buck regulator switches at a fixed frequency of 2.0MHz when the load is heavy, providing a low-noise, small-size solution. When the load on the buck output is reduced to light levels, it changes operation to a pulse frequency modulation (PFM) mode to minimize quiescent current drawn from the battery. No inter-vention is necessary for smooth transition from one mode to another.The LDO provides a 300mA auxiliary output that requires a single 1µF ceramic output capacitor, minimizing board area and cost. Typical dropout voltage for the LDO output is 137mV for a 200mA load.For the TC1303C, the power-good output is based on the regulation of the buck regu-lator output, the LDO output or the combination of both. Additional protection features include UVLO, overtemperature and overcurrent protection on both outputs.This chapter covers the following topics.•What is the TC1303 DFN Adjustable Output Demo Board?•What the TC1303 DFN Adjustable Output Demo Board Kit includes.FIGURE 1-1:TC1303 DFN Adjustable Output Demo Board Block Diagram.INPUT VOLTAGE:2.7V - 5.5VResistor DividerNetworkLDO Regulator Output Voltage 2.5V @300mASwitch S1 for SHDN1 and SHDN2TC1303C500mA Synchronous Buck Regulator + 300mA LDO with Power-Good OutputBuck Regulator Output Voltage 1.8V,2.5V,3.3V,4.0V @500mATC1303 DFN Adjustable Output Demo Board User’s Guide1.2WHAT IS THE TC1303 DFN ADJUSTABLE OUTPUT DEMO BOARD?The TC1303 DFN Adjustable Output demo board demonstrates the use of Microchip’sTC1303C device in applications that require dual supply voltage.The demo board isused to evaluate the TC1303C device over the input voltage range, output voltage andcurrent range for both the synchronous buck regulator output and the low dropout linearregulator output.Test points are provided to monitor the Input voltage, Output voltage, shut down controland power good signal.1.3WHAT THE TC1303 DFN ADJUSTABLE OUTPUT DEMO BOARD KITINCLUDESThis TC1303 DFN Adjustable Output Demo Board kit includes:•TC1303 DFN Adjustable Output Demo Board (102-00092)•TC1303 DFN Adjustable Output Demo Board User’s Guide(Electronic version on CD-ROM)•Analog and Interface Products Demonstration Boards CD-ROM (DS21912)DS51617A-page 6© 2006 Microchip Technology Inc.TC1303 DFN ADJUSTABLE OUTPUTDEMO BOARD USER’S GUIDE Chapter 2. Installation and Operation2.1INTRODUCTIONThe TC1303 DFN Adjustable Output Demo Board demonstrates the use of Microchip'sTC1303C 500mA Synchronous Buck Regulator, + 300mA LDO with Power-Goodoutput device for dual supply voltage applications.2.2FEATURESTheTC1303 DFN Adjustable Output Demo Board has the following features.•Test points for applying Input voltage (2.7V to 5.5V)•Using Potentiometer, one can set the Buck regulator output voltage from 1.8V to4.0V•Fixed LDO regulator output voltage of 2.5V•Test points for connecting external loads:-Buck regulator Output V OUT1 = 0mA to 500mA-LDO regulator Output V OUT2 = 0mA to 300mA•Test points for monitoring:-Power-Good Output for both V OUT1 and V OUT2-Shutdown for V OUT1 and Shutdown for V OUT2-Feedback voltage•Switch S1 can used to perform the shutdown operation on V OUT1 and V OUT22.3GETTING STARTEDThe TC1303 DFN Adjustable Output Demo Board is fully assembled and tested forevaluating the TC1303C device. The board requires the use of an external input volt-age source of (2.7V to 5.5V) and maximum external load of 500mA for buck regulatoroutput and 300mA for LDO regulator output.2.3.1Power Input and Output Connection2.3.1.1POWERING THE TC1303 DFN ADJUSTABLE OUTPUT DEMO BOARDFor normal operation, it is necessary to pull up the shutdown pins of TC1303C device,the pull up is provided through switch S1 provided on-board.1.Apply the Input voltage (2.7V to 5.5V for normal operation) to the board testpoints to TP1 (+V IN) and TP2 (P GND) (refer to Figure2-1).2.Connect the buck regulator load (0mA to 500mA for normal operation) to theboard test points TP3 (V OUT1) and TP4 (P GND).The output voltage can be variedfrom 1.8V to 4.0V using the potentiometer provided on-board. By turning thepotentiometer clockwise or counterclockwise, the voltage can be increased ordecreased within the 1.8V to 4.0V range.3.Connect the LDO regulator load (0mA to 300mA for normal operation) to testpoint TP6 (V OUT2) and TP10 (A GND). The LDO regulator provides a fixed outputvoltage of 2.5V.© 2006 Microchip Technology Inc.DS51617A-page 7TC1303 DFN Adjustable Output Demo Board User’s GuideDS51617A-page 8© 2006 Microchip Technology Inc.4.The power-good output signal is available on the test point TP5 (PG).5.The switch S1, position 1 and position 2 are used to determine the SHDN1 and SHDN2 modes for the TC1303C device.6.With switch S1, position 1 pushed to the right, the SHDN1 pin is pulled up andthe output V OUT1 of the TC1303C device is enabled. When switch S1, position 1 is to the left, the TC1303C device is in low quiescent current SHDN1 mode andthe output V OUT1 is disabled. The signal is available on test point TP8.7.Similarly with switch S1, position 2 pushed to the right, the SHDN2 pin is pulledup and the output V OUT2 of the TC1303C device is enabled. When switch S1, position 2 is to the left, the TC1303C device is in low quiescent current SHDN2mode and the output V OUT2 is disabled. The signal is available on test point TP7.FIGURE 2-1:Setup Configuration DiagramInstallation and Operation© 2006 Microchip Technology Inc.DS51617A-page 92.3.1.2APPLYING LOAD TO TC1303 DFN ADJUSTABLE OUTPUT DEMOBOARDA variable resistive load can be used to verify the line and load regulation. The loadresistance is connected between the points TP3 and TP4 for the buck regulator. Tomeasure the output voltage, connect the common point of multi-meter to TP4 and thepositive terminal to TP3. By varying the load one can verify the load regulation bymeasuring the output voltage over entire load range of 0mA to 500mA. Similarly, byvarying the line voltage from 2.7V to 5.5V and checking the output voltage, the lineregulation can be calculated.The best way to evaluate the TC1303 DFN Adjustable Output Demo Board is to dig intothe circuit. Measure voltages and currents with a DVM and probe the board with anoscilloscope.Calculating Adjustable Output VoltageThe buck regulator output voltage is adjustable by using two external resistors as avoltage divider. For adjustable-output voltages, it is recommended that the top resistordivider value be 200kohm. The bottom resistor can be calculated using the followingformula.EQUATION 2-1:ExampleFor setting the output voltage to 3.2V.EQUATION 2-2:The R BOT resistor can be set using the potentiometer (R7) provided on board so as toprovide an output voltage of 3.2V.R BOT R TOP V FB V OUT1V FB –------------------------------------⎠⎟⎞⎝⎜⎛×=Where:R TOP=Top resistor (200 kohm)V OUT1=Output Voltage V FB=0.8V R BOT =Bottom resistorWhere:R TOP=200 kohm V OUT1= 3.2V V FB =0.8VR BOT 200 kohm 0.8V 3.2V 0.8V –----------------------------⎠⎞⎝⎛×=66.66 kohm=TC1303 DFN Adjustable Output Demo Board User’s Guide NOTES:DS51617A-page 10© 2006 Microchip Technology Inc.TC1303 DFN ADJUSTABLE OUTPUTDEMO BOARD USER’S GUIDE Appendix A. Schematic and LayoutsA.1INTRODUCTIONThis appendix contains the following schematics and layouts for the TC1303 DFNAdjustable Output Demo board:•Board – Schematic•Board – Top Silk Screen Layer•Board – Top Metal Layer•Board – Bottom Metal Layer© 2006 Microchip Technology Inc.DS51617A-page 11TC1303 DFN Adjustable Output Demo Board User’s GuideDS51617A-page 12© 2006 Microchip Technology Inc.Schematic and Layouts© 2006 Microchip Technology Inc.DS51617A-page 13TC1303 DFN Adjustable Output Demo Board User’s GuideDS51617A-page 14© 2006 Microchip Technology Inc.Schematic and Layouts© 2006 Microchip Technology Inc.DS51617A-page 15TC1303 DFN Adjustable Output Demo Board User’s Guide NOTES:DS51617A-page 16© 2006 Microchip Technology Inc.TC1303 DFN ADJUSTABLE OUTPUTDEMO BOARD USER’S GUIDE© 2006 Microchip Technology Inc.DS51617A-page 17Appendix B. Bill Of Materials (BOM)TABLE B-1:BILL OF MATERIALS (BOM)QTY ReferenceDescriptionManufacturerPart Number 1C1Cap Ceramic 4.7μF 6.3V X5R 0805Panasonic ® - ECG ECJ-2FB0J475K 1C2Cap 10uF 6.3V Ceramic X5R 0805Panasonic - ECG ECJ-2FB0J106M 1C3Cap 33pF 50V Cerm Chip 0805 SMD Panasonic - ECG ECJ-2VC1H330J 2C4,C5Cap 1uF 16V Ceramic 0805 X5R Panasonic - ECG ECJ-2FB1C105K 1L1Inductor power shield 4.7μH Coiltronics/Div of Coo-per/Bussmann SD3118-4R7-R 3R1, R2, R3Res 1.0M Ohm 1/8W 5% 0805 SMD Panasonic - ECG ERJ-6GEYJ105V 1R4Res 200K Ohm 1/8W 1% 0805 SMD Panasonic - ECG ERJ-6ENF2003V 1R5Res 4.99K Ohm 1/8W 1% 0805 SMD Panasonic - ECG ERJ-6ENF4991V 1R6Res 49.9K Ohm 1/8W 1% 0805 SMD Panasonic - ECG ERJ-6ENF4992V 1R7Trimpot 500K Ohm 11 Trn 5mm Top Murata Electronics ®North AmericaPVG5A504C01R001S1Switch Dip 2 Pos half pitch SMTITT Industries / C&K Div TDA02H0SK110TP1, TP2, TP3, TP4, TP5, TP6, TP7, TP8, TP9, TP10PC Test point compact SMTKeystone ® Electronics50161U1IC PWM 500mA/ LDO 300mA 10 DFN Microchip Technology Inc TC1303C-ZI0EMFAMERICASCorporate Office2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200Fax: 480-792-7277 Technical Support: Web Address:Asia Pacific OfficeSuites 3707-14, 37th Floor Tower 6, The Gateway Habour City, KowloonHong KongTel: 852-2401-1200Fax: 852-2401-3431 AtlantaAlpharetta, GATel: 770-640-0034Fax: 770-640-0307BostonWestborough, MATel: 774-760-0087Fax: 774-760-0088 ChicagoItasca, ILTel: 630-285-0071Fax: 630-285-0075DallasAddison, TXTel: 972-818-7423Fax: 972-818-2924DetroitFarmington Hills, MITel: 248-538-2250Fax: 248-538-2260 KokomoKokomo, INTel: 765-864-8360Fax: 765-864-8387Los AngelesMission Viejo, CATel: 949-462-9523Fax: 949-462-9608San JoseMountain View, CATel: 650-215-1444Fax: 650-961-0286 TorontoMississauga, Ontario, CanadaTel: 905-673-0699Fax: 905-673-6509ASIA/PACIFICAustralia - SydneyTel: 61-2-9868-6733Fax: 61-2-9868-6755China - BeijingTel: 86-10-8528-2100Fax: 86-10-8528-2104China - ChengduTel: 86-28-8676-6200Fax: 86-28-8676-6599China - FuzhouTel: 86-591-8750-3506Fax: 86-591-8750-3521China - Hong Kong SARTel: 852-2401-1200Fax: 852-2401-3431China - QingdaoTel: 86-532-8502-7355Fax: 86-532-8502-7205China - ShanghaiTel: 86-21-5407-5533Fax: 86-21-5407-5066China - ShenyangTel: 86-24-2334-2829Fax: 86-24-2334-2393China - ShenzhenTel: 86-755-8203-2660Fax: 86-755-8203-1760China - ShundeT el: 86-757-2839-5507Fax: 86-757-2839-5571China - WuhanTel: 86-27-5980-5300Fax: 86-27-5980-5118China - XianTel: 86-29-8833-7250Fax: 86-29-8833-7256ASIA/PACIFICIndia - BangaloreTel: 91-80-4182-8400Fax: 91-80-4182-8422India - New DelhiTel: 91-11-5160-8631Fax: 91-11-5160-8632India - PuneTel: 91-20-2566-1512Fax: 91-20-2566-1513Japan - YokohamaTel: 81-45-471- 6166Fax: 81-45-471-6122Korea - GumiTel: 82-54-473-4301Fax: 82-54-473-4302Korea - SeoulTel: 82-2-554-7200Fax: 82-2-558-5932 or82-2-558-5934Malaysia - PenangTel: 60-4-646-8870Fax: 60-4-646-5086Philippines - ManilaTel: 63-2-634-9065Fax: 63-2-634-9069SingaporeTel: 65-6334-8870Fax: 65-6334-8850Taiwan - Hsin ChuTel: 886-3-572-9526Fax: 886-3-572-6459Taiwan - KaohsiungTel: 886-7-536-4818Fax: 886-7-536-4803Taiwan - TaipeiTel: 886-2-2500-6610Fax: 886-2-2508-0102Thailand - BangkokTel: 66-2-694-1351Fax: 66-2-694-1350EUROPEAustria - WelsTel: 43-7242-2244-3910Fax: 43-7242-2244-393Denmark - CopenhagenTel: 45-4450-2828Fax: 45-4485-2829France - ParisTel: 33-1-69-53-63-20Fax: 33-1-69-30-90-79Germany - MunichTel: 49-89-627-144-0Fax: 49-89-627-144-44Italy - MilanTel: 39-0331-742611Fax: 39-0331-466781Netherlands - DrunenTel: 31-416-690399Fax: 31-416-690340Spain - MadridTel: 34-91-708-08-90Fax: 34-91-708-08-91UK - WokinghamTel: 44-118-921-5869Fax: 44-118-921-5820 W ORLDWIDE S ALES AND S ERVICE06/08/06DS51617A-page 18© 2006 Microchip Technology Inc.。
PCIE-1758 Series Startup Manual
PCIE-1758 Series Startup Manual 1Before installation, please ensure that the following items are included in your shipment:• 1 x PCIE-1758 series card • 1 x PCIE-1758 startup manualIf any item is missing or damaged, contact your distributor or sales representative immediately.For more detailed product information, please refer to the PCIE-1758 series user manual provided on the Advantech Support Portal at /support/new_default.aspx.FCC Class AThis equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC rules. These limits are designed to provide rea-sonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses, and can radiate radio frequen-cy energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause interference. In such cases, users are required to correct the interference at their own expense.CEThis product has passed the CE test for environmental specifications when shielded cables are used for external wiring. We recommend the use of shielded cables. This type of cable is available from Advantech. Please contact your local supplier for ordering information.PCIE-1758DIO 128-Ch Isolated Digital I/O Card, PCIE-1758DI 128-Ch Isolated Digital Input Card,PCIE-1758DO 128-Ch Isolated Digital Output Card Startup ManualAdvantech’s PCIE-1758 series comprises multiple cards with various I/O configurations that can be selected ac-cording to application scenario.Each PCIE-1758 digital I/O card provides 128 isolated DI/O channels with 2500 V DC protection. Equipped with high sink current capabilities, these cards can support diverse industrial automation applications. Moreover, the added inclusion of Advantech’s DAQNavi driver software ensures easy configuration and efficient programming.Isolated Digital Input• Input Channels: - PCIE-1758DIO: 64 - PCIE-1758DI: 128• Input Voltage:- Logic 0: 3 V max. (0 V DC min.) - Logic 1: 10 V min. (30 V DC max.)• Input Current: 3.8mA @ 12 V DC 7.2mA @ 24 V DC• Interrupt-Capable Channel: - PCIE-1758DIO: 64 - PCIE-1758DI: 128• Digital Filter Channel: - PCIE-1758DIO: 64 - PCIE-1758DI: 128• Isolation Protection: 2,500 V DC • Overvoltage Protection: 70 V DC • Opto-Isolator Response: 100 μs • Input Resistance: 3.6 K Ω @ 1WIsolated Digital Output• Output Channels: PCIE-1758DIO: 64 PCIE-1758DO: 128• Output Type: Sink (NPN)• Isolation Protection: 2,500 V DC • Output Voltage: 5 ~ 40 V DC • Sink Current:350mA/ch (sink) @25 °C 250mA/ch (sink) @60 °C• Opto-Isolator Response: 100 μsFor more information about this or other Advantech products, please visit our website at/products/ProView/For technical support and service, visit our support website at This manual is for the PCIE-1758 series.Part No. 2041175810 Printed in TaiwanEdition 1November 20182 PCIE-1758 Series Startup ManualDigital Filter• Digital Filter Time [sec] = 2^n/(8 x 10^6) n = setting data (0 ~ 20)Setting Data (n)Digital Filter Time Setting Data (n)Digital Filter Time 7 (07h)16 μsec 14 (0Eh) 2.048 msec 8 (08h)32 μsec 15 (0Fh) 4.096 msec 9 (09h)64 μsec 16 (10h)8.192 msec 10 (0Ah)128 μsec 17 (11h)16.384 msec 11 (0Bh)256 μsec 18 (12h)32.768 msec 12 (0Ch)512 μsec 19 (13h)65.536 msec 13 (0Dh)1.024 msec20 (14h)131.072 msecThe connector, switch, and jumper locations on the PCIE-1758 series digital I/O cards are shown in Figures 1 ~ 3.Figure 1. PCIE-1758 DIO Card LayoutFigure 2. PCIE-1758 DI Card LayoutFigure 3. PCIE-1758 DO Card LayoutBoard ID (SW1)The PCIE-1758 series have a built-in DIP switch (SW1), which is used to define each card’s board ID. When there are multiple cards on the same chassis, this board ID switch is useful for identifying each card’s device number. After setting for each PCIE-1758 series, you can identify each card in system with different device numbers. The default value of board ID is 0 and if you need to adjust it to other value, please set the SW1 by referring to the below table.Board ID (dec)Switch Position * = default 1 (ID3) 2 (ID2) 3 (ID1) 4 (ID0)*0On On On On 1On On On Off :::::14Off Off Off On 15OffOffOffOffPower-On Configuration (JP2)The default configuration after a system power on or hard-ware reset for all isolated output channels is set to open (the current of the load cannot be in sink mode). This is to prevent system starts or resets from damaging external devices.When the system is hot reset, the status of the isolated digital output channels is selected by jumper JP2. The configuration of jumper JP2 is shown below.JP2Power-On Configuration After HotResetsRetain last status after hot resetsDefault configuration (default settings)PCIE-1758 Series Startup Manual 3Figure 4. PCIE-1758 DIO Card Connector Pin Assignments4 PCIE-1758 Series Startup ManualFigure 5. PCIE-1758 DI Card Connector Pin AssignmentsPCIE-1758 Series Startup Manual 5Figure 6. PCIE-1758 DO Card Connector Pin Assignments6 PCIE-1758 Series Startup ManualPin NameDescriptionIsolated Digital Input Pn_IDI00~07Isolated digital input of port n(n = 0~7 for PCIE-1758DIO, 0~F for PCIE-1758DI, hex)P01_ECOM Common port of isolated digital input ports 0 and 1P23_ECOM Common port of isolated digital input ports 2 and 3P45_ECOM Common port of isolated digital input ports 4 and 5P67_ECOM Common port of isolated digital input ports 6 and 7P89_ECOM Common port of digital input ports 8 and 9P AB_ECOM Common port of digital input ports A and BPCD_ECOM Common port of digital input ports C and DPEF_ECOMCommon port of digital input ports E and FIsolated Digital Output Pn_IDO00~07Isolated digital output of port n(n = 0~7 for PCIE-1758DIO, 0~F for PCIE-1758DO, hex)P01_PCOM Free wheeling common diode for isolated digital output ports 0 1P23_PCOM Free wheeling common diode for isolated digital output ports 2 and 3P45_PCOM Free wheeling common diode for isolated digital output ports 4 and 5P67_PCOM Free wheeling common diode for Isolat-ed digital output of port 6 & port 7P89_PCOM Free wheeling common diode for isolated digital output ports 8 and 9P AB_PCOM Free wheeling common diode for isolated digital output ports A and B PCD_PCOM Free wheeling common diode for isolated digital output ports C and D PEF_PCOM Free wheeling common diode for isolated digital output ports E and F GNDIsolation groundingIsolated Digital InputAll of the isolated digital input channels accept bi-directional 10 ~ 30 V DC voltage inputs. This means positive or negative voltage can be applied to an isolated input pin (IDIn) The figure below shows how to connect an external input source to one of the card’s isolated input channels.Figure 7. Isolated Digital Input ConnectionIsolated Digital OutputAll of the isolated output channels are equipped with a MOSFET , polyswitch (for current protection), and flywheel diode that can be activated by connecting PCOM to V DC for use with inductive loads. If external voltage (5 ~ 40 V DC ) is applied to an isolated output channel, the current will flow from the external voltage source to the card. Please note that the current passed through each IDO channel shouldnot exceed 350 mA.Figure 8. Isolated Digital Output Connection1. Power off the computer and unplug the power cord and cables before installing or removing any components.2. Remove the computer cover.3. Remove the slot cover on the back panel of the computer.4. T ouch the metal surface of the computer to neutralize any static electricity that might be in your body.5. Insert the PCIE-1758 series card into a PCI Express slot. Holding the card by its edges, carefully push it into the PCIEcard slot. Be careful not to use excessive force in order to avoid damaging the card.6. Fasten the PCIE-1758 card bracket to the back panel rail of the computer using screws.7. Connect any accessories (100-pin cable, wiring terminals, etc.) to the PCIE-1758 card.8. Replace the cover of the computer chassis. Reconnect any cables that were disconnected in Step 2.9. Plug in the power cord and turn on the computer.PCIE-1758 Series Startup Manual 7。
MEMORY存储芯片VIPER17LN中文规格书
February 2017 DocID14419 Rev 11This is information on a product in full production.Energy saving VIPerPlus: HV switching regulator for flybackconverterDatasheet - production dataFigure 1: Typical topologyFeatures∙800 V avalanche rugged power section ∙PWM operation with frequency jittering for low EMI∙Operating frequency:-60 kHz for L type -115 kHz for H type∙Standby power < 30 mW at 265 V AC∙Limiting current with adjustable set point ∙Adjustable and accurate overvoltage protection∙On-board soft-start∙Safe auto-restart after a fault condition ∙Hysteresis thermal shutdownApplications∙Adapters for PDA, camcorders, shavers,cellular phones, videogames∙Auxiliary power supply for LCD/PDP TV,monitors, audio systems, computer,industrial systems, LED driver, No el-cap LED driver∙SMPS for set-top boxes, DVD players and recorders, white goodsDescriptionThe device is an off-line converter with an 800 V rugged power section, a PWM control, two levels of overcurrent protection, overvoltage and overload protections, hysteresis thermalprotection, soft-start and safe auto-restart after any fault condition removal. The burst modeoperation and the device’s very low consumption meet the standby energy saving regulations.Advance frequency jittering reduces EMI filter cost. Brown-out function protects the switch mode power supply when the rectified input voltage level is below the normal minimum level specified for the system. The high voltage startup circuit is embedded in the device.Operation descriptions VIPER17 7.9 About CONT pinReferring to the Figure 27: "CONT pin configuration", through the CONT pin, the belowfeatures can be implemented:1.Current Limit set point2.Over voltage protection on the converter output voltageThe Table 9: "CONT pin configurations" referring to the Figure 27: "CONT pinconfiguration", lists the external components needed to activate one or plus of the CONTpin functions.Notes:(1)R LIM has to be fixed before of R OVP.7.10 Feed-back and overload protection (OLP)The VIPER17 is a current mode converter: the feedback pin controls the PWM operation,controls the burst mode and actives the overload protection. Figure 28: "FB pinconfiguration (minimal) " and Figure 29: " FB pin configuration ( two poles and one zero)"show the internal current mode structure.With the feedback pin voltage between V FBbm and V FBlin, see Table 8: "Controller section ",the drain current is sensed and converted in voltage that is applied to the non inverting pinof the PWM comparator. See Figure 2: "Block diagram".This voltage is compared with the one on the feedback pin through a voltage divider oncycle by cycle basis. When these two voltages are equal, the PWM logic orders the switchoff of the power MOSFET. The drain current is always limited to I Dlim value.DocID14419 Rev 11VIPER17 Operation descriptionsDocID14419 Rev 11Operation descriptionsVIPER17DocID14419 Rev 11Equation 7f PFB1=R FB(DYN)+R FB12∙π∙C FB ∙(R FB(DYN)∙R FB1)Equation 8f PFB1=12∙π∙C FB1∙(R FB1+R FB(DYN))The R FB(DYN) is the dynamic resistance seen by the FB pin.The C FB1 capacitor fixes the OLP delay and usually C FB1 results much higher than C FB . The Equation 5 can be still used to calculate the OLP delay time but C FB1 has to be considered instead of C FB . Using the alternative compensation network, the designer can satisfy, in all case, the loop stability and the enough OLP delay time alike.Figure 28: FB pin configuration (minimal)VIPER17 Operation descriptions 7.11 Burst-mode operation at no load or very light loadWhen the load decrease the feedback loop reacts lowering the feedback pin voltage. If itfalls down the burst mode threshold, V FBbm, the power MOSFET is not more allowed to beswitched on. After the MOSFET stops, as a result of the feedback reaction to the energydelivery stop, the feedback pin voltage increases and exceeding the level, V FBbm + V FBbmhys,the power MOSFET starts switching again. The burst mode thresholds are reported onTable 8: "Controller section " and Figure 30: "Burst mode timing diagram, light loadmanagement" shows this behavior. Systems alternates period of time where powerMOSFET is switching to period of time where power MOSFET is not switching; this deviceworking mode is the burst mode. The power delivered to output during switching periodsexceeds the load power demands; the excess of power is balanced from not switchingperiod where no power is processed. The advantage of burst mode operation is an averageswitching frequency much lower then the normal operation working frequency, up to somehundred of hertz, minimizing all frequency related losses. During the burst-mode the draincurrent peak is clamped to the level, I D_BM, reported on Table 8: "Controller section ".7.12 Brown-out protectionBrown-out protection is a not-latched shutdown function activated when a condition ofmains under voltage is detected. The Brown-out comparator is internally referenced to V BRththreshold, see Table 8: "Controller section ", and disables the PWM if the voltage applied atthe BR pin is below this internal reference. Under this condition the power MOSFET isturned off. Until the Brown out condition is present, the V DD voltage continuously oscillatesbetween the V DDon and the UVLO thresholds, as shown in the timing diagram of Figure 31:"Brown-out protection: BR external setting and timing diagram". A voltage hysteresis ispresent to improve the noise immunity.The switching operation is restarted as the voltage on the pin is above the reference plusthe before said voltage hysteresis. See Figure 5: "Brown out threshold test circuit".The Brown-out comparator is provided also with a current hysteresis, I BRhyst. The designerhas to set the rectified input voltage above which the power MOSFET starts switching afterbrown out event, V INon, and the rectified input voltage below which the power MOSFET isswitched off, V INoff. Thanks to the I BRhyst, see Table 8: "Controller section ", these twothresholds can be set separately.DocID14419 Rev 11。
伯南克ATP云恶意软件检测API设置指南说明书
Table of ContentsThreat Intelligence Open APIThreat Intelligence Open APIJuniper Advanced Threat Prevention Cloud (Juniper ATP Cloud) provides the following APIs that can help you keep your network free of sophisticated malware and cyberattacks by using superior cloud-based protection:Threat Intelligence API OverviewThe Threat Intelligence open API allows you to program the Juniper ATP Cloud Command and Control server (C&C) feeds to suit your requirements. You can perform the following operations using the threat intelligence API:•Inject an IP, URL, or domain into a C&C feed with a threat level from 1 through 10. You can create up to 30 different custom C&C feeds.•An IP can be an IP address, IP range, or IP subnet.•Both IPv4 and IPv6 addresses are supported.•Update the threat level of an IP, URL, or domain from 1 through 10.•Delete a specific server in the feed or delete the entire feed.•Retrieve the current status of an operation (processing) or errors (if any) from the feed processing engine.The Threat Intelligence API supports a Swagger API specification in JSON format to allow programmatic access to it. For more information on the Swagger API specification, see https://threat-/swagger.json.NOTE: Starting in Junos OS 19.2, SRX Series Firewalls support inspection of encrypted traffic(HTTPS) as well as HTTP traffic in threat intelligence feeds. Server name identification (SNI)checks are also supported. These changes do not introduce new CLI commands. Existingcommands make use of this functionality.The following table lists the rate limits (number of requests you can make per minute) for the Threat Intelligence APIs. If you exceed these rate limits, you will receive a 429 - Too many Requests error.Configuration and SetupT o access the API, you must create an application token in the Juniper ATP Cloud Web UI and use that token as the bearer token in the authorization header.T o generate an application token:1.Log in to the Juniper ATP Cloud Web UI using your credentials. Select Administration > ApplicationT okens and click the plus (+) sign. Fill in the name of the token and other required details in the pop-up box that appears and click OK to create a new token. See Figure 1 on page 3.Figure 1: Creating an Application T oken2.A confirmation pop-up message appears, indicating the creation of a new token, as shown in Figure 2on page 3. You can now use this token to access the Juniper ATP Cloud API.Figure 2: Confirming the Creation of an Application T okenNOTE: You can generate a maximum of 10 tokens per user, and each token is valid for oneyear.For more information on how to create application tokens, see Creating Application T okens.Usage ExamplesThe following cURL examples illustrate the use of the threat intelligence API:•curl -k -v -XPOST -H "Authorization: Bearer <TOKEN>" -F file=@/tmp/whitelist.txt <API HOST>/v1/cloudfeeds/ whitelist/file/ip/<FEEDNAME>•curl -k -v -XPOST -H "Authorization: Bearer <TOKEN>" -F file=@/tmp/whitelist.txt <API HOST>/v1/cloudfeeds/cc/ file/ip/<FEEDNAME>where:•API HOST is the name of the Open API hostname corresponding to the location of the customer portal.Please refer to Table 1 on page 5 for the correct hostname for your location.•TOKEN is the application token generated in the Juniper ATP Cloud Web UI.•FEED NAME is the name of the feed you want to create.Juniper ATP Cloud API OverviewYou can perform the following operations using the Juniper ATP Cloud API:•Retrieve the blocklist or allowlist for the specific server type.•Update an IP, URL, or FQDN in a blocklist or allowlist server list.•An IP can be an IP address, IP range, or IP subnet.•Both IPv4 and IPv6 addresses are supported.•Delete a specific server in the list or delete the entire list.The Juniper ATP Cloud API supports a Swagger API specification in JSON format to allow programmatic access to it. For more information on the Swagger API specification, see https:///swagger.json.The following table lists the rate limits (number of requests you can make per minute) for the Juniper ATP Cloud APIs. If you exceed these rate limits, you will receive a 429 - Too many Requests error.NOTE: Juniper ATP Cloud supports up to 3,000 entries in the allowlist and 3,000 entires in the blocklist.Configuration and SetupT o access the API, you must create an application token in the Juniper ATP Cloud Web UI and use that token as the bearer token in the authorization header. See section"Configuration and Setup" on page 2 for more information on the creation of the token.Juniper ATP Cloud URLsJuniper ATP Cloud hostnames varies by location. Please refer to the following table:Table 1: Juniper ATP Cloud URLs by LocationTable 1: Juniper ATP Cloud URLs by Location(Continued)Usage ExampleThe following cURL example illustrates the use of the Juniper ATP Cloud API:•curl -k -v -XPOST -H "Authorization: Bearer <TOKEN>” -F file=@/tmp/blacklist.txt <API HOSTNAME>/v1/skyatp/ blacklist/file/ip/<FEED NAME>where:•API HOST is the name of the Open API hostname corresponding to the location of the customer portal.Please refer to Table 1 on page 5 for the correct hostname for your location.•TOKEN is the application token generated in the Juniper ATP Cloud Web UI.•FEED NAME is the name of the feed you want to create.File/Hash API OverviewThe file/hash API lets you submit files for analysis. You can perform the following operations:•Look up sample malware scores by hash.•Submit samples for malware analysis.•Update an IP, URL, or FQDN from a file in a specific list.•An IP can be an IP address, IP range, or IP subnet.•Both IPv4 and IPv6 addresses are supported.The file/hash API supports a Swagger API specification in JSON format to allow programmatic access to it. For more information on the Swagger API specification, see https:/// swagger.json.Configuration and SetupT o access the API, you must create an application token in the Juniper ATP Cloud Web UI and use that token as the bearer token in the authorization header. See section"Configuration and Setup" on page 2 for more information on the creation of the token.Usage ExampleThe following cURL example illustrates the use of the file/hash API:•curl -H "Authorization: Bearer<TOKEN>” -k <API HOSTNAME>/v1/skyatp/lookup/hash/<SHA256>?full_report=true •curl -H "Authorization: Bearer<TOKEN>” -k -F file=@/srv/sample.exe <API HOSTNAME>/v1/skyatp/submit/sampleNOTE: API HOST is the name of the Open API hostname corresponding to the location of thecustomer portal. Please refer to Table 1 on page 5 for the correct hostname for your location.where:•TOKEN is the application token generated in the Juniper ATP Cloud Web UI.•SHA256 is the sample hash. Only SHA256 is supported at this time.Full reports will be completely supported in an upcoming release. The report you receive right now may slightly different in appearance and content.Infected Host API OverviewThe infected host feed is generated by Juniper ATP Cloud and is used to flag compromised hosts. The feed is dynamic. Hosts are automatically added when Juniper ATP Cloud suspects a host has been compromised (through a proprietary algorithm) and can be manually removed from the list through the user interface once you feel the host is no longer compromised. The feed lists the IP address or IP subnet of the host along with a threat level, for example, xxx.xxx.xxx.133 and threat level 5. This feed is unique to a realm and IP addresses within the real are assumed to be non-overlapping.Associated with the infected host feed are a allowlist and blocklist. These are different from the generic Juniper ATP Cloud allowlist and blocklist. The infected host feed uses these lists to remove hosts that are currently on an infected host feed (allowlist) and to always list a host in the infected host feed (blocklist.)With the infected host API, you can do the following:•Return a list of all IP addresses in the current infected host feed.•Return a list of all IP addresses in the infected host allowlist or blocklist.•Delete an IP address from the infected host allowlist or blocklist.•Add an IP address to the infected host allowlist or blocklist.The infected host API supports a Swagger API specification in JSON format to allow programmatic access to it. For more information on the Swagger API specification, see https:///swagger.json.Configuration and SetupT o access the API, you must create an application token in the Juniper ATP Cloud Web UI and use that token as the bearer token in the authorization header. See section"Configuration and Setup" on page 2 for more information on the creation of the token.IP Filter API OverviewA Dynamic Address Entry (DAE) provides dynamic IP address information to security policies. A DAE is a group of IP addresses, not just a single IP prefix, that can be imported. These IP addresses are for specific domains or for entities that have a common attribute such as a particular undesired location that poses a threat. The administrator can then configure security policies to use the DAE within a security policy. When the DAE is updated, the changes automatically become part of the security policy. There isno need to update the policy manually. Note that this is an IP address-only feed. It does not support URLs or fully qualified domain names (FQDNs).The IP filter APIs let you perform the following tasks:•Remove IP addresses (in a .csv file) from an IP filter feed•Add IP addresses (in a .csv file) to an IP filter feed.•Remove a specific IP address from the IP filter feed.•Add a specific IP address to the IP filter feed.•Remove a specific IP filter feed.•Get the processing status of a specific IP Filter feed.The IP filter API supports a Swagger API specification in JSON format to allow programmatic access to it. For more information on the Swagger API specification, see https:/// swagger.json.Configuration and SetupT o access the API, you must create an application token in the Juniper ATP Cloud Web UI and use that token as the bearer token in the authorization header. See section"Configuration and Setup" on page 2 for more information on the creation of the token.ExampleIn this example, targeted attacked are being performed against web servers in a DMZ while concealing their identities via T or. T or exit nodes move frequently and keeping an up-to-date list of all 1000+ exit nodes within a firewall policy is almost impossible. This can, however, be done easily using Juniper ATP Cloud APIs. For more information on this example, see Automating Cyber Threat Intelligence with Sky ATP.Shown below is an example script that performs the following actions:•Polls the official T orProject's exit-node list via cURL and extracts legitimate IP information via grep.•Utilizes Juniper ATP Cloud open API to install and propagate third-party threat intelligence to all SRX Series Firewalls in the network.•Runs on an hourly basis via cron to ensure that the active T or Relays are always being blocked. #!/bin/bash# Define Application Token (Paste in your value between the "")APPToken="Your_Application_Token_Here"# Define the name of the feed you wish to createFeedName="Tor_Exit_Nodes"#Define temporary file to store address listTorList=/var/tmp/torlist.txt# cURL fetches Tor Relay list from https:///exit-addresses# grep identifies and extracts valid IP addresses from the listcurl -k https:///exit-addresses | grep -E -o'(25[0-5]|2[0-4][0-9]|[01]?[0-9][0-9]?)\.(25[0-5]|2[0-4][0-9]|[01]?[0-9][0-9]?)\.(25[0-5]|2[0-4][0-9]|[01]?[0-9][0-9]?)\.(25[0-5]|2[0-4][0-9]|[01]?[0-9][0-9]?)' > $TorList#Remove old Feed information before uploading new listcurl -k -v -XDELETE -H "Authorization: Bearer $APPToken" -F server='*' https:///v1/cloudfeeds/blacklist/param/ip/${FeedName}# Wait for 5 seconds before uploading new listsleep 5#Upload List to SkyATP as Feed Tor_Exit_Nodescurl -k -v -XPOST -H "Authorization: Bearer $APPToken" -F file=@${TorList} https:///v1/cloudfeeds/blacklist/file/ip/${FeedName}# Cleanuprm $TorList# ExitOnce the script has been run successfully, we can see that the latest T or Nodes are being blocked during an ICMP request below (feed-name=Tor_Exit_Nodes)<14>12016-10-17T15:18:11.618ZSRX-1500RT_SECINTEL-SECINTEL_ACTION_LOG[*********.x.x.x.137 category="secintel" sub-category="Blacklist" action="BLOCK" action-detail="DROP" http-host="N/A" threat-severity="0" source-address="5.196.121.161" source-port="1" destination-address="x.x.0.10" destination-port="24039" protocol-id="1" application="N/A" nested-application="N/A" feed-name="Tor_Exit_Nodes" policy-name="cc_policy" profile-name="Blacklist" username="N/A" roles="N/A" session-id-32="572564" source-zone-name="Outside" destination-zone-name="DMZ"] category=secintel sub-category=Blacklist action=BLOCK action-detail=DROP http-host=N/A threat-severity=0 source-address=x.x.0.110 source-port=1 destination-address=x.x.x.161 destination-port=24039 protocol-id=1 application=N/A nested-application=N/A feed-name=Tor_Exit_Nodes policy-name=cc_policy profile-name=Blacklist username=N/A roles=N/A session-id-32=572564 source-zone-name=Outside destination-zone-name=DMZSRX Series Update Intervals for Cloud FeedsThe following table provides the update intervals for each feed type. Note that when the SRX Series Firewall makes requests for new and updated feed content, if there is no new content, no updates are downloaded at that time.Table 2: Feed Update IntervalsTable 2: Feed Update Intervals (Continued)Open API for DNS CategoryThe following table provides the feed manifest that is downloaded by the SRX Series Firewall. Table 3: Feed ManifestTable 3: Feed Manifest (Continued)RELATED DOCUMENTATIONThreat Intelligence Open API Reference GuideJuniper Sky ATP Open API Reference GuideJuniper Networks, the Juniper Networks logo, Juniper, and Junos are registered trademarks of JuniperNetworks, Inc. in the United States and other countries. All other trademarks, service marks, registeredmarks, or registered service marks are the property of their respective owners. Juniper Networks assumes no responsibility for any inaccuracies in this document. Juniper Networks reserves the right to change,modify, transfer, or otherwise revise this publication without notice. Copyright © 2023 Juniper Networks, Inc. All rights reserved.。
AZ 17 产品说明书
DataOrdering dataProduct type descriptionAZ 17-11ZRK-ST Article number (order number)101140774EAN (European Article Number)4030661119731eCl@ss number, Version 9.027-27-26-02eCl@ss number, Version 11.027-27-26-02Approval - StandardsCertificates BGcULusCCCEAC CNCAGeneral dataProduct nameAZ 17Coding level according to ISO 14119Low Enclosure materialPlastic, glass-fibre reinforced thermoplastic, self-extinguishing Material of the contacts, electricalSilver Gross weight 85 g General data - Featureshigher Latching force Yes AZ17-11ZRK-STLong lifeSmall bodyMultiple codingDouble-insulated8 actuating planesInsensitive to soiling30 mm x 78.5 mm x 30 mmThermoplastic enclosure Connector M12 x 1, 4-pole High level of contact reliability with low voltages and currentsNumber of auxiliary contacts1Number of safety contacts1Safety appraisalStandards EN ISO 13849-1Mission Time20 Year(s)Safety appraisal - Safety outputsB10d Normally-closed contact (NC)2,000,000 OperationsB10d Normally open contact (NO)1,000,000 Operationsand ohmic loadNote (B10d Normally open contact (NO))at 10% IeMechanical dataMechanical life, minimum1,000,000 OperationsLatching force30 Npositive break travel11 mmPositive break force, minimum17 NActuating speed, maximum 2 m/sMechanical data - Connection techniqueTerminal Connector Connector plug M12, 4-pole, (A-coding) Mechanical data - DimensionsLength of sensor30 mmWidth of sensor30 mmHeight of sensor78.5 mmAmbient conditionsDegree of protection IP 67 to IEC/EN 60529Ambient conditions - Insulation valueRated insulation voltage U250 Vi4 kVRated impulse withstand voltage UimpElectrical dataThermal test current10 AUtilisation category AC-15230 VACUtilisation category AC-15 4 AUtilisation category DC-1324 VDCUtilisation category DC-13 4 ASwitching element NO contact, NC contactSwitching principle Creep circuit element Scope of deliveryIncluded in delivery Actuators must be ordered separately.Slot cover for dust-proof covering of the opening not in useNotesNote (General)Individual coding available on request Ordering codeProduct type description:AZ 17-(1)Z(2)K-(3)-(4)-(5)(1)111 NO contacts/1 NC contact022 NC contact(2)without Latching force 5 NR Latching force 30 N(3)without M16 cable gland2243Front cable entry2243-1Rear cable entryST M12 connector, 4 pole(4)1637Gold-plated contacts(5)5M Cable length 5 m6M Cable length 6 mPicturesProduct picture (catalogue individual photo)ID: kaz17f17| 106,0 kB | .png | 74.083 x 160.161 mm - 210 x 454Pixel - 72 dpi| 651,2 kB | .jpg | 221.192 x 478.367 mm - 627 x 1356Pixel - 72 dpiDimensional drawing basic componentID: kaz17g03| 265,7 kB | .jpg | 352.778 x 626.533 mm - 1000 x1776 Pixel - 72 dpi| 44,7 kB | .cdr || 8,1 kB | .png | 74.083 x 131.586 mm - 210 x 373Pixel - 72 dpiSwitch travel diagramID: kaz17s01| 52,6 kB | .jpg | 352.778 x 125.236 mm - 1000 x 355Pixel - 72 dpi| 2,0 kB | .png | 74.083 x 26.458 mm - 210 x 75 Pixel -72 dpi| 19,6 kB | .cdr |DiagramID: kaz17k03| 104,8 kB | .jpg | 352.778 x 369.358 mm - 1000 x1047 Pixel - 72 dpi| 18,6 kB | .cdr |K.A. Schmersal GmbH & Co. KG, Möddinghofe 30, D-42279 WuppertalThe details and data referred to have been carefully checked. Images may diverge from original. Further technical data can be found in the manual. Technical amendments and errors possible.Generated on 24/05/2021 04:38:39。
viper16
October 2011Doc ID 15232 Rev 51/25VIPER16Fixed frequency VIPer TM plus familyFeatures■800 V avalanche rugged power section ■PWM operation with frequency jittering for low EMI■Operating frequency: –60 kHz for L type –115 kHz for H type■No need of auxiliary winding for low power application■Standby power < 50 mW at 265 V AC ■Limiting current with adjustable set point ■On-board soft-start■Safe auto-restart after a fault condition ■Hysteretic thermal shutdownApplication■Replacement of capacitive power supply ■Auxiliary power supply for appliances, ■Power metering ■LED driversDescriptionThe device is an off-line converter with an 800 V avalanche ruggedness power section, a PWM controller, user defined overcurrent limit, protection against feedback networkdisconnection, hysteretic thermal protection, soft start up and safe auto restart after any faultcondition. It is able to power itself directly from the rectified mains, eliminating the need for an auxiliary bias winding.Advance frequency jittering reduces EMI filter cost. Burst mode operation and the devices very low consumption both help to meet the standard set by energy saving regulations.Figure 1.Typical applicationTable 1.Device summaryOrder codes Package Packaging VIPER16LN DIP-7Tube VIPER16HN VIPER16HD SO16 narrow Tube VIPER16HDTR T ape and reelVIPER16LD Tube VIPER16LDTRT ape and reelContents VIPER16Contents1Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2Typical power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54.1Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54.2Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54.3Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5Typical electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6Typical circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8High voltage current generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 9Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 10Soft start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 11Adjustable current limit set point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 12FB pin and COMP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 13Burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 14Automatic auto restart after overload or short-circuit . . . . . . . . . . . . . 17 15Open loop failure protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 16Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 17Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2/25Doc ID 15232 Rev 5VIPER16Block diagramDoc ID 15232 Rev 53/251 Block diagram2 Typical powerFigure 2.Block diagramTable 2.Typical powerPart number 230 V AC85-265 V ACAdapter (1)1.Typical continuous power in non ventilated enclosed adapter measured at 50 °C ambient.Open frame (2)2.Maximum practical continuous power in an open frame design at 50 °C ambient, with adequate heatsinking.Adapter (1)Open frame (2)VIPER169 W10 W5 W6 WPin settings VIPER164/25Doc ID 15232 Rev 53 Pin settingsNote:The copper area for heat dissipation has to be designed under the DRAIN pins.Table 3.Pin descriptionPin N.NameFunctionDIP-7SO1611-2GND Connected to the source of the internal power MOSFET and controllerground reference.-4N.A.Not available for user. It can be connected to GND (pins 1-2) or left not connected.25VDDSupply voltage of the control section. This pin provides the charging current of the external capacitor.36LIMThis pin allows setting the drain current limitation. The limit can be reduced by connecting an external resistor between this pin and GND. Pin left open if default drain current limitation is used.47FBInverting input of the internal trans conductance error amplifier. Connecting the converter output to this pin through a single resistor results in an output voltage equal to the error amplifier reference voltage (See V FB_REF on Table 7). An external resistors divider is required for higher output voltages.58COMPOutput of the internal trans conductance error amplifier. Thecompensation network have to be placed between this pin and GND to achieve stability and good dynamic performance of the voltage control loop. The pin is used also to directly control the PWM with an optocoupler. The linear voltage range extends from V COMPL to V COMPH (T able 7).7,813-16DRAINHigh voltage drain pin. The built-in high voltage switched start-up bias current is drawn from this pin too.Pins connected to the metal frame to facilitate heat dissipation.VIPER16Electrical dataDoc ID 15232 Rev 55/254 Electrical data4.1 Maximum ratings4.2 Thermal dataTable 4.Absolute maximum ratingsSymbolPin(DIP-7)ParameterValueUnitMinMax V DRAIN 7, 8Drain-to-source (ground) voltage800V E AV 7, 8Repetitive avalanche energy (limited by T J = 150 °C)2mJ I AR 7, 8Repetitive avalanche current (limited by T J = 150 °C)1A I DRAIN 7, 8Pulse drain current (limited by T J = 150 °C) 2.5A V COMP 5Input pin voltage -0.3 3.5V V FB 4Input pin voltage -0.3 4.8V V LIM 3Input pin voltage -0.3 2.4V V DD 2Supply voltage -0.3Selflimited V I DD 2Input current20mA P TOT Power dissipation at T A < 40 °C (DIP-7)1W Power dissipation at T A < 60 °C (SO16N)1W T J Operating junction temperature range -40150°C T STGStorage temperature-55150°C Table 5.Thermal dataSymbol ParameterMax value SO16N Max value DIP-7Unit R thJP Thermal resistance junction pin(Dissipated power = 1 W)3540°C/W R thJA Thermal resistance junction ambient (Dissipated power = 1 W)90110°C/W R thJAThermal resistance junction ambient (1)(Dissipated power = 1 W)1.When mounted on a standard single side FR4 board with 100 mm 2 (0.155 sq in) of Cu (35 μm thick)8090°C/WElectrical data VIPER166/25Doc ID 15232 Rev 54.3 Electrical characteristics(T J = -25 to 125 °C, V DD = 14 V (a); unless otherwise specified)a.Adjust V DD above V DDon start-up threshold before setting to 14 VTable 6.Power sectionSymbol ParameterTest conditionMin Typ Max Unit V BVDSS Break-down voltage I DRAIN = 1 mA,V COMP = GND, T J = 25 °C 800V I OFF OFF state drain currentV DRAIN = max rating,V COMP = GND60μA R DS(on)Drain-source on state resistanceI DRAIN = 0.2 A, T J = 25 °C 2024ΩI DRAIN = 0.2 A, T J = 125 °C4048ΩC OSSEffective (energy related) output capacitance V DRAIN = 0 to 640 V10pFTable 7.Supply sectionSymbol ParameterTest conditionMin Typ Max UnitVoltageV DRAIN _STARTDrain-source start voltage 405060V I DDch1Start up charging current V DRAIN = 100 V to 640 V , V DD = 4 V-0.6-1.8mA I DDch2Charging current during operation V DRAIN = 100 V to 640 V , V DD = 9 V falling edge-7-13mA V DD Operating voltage range 11.523.5V V DDclamp V DD clamp voltage I DD = 15 mA23.5V V DDon V DD start up threshold121314V V DDCSon VDD on internal high voltage current generator threshold9.510.511.5V V DDoff V DD under voltage shutdown threshold789VCurrentI DD0Operating supply current, not switchingF OSC = 0 kHz, V COMP = GND 0.6mA I DD1Operating supply current, switchingV DRAIN = 120 V , F SW = 60 kHz1.3mA V DRAIN = 120 V ,F SW = 115 kHz1.5mA I DDoff Operating supply current with V DD < V DDoff V DD < V DDoff 0.35mAI DDolOpen loop failure current thresholdV DD = V DDclamp V COMP = 3.3 V ,4 mAVIPER16Electrical dataDoc ID 15232 Rev 57/25Table 8.Controller sectionSymbol ParameterTest conditionMin Typ Max UnitError amplifier V REF_FBFB reference voltage3.23.3 3.4V I FB_PULL UP Current pull up-1μA G MT rans conductance2mA/VCurrent setting (LIM) pin V LIM_LOWLow level clamp voltageI LIM = -100 μA0.5VCompensation (COMP) pin V COMPH Upper saturation limit T J = 25 °C 3V V COMPLBurst mode thresholdT J = 25 °C 11.1 1.2V V COMPL_HYS Burst mode hysteresis T J = 25 °C40mV H COMPΔV COMP / ΔI DRAIN49V/AR COMP(DYN)Dynamic resistance V FB = GND 15k ΩI COMPSource / sink current V FB > 100 mV150μA Max source currentV COMP = GND, V FB = GND220μACurrent limitationI Dlim Drain current limitation I LIM = -10 μA, V COMP = 3.3 V ,T J = 25 °C0.380.40.42A t SS Soft-start time8.5ms T ON_MIN Minimum turn ON time 450ns I Dlim_bm Burst mode current limitationV COMP = V COMPL85mAOverloadt OVL Overload time 50ms t RESTARTRestart time after fault1sOscillator sectionF OSCSwitching frequencyVIPer16L 546066kHz VIPer16H 103115127kHz F D Modulation depth F OSC = 60 kHz ±4kHz F OSC = 115 kHz±8kHz F M Modulation frequency 230Hz D MAXMaximum duty cycle7080%Thermal shutdownT SD Thermal shutdown temperature 150160°C T HYSTThermal shutdown hysteresis30°C5 Typical electrical characteristics8/25Doc ID 15232 Rev 5Figure 10.I COMP vs T J Figure 11.Operating supply currentFigure 12.Operating supply currentFigure 13.IDlim vs R LIMFigure 14.Power MOSFET on-resistance vs T J Figure 15.Power MOSFET break down voltagevs TJDoc ID 15232 Rev 59/2510/25Doc ID 15232 Rev 5VIPER16Typical circuitcircuit6 TypicalTypical circuit VIPER16VIPER16Power section section7 PowerThe power section is implemented with an n-channel power MOSFET with a breakdownvoltage of 800 V min. and a typical R DS(on) of 20 Ω. It includes a SenseFET structure toallow a virtually lossless current sensing and the thermal sensor.The gate driver of the power MOSFET is designed to supply a controlled gate current duringboth turn-ON and turn-OFF in order to minimize common mode EMI. During UVLOconditions, an internal pull-down circuit holds the gate low in order to ensure that the powerMOSFET cannot be turned ON accidentally.8 High voltage current generatorThe high voltage current generator is supplied by the DRAIN pin. At the first start up of theconverter it is enabled when the voltage across the input bulk capacitor reaches theV DRAIN_START threshold, sourcing a I DDch1 current (see Table7 on page6); as the V DDvoltage reaches the V DDon threshold, the power section starts switching and the highvoltage current generator is turned OFF. The VIPer16 is powered by the energy stored in theV DD capacitor.In steady state condition, if the self biasing function is used, the high voltage currentgenerator is activated between V DDCSon and V DDon (see T able7 on page6), deliveringI DDch2, see Table7 on page6 to the V DD capacitor during the MOSFET off time (seeFigure21 on page13).The device can also be supplied through the auxiliary winding; in this case the high voltagecurrent source is disabled during steady-state operation, provided that VDD is aboveV DDCSon.At converter power-down, the V DD voltage drops and the converter activity stops as it fallsbelow V DDoff threshold (see T able7 on page6).Oscillator VIPER16 9 OscillatorThe switching frequency is internally fixed at 60 kHz (part number VIPER16LN or LD) or 115kHz (part number VIPER16HN or HD).In both cases the switching frequency is modulated by approximately ±4 kHz (60 kHzversion) or ±8 kHz (115 kHz version) at 230 Hz (typical) rate, so that the resulting spread-spectrum action distributes the energy of each harmonic of the switching frequency over anumber of sideband harmonics having the same energy on the whole but smalleramplitudes.start-up10 SoftDuring the converters' start-up phase, the soft-start function progressively increases thecycle-by-cycle drain current limit, up to the default value I Dlim. By this way the drain current isfurther limited and the output voltage is progressively increased reducing the stress on thesecondary diode. The soft-start time is internally fixed to t SS, see typical valueon Table8 on page7, and the function is activated for any attempt of converter start-up andafter a fault event.This function helps prevent transformers' saturation during start-up and short-circuit.11 Adjustable current limit set pointThe VIPer16 includes a current mode PWM controller: cycle by cycle the drain current issensed through the integrated resistor R SENSE and the voltage is applied to the noninverting input of the PWM comparator, see Figure2 on page3. As soon as the sensedvoltage is equal to the voltage derived from the COMP pin, the power MOSFET is switchedOFF.In parallel with the PWM operations, the comparator OCP, see Figure2 on page3, checksthe level of the drain current and switch OFF the power MOSFET in case the current ishigher than the threshold I Dlim, see Table8 on page7.The level of the drain current limit, I Dlim, can be reduced depending from the sunk currentfrom the pin LIM. The resistor R LIM, between LIM and GND pins, fixes the current sunk andthan the level of the current limit, I Dlim, see Figure13 on page9.When the LIM pin is left open or if the R LIM has an high value (i.e. > 80 kΩ) the current limitis fixed to its default value, I Dlim, as reported on T able8 on page7.VIPER16FB pin and COMP pin 12 FB pin and COMP pinThe device can be used both in non-isolated and in isolated topology. In case of non-isolated topology, the feedback signal from the output voltage is applied directly to the FBpin as inverting input of the internal error amplifier having the reference voltage, V REF_FB,see the Table8 on page7.The output of the error amplifier sources and sinks the current, I COMP, respectively to andfrom the compensation network connected on the COMP pin. This signal is then compared,in the PWM comparator, with the signal coming from the SenseFET; the power MOSFET isswitched off when the two values are the same on cycle by cycle basis. See the Figure2 onpage3and the Figure22 on page15.When the power supply output voltage is equal to the error amplifier reference voltage,V REF_FB, a single resistor has to be connected from the output to the FB pin. For higheroutput voltages the external resistor divider is needed. If the voltage on FB pin isaccidentally left floating, an internal pull-up protects the controller.The output of the error amplifier is externally accessible through the COMP pin and it’s usedfor the loop compensation: usually an RC network.As reported on Figure22 on page15, in case of isolated power supply, the internal erroramplifier has to be disabled (FB pin shorted to GND). In this case an internal resistor isconnected between an internal reference voltage and the COMP pin, see the Figure22 onpage15. The current loop has to be closed on the COMP pin through the opto-transistor inparallel with the compensation network. The V COMP dynamics ranges is between V COMPLand V COMPH as reported on Figure23 on page16.When the voltage V COMP drops below the voltage threshold V COMPL, the converter entersburst mode, see Section13 on page 16.When the voltage V COMP rises above the V COMPH threshold, the peak drain current willreach its limit, as well as the deliverable output power.Burst mode VIPER1613 BurstmodeWhen the voltage V COMP drops below the threshold, V COMPL, the power MOSFET is kept inOFF state and the consumption is reduced to I DD0 current, as reported on T able7 onpage6. As reaction at the energy delivery stop, the V COMP voltage increases and as soonas it exceeds the threshold V COMPL + V COMPL_HYS, the converter starts switching again withconsumption level equal to I DD1 current. This ON-OFF operation mode, referred to as “burstmode” and reported on Figure24 on page16, reduces the average frequency, which can godown even to a few hundreds hertz, thus minimizing all frequency-related losses andmaking it easier to comply with energy saving regulations. During the burst mode, the draincurrent limit is reduced to the value I Dlim_bm (reported on Table8 on page7) in order toavoid the audible noise issue.VIPER16Automatic auto restart after overload or short-circuit 14 Automatic auto restart after overload or short-circuitThe overload protection is implemented in automatic way using the integrated up-downcounter. Every cycle, it is incremented or decremented depending if the current logic detectsthe limit condition or not. The limit condition is the peak drain current, I Dlim , reported onTable8 on page7 or the one set by the user through the R LIM resistor, as reported inFigure13 on page9. After the reset of the counter, if the peak drain current is continuouslyequal to the level I Dlim, the counter will be incremented till the fixed time, t OVL, after that willbe disabled the power MOSFET switch ON. It will be activated again, through the soft start,after the t RESTART time, see the Figure25 and Figure26 on page17 and the mentioned timevalues on Table8 on page7.In case of overload or short-circuit event, the power MOSFET switching will be stopped aftera time that depends from the counter and that can be as maximum equal to t OVL. Theprotection will occur in the same way until the overload condition is removed, see Figure25and Figure26 on page17. This protection ensures restart attempts of the converter with lowrepetition rate, so that it works safely with extremely low power throughput and avoiding theIC overheating in case of repeated overload events. If the overload is removed before theprotection tripping, the counter will be decremented cycle by cycle down to zero and the ICwill not be stopped.15 Open loop failure protectionIn case the power supply is built in fly-back topology and the VIPer16 is supplied by anauxiliary winding, as shown in Figure27 on page18 and Figure28 on page19, theconverter is protected against feedback loop failure or accidental disconnections of thewinding.The following description is applicable for the schematics of Figure27 on page18 andFigure28 on page19, respectively the non-isolated fly-back and the isolated fly-back.If R H is opened or R L is shorted, the VIPer16 works at its drain current limitation. The outputvoltage, V OUT, will increase and so the auxiliary voltage, V AUX, which is coupled with theoutput through the secondary-to-auxiliary turns ratio.As the auxiliary voltage increases up to the internal V DD active clamp, V DDclamp (the value isreported on Table8 on page7) and the clamp current injected on VDD pin exceeds the latchthreshold, I DDol (the value is reported on Table8on page7), a fault signal is internallygenerated.In order to distinguish an actual malfunction from a bad auxiliary winding design, both theabove conditions (drain current equal to the drain current limitation and current higher thanI DDol through VDD clamp) have to be verified to reveal the fault.If R L is opened or R H is shorted, the output voltage, V OUT, will be clamped to the referencevoltage V REF_FB (in case of non isolated fly-back) or to the external TL voltage reference (incase of isolated fly-back).Package mechanical data VIPER16 16 Package mechanical dataIn order to meet environmental requirements, ST offers these devices in different grades ofECOPACK® packages, depending on their level of environmental compliance. ECOPACK®specifications, grade definitions and product status are available at: .ECOPACK® is an ST trademark.Table 9.DIP-7 mechanical datammDim.Typ Min MaxA 5,33A1 0,38A2 3,30 2,92 4,95b 0,46 0,36 0,56b2 1,52 1,14 1,78c 0,25 0,20 0,36D 9,27 9,02 10,16E 7,87 7,62 8,26E1 6,35 6,10 7,11e 2,54eA 7,62eB 10,92L 3,30 2,92 3,81M (6)(8)2,508N 0,50 0,40 0,60N1 0,60O (7)(8)0,5481- The leads size is comprehensive of the thickness of the leads finishing material.2- Dimensions do not include mold protrusion, not to exceed 0,25 mm in total (both side).3- Package outline exclusive of metal burrs dimensions.4- Datum plane “H” coincident with the bottom of lead, where lead exits body.5- Ref. POA MOTHER doc. 00378806- Creepage distance > 800 V7- Creepage distance 250 V8- Creepage distance as shown in the 664-1 CEI / IEC standard.VIPER16Package mechanical data Figure 29.DIP-7 package dimensionsPackage mechanical data VIPER16Table 10.SO16N mechanical datammDim.Min Typ MaxA 1.75A1 0.10.25A2 1.25b 0.310.51c 0.170.25D 9.89.910E 5.86 6.2E1 3.8 3.94e 1.27h 0.250.5L 0.4 1.27k 08ccc0.1VIPER16Package mechanical data Figure 30.SO16N Package dimensionsRevision history VIPER16 17 RevisionhistoryTable 11.Document revision historyDate Revision Changes21-Jan-20091Initial release07-Dec-20092Updated Figure7 on page814-May-20103Updated Figure3 on page4 and Table3 on page426-Aug-20104Updated T able3 on page4, Figure16 on page10 and Figure21 on page1310-Oct-20115Updated Figure30 on page23 and T able7 on page6VIPER16Please Read Carefully:Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice.All ST products are sold pursuant to ST’s terms and conditions of sale.Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein.No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.UNL ESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SAL E ST DISCL AIMS ANY EXPRESS OR IMPL IED WARRANTY WITH RESPECT TO THE USE AND/OR SAL E OF ST PRODUCTS INCL UDING WITHOUT L IMITATION IMPL IED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNL ESS EXPRESSL Y APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST.ST and the ST logo are trademarks or registered trademarks of ST in various countries.Information in this document supersedes and replaces all information previously supplied.The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.© 2011 STMicroelectronics - All rights reservedSTMicroelectronics group of companiesAustralia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America。
IEC-61162-420
Commission Electrotechnique Internationale International Electrotechnical Commission
PRICE CODE
XD
For price, see current cata001(E)
CONTENTS
FOREWORD...........................................................................................................................6 INTRODUCTION .....................................................................................................................8 1 2 3 Scope and object ..............................................................................................................9 Normative references...................................................................................................... 10 Definitions ...............................................................................................................
RE17R时延时间电源控制器说明书
Offer Sustainability
Sustainable offer status RoHS (date code: YYWW) REACh Product environmental profile
Operating rate in Hz Electrical durability Mechanical durability Dielectric strength [Uimp] rated impulse withstand voltage Delay response Marking Creepage distance Safety reliability data Mounting position Mounting support Local signalling
Product datasheet
Characteristics
Complementary
Contacts type and composition Contacts material Control type [Us] rated supply voltage Voltage range Supply frequency Input voltage Connections - terminals
RE17RAMU
on-delay timing relay - 1 s..100 h - 24..240 V AC - 1 OC
Main
Range of product Product or component type Discrete output type Width Device short name Time delay type Time delay range
viper 解析命令行参数
viper 解析命令行参数在Go语言中，Viper是一个强大的配置管理库，广泛用于解析和管理应用程序的配置信息。
除了支持多种配置文件格式外，Viper还提供了方便的命令行参数解析功能。
本文将深入解析Viper库在Go语言中如何处理命令行参数，以及如何利用其强大的功能进行灵活的配置管理。
第一：Viper简介Viper是Go语言中一个流行的配置管理库，它提供了简单而强大的接口，用于管理应用程序的配置信息。
Viper支持多种配置文件格式，包括JSON、YAML、TOML等，使得配置文件的读取和解析变得更加灵活。
此外，Viper还提供了命令行参数解析的功能，方便应用程序在启动时从命令行接收配置信息。
第二：导入Viper库在使用Viper进行命令行参数解析之前，首先需要导入Viper库。
可以使用以下方式在Go语言项目中导入Viper：goimport "githubcom/spf13/viper"确保你的项目中已经安装了Viper库，如果没有，可以使用以下命令进行安装：shgo get -u githubcom/spf13/viper第三：Viper的基本用法在开始解析命令行参数之前，让我们先了解一下Viper的基本用法。
以下是一个简单的Viper示例，演示了如何读取配置文件和获取配置项的值：gopackage mainimport("fmt""githubcom/spf13/viper")func main(){// 设置配置文件的路径和文件名viper.SetConfigFile("config.yaml")// 读取配置文件if err :=viper.ReadInConfig();err !=nil{fmt.Println("Error reading config file:",err)return}// 获取配置项的值port :=viper.GetInt("server.port")dbHost :=viper.GetString("database.host")fmt.Printf("Server Port: %d\n",port)fmt.Printf("Database Host: %s\n",dbHost)}在这个示例中，我们假设存在一个名为config.yaml的配置文件，其中包含server.port和database.host两个配置项。
17CE测速接口文档说明书
17CE测速接口文档说明书(版本号V1.32)上海云测网络科技有限公司2017年11月目录目录 (2)1. GET测试 (2)1.1 请求地址 (2)1.2 请求参数 (2)1.3 返回数据 (3)1.4 请求URL实例 (3)1.5 返回数据实例 (3)2. PING测试 (6)2.1 请求地址 (6)2.2 请求参数 (6)2.3 返回数据 (7)2.4 请求URL实例 (7)2.5 返回数据实例 (7)3. tracert测试 (10)3.1 请求地址 (10)3.2 请求参数 (10)3.3 返回数据 (10)3.4 请求URL实例 (11)3.5 返回数据实例 (11)接口只支持IDC节点，新功能停止维护，请优先使用WS版本。
1.GET测试1.4请求URL实例1.5返回数据实例{"url": "/doc/api/1.1/CDbCacheDependency","host": "","file": "/doc/api/1.1/CDbCacheDependency","port": 80,"title": "","id": "113547","tid": "201706_11d8d1b4dbcdf7848178c644b42e0c20","check_time": """teststatus": 1,"fullips": [{"linkname": "","link": "","name": "陕西西安移动","pro_id": "194","client_type": "1","isp": "移动","ispid": "7","province": "陕西","city": "西安市","fullname": "陕西西安市移动","sid": "2982","py": "SX"},{"linkname": "","link": "","name": "福建地区移动","pro_id": "79","client_type": "1","isp": "移动","ispid": "7","province": "福建","city": "福州市","fullname": "福建福州市移动","sid": "3092","py": "FJ"}],}❉❉更新GET测试数据❉❉1.> 根据上一个请求得到的任务ID, 可以实时去请求更新测试结果或者设置setTimeout 定时5分钟后一次获取得到所有测试结果：https:///ajaxfresh2.> 请求参数user <string> 17ce用户名code <string> token验证t <string> 时间戳tid <string> 任务IDnum <string> 已返回测试点数据个数, 默认开始为0ajax_over <int> 更新数据0 停止更新数据13.> 请求url实例4.> 返回数据实例{"url": "/doc/api/1.1/CDbCacheDependency","host": "","tid": "201706_11d8d1b4dbcdf7848178c644b42e0c20","type": 1,// GET测试"taskstatus": 3, // 测试完成"teststatus": 1,"num": "5","num2": "5","check_time": "2017-06-08 15:11:53","freshdata": {"2982": {"linkname": "","link": "","name": "陕西西安移动","isp": "移动","view": "陕西","sid": "2982","SrcIP": {// 解析IP"srcip": "123.56.193.192","ipfrom": "中国北京阿里云/电信/联通/移动/铁通/教育网"},"IP": "111.20.248.83","HttpCode": "200",// http状态码"TotalTime": "0.617s", // 总时间"NsLookup": "0.185s", // 解析时间"ConnectTime": "0.042s", // 连接时间"downtime": "0.39s", //下载时间"FileSize": "12.324KB", // 文件大小"realsize": "12.314KB", // 下载文件大小"speed": "31.628KB/s", // 下载速度"HpptHead": "HTTP/1.1 200 OK\r <br>Server: nginx/1.10.2\r <br>Date: Thu,08 Jun 2017 07:11:52 GMT\r <br>Content-Type: text/html; charset=UTF-8\r<br>Transfer-Encoding: chunked\r <br>Connection: close\r <br>X-Powered-By: PHP/7.0.16\r <br>Set-Cookie: PHPSESSID=5lm8eigfve10o05u0j3lfd9i33; path=/;HttpOnly\r <br>Expires: Thu, 19 Nov 1981 08:52:00 GMT\r <br>Cache-Control: no-store, no-cache, must-revalidate\r <br>Pragma: no-cache\r <br>Content-Encoding: gzip\r <br>\r <br>" // http头信息},{...}},"average_data": { // 平均值数据"HttpCode": "200","realsize": " <font color=\"#D50000\">文件不一致</font>","filesize": " <font color=\"#D50000\">文件不一致</font>","SrcipNum": 1,"ipfromNum": 1,"TotalTime": "0.689s","NsLookup": "0.346s","ConnectTime": "0.046s","downtime": "0.297s","speed": "42.81KB/s","diffspeed": 42.8096,"diffTotalTime": 0.689,"diffNsLookup": 0.346,"diffConnectTime": 0.046,"diffdowntime": 0.297},"ajax_over": 0,"port": 80}2.PING测试2.4请求URL实例2.5返回数据实例{"url": "/doc/api/1.1/CDbCacheDependency","host": "","file": "/doc/api/1.1/CDbCacheDependency","port": 80,"title": "","id": "113547","tid": "201706_bc730156b986cb428802744ed5632713","check_time": """teststatus": 1,"fullips": [{"linkname": "","link": "","name": "陕西西安移动","pro_id": "194","client_type": "1","isp": "移动","ispid": "7","province": "陕西","city": "西安市","fullname": "陕西西安市移动","sid": "2982","py": "SX"},{"linkname": "","link": "","name": "福建地区移动","pro_id": "79","client_type": "1","isp": "移动","ispid": "7","province": "福建","city": "福州市","fullname": "福建福州市移动","sid": "3092","py": "FJ"}],}❉❉更新PING测试数据❉❉1.> 根据上一个请求得到的任务ID, 可以实时去请求更新测试结果或者设置setTimeout 定时5分钟后一次获取得到所有测试结果：https:///ajaxfresh2.> 请求参数user <string> 17ce用户名code <string> token验证t <string> 时间戳tid <string> 任务IDnum <string> 已返回测试点数据个数, 默认开始为0ajax_over <int> 更新数据0 停止更新数据13.> 请求url实例4.> 返回数据实例{"url": "/doc/api/1.1/CDbCacheDependency","host": "","tid": "201706_bc730156b986cb428802744ed5632713", // 任务ID"type": 2, // ping测试"taskstatus": "3", //测试完成"teststatus": 1,"num": "4","num2": "4","check_time": "2017-06-08 17:34:33","freshdata": {"2982": {"linkname": "","link": "","name": "陕西西安移动","isp": "移动","view": "陕西","SrcIP": {"srcip": "123.56.193.192", // 解析IP"ipfrom": "中国北京阿里云/电信/联通/移动/铁通/教育网"},"sid": "2982", // 节点id"DataSize": "100B", // 包大小"PacketsSent": 10, // 发送"PacketsRecv": 10, // 接收"PacketsLost": 0, // 丢弃"Avg": "36.827ms", // 平均时间"Max": "37.149ms", // 最大时间"Min": "36.721ms", // 最小时间"PingStr": "PING <br>PING (123.56.193.192) with 100 bytes of data: <br>Reply from 123.56.193.192: bytes=100 time=37ms TTL=51 <br>Reply from 123.56.193.192: bytes=100 time=37ms TTL=51 <br>Reply from 123.56.193.192: bytes=100 time=37ms TTL=51 <br>Reply from 123.56.193.192: bytes=100 time=37ms TTL=51 <br>Reply from 123.56.193.192: bytes=100 time=37ms TTL=51 <br>Reply from 123.56.193.192: bytes=100 time=37ms TTL=51 <br>Reply from 123.56.193.192: bytes=100 time=37ms TTL=51 <br>Reply from 123.56.193.192: bytes=100 time=37ms TTL=51 <br>Reply from 123.56.193.192: bytes=100 time=37ms TTL=51 <br>Reply from 123.56.193.192: bytes=100 time=37ms TTL=51 <br> <br>Ping statistics for 123.56.193.192: <br>Packets: Sent = 10, Received = 10, Lost = 0 (0% loss), <br>Approximate round trip times in milli-seconds: <br>Minimum = 37ms, Maximum = 37ms, Average = 37ms" // 详细信息},},"average_data": { // 平均值数据"SrcipNum": 1,"ipfromNum": 1,"PacketsSent": 10,"PacketsRecv": 10,"PacketsLost": 0,"Avg": "40.646ms","Max": "41.439ms","Min": "40.063ms","diffPacketsSent": 0,"diffPacketsRecv": 0,"diffPacketsLost": 0,"diffAvg": "0ms","diffMax": "0ms","diffMin": "0ms"},"ajax_over": 0,"port": 80}3.tracert测试2host域名3file地址路径4port端口5title标题6id记录ID7tid任务ID8check_time检测时间9teststatus测试状态1测试成功2无有效数据可以显示在地图上10fullips测速点信息Name/province/city/isp/sid3.4请求URL实例3.5返回数据实例{"url": "","host": "","file": "/","port": 80,"title": "","id": "115917","tid": "201706_ed83fb15221ec39ed478d5bc74f31add","teststatus": 1,"fullips": [{"linkname": "","link": "","name": "福建省福州电信","pro_id": "79","client_type": "1","isp": "电信","ispid": "1","province": "福建","city": "福州市","fullname": "福建福州市电信","sid": "3045","py": "FJ"},{"linkname": "","link": "","name": "安徽电信合肥","pro_id": "236","client_type": "1","isp": "电信","ispid": "1","province": "安徽","city": "合肥市","fullname": "安徽合肥市电信","sid": "3273","py": "AH"}],"check_time": "",}❉❉更新tracert测试数据❉❉1.> 根据上一个请求得到的任务ID, 可以实时去请求更新测试结果或者设置setTimeout 定时5分钟后一次获取得到所有测试结果：https:///ajaxfresh2.> 请求参数user <string> 17ce用户名code <string> token验证t <string> 时间戳tid <string> 任务IDnum <string> 已返回测试点数据个数, 默认开始为0ajax_over <int> 更新数据0 停止更新数据13.> 请求url实例4.> 返回数据实例{"url": "","host": "","tid": "201706_ed83fb15221ec39ed478d5bc74f31add","type": 3, // tracert 测试"taskstatus": "3", // 测试完成"teststatus": 1,"num": "2","num2": "2","check_time": "2017-06-08 17:56:13","freshdata": {"3045": {// 节点id"SrcIP": "123.56.193.192","IP": "117.27.251.7","linkname": "","link": "","view": "福建","name": "福建省福州电信","isp": "电信","sid": "3045","TraRouteAry": [{"Ip": {// 第一跳"srcip": "117.27.251.1","ipfrom": "中国福建福州电信","dnsname": "*"},"PacketsSent": "6","PacketsRecv": "6","PacketsLost": "0","Avg": 0.004502,"Max": 0.005874,"Min": 0.002842},{"Ip": {// 第二跳"srcip": "192.168.100.25","ipfrom": "Local Address","dnsname": "*"},"PacketsSent": "6","PacketsRecv": "6","PacketsLost": "0","Avg": 0.002509,"Max": 0.002815,"Min": 0.002379},{"Ip": { // 第三跳"srcip": "192.168.250.25","ipfrom": "Local Address","dnsname": "*"},"PacketsSent": "6","PacketsRecv": "6","PacketsLost": "0","Avg": 0.003458,"Max": 0.004131,"Min": 0.000868},{"Ip": {"srcip": "*","dnsname": "*","ipfrom": "*"},"PacketsSent": "6","PacketsRecv": "0","PacketsLost": "6","Avg": 0,"Max": 0,"Min": 0}]},},"ajax_over": 0,"port": 80}附TOKEN加密方式（$user：17ce用户名$pwd：17ce密码$t 时间戳）md5(base64_encode(substr(md5($pwd),4,19).trim($user).$t));对密码md5加密后第4位起截取19位字符，拼接用户名和时间戳进行base64和md5加密。
NVIDIA Hopper 应用调优指南说明书
Application NoteTable of Contents Chapter 1. NVIDIA Hopper Tuning Guide (1)1.1. NVIDIA Hopper GPU Architecture (1)1.2. CUDA Best Practices (1)1.3. Application Compatibility (2)1.4. NVIDIA Hopper Tuning (2)1.4.1. Streaming Multiprocessor (2)1.4.1.1. Occupancy (2)1.4.1.2. Tensor Memory Accelerator (2)1.4.1.3. Thread Block Clusters (3)1.4.1.4. Improved FP32 Throughput (3)1.4.1.5. Dynamic Programming Instructions (3)1.4.2. Memory System (4)1.4.2.1. High-Bandwidth Memory HBM3 Subsystem (4)1.4.2.2. Increased L2 Capacity (4)1.4.2.3. Inline Compression (4)1.4.2.4. Unified Shared Memory/L1/Texture Cache (5)1.4.3. Fourth-Generation NVLink (5)Appendix A. Revision History (6)Chapter 1.NVIDIA Hopper TuningGuide1.1. NVIDIA Hopper GPU ArchitectureThe NVIDIA® Hopper GPU architecture is NVIDIA's latest architecture for CUDA® compute applications. The NVIDIA Hopper GPU architecture retains and extends the same CUDA programming model provided by previous NVIDIA GPU architectures such as NVIDIA Ampere GPU architecture and NVIDIA Turing, and applications that follow the best practices for those architectures should typically see speedups on the NVIDIA H100 GPU without anycode changes. This guide summarizes the ways that an application can be fine-tuned to gain additional speedups by leveraging the NVIDIA Hopper GPU architecture's features.1For further details on the programming features discussed in this guide, refer to the CUDA C+ + Programming Guide.1.2. CUDA Best PracticesThe performance guidelines and best practices described in the CUDA C++ Programming Guide and the CUDA C++ Best Practices Guide apply to all CUDA-capable GPU architectures. Programmers must primarily focus on following those recommendations to achieve the best performance.The high-priority recommendations from those guides are as follows:‣Find ways to parallelize sequential code.‣Minimize data transfers between the host and the device.‣Adjust kernel launch configuration to maximize device utilization.‣Ensure that global memory accesses are coalesced.‣Minimize redundant accesses to global memory whenever possible.1Throughout this guide, NVIDIA Volta refers to devices of compute capability 7.0, NVIDIA Turing refers to devices of compute capability 7.5, NVIDIA Ampere GPU Architecture refers to devices of compute capability 8.x, and NVIDIA Hopper refers to devices of compute capability 9.0.‣Avoid long sequences of diverged execution by threads within the same warp.1.3. Application CompatibilityBefore addressing specific performance tuning issues covered in this guide, refer to the Hopper Compatibility Guide for CUDA Applications to ensure that your application is compiled in a way that is compatible with NVIDIA Hopper.1.4. NVIDIA Hopper Tuning1.4.1. Streaming MultiprocessorThe NVIDIA Hopper Streaming Multiprocessor (SM) provides the following improvements over Turing and NVIDIA Ampere GPU architectures.1.4.1.1. OccupancyThe maximum number of concurrent warps per SM remains the same as in NVIDIA Ampere GPU architecture (that is, 64), and other factors influencing warp occupancy are:‣The register file size is 64K 32-bit registers per SM.‣The maximum number of registers per thread is 255.‣The maximum number of thread blocks per SM is 32 for devices of compute capability 9.0 (that is, H100 GPUs).‣For devices of compute capability 9.0 (H100 GPUs), shared memory capacity per SM is 228 KB, a 39% increase compared to A100's capacity of 164 KB.‣For devices of compute capability 9.0 (H100 GPUs), the maximum shared memory per thread block is 227 KB.‣For applications using Thread Block Clusters, it is always recommended to compute the occupancy using cudaOccupancyMaxActiveClusters and launch cluster-based kernels accordingly.Overall, developers can expect similar occupancy as on NVIDIA Ampere GPU architecture GPUs without changes to their application.1.4.1.2. Tensor Memory AcceleratorThe Hopper architecture builds on top of the asynchronous copies introduced by NVIDIA Ampere GPU architecture and provides a more sophisticated asynchronous copy engine: the Tensor Memory Accelerator (TMA).TMA allows applications to transfer 1D and up to 5D tensors between global memory and shared memory, in both directions, as well as between the shared memory regions of different SMs in the same cluster (refer to Thread Block Clusters). Additionally, for writes from sharedmemory to global memory, it allows specifying element wise reduction operations such as add/min/max as well as bitwise and/or for most common data types.This has several advantages:‣Avoids using registers for moving data between the different memory spaces.‣Avoids using SM instructions for moving data: a single thread can issue large data movement instructions to the TMA unit. The whole block can then continue working on other instructions while the data is in flight and only wait for the data to be consumed when actually necessary.‣Enables users to write warp specialized codes, where specific warps specialize on data movement between the different memory spaces while other warps only work on local data within the SM.This feature will be exposed through cuda::memcpy_async along with the cuda::barrier and cuda::pipeline for synchronizing data movement.1.4.1.3. Thread Block ClustersNVIDIA Hopper Architecture adds a new optional level of hierarchy, Thread Block Clusters, that allows for further possibilities when parallelizing applications. A thread block can read from, write to, and perform atomics in shared memory of other thread blocks within its cluster. This is known as Distributed Shared Memory. As demonstrated in the CUDA C++ Programming Guide, there are applications that cannot fit required data within shared memory and must use global memory instead. Distributed shared memory can act as an intermediate step between these two options.Distributed Shared Memory can be used by an SM simultaneously with L2 cache accesses. This can benefit applications that need to communicate data between SMs by utilizing the combined bandwidth of both distributed shared memory and L2.The maximum portable cluster size supported is 8; however, NVIDIA Hopper H100 GPU allows for a nonportable cluster size of 16 by opting in. Launching a kernel with a nonportable cluster size requires setting the cudaFuncAttributeNonPortableClusterSizeAllowed function attribute. Using larger cluster sizes may reduce the maximum number of active blocks across the GPU (refer to Occupancy).1.4.1.4. Improved FP32 ThroughputDevices of compute capability 9.0 have 2x more FP32 operations per cycle per SM than devices of compute capability 8.0.1.4.1.5. Dynamic Programming InstructionsThe NVIDIA Hopper architecture adds support for new instructions to accelerate dynamic programming algorithms, such as the Smith-Waterman algorithm for sequence alignment in bioinformatics, and algorithms in graph theory, game theory, ML, and finance problems. The new instructions permit computation of max and min values among three operands, max and min operations yielding predicates, combined add operation with max or min, operating onsigned and unsigned 32-bit int and 16-bit short2 types, and half2. All DPX instructions with 16-bit short types DPX instructions enable 128 operations per cycle per SM.1.4.2. Memory System1.4.2.1. High-Bandwidth Memory HBM3 SubsystemThe NVIDIA H100 GPU has support for HBM3 and HBM2e memory, with capacity up to 80 GB. GPUs HBM3 memory system supports up to three TB/s memory bandwidth, a 93% increase over the 1550 GB/s on A100.1.4.2.2. Increased L2 CapacityThe NVIDIA Hopper architecture increases the L2 cache capacity from 40 MB in the A100 GPU to 50 MB in the H100 GPU. Along with the increased capacity, the bandwidth of the L2 cacheto the SMs is also increased. The NVIDIA Hopper architecture allows CUDA users to control the persistence of data in L2 cache similar to the NVIDIA Ampere GPU Architecture. For more information on the persistence of data in L2 cache, refer to the section on managing L2 cache in the CUDA C++ Programming Guide.1.4.2.3. Inline CompressionThe NVIDIA Hopper architecture allows CUDA compute kernels to benefit from the newinline compression (ILC). This feature can be applied to individual memory allocation, and the compressor automatically chooses between several possible compression algorithms, or none if there is no suitable pattern.In case compression can be used, this feature allows accessing global memory at significantly higher bandwidth than global memory bandwidth, since only compressed data needs to be transferred between global memory and SMs.However, the feature does not allow for reducing memory footprint: since compression is automatic, even if compression is active, the memory region will use the same footprint asif there was no compression. This is because underlying data may be changed by the user application and may not be compressible during the entire duration of the application.The feature is available through the CUDA driver API. See the CUDA C++ Programming Guide section on compressible memory:CUmemGenericAllocationHandle allocationHandle;CUmemAllocationProp prop = {};memset(prop, 0, sizeof(CUmemAllocationProp));prop->type = CU_MEM_ALLOCATION_TYPE_PINNED;prop->location.type = CU_MEM_LOCATION_TYPE_DEVICE;prop->location.id = currentDevice;prop->pressionType = CU_MEM_ALLOCATION_COMP_GENERIC; cuMemCreate(&allocationHandle, size, &prop, 0);One can check whether compressible memory is available on the given device with:cuDeviceGetAttribute(&compressionAvailable,CU_DEVICE_ATTRIBUTE_GENERIC_COMPRESSION_SUPPORTED, currentDevice)Note that this example code does not handle errors and compiling this code requires linking against the CUDA library (libcuda.so).1.4.2.4. Unified Shared Memory/L1/Texture CacheThe NVIDIA H100 GPU based on compute capability 9.0 increases the maximum capacity of the combined L1 cache, texture cache, and shared memory to 256 KB, from 192 KB in NVIDIA Ampere Architecture, an increase of 33%.In the NVIDIA Hopper GPU architecture, the portion of the L1 cache dedicated to shared memory (known as the carveout) can be selected at runtime as in previous architectures such as NVIDIA Ampere Architecture and NVIDIA Volta, using cudaFuncSetAttribute() with the attribute cudaFuncAttributePreferredSharedMemoryCarveout. The NVIDIA H100 GPU supports shared memory capacities of 0, 8, 16, 32, 64, 100, 132, 164, 196 and 228 KB per SM. CUDA reserves 1 KB of shared memory per thread block. Hence, the H100 GPU enables a single thread block to address up to 227 KB of shared memory. To maintain architectural compatibility, static shared memory allocations remain limited to 48 KB, and an explicitopt-in is also required to enable dynamic allocations above this limit. See the CUDA C++ Programming Guide for details.Like the NVIDIA Ampere Architecture and NVIDIA Volta GPU architectures, the NVIDIA Hopper GPU architecture combines the functionality of the L1 and texture caches into a unified L1/ Texture cache which acts as a coalescing buffer for memory accesses, gathering up the data requested by the threads of a warp before delivery of that data to the warp. Another benefit of its union with shared memory, similar to previous architectures, is improvement in terms of both latency and bandwidth.1.4.3. Fourth-Generation NVLinkThe fourth generation of NVIDIA’s high-speed NVLink interconnect is implemented in H100 GPUs, which significantly enhances multi-GPU scalability, performance, and reliability with more links per GPU, much faster communication bandwidth, and improved error-detection and recovery features. The fourth-generation NVLink has the same bidirectional data rate of 50 GB/s per link. The total number of links available is increased to 18 in H100, compared to 12 in A100, yielding 900 GB/s bidirectional bandwidth compared to 600 GB/s for A100. NVLink operates transparently within the existing CUDA model. Transfers between NVLink-connected endpoints are automatically routed through NVLink, rather than PCIe. The cudaDeviceEnablePeerAccess() API call remains necessary to enable direct transfers (over either PCIe or NVLink) between GPUs. The cudaDeviceCanAccessPeer() can be used to determine if peer access is possible between any pair of GPUs.Appendix A.Revision HistoryVersion 1.0‣Initial Public Release‣Added support for compute capability 9.0NoticeThis document is provided for information purposes only and shall not be regarded as a warranty of a certain functionality, condition, or quality of a product. NVIDIA Corporation (“NVIDIA”) makes no representations or warranties, expressed or implied, as to the accuracy or completeness of the information contained in this document and assumes no responsibility for any errors contained herein. NVIDIA shall have no liability for the consequences or use of such information or for any infringement of patents or other rights of third parties that may result from its use. This document is not a commitment to develop, release, or deliver any Material (defined below), code, or functionality.NVIDIA reserves the right to make corrections, modifications, enhancements, improvements, and any other changes to this document, at any time without notice. Customer should obtain the latest relevant information before placing orders and should verify that such information is current and complete.NVIDIA products are sold subject to the NVIDIA standard terms and conditions of sale supplied at the time of order acknowledgement, unless otherwise agreed in an individual sales agreement signed by authorized representatives of NVIDIA and customer (“Terms of Sale”). NVIDIA hereby expressly objects to applying any customer general terms and conditions with regards to the purchase of the NVIDIA product referenced in this document. No contractual obligations are formed either directly or indirectly by this document.OpenCLOpenCL is a trademark of Apple Inc. used under license to the Khronos Group Inc.TrademarksNVIDIA and the NVIDIA logo are trademarks or registered trademarks of NVIDIA Corporation in the U.S. and other countries. Other company and product names may be trademarks of the respective companies with which they are associated.Copyright© 2022-2022 NVIDIA Corporation & affiliates. All rights reserved.NVIDIA Corporation | 2788 San Tomas Expressway, Santa Clara, CA 95051https://。
NVIDIA Ampere GPU 兼容性指南说明书
6.2 OpenCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.3 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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Ampere Compatibility Guide, Release 12.1
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Chapter 1. About this Document
Chapter 2. Application Compatibility on the NVIDIA Ampere GPU Architecture
A CUDA application binary (with one or more GPU kernels) can contain the compiled GPU code in two forms, binary cubin objects and forward-compatible PTX assembly for each kernel. Both cubin and PTX are generated for a certain target compute capability. A cubin generated for a certain compute capability is supported to run on any GPU with the same major revision and same or higher minor revision of compute capability. For example, a cubin generated for compute capability 7.0 is supported to run on a GPU with compute capability 7.5, however a cubin generated for compute capability 7.5 is not supported to run on a GPU with compute capability 7.0, and a cubin generated with compute capability 7.x is not supported to run on a GPU with compute capability 8.x. Kernel can also be compiled to a PTX form. At the application load time, PTX is compiled to cubin and the cubin is used for kernel execution. Unlike cubin, PTX is forward-compatible. Meaning PTX is supported to run on any GPU with compute capability higher than the compute capability assumed for generation of that PTX. For example, PTX code generated for compute capability 7.x is supported to run on compute capability 7.x or any higher revision (major or minor), including compute capability 8.x. Therefore although it is optional, it is recommended that all applications should include PTX of the kernels to ensure forward-compatibility. To read more about cubin and PTX compatibilities see Compilation with NVCC from the Programming Guide. When a CUDA application launches a kernel on a GPU, the CUDA Runtime determines the compute capability of the GPU in the system and uses this information to find the best matching cubin or PTX version of the kernel. If a cubin compatible with that GPU is present in the binary, the cubin is used as-is for execution. Otherwise, the CUDA Runtime first generates compatible cubin by JIT-compiling1 the PTX and then the cubin is used for the execution. If neither compatible cubin nor PTX is available, kernel launch results in a failure. Application binaries that include PTX version of kernels, should work as-is on the NVIDIA Ampere architecture based GPUs. In such cases, rebuilding the application is not required. However application binaries which do not include PTX (only include cubins), need to be rebuilt to run on the NVIDIA Ampere architecture based GPUs. To know more about building compatible applications read Building Applications with the NVIDIA Ampere GPU Architecture Support.
API17-CPU ABI设置(AVD在API 17下黑屏等问题的解决)
AVD在API 17下黑屏等问题的解决CPU/ABI 配置出现的问题主要问题：1、CPU/ABI找不到当选择Target Android4.2.2-API Level 117时，CPU/ABI 一直显示灰色，无法选择确定是缺少：ARM EABI v7a System Image网上找到，ARM EABI v7a System Image，下载后，放在SDK/Platform/Android 4.2/Images 目录下2、在启动AVD时出现下面提示错误信息：failed to load libgl.so3、解决：failed to load libgl.so问题后出现黑屏4、黑屏：下载好多网上提供的文件，都没有解决：找到网上的文件后放到sdk-platfom-Android4.2目录image是目录下（ARM EABI v7a System Image）5、从过去Windows的开发环境下找到这个文件Copy到Linux环境下，好了！配置AVD出现错误：failed to load libgl.so下面窗口中显示：failed to load libgl.so但是能够出现下面的AVD窗口：解决：failed to load libgl.so先用locate 命令定位libGL库，然后添加一个链接即可：[david@dav-linus ~]$ locate libGL显示：/home/david/AndroidBundle/adt-bundle-linux-x86-20140702/sdk/tools/lib/libGLES_CM_translator.so/home/david/AndroidBundle/adt-bundle-linux-x86-20140702/sdk/tools/lib/libGLES_V2_translator.so/home/david/AndroidBundle-R23/adt-bundle-linux-x86-20140702/sdk/tools/lib/libGLES_CM_translator.so /home/david/AndroidBundle-R23/adt-bundle-linux-x86-20140702/sdk/tools/lib/libGLES_V2_translator.so /home/david/android/android-sdk-linux/tools/lib/libGLES_CM_translator.so/home/david/android/android-sdk-linux/tools/lib/libGLES_V2_translator.so/home/david/android/android-sdk-linux/tools/lib/gles_mesa/libGL.so/home/david/android/android-sdk-linux/tools/lib/gles_mesa/libGL.so.1/home/david/android/android-sdk-linux/tools/lib64/gles_mesa/libGL.so/home/david/android/android-sdk-linux/tools/lib64/gles_mesa/libGL.so.1/usr/lib/libGL.so.1/usr/lib/libGL.so.1.2.0/usr/lib/libGLESv2.so.2/usr/lib/libGLESv2.so.2.0.0/usr/lib/libGLEW.so.1.10/usr/lib/libGLEW.so.1.10.0/usr/lib/libGLU.so.1/usr/lib/libGLU.so.1.3.1/usr/share/doc/libGLEW/usr/share/doc/mesa-libGL/usr/share/doc/mesa-libGLES/usr/share/doc/libGLEW/LICENSE.txt/usr/share/doc/mesa-libGL/COPYING/usr/share/doc/mesa-libGLES/COPYING[david@dav-linus ~]$ln -s /home/david/android/android-sdk-linux/tools/lib/gles_mesa/libGL.so.1/home/david/AndroidBundle/adt-bundle-linux-x86-20140702/sdk/tools/lib/libGL.so这个问题排除后：仍然无法启动，黑窗口：Eclipse 显示检查使用命令行方式检查：但环境变量必须设置：1、临时设置，系统启动后不再有效：export PATH=$PATH:/home/david/AndroidBundle/adt-bundle-linux-x86-20140702/sdk/tools 2、永久设置：(1)编辑/etc/profile 中增加：export ANDROID_TOOLS=/home/david/AndroidBundle/adt-bundle-linux-x86-20140702/sdk/toolsexport PATH=$PATH:$ANDROID_TOOLS(2)重新启动profile[david@dav-linus tools]$ source /etc/profile环境变量生效后，可以使用android 命令了[david@dav-linus etc]$ android list avd显示：Available Android Virtual Devices:Name: API13Device: 3.7 FWVGA slider (Generic)Path: /home/david/.android/avd/API13.avdTarget: Android 3.2 (API level 13)Tag/ABI: default/armeabiSkin: 480x854Sdcard: 200M---------Name: Nexus-Api-17Device: Nexus S (Google)Path: /home/david/.android/avd/Nexus-Api-17.avdTarget: Android 4.2.2 (API level 17)Tag/ABI: default/armeabiSkin: 480x800Sdcard: 200M---------Name: Xt800-2Device: 3.7 FWVGA slider (Generic)Path: /home/david/.android/avd/Xt800-2.avdTarget: Android 2.2 (API level 8)Tag/ABI: default/armeabiSkin: WVGA854Sdcard: 300M---------Name: XT800-For_Studio_API_13Device: Nexus S (Google)Path: /home/david/.android/avd/XT800-For_Studio_API_13.avd Target: Android 3.2 (API level 13)Tag/ABI: default/armeabiSkin: 480x800Sdcard: 200M命令行方式启动模拟器：[david@dav-linus etc]$ emulator -avd Nexus-Api-17仍然显示黑屏最终解决方案【好辛苦啊，网上好多办法都想了没有结果，这次解决了】1、在Windows开发环境下，找到system-images目录Windows目录结构：下面是看到Windows下的Android SDK Manager，显示有ARM EABI v7a System Image2、把这个目录copy到 Linux开发SDK目录下（这里奇怪，API13、API8 都有影像，但都放在其相对应的目录（Images目录）下面，如：而这次解决问题，却是直接放到SDK目录下，如下：Linux目录结构：这下问题解决了。
viper17芯片工作原理
viper17芯片工作原理
Viper17芯片是一种用于开关电源应用的集成电路。
它是由STMicroelectronics公司生产的，具有较高的集成度和可靠性。
Viper17芯片的工作原理可以分为以下几个方面：
1. 输入电源经过桥式整流得到直流电压，并经过输入滤波器进行滤波。
2. 先导电路：Viper17芯片内部包含一个先导电路，在输入电
压超过一定阈值后开始启动。
3. PWM控制器：Viper17芯片内部集成了一个PWM控制器，用于控制开关管的导通和截止。
PWM控制器根据反馈信号
（通常为输出电压信号）和内部参考电压进行比较，以调整开关管的导通和截止时间，从而稳定输出电压。
4. MOSFET开关管：Viper17芯片内部集成了一个MOSFET
开关管。
当PWM控制器控制开关管导通时，输入电源通过开
关管流入输出电路，从而向负载提供电能。
当PWM控制器控
制开关管截止时，开关管断开，负载断开与输入电源的连接。
5. 输出滤波器：Viper17芯片通过一个输出滤波器来减小输出
电压的纹波和噪声。
6. 保护电路：Viper17芯片还包含了多种保护电路，如过载保护、过温保护和短路保护等，以保护开关电源和负载的安全。
总体而言，Viper17芯片通过PWM控制器和MOSFET开关管来实现对输入电源的调节和控制，从而稳定输出电压，并提供多种保护功能，使其适用于各种开关电源应用。
TI-Nspire_软件安装和激活指导手册
打开属性文件。 3. 根据属性文件中提供的选项说明和值指定应用于安装的值。
注 : 如果您使用并发或学校管理许可证，则 settings.properties 文件中至 少需要包含 license.server 选项的值才能保证将运行 TI-Nspire™ 软件的计 算机配置为访问许可证服务。 详细信息请参见附录 B: 属性文件 选项。 4. 保存每个属性文件。 5. 您可自行选择部署软件的平台或流程，也可运行安装文件并根据向导的 提示进行操作。 注 : 属性文件应与 TI-Nspire™ 安装程序( .exe、.msi 或 .pkg) 文件位于同一 文件夹。 如果包含 license.number 值的 deployment.properties 文件与 TI-Nspire™ 安 装 程 序 一 起 部 署 ，安 装 程 序 会 自 动 尝 试 以 静 默 方 式 激 活 该 许 可 证 。此 过程可能需要长达 10 分钟，并且部署时客户机须接入 Internet。
算机上一个合适的文件夹中。
设置代理服务器的环境变量
若使用代理服务器，您必须在使用 TI-Nspire™ 软件之前设置环境变量。 环境变量是指向激活许可证所用代理服务器和端口的。
在 Windows® 上 设 置 环 境 变 量 若要在 Windows® 上设置环境变量，请执行以下步骤。 1. 单击开 始 >控 制 面 板 >系 统 。
Teacher 软件 • TI-Nspire™ Navigator™ NC Teacher 软件和 TI-Nspire™ CAS Navigator™
NC Teacher 软件 • TI-Nspire™ Teacher 软件 和 TI-Nspire™ CAS Teacher 软件 • TI-Admin 软件
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ST VIPER17 6W单输出电源解决方案
ST公司的VIPER17是离线高压转换器,集成了高压800V的功率部分,PWM控制,两级过流保护,过压保护和过负载保护,以及滞后热保护,软起动和故障条件消除后自动重起等功能. VIPER17采用突发模式工作,消耗非常低电流,有助于满足待机时节能指标.本文介绍了VIPER17的主要特性,方框图, 简单特性和全特性的反激应用方框图,以及6W单输出VIPer17演示板电路图和所用材料清单与变压器特性参数。
VIPer17: Off-line high voltage converters
The device is an off-line converter with an 800 V rugged power section, a PWM control, two levels of over current protection, over voltage and overload protections, hysteretic thermal protection, soft-start and safe auto-restart after any fault condition removal. Burst mode operation and device very low consumption help to meet the standby energy saving regulations.
Advance frequency jittering reduces EMI filter cost. Brown-out function protects the switch mode power supply when the rectified input voltage level is below the normal minimum level specified for the system. The high voltage start-up circuit is embedded in the device.
VIPER17主要特性:
■800 V avalanche rugged power section
■PWM operation with frequency jittering for low EMI
■Operating frequency:
–60 kHz for L type
–115 kHz for H type
■Standby power < 50 mW at 265 Vac
■Limiting current with adjustable set point
■Adjustable and accurate over voltage protection
■On-board soft-start
■Safe auto-restart after a fault condition
■Hysteretic thermal shutdown
VIPER17应用:
■Adapters for PDA, camcorders, shavers, cellular phones, video games
■Auxiliary power supply for LCD/PDP TV, monitors, audio systems, computer, industrial systems
■SMPS for set-top boxes, DVD players and recorders, white goods
图1.VIPER17方框图
图2.简单特性反激应用方框图
图3.全特性反激应用方框图
6W单输出VIPer17演示板
6 W single-output VIPer1
7 demonstration board
The new VIPer17 device integrates in the same package two components: an advanced PWM controller with built-in BCD6 technology and an 800 V avalanche rugged vertical power MOSFET. The device is suitable for offline power conversion operating either with wide range input voltage (85 V AC - 270 V AC) up to 6 W or with single range input voltage (85 V AC - 132 V AC or 175 V AC - 265 V AC). With European range input voltage (175 V AC–265 V AC) the device can handle up to 10 W of output power. The proposed solution has the advantage of using few external components compared to a discrete solution, providing several switch mode power supply protections and very low standby consumption in no-load condition. The device operates at fixed frequency that can be 115 kHz or 60 kHz.
Frequency jittering is implemented which helps to meet the standards regarding electromagnetic disturbance. The protections present on the device such as overload and output overvoltage protections, secondary winding short-circuit protection, hard transformer saturation and brownout protections improve the reliability and safety of the design.
Moreover internal thermal shutdown and an 800 V avalanche rugged power MOSFET improve the robustness of the system. The VIPer17 demonstration board is a standard single-output isolated flyback converter that uses all the protections mentioned above. If brownout and overvoltage protection are not necessary, the number of external components is further reduced.
图4.VIPer17演示板外形图
图5. VIPer17演示板电路图VIPer17演示板材料清单(BOM):
变压器特性参数:。