CDC924DL;CDC924DLR;CDC924DLRG4;CDC924DLG4;中文规格书,Datasheet资料

GND REF0 REF1 VDD3.3V XIN XOUT GND PCI_F PCI1 VDD3.3V PCI2 PCI3 GND PCI4 PCI5 VDD3.3V PCI6 PCI7 GND GND 3V66(0) 3V66(1) VDD3.3V GND 3V66(2) 3V66(3) VDD3.3V SEL133/100
D D
description
The CDC924 is a clock synthesizer/driver that generates system clocks necessary to support Intel Pentium III systems on CPU, CPU_DIV2, 3V66, PCI, APIC, 48MHz, and REF clock signals.
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function tables
SELECT FUNCTIONS INPUTS SEL133/ 100 L L L L H H H H SEL1 L L H H L L H H SEL0 L H L H L H L H CPU Hi-Z N/A 100 MHz 100 MHz TCLK/2 N/A 133 MHz 133 MHz CPU_DIV2 Hi-Z N/A 50 MHz 50 MHz TCLK/4 N/A 66 MHz 66 MHz 3V66 Hi-Z N/A 66 MHz 66 MHz TCLK/4 N/A 66 MHz 66 MHz OUTPUTS PCI, PCI_F Hi-Z N/A 33 MHz 33 MHz TCLK/8 N/A 33 MHz 33 MHz 48MHz Hi-Z N/A Hi-Z 48 MHz TCLK/2 N/A Hi-Z 48 MHz REF Hi-Z N/A 14.318 MHz 14.318 MHz TCLK N/A 14.318 MHz 14.318 MHz APIC Hi-Z N/A 16.67 MHz 16.67 MHz TCLK/16 N/A 16.67 MHz 16.67 MHz FUNCTION 3-state Reserved 48-MHz PLL off 48-MHz LL on Test Reserved 48-MHz PLL off 48-MHz PLL on
ENABLE FUNCTIONS INPUTS CPU_STOP X L L H H PWR_DWN L H H H H PCI_STOP X L H L H CPU L L L On On CPU_DIV2 L On On On On APIC L On On On On OUTPUTS 3V66 L L L On On PCI L L On L On PCI_F L On On On On REF, 48MHz L On On On On INTERNAL Crystal Off On On On On VCOs Off On On On On
CDC924 133ĆMHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3ĆSTATE OUTPUTS
SCAS607B − NOVEMBER 1998 − REVISED JULY 2005
D Supports Pentium III Class Motherboards D Uses a 14.318-MHz Crystal Input to
VDD2.5V APIC2 APIC1 APIC0 GND VDD2.5V CPU_DIV2(1) CPU_DIV2(0) GND VDD2.5V CPU3 CPU2 GND VDD2.5V CPU1 CPU0 GND VDD3.3V GND PCI_STOP CPU_STOP PWR_DWN SPREAD SEL1 SEL0 VDD3.3V 48MHz GND
OUTPUT BUFFER SPECIFICATIONS BUFFER NAME CPU, CPU_DIV2, APIC 48MHz, REF PCI, PCI_F, 3V66 VDD RANGE (V) 2.375 − 2.625 3.135 − 3.465 3.135 − 3.465 IMPEDANCE (Ω) 13.5 − 45 20 − 60 12 − 55 BUFFER TYPE TYPE 1 TYPE 3 TYPE 5
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Intel and Pentium III are trademarks of Intel Corporation. Direct Rambus and Rambus are trademarks of Rambus Inc.
CDC924 133ĆMHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3ĆSTATE OUTPUTS
description (continued)
Since the CDC924 is based on PLL circuitry, it requires a stabilization time to achieve phase lock of the PLL. This stabilization time is required after power up or after changes to the SEL inputs are made. With use of an external reference clock, this signal must be fixed-frequency and fixed-phase before the stabilization time starts.
Copyright 2005, Texas Instruments Incorporated
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SCAS607B − NOVEMBER 1998 − REVISED JULY 2005
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Generate Multiple Output Frequencies
DL PACKAGE (TOP VIEW)
D Includes Spread Spectrum Clocking (SSC), D D D D
0.5% Downspread for Reduced EMI Performance Power Management Control Terminals Low Output Skew and Jitter for Clock Distribution 2.5-V and 3.3-V Supplies Generates the Following Clocks: − 4 CPU (2.5 V, 100/133 MHz) − 7 PCI (3.3 V, 33.3 MHz) − 1 PCI_F (Free Running, 3.3 V, 33.3 MHz) − 2 CPU/2 (2.5 V, 50/66 MHz) − 3 APIC (2.5 V, 16.67 MHz) − 4 3V66 (3.3 V, 66 MHz) − 2 REF (3.3 V, 14.318 MHz) − 1 48MHz (3.3 V, 48 MHz) Packaged in 56-Pin SSOP Package Designed for Use with TI’s Direct Rambus Clock Generators (CDCR81, CDCR82, CDCR83)
All output frequencies are generated from a 14.318-MHz crystal input. A reference clock input instead of a crystal can be provided at the XIN input. Two phase-locked loops (PLLs) are used, one to generate the host frequencies and the other to generate the 48-MHz clock frequency. On-chip loop filters and internal feedback loops eliminate the need for external components. The host and PCI clock outputs provide low-skew and low-jitter clock signals for reliable clock operation. All outputs have 3-state capability, which can be selected via control inputs SEL0, SEL1, and SEL133/100. The outputs are either 3.3-V or 2.5-V single-ended CMOS buffers. With a logic high-level on the PWR_DWN terminal, the device operates normally, but when a logical low-level input is applied, the device powers down completely, with the outputs in a low-level output state. When a high-level is applied to the PCI_STOP or CPU_STOP, the outputs operate normally. With a low-level applied to the PCI_STOP or CPU_STOP terminals, the PCI or CPU and 3V66 outputs, respectively, are held in a low-level state. The CPU bus can operate at 100 MHz or 133 MHz. Output frequency selection is done with corresponding setting for SEL133/100 control input. The PCI bus frequency is fixed to 33MHz.