TPS659113
2景阳公司模拟产品对应技术方案和芯
景阳公司模拟产品对应技术方案和芯片介绍景阳公司模拟产品对应技术方案和芯片介绍1、方案名：HQ1芯片供应商：SONY主芯片构架：DSP(CXD3172)+AFE(CXA2096或CXA3796N)兼容CCD ：760H(NTSC:ICX638;PAL:ICX639);510H(NTSC:ICX632;PAL:ICX633)，还有其他四分一和二分一的CCD 就不介绍了。
景阳公司产品型号：0580DCBW,468等2、方案名：SS-11RM 芯片供应商：SONY 主芯片构架：DSP(CXD3142)+AFE(CXA2096或CXA3796N)+V-DRIVER(CXD1267/7221等)兼容CCD ：510H(NTSC:ICX632;PAL:ICX633)，还有其他四分一的CCD 就不介绍了。
景阳公司产品型号：2423、方案名：无。
主芯片：NVP2010,2020芯片供应商：NEXTCHIP主芯片构架：DSP(NVP2010,2020)+AFE(AD9943)兼容CCD ：510H(NTSC:ICX632;PAL:ICX633)景阳公司产品型号：59014、方案名：HAWK芯片供应商：NEXTCHIP主芯片构架：DSP(NVP2170、2170E)+AFE(AD9943)兼容CCD ：760H(NTSC:ICX638;PAL:ICX639)景阳公司产品型号：59105、方案名：EFFIO-E芯片供应商：SONY主芯片构架：DSP(CXD4127GG)+AFE(CXD4816GG)兼容CCD ：510H(NTSC:ICX632;PAL:ICX633);760H(NTSC:ICX638;PAL:ICX639);960H (NTSC:ICX672;PAL:ICX673)景阳公司产品型号：4920;5920;5930等6、方案名：ENHANCE(增强型) EFFIO-E 芯片供应商：SONY主芯片构架：DSP(CXD4140GG)+AFE(CXD5148GG)兼容CCD ：第 1 页 景阳技术资料研发中心：吴文宪510H(NTSC:ICX632;PAL:ICX633);760H(NTSC:ICX638;PAL:ICX639);960H (NTSC:ICX672/810;PAL:ICX673/811)景阳公司产品型号：4920;5920;5930二代等7、方案名：EFFIO-S 芯片供应商：SONY 主芯片构架：DSP(CXD4130GG)+AFE(CXD5148GG)兼容CCD ：510H(NTSC:ICX632;PAL:ICX633);760H(NTSC:ICX638;PAL:ICX639);960H (NTSC:ICX672/810;PAL:ICX673/811)景阳公司产品型号：目前搭配960H 的产品型号是5940系列等8、方案名：EFFIO-p 芯片供应商：SONY 主芯片构架：DSP(CXD4129GG)+AFE(CXD5148GG)兼容CCD ：960H(NTSC:ICX662;PAL:ICX663)景阳公司产品型号：5950系列等9、方案名：seawolf芯片供应商：pixim主芯片构架：D8800C （含cmos sensor 和ISP ）景阳公司产品型号：0586系列等10、方案名：无，主芯片mt9v136芯片供应商：Aptina(MICRON)主芯片构架：mt9v136（含cmos sensor 和ISP ）10、方案名：无，主芯片OV7960芯片供应商：OV主芯片构架：OV7960（含cmos sensor 和ISP ）第 2 页景阳技术资料研发中心：吴文宪。
TPS65910A3A1RSLR;TPS65910A3A1RSL;中文规格书,Datasheet资料
TPS65910,TPS65910A,TPS65910A3,TPS659101,TPS659102,TPS659103TPS659104,TPS659105,TPS659106,TPS659107,TPS659108,TPS659109 SWCS046O–MARCH2010–REVISED JULY2012 Integrated Power Management Unit Top SpecificationCheck forSamples:TPS65910,TPS65910A,TPS65910A3,TPS659101,TPS659102,TPS659103,TPS659104,TPS659105,TPS659106,TPS659107,TPS659108,TPS659109FEATURES APPLICATIONSThe purpose of the TPS65910device is to•Portable and handheld systemsprovide the following resources:•OMAP3power management•Embedded power controllerDESCRIPTION•Two efficient step-down dc-dc converters forThe TPS65910is an integrated power-management processor coresIC available in48-QFN package and dedicated to •One efficient step-down dc-dc converter for I/Oapplications powered by one Li-Ion or Li-Ion polymer powerbattery cell or3-series Ni-MH cells,or by a5-V input;•One efficient step-up5-V dc-dc converter it requires multiple power rails.The device providesthree step-down converters,one step-up converter,•SmartReflex™compliant dynamic voltageand eight LDOs and is designed to support the management for processor coresspecific power requirements of OMAP-based •8LDO voltage regulators and one RTC LDOapplications.(internal purpose)Two of the step-down converters provide power for •One high-speed I2C interface for general-dual processor cores and are controllable by a purpose control commands(CTL-I2C)dedicated class-3SmartReflex interface for optimum •One high-speed I2C interface for SmartReflex power savings.The third converter provides power for Class3control and command(SR-I2C)the I/Os and memory in the system.•Two enable signals multiplexed with SR-I2C,The device includes eight general-purpose LDOs configurable to control any supply state and providing a wide range of voltage and current processor cores supply voltage capabilities;they are fully controllable by the I2Cinterface.The use of the LDOs is flexible;they are •Thermal shutdown protection and hot-dieintended to be used as follows:Two LDOs are detectiondesignated to power the PLL and video DAC supply •A real-time clock(RTC)resource with:rails on the OMAP based processors,four general-–Oscillator for32.768-kHz crystal or32-kHz purpose auxiliary LDOs are available to provide built-in RC oscillator power to other devices in the system,and two LDOsare provided to power DDR memory supplies in –Date,time and calendarapplications requiring these memories.–Alarm capabilityIn addition to the power resources,the device •One configurable GPIOcontains an embedded power controller(EPC)to •DC-DC switching synchronization through manage the power sequencing requirements of the internal or external3-MHz clock OMAP systems and an(RTC).Figure1shows the top-level diagram of the device.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Copyright©2010–2012,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasPSWCS046-001Ci Co Ci Ci Ci (VCCIO)Ci (VCC2)Ci (VCC1)TPS65910,TPS65910A,TPS65910A3,TPS659101,TPS659102,TPS659103TPS659104,TPS659105,TPS659106,TPS659107,TPS659108,TPS659109SWCS046O –MARCH 2010–REVISED JULY 2012Figure 1.48-QFN Top-Level Diagram2Submit Documentation Feedback Copyright ©2010–2012,Texas Instruments IncorporatedTPS65910,TPS65910A,TPS65910A3,TPS659101,TPS659102,TPS659103TPS659104,TPS659105,TPS659106,TPS659107,TPS659108,TPS659109 SWCS046O–MARCH2010–REVISED JULY2012 Table1.SUPPORTED PROCESSORS AND CORRESPONDING PART NUMBERSCompatible Processor(1)Part Number(1)TI processor-AM335x with DDR2TPS65910AA1RSLTI processor-AM335x with DDR3TPS65910A3A1RSL TI processors-AM1705/07,AM1806/08,AM3505/17,AM3703/15,DM3730/25,TPS65910A1RSL OMAP-L137/38,OMAP3503/15/25/30,TMS320C6742/6/8Samsung-S5PV210,S5PC110TPS659101A1RSLRockchip-RK29xx TPS659102A1RSLSamsung-S5PC100TPS659103A1RSLSamsung-S5P6440TPS659104A1RSLTI processors-DM643x,DM644x TPS659105A1RSLReserved TPS659106A1RSLFreescale-i.MX27,Freescale-i.MX35TPS659107A1RSLFreescale-i.MX508TPS659108A1RSLFreescale-i.MX51TPS659109A1RSL(1)The RSL package is available in tape and reel.See for details for corresponding part numbers,quantities and ordering information. ABSOLUTE MAXIMUM RATINGSover operating free-air temperature range(unless otherwise noted)Stresses beyond those listed under below may cause permanent damage to the device.These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated below are not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.The absolute maximum ratings for the TPS65910device are listed below:PARAMETER MIN MAX UNITVoltage range on pins/balls VCC1,VCC2,VCCIO,VCC3,VCC4,–0.37VVCC5,VCC6,VCC7Voltage range on pins/balls VDDIO–0.3 3.6VVoltage range on pins/balls OSC32KIN,OSC32KOUT,BOOT1,–0.3VRTC MAX+0.3VBOOT0Voltage range on pins/balls SDA_SDI,SCL_SCK,SDASR_EN2,–0.3VDDIO MAX+0.3VSCLSR_EN1,SLEEP,INT1,CLK32KOUT,NRESPWRONVoltage range on pins/balls PWRON–0.37VVoltage range on pins/balls PWRHOLD(1)GPIO_CKSYNC(2)–0.37V Functional junction temperature range–45150°CPeak output current on all other terminals than power resources–55mA(1)I/O supplied from VDDIO but which can be driven from to a VBAT voltage level(2)I/O supplied from VRTC but can be driven to a VBAT voltage levelTHERMAL CHARACTERISTICSover operating free-air temperature range(unless otherwise noted)DERATINGTA<25°C Power FACTOR ABOVE TA=70°C Power TA=85°C Power Package Rθja(°C/W)Rating(W)25°C(W)Rating(W)(mW/°C)RSL48-QFN37 2.637 1.481The thermal resistance RθJP junction-to-power PAD of the RSL package is1.1°C/WThe value of thermal resistance RθJA junction-to-ambient was measured on a high K.Copyright©2010–2012,Texas Instruments Incorporated Submit Documentation Feedback3TPS65910,TPS65910A,TPS65910A3,TPS659101,TPS659102,TPS659103TPS659104,TPS659105,TPS659106,TPS659107,TPS659108,TPS659109SWCS046O–MARCH2010–REVISED RECOMMENDED OPERATING CONDITIONSover operating free-air temperature range(unless otherwise noted)Lists of the recommended operating maximum ratings for the TPS65910device are given below.Note1:VCC7should be connected to the highest supply that is connected to the device VCCx pin.The exception is thatVCC2and VCC4can be higher than VCC7.Note2:VCC2and VCC4must be connected together(to the same voltage).Note3:If VDD3boost is used,VAUX33must be set to2.8V or higher and enabled before VDD3.PARAMETER TEST CONDITIONS MIN NOM MAX UNITV CC:Input voltage range on pins/balls VCC1,VCC2,VCCIO,VCC3,VCC4,VCC5,2.73.6 5.5VVCC7V CCP:Input voltage range on pins/balls VCC6 1.7 3.6 5.5VInput voltage range on pins/balls VDDIO 1.65 1.8/3.3 3.45VInput voltage range on pins/balls PWRON0 3.6 5.5VInput voltage range on pins/balls SDA_SDI,SCL_SCK,SDASR_EN2,SCLSR_EN1,1.65VDDIO 3.45V SLEEPInput voltage range on pins/balls PWRHOLD,GPIO_CKSYNC 1.65VDDIO 5.5VInput voltage range on balls BOOT1,BOOT0,OSC32KIN 1.65VRTC 1.95VOperating free-air temperature,T A–402785°CJunction temperature T J–4027125°CStorage temperature range–6527150°CLead temperature(soldering,10s)260°CPower ReferencesVREF filtering capacitor C O(VREF)Connected from VREF to REFGND100nFVDD1SMPSInput capacitor C I(VCC1)X5R or X7R dielectric10µFFilter capacitor C O(VDD1)X5R or X7R dielectric41012µFC O filter capacitor ESR f=3MHz10300mΩInductor L O(VDD1) 2.2µHL O inductor dc resistor DCR L125mΩVDD2SMPSInput capacitor C I(VCC2)X5R or X7R dielectric10µFFilter capacitor C O(VDD2)X5R or X7R dielectric41012µFC O filter capacitor ESR f=3MHz10300mΩInductor L O(VDD2) 2.2µHL O inductor dc resistor DCR L125mΩVIO SMPSInput capacitor C I(VIO)X5R or X7R dielectric10µFFilter capacitor C O(VIO)X5R or X7R dielectric41012µFC O filter capacitor ESR f=3MHz10300mΩInductor L O(VIO) 2.2µHL O inductor dc resistor DCR L125mΩVDIG1LDOInput capacitor C I(VCC6)X5R or X7R dielectric 4.7µFFiltering capacitor C O(VDIG1)0.8 2.2 2.64µFC O filtering capacitor ESR0500mΩVDIG2LDOFiltering capacitor C O(VDIG2)0.8 2.2 2.64µFC O filtering capacitor ESR0500mΩVPLL LDOInput capacitor C I(VCC5)X5R or X7R dielectric 4.7µFFiltering capacitor C O(VPLL)0.8 2.2 2.64µF4Submit Documentation Feedback Copyright©2010–2012,Texas Instruments IncorporatedTPS65910,TPS65910A,TPS65910A3,TPS659101,TPS659102,TPS659103TPS659104,TPS659105,TPS659106,TPS659107,TPS659108,TPS659109 SWCS046O–MARCH2010–REVISED JULY2012 RECOMMENDED OPERATING CONDITIONS(continued)over operating free-air temperature range(unless otherwise noted)Lists of the recommended operating maximum ratings for the TPS65910device are given below.Note1:VCC7should be connected to the highest supply that is connected to the device VCCx pin.The exception is thatVCC2and VCC4can be higher than VCC7.Note2:VCC2and VCC4must be connected together(to the same voltage).Note3:If VDD3boost is used,VAUX33must be set to2.8V or higher and enabled before VDD3.PARAMETER TEST CONDITIONS MIN NOM MAX UNITC O filtering capacitor ESR0500mΩVDAC LDOFiltering capacitor C O(VDAC)0.8 2.2 2.64µFC O filtering capacitor ESR0500mΩVMMC LDOInput capacitor C I(VCC4)X5R or X7R dielectric 4.7µFFiltering capacitor C O(VMMC)0.8 2.2 2.64µFC O filtering capacitor ESR0500mΩVAUX33LDOFiltering capacitor C O(VAUX33)0.8 2.2 2.64µFC O filtering capacitor ESR0500mΩVAUX1LDOInput capacitor C I(VCC3)X5R or X7R dielectric 4.7µFFiltering capacitor C O(VAUX1)0.8 2.2 2.64µFC O filtering capacitor ESR0500mΩVAUX2LDOFiltering capacitor C O(VAUX2)0.8 2.2 2.64µFC O filtering capacitor ESR0500mΩVRTC LDOInput capacitor C I(VCC7)X5R or X7R dielectric 4.7µFFiltering capacitor C O(VRTC)0.8 2.2 2.64µFC O filtering capacitor ESR0500mΩVDD3SMPSInput capacitor C I(VDD3)X5R or X7R dielectric 4.7µFFilter capacitor C O(VDD3)X5R or X7R dielectric41012µFC O filter capacitor ESR f=1MHz10300mΩInductor L O(VDD3) 2.8 4.7 6.6µHL O inductor DC resistor DCR L50500mΩBackup BatteryBattery or superCap supplying VBACKUP5102000mF Backup battery capacitor C BBCapacitor supplying VBACKUP140µF5to15mF101500Series resistorsΩ100to2000mF515I2C InterfacesSDA_SDI,SCL_SCK,SDASR_EN2,Connected to VDDIO 1.2kΩSCLSR_EN1external pull-up resistorCrystal Oscillator(connected from OSC32KIN to OSC32KOUT)Crystal frequency@specified load cap value32.768kHzCrystal tolerance@27°C–20020ppmOscillator contribution(not including crystalFrequency Temperature coefficient.–0.50.5ppm/°Cvariation)Secondary temperature coefficient–0.04–0.035–0.03ppm/°C2Voltage coefficient–22ppm/V Copyright©2010–2012,Texas Instruments Incorporated Submit Documentation Feedback5TPS65910,TPS65910A,TPS65910A3,TPS659101,TPS659102,TPS659103TPS659104,TPS659105,TPS659106,TPS659107,TPS659108,TPS659109SWCS046O–MARCH2010–REVISED RECOMMENDED OPERATING CONDITIONS(continued)over operating free-air temperature range(unless otherwise noted)Lists of the recommended operating maximum ratings for the TPS65910device are given below.Note1:VCC7should be connected to the highest supply that is connected to the device VCCx pin.The exception is thatVCC2and VCC4can be higher than VCC7.Note2:VCC2and VCC4must be connected together(to the same voltage).Note3:If VDD3boost is used,VAUX33must be set to2.8V or higher and enabled before VDD3.PARAMETER TEST CONDITIONS MIN NOM MAX UNIT Max crystal series resistor@Fundamental frequency90kΩCrystal load capacitor According to crystal data sheet612.5pFLoad crystal oscillator Coscinparallel mode Including parasitic PCB capacitor1225pF,CoscoutQuality factor800080000ESD SPECIFICATIONSover operating free-air temperature range(unless otherwise noted)TI STANDARD ESD METHOD STANDARD REFERENCE PERFORMANCEREQUIREMENTS Human body model(HBM)EIA/JESD22-A114D2000V2000VCharge device model(CDM)EIA/JESD22-C101C500V500V6Submit Documentation Feedback Copyright©2010–2012,Texas Instruments IncorporatedTPS65910,TPS65910A,TPS65910A3,TPS659101,TPS659102,TPS659103TPS659104,TPS659105,TPS659106,TPS659107,TPS659108,TPS659109 SWCS046O–MARCH2010–REVISED JULY2012 I/O PULLUP AND PULLDOWN CHARACTERISTICSover operating free-air temperature range(unless otherwise noted)(1)PARAMETER TEST CONDITIONS MIN TYP MAX UNITSDA_SDI,SCL_SCK,SDASR_EN2,SCLSR_EN1Programmable pullup(DFT,default Grounded,VDDIO=1.8V–45%8+45%kΩinactive)SLEEP programmable pulldown(default active)@1.8V,VRTC=1.8V2 4.510µA@1.8V,VRTC=1.8V,VCC7=2.72 4.510VPWRHOLD programmable pulldown(defaultµA active)@5.5V,VRTC=1.8V,VCC7=5.571430VBOOT0,BOOT1programmable pulldown(default@1.8V,VRTC=1.8V2 4.510µA active)NRESPWRON pulldown@1.8V,VCC7=5.5V,OFF state2 4.510µA32KCLKOUT pulldown(disabled in Active-sleep@1.8V,VRTC=1.8V,OFF state2 4.510µA state)PWRON programmable pullup(default active)Grounded,VCC7=5.5V–40–31–15µAGPIO_CKSYNC programmable pullup(defaultGrounded,VRTC=1.8V–27–18–9µA active)(1)The internal pullups on the CTL-I2C and SR-I2C balls are used for test purposes or when the SR-I2C interface is not used.Discretepullups to the VIO supply must be mounted on the board in order to use the I2C interfaces.The internal I2C pullups must not be used for functional applicationsCopyright©2010–2012,Texas Instruments Incorporated Submit Documentation Feedback7TPS65910,TPS65910A,TPS65910A3,TPS659101,TPS659102,TPS659103TPS659104,TPS659105,TPS659106,TPS659107,TPS659108,TPS659109SWCS046O–MARCH2010–REVISED DIGITAL I/O VOLTAGE ELECTRICAL CHARACTERISTICSover operating free-air temperature range(unless otherwise noted)PARAMETER MIN TYP MAX UNITRelated I/O:PWRONLow-level input voltage V IL0.3x VCC7V High-level input voltage V IH0.7x VCC7VRelated I/Os:PWRHOLD,GPIO_CKSYNCLow-level input voltage V IL0.45VVDDIO/VHigh-level input voltage V IH 1.3VCC7VCC7Related I/Os:BOOT0,BOOT1,OSC32KINLow-level input voltage V IL0.35x VRTC V High-level input voltage V IH0.65x VRTC VRelated I/Os:SLEEPLow-level input voltage V IL0.35x VDDIO V High-level input voltage V IH0.65x VDDIO VRelated I/Os:NRESPWRON,INT1,32KCLKOUTLow-level output voltage V OL I OL=100µA0.2VI OL=2mA0.45V High-level output voltage V OH I OH=100µA VDDIO–0.2VI OH=2mA VDDIO–0.45VRelated Open-Drain I/Os:GPIO0Low-level output voltage V OL I OL=100µA0.2VI OL=2mA0.45VI2C-Specific Related I/Os:SCL,SDA,SCLSR_EN1,SDASR_EN2Low-level input voltage V IL–0.50.3x VDDIO V High-level input voltage V IH0.7x VDDIO V Hysteresis0.1x VDDIO VLow-level output voltage V OL@3mA(sink current),VDDIO=1.8V0.2×VDDIO VLow-level output voltage V OL@3mA(sink current),VDDIO=3.3V0.4x VDDIO V8Submit Documentation Feedback Copyright©2010–2012,Texas Instruments IncorporatedTPS65910,TPS65910A,TPS65910A3,TPS659101,TPS659102,TPS659103TPS659104,TPS659105,TPS659106,TPS659107,TPS659108,TPS659109 SWCS046O–MARCH2010–REVISED JULY2012 I2C INTERFACE AND CONTROL SIGNALSover operating free-air temperature range(unless otherwise noted)NO.PARAMETER TEST CONDITIONS MIN TYP MAXINT1rise and fall times,C L=5to35pF510nsNRESPWRON rise and fall times,C L=5to35pF510nsSLAVE HIGH–SPEED MODESCL/SCLSR_EN1and SDA/SDASR_EN2rise and fall1080nstime,C L=10to100pFData rate 3.4MbpsI3t su(SDA-SCLH)Setup time,SDA valid to SCL high10nsI4t h(SCLL-SDA)Hold time,SDA valid from SCL low070nsI7t su(SCLH-SDAL)Setup time,SCL high to SDA low160nsI8t h(SDAL-SCLL)Hold time,SCL low from SDA low160nsI9t su(SDAH-SCLH)Setup time,SDA high to SCL high160nsSLAVE FAST MODESCL/SCLSR_EN1and SDA/SDASR_EN2rise and fall20+250nstime,C L=10to400pF0.1×C LData rate400KbpsI3t su(SDA-SCLH)Setup time,SDA valid to SCL high100nsI4t h(SCLL-SDA)Hold time,SDA valid from SCL low00.9µsI7t su(SCLH-SDAL)Setup time,SCL high to SDA low0.6µsI8t h(SDAL-SCLL)Hold time,SCL low from SDA low0.6µsI9t su(SDAH-SCLH)Setup time,SDA high to SCL high0.6µsSLAVE STANDARD MODESCL/SCLSR_EN1and SDA/SDASR_EN2rise and fall250nstime,C L=10to400pFData rate100KbpsI3t su(SDA-SCLH)Setup time,SDA valid to SCL high250nsI4t h(SCLL-SDA)Hold time,SDA valid from SCL low0µsI7t su(SCLH-SDAL)Setup time,SCL high to SDA low 4.7µsI8t h(SDAL-SCLL)Hold time,SCL low from SDA low4µsI9t su(SDAH-SCLH)Setup time,SDA high to SCL high4µsSWITCHING CHARACTERISTICSSLAVE HIGH–SPEED MODEI1t w(SCLL)Pulse duration,SCL low160nsI2t w(SCLH)Pulse duration,SCL high60nsSLAVE FAST MODEI1t w(SCLL)Pulse duration,SCL low 1.3µsI2t w(SCLH)Pulse duration,SCL high0.6µsSLAVE STANDARD MODEI1t w(SCLL)Pulse duration,SCL low 4.7µsI2t w(SCLH)Pulse duration,SCL high4µs Copyright©2010–2012,Texas Instruments Incorporated Submit Documentation Feedback9TPS65910,TPS65910A,TPS65910A3,TPS659101,TPS659102,TPS659103TPS659104,TPS659105,TPS659106,TPS659107,TPS659108,TPS659109SWCS046O–MARCH2010–REVISED POWER CONSUMPTIONover operating free-air temperature range(unless otherwise noted)All current consumption measurements are relative to the FULL chip,all VCC inputs set to VBAT voltage.PARAMETER TEST CONDITIONS MIN TYP MAX UNITDevice BACKUP state VBAT=2.4V,VBACKUP=0V,1116µA VBAT=0V,VBACKUP=3.2V69Device OFF state VBAT=3.6V,CK32K clock runningBOOT[1:0]=00:32-kHz RC oscillator16.523BOOT[1:0]=01:32-kHz quartz or bypass oscillator,BOOT0P1520=0µA BOOT[1:0]=01,Backup Battery Charger on,VBACKUP=3.23242VVBAT=5V,CK32K clock running:2028BOOT[1:0]=00:RC oscillatorDevice SLEEP state VBAT=3.6V,CK32K clock running,PWRHOLDP=0BOOT[1:0]=00,3DC-DCs on,5LDOs and VRTC on,no load295µA BOOT[1:0]=01,3DC-DCs on,3LDOs and VRTC on,no load,279BOOT0P=0Device ACTIVE state VBAT=3.6V,CK32K clock running,PWRHOLDP=0BOOT[1:0]=00,3DC-DCs on,5LDOs and VRTC on,no load1BOOT[1:0]=01,3DC-DCs on,3LDOs and VRTC on,no load,0.9mABOOT0P=0BOOT[1:0]=00,3DC-DCs on PWM mode(VDD1_PSKIP=VDD2_PSKIP=VIO_PSKIP=0),5LDOs and VRTC on,no21loadPOWER REFERENCES AND THRESHOLDSover operating free-air temperature range(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNITOutput reference voltage(VREFDevice in active or low-power mode–1%0.85+1%V terminal)Main battery charged Measured on VCC7terminalthreshold VMBCH(programmable)Triggering monitored through NRESPRWONVMBCH_VSEL=11,BOOT[1:0]=11or003VMBCH_VSEL=10 2.9VVMBCH_VSEL=01 2.8VMBCH_VSEL=00bypassedMain battery discharged Measured on VCC7terminal(MTL prg)VMBCH–V threshold VMBDCH(programmable)Triggering monitored through INT1100mVMain battery low threshold VMBLO Measured on VCC7terminal(Triggering2.5 2.6 2.7V (MB comparator)monitored on terminal NRESPWRON)VBACKUP=0V,measured on terminal VCC7Main battery high threshold VMBHI 2.6 2.753(MB comparator)VVBACKUP=3.2V,measured on terminal VCC7 2.5 2.553Main battery not present threshold Measured on terminal VCC71.92.1 2.2V VBNPR(Triggering monitored on terminal VRTC)V CC=3.6VGround current(analog references+comparators+backup battery Device in OFF state8µA switch)Device in ACTIVE or SLEEP state2010Submit Documentation Feedback Copyright©2010–2012,Texas Instruments Incorporated分销商库存信息:TITPS65910A3A1RSLR TPS65910A3A1RSL。
6N134中文资料
6N134中⽂资料FeaturesDual Marked with Device Part Number and DSCC Drawing NumberManufactured and Tested on a MIL-PRF-38534 Certified LineQML-38534, Class H and K Five Hermetically Sealed Package Configurations Performance Guaranteed over -55°C to +125°C ? High Speed: 10 M Bit/sCMR: > 10,000 V/µs Typical 1500 Vdc Withstand Test Voltage2500 Vdc Withstand Test Voltage for HCPL-565X High Radiation Immunity 6N137, HCPL-2601, HCPL-2630/-31 Function Compatibility ? Reliability DataTTL Circuit CompatibilityApplicationsMilitary and SpaceHigh Reliability SystemsTransportation, Medical, and Life Critical SystemsLine ReceiverVoltage Level ShiftingIsolated Input Line Receiver Isolated Output Line Driver Logic Ground Isolation Harsh Industrial EnvironmentsIsolation for Computer,Communication, and Test Equipment SystemsDescriptionThese units are single, dual and quad channel, hermetically sealed optocouplers. The products are capable of operation and storage over the full military temperature range and can be purchased as either standard product or with full MIL-PRF-38534 Class Level H or K testing or from the appropri-ate DSCC Drawing. All devices are manufactured and tested on a MIL-PRF-38534 certified line and are included in the DSCC Quali-fied Manufacturers List QML-38534 for Hybrid Microcircuits.Quad channel devices areavailable by special order in the 16 pin DIP through hole packages.Truth Table(Positive Logic)Multichannel DevicesInput Output On (H)L Off (L)HFunctional DiagramMultiple Channel Devices AvailableSingle Channel DIP Input Enable Output On (H)H L Off (L)H H On (H)L H Off (L)LH*See matrix for available extensions.Hermetically Sealed, High Speed,High CMR, Logic Gate Optocouplers Technical Data6N134*81028HCPL-563X HCPL-663X HCPL-565X 5962-98001HCPL-268K HCPL-665X 5962-90855HCPL-560XCAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.V CC V OUTV E GNDThe connection of a 0.1 µF bypass capacitor between V CC and GND is recommended.Selection Guide–Package Styles and Lead Configuration OptionsPackage16 Pin DIP 8 Pin DIP 8 Pin DIP 8 Pin DIP 16 Pin Flat Pack 20 Pad LCCC Lead Style Through Hole Through Hole Through Hole Through Hole Unformed Leads Surface MountChannels 212242Common Channel V CC , GND None V CC , GND V CC , GND V CC , GND None WiringWithstand Test Voltage 1500 Vdc 1500 Vdc 1500 Vdc 2500 Vdc 1500 Vdc 1500 Vdc Agilent Part # & Options Commercial6N134*HCPL-5600HCPL-5630HCPL-5650HCPL-6650HCPL-6630MIL-PRF-38534, Class H 6N134/883BHCPL-5601HCPL-5631HCPL-5651HCPL-6651HCPL-6631MIL-PRF-38534, Class K HCPL-268K HCPL-560K HCPL-563K HCPL-665K HCPL-663K Standard Lead Finish Gold Plate Gold Plate Gold Plate Gold Plate Gold PlateSolder PadsSolder Dipped Option #200Option #200Option #200Option #200Butt Cut/Gold Plate Option #100Option #100Option #100Gull Wing/Soldered Option #300Option #300Option #300Class H SMD Part #Prescript for all below None 5962-None None None None Either Gold or Solder 8102801EX 9085501HPX 8102802PX 8102805PX 8102804FX 81028032XGold Plate 8102801EC 9085501HPC 8102802PC 8102805PC 8102804FCSolder Dipped 8102801EA 9085501HPA 8102802PA 8102805PA81028032A Butt Cut/Gold Plate 8102801UC 9085501HYC 8102802YC Butt Cut/Soldered 8102801UA 9085501HYA 8102802YA Gull Wing/Soldered 8102801TA 9085501HXA8102802ZA Class K SMD Part #Prescript for all below 5962-5962-5962-5962-5962-Either Gold or Solder 9800101KEX 9085501KPX 9800102KPX 9800104KFX 9800103K2XGold Plate 9800101KEC 9085501KPC 9800102KPC 9800104KFCSolder Dipped 9800101KEA 9085501KPA 9800102KPA 9800103K2AButt Cut/Gold Plate 9800101KUC 9085501KYC 9800102KYC Butt Cut/Soldered 9800101KUA 9085501KYA 9800102KYA Gull Wing/Soldered9800101KTA 9085501KXA 9800102KZA*JEDEC registered part.Each channel contains a GaAsP light emitting diode which isoptically coupled to an integrated high speed photon detector. The output of the detector is an open collector Schottky clamped transistor. Internal shields provide a guaranteed common mode transient immunityspecification of 1000 V/µs. For Isolation Voltage applications requiring up to 2500 Vdc, the HCPL-5650 family is also available. Package styles for these parts are 8 and 16 pin DIP through hole (case outlines P andE respectively), and 16 pin surface mount DIP flat pack(case outline F), leadless ceramic chip carrier (case outline 2).Devices may be purchased with a variety of lead bend and plating options. See Selection Guide Table for details. Standard Microcircuit Drawing (SMD)parts are available for each package and lead style.Because the same electrical die (emitters and detectors) are used for each channel of each device listed in this data sheet, absolute maximum ratings, recommended operating conditions, electrical specifications, and performance characteristics shown in the figures are identical for all parts.Occasional exceptions exist due to package variations and limitations,and are as noted. Additionally, the same package assembly processes and materials are used in all devices. These similarities give justification for the use of data obtained from one part torepresent other parts’ performance for reliability and certain limited radiation test results.Outline Drawings16 Pin DIP Through Hole, 2 ChannelsFunctional DiagramsNote: All DIP and flat pack devices have common V CC and ground. Single channel DIP has an enable pin 7. LCCC (leadless ceramic chip carrier) package has isolated channels with separate VCC and ground connections. All diagrams are “top view.”Leaded Device MarkingLeadless Device MarkingNOTE: DIMENSIONS IN MILLIMETERS (INCHES).COMPLIANCE INDICATOR,*DATE CODE, SUFFIX (IF NEEDED)COUNTRY OF MFR.Agilent CAGE CODE*Agilent DESIGNATORDSCC SMD*PIN ONE/ ESD IDENTAgilent P/N DSCC SMD** QUALIFIED PARTS ONLYCOMPLIANCE INDICATOR,*DATE CODE, SUFFIX (IF NEEDED)DSCC SMD*Agilent CAGE CODE*Agilent DESIGNATORCOUNTRY OF MFR.Agilent P/N PIN ONE/ ESD IDENTDSCC SMD** QUALIFIED PARTS ONLYOutline Drawings (continued)16 Pin Flat Pack, 4 Channels8 Pin DIP Through Hole, 2 Channels 2500 Vdc Withstand Test Voltage20 Terminal LCCC Surface Mount,2Channels8 Pin DIP Through Hole, 1 and 2 Channels0.36 (0.014)NOTE: DIMENSIONS IN MILLIMETERS (INCHES).2.29 (0.090) 2.79 (0.110)NOTE: DIMENSIONS IN MILLIMETERS (INCHES).NOTE: DIMENSIONS IN MILLIMETERS (INCHES).NOTE: DIMENSIONS IN MILLIMETERS (INCHES). SOLDER THICKNESS 0.127 (0.005) MAX.Hermetic Optocoupler OptionsRecommended Operating ConditionsParameterSymbol Min.Max.Units Input Current, Low Level, Each Channel I FL 0250µA Input Current, High Level, Each Channel*I FH 1020mA Supply Voltage, OutputV CC 4.55.5VFan Out (TTL Load) Each ChannelN6*Meets or exceeds DSCC SMD and JEDEC requirements.Absolute Maximum Ratings(No derating required up to +125°C)Storage Temperature Range, T S ...................................-65°C to +150°C Operating Temperature, T A..........................................-55°C to +125°C Case Temperature, T C ................................................................+170°C Junction Temperature, T J ...........................................................+175°C Lead Solder Temperature ...............................................260°C for 10 s Peak Forward Input Current, I F PK , (each channel,≤1 ms duration)......................................................................40 mA Average Input Forward Current, I F AVG (each channel)................20 mA Input Power Dissipation (each channel).....................................35 mW Reverse Input Voltage, V R (each channel).........................................5 V Supply Voltage, V CC (1 minute maximum)........................................7 V Output Current, I O (each channel)...............................................25 mA Output Power Dissipation (each channel). (40)mW Output Voltage, V O (each channel)..................................................7 V*Package Power Dissipation, P D (each channel)........................200 mW*Selection for higher output voltages up to 20 V is available.Single Channel Product OnlyEmitter Input Voltage, V E ...............................................................5.5 VNote enable pin 7. An external 0.01 µF to 0.1 µF bypass capacitor must be connected between V CC and ground for each package type.8 Pin Ceramic DIP Single Channel SchematicESD Classification(MIL-STD-883, Method 3015)HCPL-5600/01/0K ...............................................................(?), Class 16N134, 6N134/883B, HCPL-5630/31/3K, HCPL-5650/51, HCPL-6630/31/3K and HCPL-6650/51/5K.......................(Dot), Class 3Electrical Characteristics (T= -55°C to +125°C, unless otherwise specified)*Identified test parameters for JEDEC registered parts.**All typical values are at V CC = 5 V , T A = 25°C. Recommended Operating Conditions (cont’d.)Single Channel Product Only [10]ParameterSymbol Min.Max.Units High Level Enable Voltage V EH 2.0V CC V Low Level Enable VoltageV EL0.8VElectrical Characteristics, (Contd.) T= -55°C to +125°C unless otherwise specifiedSingle Channel Product Only Low Level I EL V CC = 5.5 V,1, 2, 3-1.45-2.0mA Enable Current V E = 0.5 V High Level V EH 1, 2, 3 2.0V10Enable Voltage Low Level V EL 1, 2, 30.8VEnable Voltage*Identified test parameters for JEDEC registered part.**All typical values are at V CC = 5 V , T A = 25°C.Typical Characteristics, T = 25°C, V = 5 VDual and Quad Channel Product Only Input-Input I I-I 0.5nA Relative Humidity = 45%4Leakage CurrentV I-I = 500 V, t = 5 s Resistance (Input-Input)R I-I 1012V I-I = 500 V 4Capacitance (Input-Input)C I-I0.55pF f = 1 MHz4Notes:1. Each channel.2. All devices are considered two-terminal devices; I I-O is measured between all input leads or terminals shorted together and alloutput leads or terminals shorted together.3. Measured between each input pair shorted together and all output connections for that channel shorted together.4. Measured between adjacent input pairs shorted together for each multichannel device.5. t PHL propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.5 V point on the leadingedge of the output pulse. The t PLH propagation delay is measured from the 50% point on the trailing edge of the input pulse to the1.5 V point on the trailing edge of the output pulse.6. The HCPL-6630, HCPL-6631, and HCPL-663K dual channel parts function as two independent single channel units. Use the singlechannel parameter limits for each channel.7. CM L is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage in the logic low state(V O < 0.8 V). CM H is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in the logic high state (V O > 2.0 V).8. This is a momentary withstand test, not an operating condition.9. It is essential that a bypass capacitor (0.01 to 0.1 µF, ceramic) be connected from V CC to ground. Total lead length between bothends of this external capacitor and the isolator connections should not exceed 20 mm.10. No external pull up is required for a high logic state on the enable input.11. The t ELH enable propagation delay is measured from the 1.5 V point on the trailing edge of the enable input pulse to the 1.5 Vpoint on the trailing edge of the output pulse.12. The t EHL enable propagation delay is measured from the 1.5 V point on the leading edge of the enable input pulse tothe 1.5 Vpoint on the leading edge of the output pulse.13. Standard parts receive 100% testing at 25°C (Subgroups 1 and 9). SMD and 883B parts receive 100% testing at 25, 125, and-55°C (Subgroups 1 and 9, 2 and 10, 3 and 11, respectively).14. Parameters are tested as part of device initial characterization and after design and process changes. Parameters are guaranteedto limits specified for all lots not specifically tested.15. Not required for 6N134, 6N134/883B, 8102801, HCPL-268K and 5962-9800101 types.16. Required for 6N134, 6N134/883B, 8102801, HCPL-268K and 5962-9800101 types.17. Not required for HCPL-5650, HCPL-5651 and 8102805 types.18. Required for HCPL-5650, HCPL-5651 and 8102805 types only.Figure 1. High Level Output Currentvs. Temperature.5 VV O * C L INCLUDES PROBE AND STRAY WIRING CAPACITANCE. Figure 4. Test Circuit for t PHL and t PLH .*I +5 V OUTPUT V O MONITORING NODEFigure 7. Test Circuit for Common Mode Transient Immunity and Typical Waveforms.11OUTPUT V OMONITORINGNODET A = +125 °C* ALL CHANNELS TESTED SIMULTANEOUSLY.V CCI O = 25 mAFigure 10. Operating Circuit for Burn-In and Steady State Life Tests. Figure 8. Test Circuit for t EHL and t ELH.Figure 9. Enable Propagation Delayvs. Temperature.MIL-PRF-38534 Class H,Class K, and DSCC SMDTest ProgramAgilent’s Hi-Rel Optocouplers arein compliance with MIL-PRF-38534 Classes H and K. Class Hand Class K devices are also incompliance with DSCC drawings81028, 5962-90855 and 5962-98001.Testing consists of 100% screen-ing and quality conformanceinspection to MIL-PRF-38534./doc/4e2d970a03d8ce2f006623a8.htmlData subject to change.Copyright ? 1999 Agilent TechnologiesObsoletes 5968-4743E5968-9407E (10/00)。
TPS65100中文资料
FB2 REF FB4 BASE
SW SW FB1 SUP
C2+ C2−/MODE
OUT3
FB3 VCOM PGND PGND
GND
R4
VO1
D1
Up to 15 V/350 mA
C5 R1
C4 22 µF
C2 0.22 µF R2
Vo3 up to 30 V/20 mA
R5
C7
0.22 µF
R6
C11 220 nF
Copyright © 2003–2004, Texas Instruments Incorporated
Байду номын сангаас
元器件交易网
TPS65100 TPS65105
SLVS496B – SEPTEMBER 2003 – REVISED MARCH 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
Freescale i.MX6 Dual Quad TPS659114电源管理集成电路用户指南说明书
1SWCU181C–January 2016–Revised September 2016Submit Documentation FeedbackCopyright ©2016,Texas Instruments IncorporatedTPS659114for Freescale i.MX6Dual/Quad User's Guide User's GuideSWCU181C–January 2016–Revised September 2016TPS659114for Freescale i.MX6Dual/Quad User's Guide1IntroductionThis document is an application note describing the EEPROM configuration and the power-up sequence of the TPS659114power-management integrated circuit (PMIC).For details of the PMIC features and performance,refer to the full specification document TPS65911data manual (SWCS049).SWCU181-0012.7V < Vin <3.6V If LDO1 or LDO2usedPlatform Connection 2SWCU181C–January 2016–Revised September 2016Submit Documentation FeedbackCopyright ©2016,Texas Instruments IncorporatedTPS659114for Freescale i.MX6Dual/Quad User's Guide2Platform ConnectionFigure 1.Connecting TPS659114to Freescale i.MX6 EEPROM Setting3SWCU181C–January 2016–Revised September 2016Submit Documentation FeedbackCopyright ©2016,Texas Instruments IncorporatedTPS659114for Freescale i.MX6Dual/Quad User's Guide 3EEPROM SettingTable 1describes the EEPROM configuration for the TPS659114power-up sequence with BOOT1=1.When a resource is associated to time slot 0,it means that the resource is OFF at power up.Table 1.EEPROM Configuration for TPS659114REGISTERBITDESCRIPTIONOPTION SELECTEDVDD1_OP_REG/VDD1_SR_REG SEL VDD1voltage level selection for boot. 1.5V VDD1_REG VGAIN_SELVDD1gain selection,x1or x2x1EEPROM VDD1time slot selection 7DCDCCTRL_REG VDD1_PSKIP VDD1pulse skip mode enable Skip enabledVDD2_OP_REG/VDD2_SR_REG SEL VDD2voltage level selection for boot 1.1V VDD2_REG VGAIN_SEL VDD2gain selection,x1or x3x3EEPROM VDD2time slot selection 3DCDCCTRL_REG VDD2_PSKIP VDD2pulse skip mode enable Skip enabledVIO_REG SEL[3:9]VIO voltage selection 1.5V EEPROM VIO time slot selection 7DCDCCTRL_REG VIO_PSKIP VIO pulse skip mode enableSkip enabled VDDCtrl_OP_REG/VDDCtrl_SR_REG SELVDDCtrl voltage level selection for boot 1.35V EEPROM VDDCtrl time slot 6LDO1_REG SEL[7:2]LDO1voltage selection 1.8V EEPROM LDO1time slot 5LDO2_REG SEL[7:2]LDO2voltage selection 1.5V EEPROM LDO2time slot 4LDO3_REG SEL[6:2]LDO3voltage selection 2.5V EEPROM LDO3time slot 5LDO4_REG SEL[7:2]LDO4voltage selection 3.0V EEPROM LDO4time slot 1LDO5_REG SEL[6:2]LDO5voltage selection 2.8V EEPROM LDO5time slot 2LDO6_REG SEL[6:2]LDO6voltage selection 3.3V EEPROM LDO6time slot 4LDO7_REG SEL[6:2]LDO7voltage selection 3.3V EEPROM LDO7time slot 4LDO8_REG SEL[6:2]LDO8voltage selection 3.3V EEPROM LDO8time slot 5CLK32KOUT pinCLK32KOUT time slot 8NRESPWRON,NRESPWRON2pin NRESPWRON time slot 9GPIO0pin GPIO0time slot 1GPIO2pin GPIO2time slot 0GPIO6pin GPIO6time slot 0GPIO7pin GPIO7time slotVRTC_REGVRTC_OFFMASK 0=VRTC LDO will be in low-power mode during OFF state.1=VRC LDO will be in full-power mode during OFF state.Full-power modeDEVCTRL_REG CK32K_CTRL 0=Clock source is crystal/external clock.1=Clock source is internal RC oscillator.ExternalEEPROM Setting 4SWCU181C–January 2016–Revised September 2016Submit Documentation FeedbackCopyright ©2016,Texas Instruments IncorporatedTPS659114for Freescale i.MX6Dual/Quad User's GuideTable 1.EEPROM Configuration for TPS659114(continued)REGISTERBITDESCRIPTIONOPTION SELECTEDDEVCTRL_REGDEV_ON0=No impact1=Will maintain device on,in ACTIVE or SLEEP stateDEVCTRL2_REG TSLOT_LENGTH Boot sequence time slot duration:0=0.5ms 1=2ms2msDEVCTRL2_REG PWON_LP_OFF 0=Turn-off after PWRON long press not allowed.1=Turn-off after PWRON long press.1DEVCTRL2_REG PWON_LP_RST 0=No impact1=Reset digital core when device is OFF.0DEVCTRL2_REG IT_POL 0=INT1signal will be active low.1=INT1signal will be active high.Active lowINT_MSK_REGVMBHI_IT_MSK0=Device automatically switches on at NO SUPPLY-to-OFF or BACKUP-to-OFF transition.1=Start-up is reason required before switch-on.1=Start-up requires activity on PWRHOLDor PWRONINT_MSK3_REG GPIO5_F_IT_MSK0=GPIO5falling edge detection interrupt not masked.1=GPIO5falling edge detection interrupt masked.MaskedINT_MSK3_REG GPIO5_R_IT_MSK 0=GPIO5rising edge detection interrupt not masked.1=GPIO5rising edge detection interrupt masked.MaskedINT_MSK3_REG GPIO4_F_IT_MSK 0=GPIO4falling edge detection interrupt not masked.1=GPIO4falling edge detection interrupt masked.MaskedINT_MSK3_REG GPIO4_R_IT_MSK 0=GPIO4rising edge detection interrupt not masked.1=GPIO4rising edge detection interrupt masked.MaskedGPIO0_REG GPIO_ODEN 0=GPIO0configured as push-pull output.1=GPIO0configured as open-drain output.Push-pull WATCHDOG_REGWATCHDOG_EN0=Watchdog disabled1=Watchdog enabled,periodic operation with 100sDisabledVMBCH_REG VMBBUF_BYPASS 0=Enable input buffer for external resistive divider.1=In single-cell system,disable buffer for lower power consumption.Enable bufferVMBCH_REG VMBCH_SEL[5:1]Select threshold for boot gating comparator COMP1,2.5–3.5V.3.1VEEPROMAUTODEV_ON0=PWRHOLD pin is used as PWRHOLD feature.1=PWRHOLD pin is GPI.After power-on,DEV_ON is set high internally,no processor action needed to maintain supplies.PWRHOLD feature implementedEEPROM PWRDN_POL 0=PWRDN signal is active low.1=PWRDN signal is active high.Active low1PWRON button press falling edge 2Valid press after debounce3First step of power up sequence available for DCDC,LDO activation.Time slot (2ms between slots):Event DescriptionEvent:VIO,1.3-A limit LDO6, 300-mA limit LDO7, 300-mA limit VDD1,2-A limit LDO1, 320-mA limit LDO8, 300-mA limit VDDCTRL,6-A+limitCLK32KOUTLDO3, 200-mA limit PWRON buttonVDD_RTC/VRTCLDO4, 50-mA limit LDO5, 300-mA limit VDD2, 1.2-A limit LDO2, 320-mA limit GPIO0, push-pull NRESPWRONEEPROM Setting5SWCU181C–January 2016–Revised September 2016Submit Documentation FeedbackCopyright ©2016,Texas Instruments IncorporatedTPS659114for Freescale i.MX6Dual/Quad User's Guide Figure 2.Timing DiagramGetting Started With 6SWCU181C–January 2016–Revised September 2016Submit Documentation FeedbackCopyright ©2016,Texas Instruments IncorporatedTPS659114for Freescale i.MX6Dual/Quad User's Guide4Getting Started With TPS6591144.1First Initialization4.1.1DCDC Maximum Current CapabilityUpon reset,all buck converters initialize with ILMAX =0,which may not allow proper regulation across all expected loads.In VIO_REG,VDD1_REG,and VDD2_REG,set the ILMAX bit according to the required maximum current.4.1.2I/O Polarity/Muxing ConfigurationVoltage scaling for VDD1,VDD2,and VDDCtrl can be done either through the main I 2C interface orthrough dedicated interface EN1/EN2.Refer to the processor documentation for information on which one is supported.To enable the dedicated voltage scaling interface,set the SR_CTL_I2C_SEL bit to 0in the DEVCTRL_REG register.If sleep mode is supported,program the SLEEPSIG_POL bit in the DEVCTRL2_REG register according to the GPIO from the processor.This can be set to active-low or active-high for SLEEP transitions.Software can configure specific power resources to enter the LOW-POWER or OFF state in sleep mode.In the DEVCTRL_REG register,set the DEV_SLP bit to 1to allow the SLEEP transition when requested through the SLEEP pin.Update the GPIOx configuration (GPIOx_REG)based on the specification needs.4.1.3Define Wake Up/Interrupt Event (SLEEP or OFF)Select the appropriate bits in the INT_MSK_REG,INT_MSK2_REG,and INT_MSK3_REG registers to activate an interrupt to the processor on the INT1line.4.1.4Backup Battery ConfigurationBackup Battery charging is disabled by default.To enable,set the BBCHEN bit to 1in the BBCH_REG register.The maximum voltage can be set based on backup battery specifications by using the BBSEL bits in the BBCH_REG register.4.1.5Sleep Platform ConfigurationSleep mode is disabled by default.To use the sleep pin,sleep mode must first be enabled by setting DEV_SLP to 1in the DEVCTRL_REG.Configure the state of the DC-DCs and LDOs when the SLEEP signal is used.By default,in sleep mode all resources maintain their output voltage and load capability,but response to transients (load change)is reduced.GPIO0can follow sleep state.Resources that must provide full load capability must be set in the SLEEP_KEEP_LDO_ON_REG and SLEEP_KEEP_RES_ON_REG registers.Resources that can be set to off in the SLEEP state to optimize power consumption must be set in the SLEEP_SET_LDO_OFF_REG and SLEEP_SET_RES_OFF_REG registers.4.2Event Management Through InterruptsThis section describes the TPS659114interrupts.4.2.1INT_STS_REG.VMBHI_ITThe VMBHI_IT interrupt bit indicates that a supply (VBAT)is connected (PMIC leaving the BACKUP or NO SUPPLY state)and the system must be initialized (see Section 4.1,First Initialization ).4.2.2INT_STS_REG.PWRON_ITThe PWRON_IT interrupt bit is triggered by pressing the PWRON button.If the device is in the OFF or SLEEP state,then this acts as a wake-up event and resources are reinitialized. Ordering Information7SWCU181C–January 2016–Revised September 2016Submit Documentation FeedbackCopyright ©2016,Texas Instruments IncorporatedTPS659114for Freescale i.MX6Dual/Quad User's Guide 4.2.3INT_STS_REG.PWRON_LP_ITThe PWRON_LP_IT interrupt bit is the PWRON long-press interrupt.This interrupt is generated when the PWRON button is pressed for 4seconds.The application processor can make a decision to acknowledge the interrupt.If this interrupt is not acknowledged within the next second,the device interprets this as a power-down event.4.2.4INT_STS_REG.HOTDIE_ITThe HOTDIE_IT interrupt bit indicates that the temperature of the die is reaching the limit.The software must take action to decrease the power consumption before automatic shutdown.4.2.5INT_STS_REG.PWRHOLD_R/F_ITThe PWRHOLD_R/F_IT interrupt bit indicates a GPI interrupt event.4.2.6INT_STS_REG.RTC_ALARM_ITThe RTC_ALARM_IT interrupt bit is triggered when the RTC alarm set time is reached.4.2.7INT_STS2(3)_REG.GPIO_R/F_ITThe GPIOx_R/F_IT interrupt bit indicates a GPIO1,GPIO2or GPIO3interrupt event.It can be used to wake up the device from SLEEP state.This can be an interrupt coming from any peripheral device or alike.4.2.8INT_STS3_REG.PWRDN_ITThe PWRDN_IT interrupt bit is triggered when PWRDN reset is detected.4.2.9INT_STS3_REG.VMBDCH2_H/L_ITThe VMBDCH2_H_IT or VMBDCH2_L_IT interrupt bit is triggered when comparator 2input (VCCS)is above or below the threshold,respectively.4.2.10INT_STS3_REG.WATCHDOG_ITThe WATCHDOG_IT interrupt bit is triggered from the watchdog (periodic or interrupt mode).5Ordering InformationTable 2.Ordering InformationPART NUMBER ORDERING INFORMATIONPROCESSOR TPS659114TPS659114A2ZRC/RFreescale i.MX6Revision History 8SWCU181C–January 2016–Revised September 2016Submit Documentation FeedbackCopyright ©2016,Texas Instruments IncorporatedRevision HistoryRevision HistoryChanges from B Revision (August 2016)to C Revision Page •Changed document title from TPS659114User's Guide :to TPS659114for Freescale i.MX6Dual/Quad User's Guide..1Changes from A Revision (January 2016)to B Revision Page •Changed VMBHI_IT_MSK Bit OPTION SELECTED in Table 1 (4)Changes from Original (January 2016)to A Revision Page •Updated Figure 1 (2)IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,enhancements,improvements and other changes to its semiconductor products and services per JESD46,latest issue,and to discontinue any product or service per JESD48,latest issue.Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.All semiconductor products(also referred to herein as“components”)are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its components to the specifications applicable at the time of sale,in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products.Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty.Except where mandated by applicable law,testing of all parameters of each component is not necessarily performed.TI assumes no liability for applications assistance or the design of Buyers’products.Buyers are responsible for their products and applications using TI components.To minimize the risks associated with Buyers’products and applications,Buyers should provide adequate design and operating safeguards.TI does not warrant or represent that any license,either express or implied,is granted under any patent right,copyright,mask work right,or other intellectual property right relating to any combination,machine,or process in which TI components or services are rmation published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement e of such information may require a license from a third party under the patents or other intellectual property of the third party,or a license from TI under the patents or other intellectual property of TI.Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties,conditions,limitations,and notices.TI is not responsible or liable for such altered rmation of third parties may be subject to additional restrictions.Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.Buyer acknowledges and agrees that it is solely responsible for compliance with all legal,regulatory and safety-related requirements concerning its products,and any use of TI components in its applications,notwithstanding any applications-related information or support that may be provided by TI.Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures,monitor failures and their consequences,lessen the likelihood of failures that might cause harm and take appropriate remedial actions.Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications.In some cases,TI components may be promoted specifically to facilitate safety-related applications.With such components,TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements.Nonetheless,such components are subject to these terms.No TI components are authorized for use in FDA Class III(or similar life-critical medical equipment)unless authorized officers of the parties have executed a special agreement specifically governing such use.Only those TI components which TI has specifically designated as military grade or“enhanced plastic”are designed and intended for use in military/aerospace applications or environments.Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk,and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use.TI has specifically designated certain components as meeting ISO/TS16949requirements,mainly for automotive use.In any case of use of non-designated products,TI will not be responsible for any failure to meet ISO/TS16949.Products ApplicationsAudio /audio Automotive and Transportation /automotiveAmplifiers Communications and Telecom /communicationsData Converters Computers and Peripherals /computersDLP®Products Consumer Electronics /consumer-appsDSP Energy and Lighting /energyClocks and Timers /clocks Industrial /industrialInterface Medical /medicalLogic Security /securityPower Mgmt Space,Avionics and Defense /space-avionics-defense Microcontrollers Video and Imaging /videoRFID OMAP Applications Processors /omap TI E2E Community Wireless Connectivity /wirelessconnectivityMailing Address:Texas Instruments,Post Office Box655303,Dallas,Texas75265Copyright©2016,Texas Instruments Incorporated。
DM8127平台入门教程
所以本人这里先把DM8127板子的启动过程先描述一下，让大家从硬件上和软件运行角度了解整个DM8127的工作过程，然后再去学习IPNC_RDK里面的开发包架构以及开发包的移植工作。
启动过程：上电——→DM8127内部片上的ROM CODE运行——→ROM CODE读取SYSBOOT PINS电平状态决定是从NAND FLASH BOOT还是UART0串口BOOT或者SD卡BOOT或者PCIe BOOT或者EMAC BOOT或者XIP BOOT ——→读取ubootmin并运行ubootmin（ubootmin取得ARM控制权）——→读取u-boot并运行u-boot（u-boot取得ARM控制权）——→读取linux 内核BIN并运行linux 内核（linux-2.6.37取得ARM控制权一直到板子复位或者断电）——→挂载文件系统（可以是存放在NAND FLASH的ubifs，squashfs，或者NFS）——→运行文件系统的脚本——→运行IPNC_RDK整个DEMO应用程序system_server，boa和live555等，启动VPSS M3核，启动VIDEO M3核，启动浮点DSP C674X核。
整个过程可以通过上图直观了解。
一、运行ubootmin一开始上电，DM8127主芯片内部有ROM CODE，这个是使用片上的内部RAM运行的，还没用片外的DDR3，如果新做的板子什么程序也没有，只要T PS659113电源管理芯片的供电时序正常，主晶振正常工作，那么ROM CODE 就会正常运行，先读取SYSBOOT PINS（就是BOOT MODE那几个外接上拉下拉电阻的管脚状态），如果对应的那些NAND FLASH或者SD 卡或者PCIe 等接口没有程序，那么DM8127这时会通过UART0 不断输出C C C C C C ……..的打印字符，试图通过UART0进行通讯下载UBOOT-OPTI BIN文件（这个UBOOT-OPTI后面介绍UBOOT移植的时候再分析）。
MEMORY存储芯片TPS65130RGER中文规格书
V V POSV NEGL1 TPS6513x Positive and Negative Output DC-DC Converter1Features• 2.7-V to 5.5-V Input Voltage Range•Dual Adjustable Output Voltages Up to 15V and Down to –15V•800-mA Typical Switch Current Limit at Boost and Inverter Main Switches at TPS65130•2-A Typical Switch Current Limit at Boost and Inverter Main Switches at TPS65131•Up to 89%Efficiency at Positive Output Voltage Rail•Up to 81%Efficiency at Negative Output Voltage Rail•Power-Save Mode for High Efficiency at Low Load Currents•Independent Enable Inputs for Power-Up and Power-Down Sequencing•Control Output for External PFET to Support Completely Disconnecting the Battery•Minimum 1.25-MHz Fixed Frequency PWM Operation•Thermal Shutdown•Overvoltage Protection on Both Outputs •1-µA Shutdown Current•Small 4-mm x 4-mm VQFN-24Package (RGE)2Applications•LCD and OLED Displays •Industrial Applications •Data Acquisition •Audio•General-Purpose Split-Rail Supplies3DescriptionThe TPS6513x is dual-output DC-DC converter generating a positive output voltage up to 15V and a negative output voltage down to –15V with output currents in a 200-mA range in typical applications,depending on input voltage to output voltage ratio.With a total efficiency up to 85%,the device is ideal for portable battery-powered equipment.The input voltage range of 2.7V to 5.5V allows the devices to be powered from batteries or from fixed 3.3-V or 5-V supplies.The TPS6513x comes in a small 4-mm ×4-mm VQFN-24package.Together with a minimum switching frequency of 1.25MHz,the device enables designing small power supply applications because it requires only a few small external components.The converter operates with a fixed frequency PWM control topology and,if power-save mode is enabled,it uses a pulse-skipping mode at light-load currents.It operates with only 500-µA device quiescent current.Independent enable pins allow power-up and power-down sequencing for both outputs.The device has an internal current limit overvoltage protection and a thermal shutdown for highest reliability under fault conditions.Device Information (1)PART NUMBER PACKAGE BODY SIZE (NOM)TPS65130VQFN (24) 4.00mm ×4.00mm TPS65131VQFN (24)4.00mm ×4.00mm(1)For all available packages,see the orderable addendum atthe end of the data sheet.Typical Application SchematicTPS65130,TPS65131SLVS493D–MARCH2004–REVISED JANUARY2016Typical Application(continued)8.2.1Design RequirementsFigure8uses the following parameters:Table1.Design ParametersDESIGN PARAMETER EXAMPLE VALUEInput voltage range 2.7V to5.5VBoost converter output voltage,V POS R1=1MΩR2=130kΩC9=6.8pF10.5VInverting converter output voltage,V NEGR3=1MΩR4=121.2kΩC10=7.5pF–10VTable2.List of ComponentsREFERENCE SETUP VALUE,DESCRIPTIONC1,C2—4.7µF,ceramic,6.3V,X5RC30.1µF,ceramic,10V,X5RC4,C54x4.7µF,ceramic,25V,X7R C610nF,ceramic,16V,X7RC7 4.7nF,50V,C0GC8220nF,ceramic,6.3V,X5RR1V POS=10.5V1MΩV POS=15V975kΩR2V POS=10.5V130kΩV POS=15V85.8kΩR3V NEG=–10V1MΩV NEG=–15V 1.3MΩR4V NEG=–10V121.2kΩV NEG=–15V104.8kΩR7—100ΩD1,D2Schottky,1A,20V,Onsemi MBRM120L1,L2Wurth Elektronik7447789004(TPS65130), EPCOS B82462-G4472(TPS65131)Q1MOSFET,P-channel,12V,4A,Vishay Si2323DS8.2.2Detailed Design ProcedureThe TPS6513x DC-DC converter is intended for systems typically powered by a single-cell Li-ion or Li-polymer battery with a terminal voltage from2.7V up to4.2V.Because the recommended input voltage goes up to5.5V, the device is also suitable for3-cell alkaline,NiCd,or NiMH batteries,as well as any regulated supply voltages from2.7V to5.5V.It provides two independent output voltage rails which are programmed as follows.8.2.2.1Programming the Output Voltage8.2.2.1.1Boost ConverterThe output voltage of the TPS6513x boost converter stage can be adjusted with an external resistor divider connected to the FBP pin.The typical value of the voltage at the FBP pin is the reference voltage,which is1.213 V.The maximum recommended output voltage at the boost converter is15V.To achieve appropriate accuracy, the current through the feedback divider should be about100times greater than the current into the FBP pin. Typical current into the FBP pin is0.05µA,and the voltage across R2is1.213V.Based on those values,the recommended value for R2should be lower than200kΩto set the divider current at5µA or greater.TPS65130,TPS65131SLVS493D–MARCH2004–REVISED JANUARY2016Product Folder Links:TPS65130TPS65131(ESR N)NEG (ESR C5)V I R 'u (ESR P)POS (ESR C4)V I R 'uNEG NEGNEG NEG I I V C5minf V V V u u 'uPOSPOS I POS POS I V V C4min f V V u u 'u TPS65130,TPS65131SLVS493D –MARCH 2004–REVISED JANUARY 2016Product Folder Links: TPS65130 TPS65131In typical applications,the recommendation is to choose a 4.7-μH inductor.The device is optimized to work with inductance values from 3.3μH to 6.8μH.Nevertheless,operation with greater inductance values may be possible in some applications.Perform detailed stability analysis in this case.Be aware of the possibility that load transients and losses in the circuit can lead to higher currents than estimated in Equation 3and Equation 4.Also,the losses caused by magnetic hysteresis and conductor resistance are a major parameter for total circuit efficiency.Table 3shows inductors from different suppliers used with the TPS6513x converter:Table 3.List of InductorsVENDORINDUCTOR SERIES EPCOS B8246284-G4Wurth Elektronik 7447789XXX 744031XXX TDKVLF3010VLF4012Cooper Electronics TechnologiesSD128.2.2.3Capacitor Selection8.2.2.3.1Input CapacitorAs a recommendation,choose an input capacitors of at least 4.7μF for the input of the boost converter (INP)and accordingly for the input of the inverting converter (INN).This improves transient behavior of the regulators and EMI behavior of the total power-supply circuit.Choose a ceramic capacitor or a tantalum capacitor.For the use of a tantalum capacitor,an additional,smaller ceramic capacitor (100nF)in parallel is required.Place the input capacitor(s)close to the input pins..8.2.2.3.2Output CapacitorsOne of the major parameters necessary to define the capacitance value of the output capacitor is the maximum allowed output voltage ripple of the converter.This ripple is determined by two parameters of the capacitor,the capacitance and the ESR.It is possible to calculate the minimum capacitance needed for the defined ripple,supposing that the ESR is e Equation 7for the boost converter output capacitor (C4min)and Equation 8for the inverting converter output capacitor (C5min).(7)(8)The parameter f is the switching frequency.ΔV POS and ΔV NEG are the maximum allowed ripple voltages for each converter.Choosing a ripple voltage in the range of 10mV requires a minimum capacitance of 12μF.The total ripple is larger due to the ESR of the output e Equation 9for he boost converter and Equation 10for the inverting converter to calculate this additional ripple component.(9)(10)In this example,an additional ripple of 2mV is the result of using a typical ceramic capacitor with an ESR in the 10-m Ωrange.The total ripple is the sum of the ripple caused by the capacitance and the ripple caused by the ESR of the capacitor.In this example,the total ripple is 10mV.Load transients can create additional ripple.When the load current increases rapidly,the output capacitor must provide the additional current until the inductor current increases by the control loop which sets a higher ON-time (duty cycle)of the main switch.The higher duty cycle results in longer inductor charging periods.The inductance itself also limits the rate of increase of the inductor current.When the load current decreases rapidly,the output capacitor must store the excess energy (stored in the inductor)until the regulator has decreased the inductor current by reducing the duty cycle.TI recommends using greater capacitance values,as the foregoing calculations show.7.5 V C10R36.8 V C9R1TPS65130,TPS65131SLVS493D –MARCH 2004–REVISED JANUARY 2016Product Folder Links:TPS65130TPS651318.2.2.4Rectifier Diode SelectionBoth converters (the boost and inverting converter)require rectifier diodes,D1and D2.As a recommendation,to reduce losses,use Schottky diodes.The forward current rating needed is equal to the maximum output current.Consider that the maximum currents,I POS max and I NEG max,might differ for V POS and V NEG when choosing the diodes.8.2.2.5External PMOS SelectionDuring shutdown,when connected to a power supply,a path from the power supply to the positive output conducts through the inductor and an external diode.Optionally,to fully disconnect the positive output V POS during shutdown,add an external PMOS (Q1).The BSW pin controls the gate of the PMOS.When choosing a proper PMOS,the V GS and V GD voltage ratings must cover the input voltage range,the drain current rating must not be lower than the maximum input current flowing into the application,and conditions of the PMOS operating area must fit.If there is no intention to use an external PMOS,leave the BSW pin floating.8.2.2.6Stabilizing the Control Loop8.2.2.6.1Feedforward CapacitorAs a recommendation,to speed up the control loop,place feedforward capacitors in the feedback divider,parallel to R1(boost converter)and R3(inverting converter).Equation 11shows how to calculate the appropriate value for the boost converter,and Equation 12for the inverting converter.(11)(12)To avoid coupling noise into the control loop from the feedforward capacitors,the feedforward effect can bebandwith-limited by adding a series resistor.Any value from 10k Ωto 100k Ωis suitable.The greater the resistance,the lower the noise coupled into the control loop system.8.2.2.6.2Compensation CapacitorsThe device features completely internally compensated control loops for both converters.The internal feedforward system has built-in error correction which requires external capacitors.As a recommendation,use a 10-nF capacitor at the CP pin of the boost converter and a 4.7-nF capacitor at the CN pin of the inverting converter.8.2.3Application Curves。
电源管理芯片TPS65910A3与开关按键控制器STM6601的嵌入式应用
应 用于便携式和手持系统 。
智 能 型开 关按 键控 制 器芯 片 Ｓ Ｔ Ｍ６ ６ ０ １ ， 具备 更 简单 易用 的开机 、 关机 以及 解 冻／ 重 置功 能 ， 可 避免 对终 端 产 品 造 成损
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１ Ｔ Ｐ Ｓ ６ ５ ９ １ ０ Ａ ３电 源 分 配 与 上 电 时 序
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（ Ｈｉ — Ｔａ ｒ ｇ ｅ ｔ Ｓ ｕ ｒ ｖ ｅ ｙ Ｉ ｎ ｓ ｔ ｒ ｕ ｍｅ ｎ ｔ ｓ Ｃ ｏ ｍｐ ａ ｎ ｙ Ｌｔ ｄ ． ，Ｇｕ ａ ｎ ｇ ｚ ｈ ｏ ｕ ５ １ １ ４ ０ ０， Ｃｈ ｉ ｎ ａ ）
Ｓ ＴＭ ６ ６ ０ １ ｉ ｓ ｉ ｎ ｔ ｒ ｏ ｄ ｕ ｃ ｅ ｄ ，ａ ｎ ｄ ａ ｐ ｐ ｌ ｉ ｅ ｄ ｔ ｏ ｔ ｈ ｅ ｅ ｍｂ ｅ ｄ ｄ ｅ ｄ ｓ ｙ ｓ ｔ ｅ ｍ ｔ ａ ｋ ｉ ｎ ｇ ＴＩ ＡＭ ３ ３ ５ ｘ ｐ ｒ ｏ ｃ ｅ ｓ ｓ ｏ ｒ ａ ｓ ｔ ｈ ｅ ｃ ｏ ｒ ｅ ． Ｔｈ ｉ ｓ ｐ ａ ｐ ｅ ｒ ｐ ｒ ｅ ｓ ｅ ｎ ｔ ｓ ｔ ｈ ｅ ｐ ｏ ｗｅ ｒ
一种低功耗频率稳定的CMOS环形振荡器设计
1引言
随着半导体行业发展，CMOS 工艺生产技术提 高，芯片面积越来越小。对芯片内部各模块的低功 耗、高稳定、高精度要求也越来越高[1]。振荡器模块作
. 24.微处理机源自2017 年被广泛应用于工业产品和学术设计中[3]。然而，COMS 环形振荡器在功耗和相位噪声及频率稳定性等方 面，仍需要更加深入的研究[4]。
2 传统环形振荡器介绍
环形振荡器由环路中若干振荡电路单元组成， 每个电路单元由有源器件构成。如果环形振荡器满 足“巴克豪森准则”将发生振荡，产生周期变化的电 压信号[5]。典型结构如图 1 所示。
第5期 2051期7 年 10 月
微处理机 MICROPROCESSORS
. . No. 5
Oct. ，2017
一种低功耗频率稳定的 CMOS 环形振荡器设计
张 可 1，代雪峰 2，张海涛 3
（1. 中国电子科技集团公司第四十七研究所，沈阳 110032；2. 东北大学理学院物理系，沈阳 110004； 3. 中国人民解放军 95979 部队，沈阳 110045）
摘 要：COMS 环形振荡器具有版图面积小，频率调谐范围大、线性度好等优点，可作为系统时钟
的关键部件，广泛应用于电子及通信系统中。对传统的环形振荡器及其频率稳定的改进方式进行介
绍，设计新的延时单元，搭建环形振荡器电路结构，实现了一种频率稳定的 CMOS 环形振荡器。该振
荡器电路结构简单，易于集成。通过 0.25滋m CMOS 工艺仿真对比分析，环形振荡器功耗降低了 40%，
汽车电路板上的TPS65917-Q1电源管理单元(PMU)为处理器1设备概述说明书
ProductFolderSample &BuyTechnical Documents Tools &SoftwareSupport &CommunityTPS65917-Q1SLVSD22–JULY 2015TPS65917-Q1Power Management Unit (PMU)for Processor1Device Overview1.1Features•Qualified for Automotive Applications•Five Low-Dropout (LDO)Linear Regulators:•AEC-Q100Qualified With the Following Results:–0.9-to 3.3-V Output Range in 50-mV steps –Device Temperature Grade 2:–40°C to +105°C –Two With 300-mA Capability and Bypass Mode Ambient Operating Temperature Range –One With 100-mA Capability and Capable of –Device HBM Classification Level 2Low-Noise Performance up to 50mA –Device CDM Classification Level C4B–Two Other LDOs With 200-mA Current Capability•System Voltage Range from 3.135V to 5.25V –Short-Circuit Protection•Low-Power Consumption •12-Bit Sigma-Delta General-Purpose ADC –20μA in Off Mode(GPADC)With 8Input Channels (2external)–90μA in Sleep Mode With Two SMPSs Active •Thermal Monitoring With High Temperature •Five Step-Down Switched-Mode Power Supply Warning and Thermal Shutdown (SMPS)Regulators:•Power Sequence Control:–0.7-to 3.3-V Output Range in 10-or 20-mV –Configurable Power-Up and Power-Down StepsSequences (OTP)–Two SMPS Regulators With 3.5-A Capability,–Configurable Sequences Between the SLEEP With the Ability to Combine into 7-A Output in and ACTIVE State Transition (OTP)Dual-Phase Configuration,With Differential Remote Sensing (Output and Ground)–Three Digital Output Signals that can be Included in the Startup Sequence –Three Other SMPS Regulators with 3-A,2-A,and 1.5-A Capabilities•Selectable Control Interface:–Dynamic Voltage Scaling (DVS)Control and –One SPI for Resource Configurations and DVS Output Current Measurement in 3.5-A and 3-A ControlSMPS Regulators–Two I 2C Interfaces.–Hardware and Software Controlled Eco-mode™•One Dedicated for DVS ControlSupplying up to 5mA •One General Purpose I 2C Interface for –Short-Circuit ProtectionResource Configuration and DVS Control–Power-Good Indication (Voltage and •OTP Bit-Integrity Error Detection With Options to Overcurrent Indication)Proceed or Hold Power-Up Sequence and –Internal Soft-Start for In-Rush Current Limitation RESET_OUT Release –Ability to Synchronize to External Clock between •Package Option:1.7MHz and2.7MHz–7-×7-mm 48-pin VQFN With 0.5-mm Pitch 1.2Applications•Automotive Infotainment •Automotive Advanced Driver Assistance System (ADAS)•Automotive Digital Cluster•Automotive Navigation Systems1.3DescriptionThe TPS65917-Q1device is an integrated PMIC with AEC-Q100qualification.The device provides 5configurable step-down converters with up to 3.5A of output current for memory,processor core,I/O,or preregulation of LDOs.These step-down converters can be synchronized to an external clock between 1.7MHz and 2.7MHz,or an internal fallback clock at 2.2MHz.Two of these configurable step-down converters can be combined together to allow up to 7A of output current.The device also contains 5LDO regulators for external use.These LDOs can be supplied from either the system supply or an external preregulated supply.An IMPORTANT NOTICE at the end of this data sheet addresses availability,warranty,changes,use in safety-critical applications,intellectual property matters and other important disclaimers.PRODUCTION DATA.TPS65917-Q1SLVSD22– The power-up and power-down controller is configurable and can support any power-up and power-down sequences(OTP based).As an additional safety feature,the OTP bit-integrity error-detection feature provides the option to stop the power-up sequence if an error is detected.The TPS65917-Q1device includes an internal32-kHz RC oscillator to sequence all resources during power up and power down.All LDOs and SMPS converters can be controlled by the SPI or I2C interface,or by power request signals.In addition,voltage scaling registers allow transition of the SMPS to different voltages by SPI,I2C,or roof-and-floor control.GPIO functionality is available and3GPIOs can be configured as part of the power-up sequence to control external resources.The fallback clock of the step-down converters can be output through the SYNCCLKOUT pin to provide synchronization clock to external resources.Power request signals enable power mode control for power optimization.The device includes a general-purpose sigma-delta analog-to-digital converter(ADC)with8channels(2with external access).The TPS65917-Q1device is available in a48-pin VQFN package with a0.5-mm pitch.Device Information(1)PART NUMBER PACKAGE BODY SIZE(NOM)TPS65917-Q1VQFN(48)7.00mm×7.00mm(1)For all available packages,see the orderable addendum at the end of the data sheet.2Device Overview Copyright©2015,Texas Instruments IncorporatedSubmit Documentation FeedbackProduct Folder Links:TPS65917-Q1TPS65917-Q1 SLVSD22–JULY20151.4Functional DiagramFigure1-1.Functional DiagramCopyright©2015,Texas Instruments Incorporated Device Overview3Submit Documentation FeedbackProduct Folder Links:TPS65917-Q1TPS65917-Q1SLVSD22– 2Device and Documentation Support2.1Documentation Support2.1.1Related DocumentationFor related documentation see the following:Guide to Using the GPADC in TPS65903x and TPS6591x Devices,SLIA0872.2Community ResourcesThe following links connect to TI community resources.Linked contents are provided"AS IS"by the respective contributors.They do not constitute TI specifications and do not necessarily reflect TI's views;see TI's Terms of Use.TI E2E™Online Community TI's Engineer-to-Engineer(E2E)Community.Created to foster collaboration among engineers.At ,you can ask questions,share knowledge,explore ideas and help solve problems with fellow engineers.Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.2.3TrademarksEco-mode,E2E are trademarks of Texas Instruments.All other trademarks are the property of their respective owners.2.4Electrostatic Discharge CautionThese devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.2.5GlossarySLYZ022—TI Glossary.This glossary lists and explains terms,acronyms,and definitions.3Mechanical,Packaging,and Orderable InformationThe following pages include mechanical,packaging,and orderable information.This information is the most current data available for the designated devices.This data is subject to change without notice and revision of this document.For browser-based versions of this data sheet,refer to the left-hand navigation.4Mechanical,Packaging,and Orderable Information Copyright©2015,Texas Instruments IncorporatedSubmit Documentation FeedbackProduct Folder Links:TPS65917-Q1IMPORTANT NOTICETexas Instruments Incorporated(TI)reserves the right to make corrections,enhancements,improvements and other changes to its semiconductor products and services per JESD46,latest issue,and to discontinue any product or service per JESD48,latest issue.Buyers should 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not responsible or liable for any such statements. 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常用开关电源芯片大全之欧阳美创编
常用开关电源芯片大全第1章DC-DC电源转换器/基准电压源1.1 DC-DC电源转换器1.低噪声电荷泵DC-DC电源转换器AAT3113/AAT31142.低功耗开关型DC-DC电源转换器ADP30003.高效3A开关稳压器AP15014.高效率无电感DC-DC电源转换器FAN56605.小功率极性反转电源转换器ICL76606.高效率DC-DC电源转换控制器IRU30377.高性能降压式DC-DC电源转换器ISL64208.单片降压式开关稳压器L49609.大功率开关稳压器L4970A10.1.5A降压式开关稳压器L497111.2A高效率单片开关稳压器L497812.1A高效率升压/降压式DC-DC电源转换器L597013.1.5A降压式DC-DC电源转换器LM157214.高效率1A降压单片开关稳压器LM1575/LM2575/LM2575HV15.3A降压单片开关稳压器LM2576/LM2576HV16.可调升压开关稳压器LM257717.3A降压开关稳压器LM259618.高效率5A开关稳压器LM267819.升压式DC-DC电源转换器LM2703/LM270420.电流模式升压式电源转换器LM273321.低噪声升压式电源转换器LM275022.小型75V降压式稳压器LM500723.低功耗升/降压式DC-DC电源转换器LT107324.升压式DC-DC电源转换器LT161525.隔离式开关稳压器LT172526.低功耗升压电荷泵LT175127.大电流高频降压式DC-DC电源转换器LT176528.大电流升压转换器LT193529.高效升压式电荷泵LT193730.高压输入降压式电源转换器LT195631.1.5A升压式电源转换器LT196132.高压升/降压式电源转换器LT343333.单片3A升压式DC-DC电源转换器LT343634.通用升压式DC-DC电源转换器LT346035.高效率低功耗升压式电源转换器LT346436.1.1A升压式DC-DC电源转换器LT346737.大电流高效率升压式DC-DC电源转换器LT378238.微型低功耗电源转换器LTC175439.1.5A单片同步降压式稳压器LTC187540.低噪声高效率降压式电荷泵LTC191141.低噪声电荷泵LTC3200/LTC3200-542.无电感的降压式DC-DC电源转换器LTC325143.双输出/低噪声/降压式电荷泵LTC325244.同步整流/升压式DC-DC电源转换器LTC340145.低功耗同步整流升压式DC-DC电源转换器LTC340246.同步整流降压式DC-DC电源转换器LTC340547.双路同步降压式DC-DC电源转换器LTC340748.高效率同步降压式DC-DC电源转换器LTC341649.微型2A升压式DC-DC电源转换器LTC342650.2A两相电流升压式DC-DC电源转换器LTC342851.单电感升/降压式DC-DC电源转换器LTC344052.大电流升/降压式DC-DC电源转换器LTC344253.1.4A同步升压式DC-DC电源转换器LTC345854.直流同步降压式DC-DC电源转换器LTC370355.双输出降压式同步DC-DC电源转换控制器LTC373656.降压式同步DC-DC电源转换控制器LTC377057.双2相DC-DC电源同步控制器LTC380258.高性能升压式DC-DC电源转换器MAX1513/MAX151459.精简型升压式DC-DC电源转换器MAX1522/MAX1523/MAX152460.高效率40V升压式DC-DC电源转换器MAX1553/MAX155461.高效率升压式LED电压调节器MAX1561/MAX159962.高效率5路输出DC-DC电源转换器MAX156563.双输出升压式DC-DC电源转换器MAX1582/MAX1582Y64.驱动白光LED的升压式DC-DC电源转换器MAX158365.高效率升压式DC-DC电源转换器MAX1642/MAX164366.2A降压式开关稳压器MAX164467.高效率升压式DC-DC电源转换器MAX1674/MAX1675/MAX167668.高效率双输出DC-DC电源转换器MAX167769.低噪声1A降压式DC-DC电源转换器MAX1684/MAX168570.高效率升压式DC-DC电源转换器MAX169871.高效率双输出降压式DC-DC电源转换器MAX171572.小体积升压式DC-DC电源转换器MAX1722/MAX1723/MAX172473.输出电流为50mA的降压式电荷泵MAX173074.升/降压式电荷泵MAX175975.高效率多路输出DC-DC电源转换器MAX180076.3A同步整流降压式稳压型MAX1830/MAX183177.双输出开关式LCD电源控制器MAX187878.电流模式升压式DC-DC电源转换器MAX189679.具有复位功能的升压式DC-DC电源转换器MAX194780.高效率PWM降压式稳压器MAX1992/MAX199381.大电流输出升压式DC-DC电源转换器MAX61882.低功耗升压或降压式DC-DC电源转换器MAX62983.PWM升压式DC-DC电源转换器MAX668/MAX66984.大电流PWM降压式开关稳压器MAX724/MAX72685.高效率升压式DC-DC电源转换器MAX756/MAX75786.高效率大电流DC-DC电源转换器MAX761/MAX76287.隔离式DC-DC电源转换器MAX8515/MAX8515A88.高性能24V升压式DC-DC电源转换器MAX872789.升/降压式DC-DC电源转换器MC33063A/MC34063A90.5A升压/降压/反向DC-DC电源转换器MC33167/MC3416791.低噪声无电感电荷泵MCP1252/MCP125392.高频脉宽调制降压稳压器MIC220393.大功率DC-DC升压电源转换器MIC229594.单片微型高压开关稳压器NCP1030/NCP103195.低功耗升压式DC-DC电源转换器NCP1400A96.高压DC-DC电源转换器NCP140397.单片微功率高频升压式DC-DC电源转换器NCP141098.同步整流PFM步进式DC-DC电源转换器NCP142199.高效率大电流开关电压调整器NCP1442/NCP1443/NCP1444/NCP1445100.新型双模式开关稳压器NCP1501101.高效率大电流输出DC-DC电源转换器NCP1550102.同步降压式DC-DC电源转换器NCP1570103.高效率升压式DC-DC电源转换器NCP5008/NCP5009 104.大电流高速稳压器RT9173/RT9173A105.高效率升压式DC-DC电源转换器RT9262/RT9262A 106.升压式DC-DC电源转换器SP6644/SP6645107.低功耗升压式DC-DC电源转换器SP6691108.新型高效率DC-DC电源转换器TPS54350109.无电感降压式电荷泵TPS6050x110.高效率升压式电源转换器TPS6101x111.28V恒流白色LED驱动器TPS61042112.具有LDO输出的升压式DC-DC电源转换器TPS6112x 113.低噪声同步降压式DC-DC电源转换器TPS6200x114.三路高效率大功率DC-DC电源转换器TPS75003115.高效率DC-DC电源转换器UCC39421/UCC39422116.PWM控制升压式DC-DC电源转换器XC6371117.白光LED驱动专用DC-DC电源转换器XC9116118.500mA同步整流降压式DC-DC电源转换器XC9215/XC9216/XC9217119.稳压输出电荷泵XC9801/XC9802120.高效率升压式电源转换器ZXLB16001.2 线性/低压差稳压器121.具有可关断功能的多端稳压器BAXXX122.高压线性稳压器HIP5600123.多路输出稳压器KA7630/KA7631124.三端低压差稳压器LM2937125.可调输出低压差稳压器LM2991126.三端可调稳压器LM117/LM317127.低压降CMOS500mA线性稳压器LP38691/LP38693128.输入电压从12V到450V的可调线性稳压器LR8129.300mA非常低压降稳压器（VLDO）LTC3025130.大电流低压差线性稳压器LX8610131.200mA负输出低压差线性稳压器MAX1735132.150mA低压差线性稳压器MAX8875133.带开关控制的低压差稳压器MC33375134.带有线性调节器的稳压器MC33998135.1.0A低压差固定及可调正稳压器NCP1117136.低静态电流低压差稳压器NCP562/NCP563137.具有使能控制功能的多端稳压器PQxx138.五端可调稳压器SI-3025B/SI-3157B139.400mA低压差线性稳压器SPX2975140.五端线性稳压器STR20xx141.五端线性稳压器STR90xx142.具有复位信号输出的双路输出稳压器TDA8133143.具有复位信号输出的双路输出稳压器TDA8138/TDA8138A144.带线性稳压器的升压式电源转换器TPS6110x145.低功耗50mA低压降线性稳压器TPS760xx146.高输入电压低压差线性稳压器XC6202147.高速低压差线性稳压器XC6204148.高速低压差线性稳压器XC6209F149.双路高速低压差线性稳压器XC64011.3 基准电压源150.新型XFET基准电压源ADR290/ADR291/ADR292/ADR293 151.低功耗低压差大输出电流基准电压源MAX610x152.低功耗1.2V基准电压源MAX6120153.2.5V精密基准电压源MC1403154.2.5V/4.096V基准电压源MCP1525/MCP1541155.低功耗精密低压降基准电压源REF30xx/REF31xx156.精密基准电压源TL431/KA431/TLV431A第2章AC-DC转换器及控制器1.厚膜开关电源控制器DP104C2.厚膜开关电源控制器DP308P3.DPA-Switch系列高电压功率转换控制器DPA423/DPA424/DPA425/DPA4264.电流型开关电源控制器FA13842/FA13843/FA13844/FA138455.开关电源控制器FA5310/FA53116.PWM开关电源控制器FAN75567.绿色环保的PWM开关电源控制器FAN76018.FPS型开关电源控制器FS6M07652R9.开关电源功率转换器FS6Sxx10.降压型单片AC-DC转换器HV-2405E11.新型反激准谐振变换控制器ICE1QS0112.PWM电源功率转换器KA1M088013.开关电源功率转换器KA2S0680/KA2S088014.电流型开关电源控制器KA38xx15.FPS型开关电源功率转换器KA5H0165R16.FPS型开关电源功率转换器KA5Qxx17.FPS型开关电源功率转换器KA5Sxx18.电流型高速PWM控制器L499019.具有待机功能的PWM初级控制器L599120.低功耗离线式开关电源控制器L659021.LINK SWITCH TN系列电源功率转换器LNK304/LNK305/LNK30622.LINK SWITCH系列电源功率转换器LNK500/LNK501/LNK52023.离线式开关电源控制器M51995A24.PWM电源控制器M62281P/M62281FP25.高频率电流模式PWM控制器MAX5021/MAX502226.新型PWM开关电源控制器MC4460427.电流模式开关电源控制器MC4460528.低功耗开关电源控制器MC4460829.具有PFC功能的PWM电源控制器ML482430.液晶显示器背光灯电源控制器ML487631.离线式电流模式控制器NCP120032.电流模式脉宽调制控制器NCP120533.准谐振式PWM控制器NCP120734.低成本离线式开关电源控制电路NCP121535.低待机能耗开关电源PWM控制器NCP123036.STR系列自动电压切换控制开关STR8xxxx37.大功率厚膜开关电源功率转换器STR-F665438.大功率厚膜开关电源功率转换器STR-G865639.开关电源功率转换器STR-M6511/STR-M652940.离线式开关电源功率转换器STR-S5703/STR-S5707/STR-S570841.离线式开关电源功率转换器STR-S6401/STR-S6401F/STR-S6411/STR-S6411F 442.开关电源功率转换器STR-S651343.离线式开关电源功率转换器TC33369～TC3337444.高性能PFC与PWM组合控制集成电路TDA16846/TDA1684745.新型开关电源控制器TDA1685046.“绿色”电源控制器TEA150447.第二代“绿色”电源控制器TEA150748.新型低功耗“绿色”电源控制器TEA153349.开关电源控制器TL494/KA7500/MB375950.Tiny SwitchⅠ系列功率转换器TNY253、TNY254、TNY25551.Tiny SwitchⅡ系列功率转换器TNY264P～TNY268G52.TOP Switch（Ⅱ）系列离线式功率转换器TOP209～TOP22753.TOP Switch-FX系列功率转换器TOP232/TOP233/TOP23454.TOP Switch-GX系列功率转换器TOP242～TOP25055.开关电源控制器UCX84X56.离线式开关电源功率转换器VIPer12AS/VIPer12ADIP57.新一代高度集成离线式开关电源功率转换器VIPer53第3章功率因数校正控制/节能灯电源控制器1.电子镇流器专用驱动电路BL83012.零电压开关功率因数控制器FAN48223.功率因数校正控制器FAN75274.高电压型EL背光驱动器HV8265.EL场致发光背光驱动器IMP525/IMP5606.高电压型EL背光驱动器/反相器IMP8037.电子镇流器自振荡半桥驱动器IR21568.单片荧光灯镇流器IR21579.调光电子镇流器自振荡半桥驱动器IR215910.卤素灯电子变压器智能控制电路IR216111.具有功率因数校正电路的镇流器电路IR216612.单片荧光灯镇流器IR216713.自适应电子镇流器控制器IR252014.电子镇流器专用控制器KA754115.功率因数校正控制器L656116.过渡模式功率因数校正控制器L656217.集成背景光控制器MAX8709/MAX8709A18.功率因数校正控制器MC33262/MC3426219.固定频率电流模式功率因数校正控制器NCP165320.EL场致发光灯高压驱动器SP440321.功率因数校正控制器TDA4862/TDA486322.有源功率因数校正控制器UC385423.高频自振荡节能灯驱动器电路VK05CFL24.大功率高频自振荡节能灯驱动器电路VK06TL第4章充电控制器1.多功能锂电池线性充电控制器AAT36802.可编程快速电池充电控制器BQ20003.可进行充电速率补偿的锂电池充电管理器BQ20574.锂电池充电管理电路BQ2400x5.单片锂电池线性充电控制器BQ2401xB接口单节锂电池充电控制器BQ2402x7.2A同步开关模式锂电池充电控制器BQ241008.集成PWM开关控制器的快速充电管理器BQ29549.具有电池电量计量功能的充电控制器DS277010.锂电池充电控制器FAN7563/FAN756411.2A线性锂/锂聚合物电池充电控制器ISL629212.锂电池充电控制器LA5621M/LA5621V13.1.5A通用充电控制器LT157114.2A恒流/恒压电池充电控制器LT176915.线性锂电池充电控制器LTC173216.带热调节功能的1A线性锂电池充电控制器LTC173317.线性锂电池充电控制器LTC173418.新型开关电源充电控制器LTC198019.开关模式锂电池充电控制器LTC400220.4A锂电池充电器LTC400621.多用途恒压/恒流充电控制器LTC400822.4.2V锂离子/锂聚合物电池充电控制器LTC405223.可由USB端口供电的锂电池充电控制器LTC405324.小型150mA锂电池充电控制器LTC405425.线性锂电池充电控制器LTC405826.单节锂电池线性充电控制器LTC405927.独立线性锂电池充电控制器LTC406128.镍镉/镍氢电池充电控制器M62256FP29.大电流锂/镍镉/镍氢电池充电控制器MAX150130.锂电池线性充电控制器MAX150731.双输入单节锂电池充电控制器MAX1551/MAX155532.单节锂电池充电控制器MAX167933.小体积锂电池充电控制器MAX1736B接口单节锂电池充电控制器MAX181135.多节锂电池充电控制器MAX187336.双路输入锂电池充电控制器MAX187437.单节锂电池线性充电控制器MAX189838.低成本/多种电池充电控制器MAX190839.开关模式单节锂电池充电控制器MAX1925/MAX192640.快速镍镉/镍氢充电控制器MAX2003A/MAX200341.可编程快速充电控制器MAX712/MAX71342.开关式锂电池充电控制器MAX74543.多功能低成本充电控制器MAX846A44.具有温度调节功能的单节锂电池充电控制器MAX8600/MAX860145.锂电池充电控制器MCP73826/MCP73827/MCP7382846.高精度恒压/恒流充电器控制器MCP73841/MCP73842/MCP73843/MCP73844 647.锂电池充电控制器MCP73861/MCP7386248.单节锂电池充电控制器MIC7905049.单节锂电池充电控制器NCP180050.高精度线性锂电池充电控制器VM7205。
NI PXIe-6592R高速序列模块安装指南说明书
GETTING STARTED GUIDENI PXIe-6592RHigh Speed Serial ModuleThis document explains how to install your NI PXIe-6592R (NI 6592R) high-speed serial module.The NI 6592R provides access to FPGA multi-gigabit transceivers (MGTs) via Component Level IP (CLIP) for use in the following applications:•Functional test for semiconductor production•Protocol functional test•Device interfacing•High performance embedded systemsFor more information about features and programming, refer to the NI High-Speed Serial Instruments User Manual. For device specifications, refer to the specifications document for your device. To access these documents, select Start»All Programs»National Instruments»High Speed Serial Instruments»High Speed Serial Instruments Documentation.For the most current versions of documentation, visit /manuals. For the latest version of the NI LabVIEW Instrument Design Libraries for High Speed Serial Instruments driver, visit /downloads.Caution The protection provided by this product may be impaired if it is used in amanner not described in this document.ContentsElectromagnetic Compatibility Guidelines (2)How to Use Your Documentation Set (2)Device Front Panels (3)Verifying the System Requirements (4)NI 6592R Kit Contents (4)Preparing the Environment (4)Unpacking the Kit (5)Installing the Software (5)Installing the NI 6592R Module (6)Configuring the NI 6592R in MAX (6)Accessing Sample Projects (7)Troubleshooting (7)What Should I Do if the NI 6592R Doesn't Appear in MAX? (7)Where to Go Next (8)Worldwide Support and Services..............................................................................................8Electromagnetic Compatibility GuidelinesThis product was tested and complies with the regulatory requirements and limits forelectromagnetic compatibility (EMC) stated in the product specifications. These requirements and limits provide reasonable protection against harmful interference when the product is operated in the intended operational electromagnetic environment.This product is intended for use in industrial locations. However, harmful interference may occur in some installations, when the product is connected to a peripheral device or test object,or if the product is used in residential or commercial areas. To minimize interference with radio and television reception and prevent unacceptable performance degradation, install and use this product in strict accordance with the instructions in the product documentation.Furthermore, any changes or modifications to the product not expressly approved by NationalInstruments could void your authority to operate it under your local regulatory rules.Caution To ensure the specified EMC performance, operate this product only withshielded cables and accessories.Caution To ensure the specified EMC performance, the length of all I/O cablesmust be no longer than 3 m (10 ft).Caution To ensure the specified EMC performance, you must install PXI EMCFiller Panels, National Instruments part number 778700-01, in all open chassis slots.A kit of six single slot EMC Filler Panels can be ordered directly from NI by visiting /info and entering partnumber .How to Use Y our Documentation SetRefer to the following table to learn how to use your documentation set.Table 1. NI 6592R Document Locations and Descriptions2 | | NI PXIe-6592R Getting Started GuideTable 1. NI 6592R Document Locations and Descriptions (Continued)Device Front PanelsThe following figure shows the available signals on the NI 6592R.Figure 1. NI 6592R Front Panel and Connector PinoutsNI PXIe-6592R Getting Started Guide| © National Instruments| 3Verifying the System RequirementsTo use the NI LabVIEW Instrument Design Libraries for High Speed Serial Instruments instrument driver, your system must meet certain requirements.For more information about minimum system requirements, recommended system, and supported application development environments (ADEs), refer to the product readme, which is available on the driver software media or online at /updates.NI 6592R Kit ContentsThe following items are included in the device kit:•The NI 6592R•The NI LabVIEW Instrument Design Libraries for High Speed Serial Instruments driver software media•Other included items:–Read Me First: Safety and Electromagnetic Compatibility–Maintain Forced-Air Cooling Note to UsersPreparing the EnvironmentEnsure that the environment you are using the NI 6592R in meets the following specifications.0 °C to 45 °C ............................................................................Operating ambient temperature(IEC-60068-2-1, IEC-60068-2-2) ............................................................................10% to 90%, noncondensingOperating relative humidity(IEC-60068-2-56)Maximum altitude2,000 m (800 mbar) ............................................................................(at 25 °C ambient temperature)Pollution degree2 ............................................................................Indoor use only.Caution Clean the hardware with a soft, nonmetallic brush. Make sure that thehardware is completely dry and free from contaminants before returning it toservice.Note Refer to the NI PXIe-6592R Specifications at /manuals for completespecifications.4| | NI PXIe-6592R Getting Started GuideUnpacking the KitCaution To prevent electrostatic discharge (ESD) from damaging the device,ground yourself using a grounding strap or by holding a grounded object, such asyour computer chassis.1.Touch the antistatic package to a metal part of the computer chassis.2.Remove the device from the package and inspect the device for loose components or anyother sign of damage.Caution Never touch the exposed pins of connectors.Notify NI if the device appears damaged in any way. Do not install a damaged device. 3.Unpack any other items and documentation from the kit.Store the device in the antistatic package when the device is not in use.Installing the SoftwareYou must install the NI LabVIEW Instrument Design Libraries for High Speed Serial Instruments driver software before installing the NI 6592R.1.Install LabVIEW. Refer to the LabVIEW Installation Guide for installation instructionsfor LabVIEW and system requirements for the LabVIEW software. Refer to theLabVIEW Upgrade Notes for additional information about upgrading to the most recent version of LabVIEW for Windows.Documentation for LabVIEW is available at /manuals and by selecting Start»All Programs»National Instruments»LabVIEW»LabVIEW Manuals.2.Install the LabVIEW FPGA Module. Refer to the LabVIEW FPGA Module Release andUpgrade Notes for installation instructions and information about getting started with the LabVIEW FPGA Module.Documentation for the LabVIEW FPGA Module is available is available at /manuals and by selecting Start»All Programs»National Instruments»LabVIEW»LabVIEW Manuals.3.Install the NI LabVIEW Instrument Design Libraries for High Speed Serial InstrumentsHelp driver. Refer to the NI High Speed Serial Instruments Readme on the NI LabVIEW Instrument Design Libraries for High Speed Serial Instruments installation media forsystem requirements and installation instructions for the NI LabVIEW Instrument Design Libraries for High Speed Serial Instruments driver.Documentation for the NI LabVIEW Instrument Design Libraries for High Speed Serial Instruments driver is available at /manuals and by selecting Start»All Programs»National Instruments»High Speed Serial Instruments»High Speed SerialInstruments Documentation.NI PXIe-6592R Getting Started Guide| © National Instruments| 5Installing the NI 6592R ModuleNote You must install the software before you install the hardware.1.Power off and unplug the chassis. Refer to your chassis manual to install or configure thechassis.2.Identify a supported module slot in the chassis. The figure below shows the symbols thatindicate the slot types in the chassis.Figure 2. Symbols for Module Slots1.PXI Express System Controller Slot2.PXI Peripheral Slot3.PXI Express Hybrid Peripheral Slot4.PXI Express System Timing Slot5.PXI Express Peripheral SlotPXI Express devices can be placed only in PXI Express slots and PXIe Express Hybrid slots. Refer to the chassis documentation for details.3.Remove the filler panel of an unused module slot.4.Touch any metal part of the chassis to discharge any static electricity. Place the moduleedges into the module guides at the top and bottom of the chassis, and slide the module into the chassis until the module is fully inserted.5.Secure the device front panel to the chassis front panel mounting rail using the front panelmounting screws.6.Plug in and power on the chassis.Configuring the NI 6592R in MAXUse Measurement & Automation Explorer (MAX) to configure your National Instruments hardware. MAX informs other programs about which devices reside in the system and how they are configured. MAX is automatically installed with NI LabVIEW Instrument Design Libraries for High Speed Serial Instruments.unch MAX by navigating to Start»All Programs»National Instruments»NI MAX orby clicking the NI MAX desktop icon.2.In the Configuration pane, double-click Devices and Interfaces to see the list of installeddevices. Installed devices appear under the name of their associated chassis.6| | NI PXIe-6592R Getting Started Guide3.Expand your Chassis tree item. MAX lists all devices installed in the chassis. Yourdefault device names may vary.Note If you do not see your device listed, press <F5> to refresh the list ofinstalled devices. If the device is still not listed, power off the system, ensurethe device is correctly installed, and restart.4.Record the device identifier MAX assigns to the hardware. Use this identifier whenprogramming the NI 6592R.5.Close MAX.Accessing Sample ProjectsNI LabVIEW Instrument Design Libraries for High Speed Serial Instruments includes sample projects to help you get started designing for the NI 6592R.1.Open LabVIEW and select Create Project.2.In the Create Project dialog box, select High-Speed Serial and select a sample projectfor your device.3.Click Next.4.Configure the Project Name, Project Root, and File Name Prefix (Optional) fields.5.Click Finish.TroubleshootingWhat Should I Do if the NI 6592R Doesn't Appear in MAX?1.In the MAX configuration tree, click Devices and Interfaces.2.Expand the Chassis tree to see the list of installed devices, and press <F5> to refresh thelist.3.If the module is still not listed, power off the system, ensure that all hardware is correctlyinstalled, and restart the system.4.Navigate to the Device Manager.5.If you are using a PXI controller, verify that a National Instruments entry appears in thesystem device list. Reinstall NI LabVIEW Instrument Design Libraries for High Speed Serial Instruments and the device if error conditions appear in the list. If you are using an MXI controller, right-click PCI-to-PCI Bridge, and select Properties from the shortcut menu to verify that the bridge is enabled.NI PXIe-6592R Getting Started Guide| © National Instruments| 7Where to Go NextRefer to the following figure for information about other product tasks and associated resources for those tasks.Worldwide Support and ServicesThe National Instruments website is your complete resource for technical support. At / support, you have access to everything from troubleshooting and application development self-help resources to email and phone assistance from NI Application Engineers.Visit /services for NI Factory Installation Services, repairs, extended warranty, and other services.Visit /register to register your National Instruments product. Product registration facilitates technical support and ensures that you receive important information updates from NI.8| | NI PXIe-6592R Getting Started GuideA Declaration of Conformity (DoC) is our claim of compliance with the Council of the European Communities using the manufacturer’s declaration of conformity. This system affords the user protection for electromagnetic compatibility (EMC) and product safety. You can obtain the DoC for your product by visiting /certification. If your product supports calibration, you can obtain the calibration certificate for your product at /calibration. National Instruments corporate headquarters is located at 11500 North Mopac Expressway, Austin, Texas, 78759-3504. National Instruments also has offices located around the world. For telephone support in the United States, create your service request at /support or dial 1 866 ASK MYNI (275 6964). For telephone support outside the United States, visit the Worldwide Offices section of /niglobal to access the branch office websites, which provide up-to-date contact information, support phone numbers, email addresses, and current events.NI PXIe-6592R Getting Started Guide| © National Instruments| 9Refer to the NI Trademarks and Logo Guidelines at /trademarks for information on National Instruments trademarks. Other product and company names mentioned herein are trademarks or trade names of their respective companies. For patents covering National Instruments products/technology, refer to the appropriate location: Help»Patents in your software, the patents.txt file on your media, or the National Instruments Patent Notice at /patents. Y ou can find information about end-user license agreements (EULAs) and third-party legal notices in the readme file for your NI product. Refer to the ExportCompliance Information at /legal/export-compliance for the National Instruments global trade compliance policy and how to obtain relevant HTS codes, ECCNs, and other import/export data. NI MAKES NO EXPRESS OR IMPLIED WARRANTIES AS TO THE ACCURACY OF THE INFORMA TION CONT AINED HEREIN AND SHALL NOT BE LIABLE FOR ANY ERRORS. U.S. Government Customers: The data contained in this manual was developed at private expense and is subject to the applicable limited rights and restricted data rights as set forth in FAR 52.227-14, DFAR 252.227-7014, and DFAR 252.227-7015.© 2014—2015 National Instruments. All rights reserved.374805B-01Jan15。
五舟系列产品
五舟系列产品1U机架服务器1103 SAS五舟1103/SAS服务器采用英特尔最新的64位高性能处理器，带4M全速二级缓存，在处理器性能上有一个大的飞跃；采用了最新的SAS硬盘传输技术，传输速率达到3.0G/S，支持RAID0、1级别1103 SATA五舟1103/SATA服务器采用英特尔最新的64位高性能处理器，带4M全速二级缓存，在处理器性能上有一个大的飞跃；采用了最新的S-ATA硬盘传输技术，支持RAID0、1级别，可极大提升数据处理性3160是一款经典的入门级应用机型，也是五舟在该行业应用领域推出的终极机型。
采用当今最先进的英特尔Core2双核处理器，是WEB、EMAIL、VPS、中小网站服务器、视频前端应用、网络游戏的首选5103 SAS支持双路处理器，采用当今最先进的Intel 双核Dempsey和Woodcrest、以及Clovertown四核处理器，Intel S5000服务器芯片组，双独立总路线提供1333MHz FSB，系统带宽可达21GB/S；超大容量的高5103 SAS热插拔五舟5103/SAS服务器是五舟5000系列服务器产品中，支持英特尔双核/四核至强处理器的一款主力热销产品，有热插拔和非热插拔两款机型。
五舟5103/SAS 服务器支持英特尔最新的45nm双核52005103 SATA五舟5103/SATA服务器是五舟5000系列服务器产品中，支持英特尔双核/四核至强处理器的一款主力热销产品，有热插拔和非热插拔两款机型。
五舟5103/SATA 服务器支持英特尔最新的45nm双核5205103 SATA 热插拔五舟5103/SATA服务器是五舟5000系列服务器产品中，支持英特尔双核/四核至强处理器的一款主力热销产品，有热插拔和非热插拔两款机型。
五舟5103/SATA 服务器支持英特尔最新的45nm双核520.5103D2双子星五舟5103D2双子星支持一机双板，在1U的空间里集合两块双路主板，最大可提供4颗4核处理器，拥有无与伦比的处理能力与空间优势，是IDC、互联网空间应用的理想选择。
TPS659113 Centaurus 用户手册说明书
User's GuideSWCU083A–August2011–Revised November2014 TPS659113Centaurus User GuideThis user's guide can be used as a reference for integrating the TPS659113power-management integrated circuit(PMIC)into a system using the TI processors DM812x/813x/814x,AM387x,C6A814x, TNETV813x/814x,DRA64x/65x,and TDA1Mx.Contents1Introduction (1)2Platform Connection (2)3Power-Up Sequencing (4)4Getting Started With the TPS659113 (8)List of Figures1Processor Connection With TPS659113 (2)2Example Power Solution With TPS659113 (3)3Power-Up Sequence Timing Diagram (5)List of Tables1EEPROM Power-Up Sequence of TPS659113 (4)2EEPROM Configuration for TPS659113 (5)1IntroductionThis user's guide can be used as a reference for connectivity between the TPS659113PMIC and the TI processors DM812x/813x/814x,AM387x,C6A814x,TNETV813x/814x,DRA64x/65x,and TDA1Mx.The TPS659113EEPROM bit configuration and power-up sequence is also described.This user's guide does not provide details about the power resources or the functionality of the device.For such information,refer to the full specification document,TPS659110,TPS659112,TPS659113Integrated Power Management Unit Top Specification.1 SWCU083A–August2011–Revised November2014TPS659113Centaurus User Guide Submit Documentation FeedbackPlatform Connection 2Platform ConnectionFigure1shows the detailed connections between the processor and the TPS659113.Figure2shows a high-level view of an example multicell system power solution proposal using the TPS659113for theprocessor.SWCU083-001Figure1.Processor Connection With TPS6591132TPS659113Centaurus User Guide SWCU083A–August2011–Revised November2014Submit Documentation Feedback Platform ConnectionFigure2.Example Power Solution With TPS659113Notes for the connection diagram and operation defined by the TPS659113EEPROM:•The TPS659113transitions from NO SUPPLY to OFF to ACTIVE states when a supply is inserted into VCC7(VMBHI_IT_MSK=0in EEPROM).•The VMBCH threshold of the TPS659113is programmed as3.1V so VCCS must be greater than3.1 V for an OFF-to-ACTIVE transition•The voltage level of the main control signals(I2C,INT2,NRESPWRON,EN1,and EN2)is defined by the VDDIO connection.•When EN1/EN2is used as a dedicated I2C for voltage scaling,pullup resistors similar to main I2C are needed.•Depending on the application and consequently the load current and level needed for power optimization,VDD2of the TPS659113can be used as supply for HDVICP or an optional discrete DC-DC can be added to system.The TPS659113power-up sequence supports an enable signal,GPIO6,for the discrete device.•The PWRHOLD pin is programmed as a GPI in the TPS659113.•The internal RC oscillator is used for boot.After boot,software can switch to using a crystal oscillator if it has been connected.•If backup battery is not used,VBACKUP should be connected to VCC7.•GPIO0is a push-pull output at the VCC7level.•GPIO2,GPIO6,and GPIO7are open drain-outputs and need an external pullup.These GPIOs can actively pull down after4ms from the time the VCC7supply is valid.3 SWCU083A–August2011–Revised November2014TPS659113Centaurus User Guide Submit Documentation FeedbackPower-Up Sequencing 3Power-Up Sequencing3.1Power-Up Sequence for ProcessorThe DM814x requirement for the power-up sequence is:1.8V→memory1.5V/1.8V→3.3V→1.2VNOTE:The power-up sequence definition was optimized in March2011.Some early samples of theTPS659113have a different power-up sequence.NOTE:Due to updated sequencing requirement from processorWhen using the TPS659113:•Connect GPIO0to the3.3V power supply enable•Connect GPIO7to the DDR power supply enableWhen using the TPS6591133which has a new power sequence:•Connect GPIO0to the DDR power supply enable•Connect GPIO7to the3.3V power supply enable3.2TPS659113EEPROM Power-Up SequenceWhen the BOOT pin is set high,the TPS659113powers up with the sequence required by the processor, see Table1.The correct power-up sequence is configured in the EEPROM(factory programmable only).Apart from the main power rails required for the processor,several LDO rails are also powered up at initial power up to support system peripherals.Table1lists the power-up sequence for TPS659113.Figure3shows the power-up sequence timing.Table1.EEPROM Power-Up Sequence of TPS659113TPS659113Power Rail TPS659113Sequence NumberSupply insertion to VCC7,VCCS(1)–VIO2LDO83LDO2,LDO44LDO15LDO3,LDO66GPIO2,GPIO77LDO5,LDO78GPIO09VDDCtrl10VDD1,CLK32KOUT11VDD2,GPIO612NRESPWRON14(1)Supply insertion is the start on event.4TPS659113Centaurus User Guide SWCU083A–August2011–Revised November2014Submit Documentation FeedbackSWCU083-003Figure3.Power-Up Sequence Timing DiagramTable2lists the EEPROM values for the TPS659113.Table2.EEPROM Configuration for TPS659113Register Bit Description Option Selected VDD1_OP_REG/SEL VDD1voltage level selection for boot. 1.2VVDD1_SR_REGVDD1_REG VGAIN_SEL VDD1gain selection,x1or x2x1EEPROM VDD1time slot selection11DCDCCTRL_REG VDD1_PSKIP VDD1pulse skip mode enable Skip enabledVDD2_OP_REG/SEL VDD2voltage level selection for boot 1.2VVDD2_SR_REGVDD2_REG VGAIN_SEL VDD2gain selection,x1or x3x1EEPROM VDD2time slot selection12DCDCCTRL_REG VDD2_PSKIP VDD2pulse skip mode enable Skip enabledVIO_REG SEL[3:9]VIO voltage selection 1.8VEEPROM VIO time slot selection2DCDCCTRL_REG VIO_PSKIP VIO pulse skip mode enable Skip enabledVDDCtrl_OP_REG/SEL VDDCtrl voltage level selection for boot 1.2VVDDCtrl_SR_REGEEPROM VDDCtrl time slot10LDO1_REG SEL[7:2]LDO1voltage selection 1.8VEEPROM LDO1time slot5LDO2_REG SEL[7:2]LDO2voltage selection 1.8VEEPROM LDO2time slot4LDO3_REG SEL[6:2]LDO3voltage selection 3.3V5 SWCU083A–August2011–Revised November2014TPS659113Centaurus User Guide Submit Documentation FeedbackPower-Up Sequencing Table2.EEPROM Configuration for TPS659113(continued)Register Bit Description Option Selected EEPROM LDO3time slot6LDO4_REG SEL[7:2]LDO4voltage selection 1.8VEEPROM LDO4time slot4LDO5_REG SEL[6:2]LDO5voltage selection 3.3VEEPROM LDO5time slot8LDO6_REG SEL[6:2]LDO6voltage selection 3.3VEEPROM LDO6time slot6LDO7_REG SEL[6:2]LDO7voltage selection 3.3VEEPROM LDO7time slot8LDO8_REG SEL[6:2]LDO8voltage selection 1.8VEEPROM LDO8time slot3CLK32KOUT pin CLK32KOUT time slot11NRESPWRON,NRESPWRON2NRESPWRON time slot14pinGPIO0pin GPIO0time slot9GPIO2pin GPIO2time slot7GPIO6pin GPIO6time slot12GPIO7pin GPIO7time slot7VRTC_REG VRTC_OFFMASK0=VRTC LDO will be in low-power mode Low-power modeduring OFF state.1=VRC LDO will be in full-power modeduring OFF state.DEVCTRL_REG CK32K_CTRL0=Clock source is crystal/external clock.RC1=Clock source is internal RC oscillator.DEVCTRL_REG DEV_ON0=No impact01=Will maintain device on,in ACTIVE orSLEEP stateDEVCTRL2_REG TSLOT_LENGTH Boot sequence time slot duration:2ms0=0.5ms1=2msDEVCTRL2_REG PWON_LP_OFF0=Turn-off after PWRON long press not1allowed.1=Turn-off after PWRON long press.DEVCTRL2_REG PWON_LP_RST0=No impact01=Reset digital core when device is OFF.DEVCTRL2_REG IT_POL0=INT1signal will be active low.Active low1=INT1signal will be active high.INT_MSK_REG VMBHI_IT_MSK0=Device automatically switches on at NO0=Automatic switch-SUPPLY-to-OFF or BACKUP-to-OFF on from supplytransition.insertion1=Start-up is reason required before switch-on.INT_MSK3_REG GPIO5_F_IT_MSK0=GPIO5falling edge detection interrupt not Maskedmasked.1=GPIO5falling edge detection interruptmasked.INT_MSK3_REG GPIO5_R_IT_MSK0=GPIO5rising edge detection interrupt not Maskedmasked.1=GPIO5rising edge detection interruptmasked.INT_MSK3_REG GPIO4_F_IT_MSK0=GPIO4falling edge detection interrupt not Maskedmasked.1=GPIO4falling edge detection interruptmasked.6TPS659113Centaurus User Guide SWCU083A–August2011–Revised November2014Submit Documentation Feedback Power-Up Sequencing Table2.EEPROM Configuration for TPS659113(continued)Register Bit Description Option Selected INT_MSK3_REG GPIO4_R_IT_MSK0=GPIO4rising edge detection interrupt not Maskedmasked.1=GPIO4rising edge detection interruptmasked.GPIO0_REG GPIO_ODEN0=GPIO0configured as push-pull output.Push-pull1=GPIO0configured as open-drain output.WATCHDOG_REG WATCHDOG_EN0=Watchdog disabled Disabled1=Watchdog enabled,periodic operation with100sVMBCH_REG VMBBUF_BYPASS0=Enable input buffer for external resistive Enable bufferdivider.1=In single-cell system,disable buffer forlower power consumption.VMBCH_REG VMBCH_SEL[5:1]Select threshold for boot gating comparator 3.1VCOMP1,2.5–3.5V.EEPROM AUTODEV_ON0=PWRHOLD pin is used as PWRHOLD PWRHOLD pin is GPIfeature.1=PWRHOLD pin is GPI.After power-on,DEV_ON is set high internally,no processoraction needed to maintain supplies.EEPROM PWRDN_POL0=PWRDN signal is active low.Active high1=PWRDN signal is active high.7 SWCU083A–August2011–Revised November2014TPS659113Centaurus User Guide Submit Documentation FeedbackGetting Started With the 4Getting Started With the TPS6591134.1First Initialization4.1.1Power-Down Sequence ConfigurationTo meet processor power-down sequence requirements,select the reverse sequence by setting thePWR_OFF_SEQ bit to1in the DEVCTRL_REG register.4.1.2I/O Polarity/Muxing ConfigurationVoltage scaling for VDD1,VDD2,and VDDCtrl can be done either through the main I2C interface orthrough dedicated interface EN1/EN2.Refer to the processor documentation for information on which one is supported.To enable the dedicated voltage scaling interface,set the SR_CTL_I2C_SEL bit to0inDEVCTRL_REG register.If sleep mode is supported,program the SLEEPSIG_POL bit in the DEVCTRL2_REG register according to the GPIO from the processor.This can be set to active-low or active-high for SLEEP transitions.Software can configure specific power resources to enter the LOW-POWER or OFF state in sleep mode.In the DEVCTRL_REG register,set the DEV_SLP bit to1to allow the SLEEP transition when requested through the SLEEP pin.Update the GPIOx configuration(GPIOx_REG)based on your needs.4.1.3Define Wake Up/Interrupt Event(SLEEP or OFF)Select the appropriate bits in the INT_MSK_REG,INT_MSK2_REG,and INT_MSK3_REG registers to enable an interrupt to the processor on the INT1line.4.1.4Backup Battery ConfigurationIf the system has a backup battery,set the BBCHEN bit to1in the BBCH_REG register to enable backup battery charging.The maximum voltage can be set based on backup battery specifications by using the BBSEL bits in the BBCH_REG register.4.1.5DC-DC Maximum Current CapabilityIn VIO_REG,VDD1_REG,and VDD2_REG registers,set ILMAX according to required maximum current.4.1.6Sleep Platform ConfigurationConfigure the state of the LDOs when the SLEEP signal is used.By default,in sleep mode all resources maintain their output voltage and load capability but response to transients(load change)is reduced.Resources that must provide full load capability must be set in the SLEEP_KEEP_LDO_ON_REG and SLEEP_KEEP_RES_ON_REG registers.Resources that can be set off in the SLEEP state to optimize power consumption must be set in theSLEEP_SET_LDO_OFF_REG and SLEEP_SET_RES_OFF_REG registers.4.2Event Management Through Interrupts4.2.1INT_STS_REG.VMBHI_ITINT_STS_REG.VMBHI_IT indicates that a supply has been connected(PMIC leaving the BACKUP or NO SUPPLY state)and the system must be initialized(see Section4.1,First Initialization).8TPS659113Centaurus User Guide SWCU083A–August2011–Revised November2014Submit Documentation Feedback Getting Started With the TPS659113 4.2.2INT_STS_REG.PWRON_ITINT_STS_REG.PWRON_IT is triggered by pressing the PWRON button.If the device is in the OFF orSLEEP state,then this acts as a wake-up event and resources are reinitialized.4.2.3INT_STS_REG.PWRON_LP_ITINT_STS_REG.PWRON_LP_IT is the PWRON long-press interrupt.This interrupt is generated when the PWRON button is pressed for4seconds.The application processor can make a decision to acknowledge the interrupt.If this interrupt is not acknowledged in the next1second,the device interprets this as apower-down event.4.2.4INT_STS_REG.HOTDIE_ITINT_STS_REG.HOTDIE_IT indicates that the temperature of the die is reaching the limit.The software must take action to decrease the power consumption before automatic shutdown.4.2.5INT_STS_REG.PWRHOLD_R/F_ITINT_STS_REG.PWRHOLD_R/F_IT indicates a GPI interrupt event.4.2.6INT_STS_REG.RTC_ALARM_ITINT_STS_REG.RTC_ALARM_IT is triggered when the RTC alarm set time is reached.4.2.7INT_STS2(3)_REG.GPIO_R/F_ITINT_STS2_REG.GPIO_R/F_IT indicates a GPIO interrupt event.It can be used to wake up the device from the SLEEP state.This can be an interrupt coming from any peripheral device or alike.4.2.8INT_STS_REG3.PWRDN_ITINT_STS_REG.PWRDN_IT is triggered when PWRDN reset is detected.4.2.9INT_STS_REG3.VMBCH2_H/L_ITINT_STS_REG.VMBCH2_H/L_IT is triggered when comparator2input(VCCS)is above or below thethreshold.4.2.10INT_STS_REG3.WATCHDG_ITINT_STS_REG.WATCHDOG_IT is triggered from the watchdog(periodic or interrupt mode).9 SWCU083A–August2011–Revised November2014TPS659113Centaurus User Guide Submit Documentation FeedbackRevision History Revision HistoryChanges from Original(August2011)to A Revision Page •Changed GPIO0and EN connections in Figure2 (3)NOTE:Page numbers for previous revisions may differ from page numbers in the current version.10Revision History SWCU083A–August2011–Revised November2014Submit Documentation FeedbackIMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,enhancements,improvements and other changes to its semiconductor products and services per JESD46,latest issue,and to discontinue any product or service per JESD48,latest issue.Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.All semiconductor products(also referred to herein as“components”)are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its components to the specifications applicable at the time of sale,in accordance with the warranty in TI’s terms and conditions of sale of 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TI is not responsible or liable for any such statements.Buyer acknowledges and agrees that it is solely responsible for compliance with all legal,regulatory and safety-related requirements concerning its products,and any use of TI components in its applications,notwithstanding any applications-related information or support that may be provided by TI.Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures,monitor failures and their consequences,lessen the likelihood of failures that might cause harm and take appropriate remedial actions.Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications.In some cases,TI components may be promoted specifically to facilitate safety-related applications.With such components,TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements.Nonetheless,such components are subject to these terms.No TI components are authorized for use in FDA Class III(or similar life-critical medical equipment)unless authorized officers of the parties have executed a special agreement specifically governing such use.Only those TI components which TI has specifically designated as military grade or“enhanced plastic”are designed and intended for use in military/aerospace applications or environments.Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk,and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use.TI has specifically designated certain components as meeting ISO/TS16949requirements,mainly for automotive use.In any case of use of non-designated products,TI will not be responsible for any failure to meet ISO/TS16949.Products ApplicationsAudio /audio Automotive and Transportation /automotiveAmplifiers Communications and Telecom /communicationsData Converters Computers and Peripherals /computersDLP®Products Consumer Electronics /consumer-appsDSP Energy and Lighting /energyClocks and Timers /clocks Industrial /industrialInterface Medical /medicalLogic Security /securityPower Mgmt Space,Avionics and Defense /space-avionics-defense Microcontrollers Video and Imaging /videoRFID OMAP Applications Processors /omap TI E2E Community Wireless Connectivity /wirelessconnectivityMailing Address:Texas Instruments,Post Office Box655303,Dallas,Texas75265Copyright©2014,Texas Instruments Incorporated。
TI推出新款低电压电源管理单元,满足高标准汽车应用
TI推出新款低电压电源管理单元，满足高标准汽车应用 2013 年 2 月19 日，北京讯，日前，德州仪器(TI) 宣布推出一款支持低于10ms 最快启动时间的低电压电源管理单元，充分满足高标准即时启动汽车应用需求，如图形群集、信息娱乐以及高级驾驶员辅助系统(ADAS) 等。
该TPS659119-Q1 经过优化，能够配合DRA6x 系列(代码Jacinto)信息娱乐处理器等TI 汽车OMAP 处理器以及其它ARM Cortex-A 器件工作。
此外，TPS659119-Q1 不但进行了工厂编程，而且还可根据客户所选处理器与系统电源需求提供可定制上电断电排序。
如欲了解更多详情或订购样片，敬请访问：TI/tps659119-q1-pr。
TPS659119-Q1 的主要特性与优势： 动态电压缩放可实现处理器内核的高灵活性：TPS659119-Q1 具有 3 个高效率降压DC/DC 转换器，2 个支持动态电压缩放，1 个用于输入/输出(I/O) 电源; 支持大电流轨：TPS659119-Q1 的控制信号可在必要时让外部FET 的外部降压控制器支持大电流轨; 高效高灵活输出：TPS659119-Q1 具有8 个低压降(LDO) 稳压器和1 个实时时钟(RTC) LDO，可为多个处理器提供高度灵活的输出电源; 高集成确保最高设计灵活性：TPS659119-Q1 针对TI 汽车OMAP 处理器进行了优化，包括DRA6x 系列信息娱乐处理器。
工具与支持： TPS659119-Q1 评估模块(EVM) 可用来加速对TPS659119-Q1 的评估，可根据客户要求提供：ti/tps659119evm-pr。
此外，同步提供的还有参考设计、原理图清单以及应用手册。
供货情况与封装 采用HTQFP 80 引脚封装的TPS659119-Q1 现已开始供货。
德州仪器推动汽车创新发展 TI 业界一流的半导体产品可帮助制造商及系统供应商为汽车市场带来世界级特性。
模康STB分布式I O解决方案产品数据手册说明书
Product data sheetSpecificationsstandard digital output kit STB - 24 V DC - 6 OSTBDDO3600KMainRange of productModicon STB distributed I/O solution Product or component type Standard digital output kitKit compositionSTBXBA1000 base STBDDO3600 moduleSTBXTS2100, 6-terminal spring clamp connector STBXTS1100, 6-terminal screw type connector Discrete output number 6Discrete output type Solid state Discrete output voltage 24 V Discrete output voltage typeDCComplementaryDiscrete output current 500 mADiscrete output logic Positive or negative Output voltage19.2...30 V DC Absolute maximum voltage 56 V 1.3 ms Response time 715 µs off-to-on 955 µs on-to-off Cold swapping YesHot swapping Yes for standard NIMsFallback State 0 basic NIMsUser configurable standard NIMsProtection typePower protection integrated fuse on PDM time lag 10 A Reverse polarity protection Short-circuit protectionThermal overload protection Insulation between channels and logic bus1500 V for 1 minuteMaximum leakage current 0.4 mA at state 0 30 V Surge current5 A 0.5 ms Maximum load capacitance 50 µFMaximum load inductance 500 mH at 4 Hz Minimum load 0.5 mAReset Manual reset COM faultD i s c l a i m e r : T h i s d o c u m e n t a t i o n i s n o t i n t e n d e d a s a s u b s t i t u t e f o r a n d i s n o t t o b e u s e d f o r d e t e r m i n i n g s u i t a b i l i t y o r r e l i a b i l i t y o f t h e s e p r o d u c t s f o r s p e c i f i c u s e r a p p l i c a t i o n sProduct compatibility Power distribution module STBPDT3100/3105I/O base STBXBA1000[Us] rated supply voltage24 V DCSupply Power distribution moduleCurrent consumption90 mA at 5 V DC for logic busMarking CEOvervoltage category IIStatus LED 1 LED (green) module status (RDY)1 LED per channel (green) channel status (OUT1 to OUT6)1 LED (red) module error (ERR)Height13.9 mmDepth70 mmWidth128.3 mmProduct weight0.114 kgEnvironmentStandards EN/IEC 61131-2Product certifications CSAULFM Class 1 Division 2Pollution degree 2 conforming to IEC 60664-1Operating altitude<= 2000 mIP degree of protection IP20 conforming to EN 61131-2 class 1Ambient air temperature for0…60 °C (without derating)operation32...140 °F without deratingAmbient air temperature for-40…85 °C without deratingstorage-40...185 °F without deratingRelative humidity95 % at 60 °C without condensationVibration resistance 3 gn at 58…150 Hz on 35 x 7.5 mm symmetrical DIN rail5 gn at 58…150 Hz on 35 x 15 mm symmetrical DIN rail+/-0.35 mm at 10…58 HzShock resistance30 gn for 11 ms conforming to IEC 88 reference 2-27 Packing UnitsUnit Type of Package 1PCENumber of Units in Package 11Package 1 Height 2.7 cmPackage 1 Width8.0 cmPackage 1 Length13.0 cmPackage 1 Weight136.0 gUnit Type of Package 2S02Number of Units in Package 228Package 2 Height40 cmPackage 2 Width30 cmPackage 2 Length15 cmPackage 2 Weight 4.425 kgOffer SustainabilitySustainable offer status Green Premium productREACh Regulation REACh DeclarationEU RoHS Directive Pro-active compliance (Product out of EU RoHS legal scope)EU RoHS DeclarationMercury free YesChina RoHS Regulation China RoHS declarationRoHS exemption information YesEnvironmental Disclosure Product Environmental ProfileCircularity Profile End of Life InformationWEEE The product must be disposed on European Union markets following specific waste collection andnever end up in rubbish binsCalifornia proposition 65WARNING: This product can expose you to chemicals including: Lead and lead compounds, which isknown to the State of California to cause cancer and birth defects or other reproductive harm. For moreinformation go to Contractual warrantyWarranty18 monthsDimensions Drawings DimensionsConnections and Schema Wiring DiagramExample6 two-wire actuatorsRecommended replacement(s)。
中芯国际在65和45纳米CMOS逻辑工艺上选择Kilopass OTP解决方案
中芯国际在65和45纳米CMOS逻辑工艺上选择Kilopass
OTP解决方案
佚名
【期刊名称】《《中国集成电路》》
【年(卷),期】2009(018)010
【摘要】Kilopass科技公司和中芯国际宣布在嵌入式OTP的合作伙伴关系。
Kilopass是中芯国际于65纳米和45纳米工艺的第一个嵌入式OTPNVM合作伙伴。
Kilopass将于2009年底及2010年年中分别实现在中芯国际65纳米和45纳米OTP测试芯片的投片。
【总页数】2页(P1-2)
【正文语种】中文
【中图分类】TP333
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User's GuideSWCU083–August2011TPS659113Centaurus User Guide This user's guide can be used as a reference for integrating the TPS659113power-management integrated circuit(PMIC)into a system using the TI processors DM812x/813x/814x, AM387x,C6A814x,TNETV813x/814x,DRA64x/65x,and TDA1Mx.Contents1Introduction (1)2Platform Connection (2)3Power-Up Sequencing (4)4Getting Started With the TPS659113 (8)List of Figures1Processor Connection Connection With TPS659113 (2)2Example Power Solution With TPS659113 (3)3Power-Up Sequence Timing Diagram (5)List of Tables1EEPROM Power-Up Sequence of TPS659113 (4)2EEPROM Configuration for TPS659113 (5)1IntroductionThis user's guide can be used as a reference for connectivity between the TPS659113PMIC and the TI processors DM812x/813x/814x,AM387x,C6A814x,TNETV813x/814x,DRA64x/65x,and TDA1Mx.The TPS659113EEPROM bit configuration and power-up sequence is also described.This user's guide does not provide details about the power resources or the functionality of the device.For such information,refer to the full specification document,TPS659110,TPS659112,TPS659113Integrated Power Management Unit Top Specification.1 SWCU083–August2011TPS659113Centaurus User Guide Submit Documentation FeedbackCopyright©2011,Texas Instruments IncorporatedSWCU083-001Platform Connection 2Platform ConnectionFigure 1shows the detailed connections between the processor and the TPS659113.Figure 2shows a high-level view of an example multicell system power solution proposal using the TPS659113for the processor.Figure 1.Processor Connection Connection With TPS6591132TPS659113Centaurus User GuideSWCU083–August 2011Submit Documentation FeedbackCopyright ©2011,Texas Instruments Incorporated Platform ConnectionSWCU083-002Figure2.Example Power Solution With TPS659113Notes for the connction diagram and operation defined by the TPS659113EEPROM:•The TPS659113transitions from NO SUPPLY to OFF to ACTIVE states when a supply is inserted into VCC7(VMBHI_IT_MSK=0in EEPROM).•The VMBCH threshold of the TPS659113is programmed as3.1V so VCCS must be greater than3.1 V for an OFF-to-ACTIVE transition•The voltage level of the main control signals(I2C,INT2,NRESPWRON,EN1,and EN2)is defined by the VDDIO connection.•When EN1/EN2is used as a dedicated I2C for voltage scaling,pullup resistors similar to main I2C are needed.•Depending on the application and consequently the load current and level needed for power optimzation,VDD2of the TPS659113can be used as supply for HDVICP or an optional discreteDC-DC can be added to system.The TPS659113power-up sequence supports an enable signal,GPIO6,for the discrete device.•The PWRHOLD pin is programmed as a GPI in the TPS659113.•The internal RC oscillator is used for boot.After boot,software can switch to using a crystal oscillator if it has been connected.•If backup battery is not used,VBACKUP should be connected to VCC7.•GPIO0is a push-pull output at the VCC7level.•GPIO2,GPIO6,and GPIO7are open drain-outputs and need an external pullup.These GPIOs can actively pull down after4ms from the time the VCC7supply is valid.3 SWCU083–August2011TPS659113Centaurus User Guide Submit Documentation FeedbackCopyright©2011,Texas Instruments IncorporatedPower-Up Sequencing 3Power-Up Sequencing3.1Power-Up Sequence for ProcessorThe DM814x requirement for the power-up sequence is:1.8V→3.3V→memory1.5V/1.8V→1.2VNOTE:Note:The power-up sequence definition was optimized in March2011.Some early samplesof the TPS659113have a different power-up sequence.3.2TPS659113EEPROM Power-Up SequenceWhen the BOOT pin is set high,the TPS659113powers up with the sequence required by the processor, see Table1.The correct power-up sequence is configured in the EEPROM(factory programmable only).Apart from the main power rails required for the processor,several LDO rails are also powered up at initial power up to support system peripherals.Table1lists the power-up sequence for TPS659113.Figure3shows the power-up sequence timing.Table1.EEPROM Power-Up Sequence of TPS659113TPS659113Power Rail TPS659113Sequence NumberSupply insertion to VCC7,VCCS(1)–VIO2LDO83LDO2,LDO44LDO15LDO3,LDO66GPIO2,GPIO77LDO5,LDO78GPIO09VDDCtrl10VDD1,CLK32KOUT11VDD2,GPIO612NRESPWRON14(1)Supply insertion is the start on event.4TPS659113Centaurus User Guide SWCU083–August2011Submit Documentation FeedbackCopyright©2011,Texas Instruments IncorporatedSWCU083-003Figure3.Power-Up Sequence Timing DiagramTable2lists the EEPROM values for the TPS659113.Table2.EEPROM Configuration for TPS659113Register Bit Description Option Selected VDD1_OP_REG/SEL VDD1voltage level selection for boot. 1.2VVDD1_SR_REGVDD1_REG VGAIN_SEL VDD1gain selection,x1or x2x1EEPROM VDD1time slot selection11DCDCCTRL_REG VDD1_PSKIP VDD1pulse skip mode enable Skip enabledVDD2_OP_REG/SEL VDD2voltage level selection for boot 1.2VVDD2_SR_REGVDD2_REG VGAIN_SEL VDD2gain selection,x1or x3x1EEPROM VDD2time slot selection12DCDCCTRL_REG VDD2_PSKIP VDD2pulse skip mode enable Skip enabledVIO_REG SEL[3:9]VIO voltage selection 1.8VEEPROM VIO time slot selection2DCDCCTRL_REG VIO_PSKIP VIO pulse skip mode enable Skip enabledVDDCtrl_OP_REG/SEL VDDCtrl voltage level selection for boot 1.2VVDDCtrl_SR_REGEEPROM VDDCtrl time slot10LDO1_REG SEL[7:2]LDO1voltage selection 1.8VEEPROM LDO1time slot5LDO2_REG SEL[7:2]LDO2voltage selection 1.8VEEPROM LDO2time slot4LDO3_REG SEL[6:2]LDO3voltage selection 3.3V5 SWCU083–August2011TPS659113Centaurus User Guide Submit Documentation FeedbackCopyright©2011,Texas Instruments IncorporatedPower-Up Sequencing Table2.EEPROM Configuration for TPS659113(continued)Register Bit Description Option Selected EEPROM LDO3time slot6LDO4_REG SEL[7:2]LDO4voltage selection 1.8VEEPROM LDO4time slot4LDO5_REG SEL[6:2]LDO5voltage selection 3.3VEEPROM LDO5time slot8LDO6_REG SEL[6:2]LDO6voltage selection 3.3VEEPROM LDO6time slot6LDO7_REG SEL[6:2]LDO7voltage selection 3.3VEEPROM LDO7time slot8LDO8_REG SEL[6:2]LDO8voltage selection 1.8VEEPROM LDO8time slot3CLK32KOUT pin CLK32KOUT time slot11NRESPWRON,NRESPWRON2NRESPWRON time slot14pinGPIO0pin GPIO0time slot9GPIO2pin GPIO2time slot7GPIO6pin GPIO6time slot12GPIO7pin GPIO7time slot7VRTC_REG VRTC_OFFMASK0=VRTC LDO will be in low-power mode Low-power modeduring OFF state.1=VRC LDO will be in full-power modeduring OFF state.DEVCTRL_REG CK32K_CTRL0=Clock source is crystal/external clock.RC1=Clock source is internal RC oscillator.DEVCTRL_REG DEV_ON0=No impact01=Will maintain device on,in ACTIVE orSLEEP stateDEVCTRL2_REG TSLOT_LENGTH Boot sequence time slot duration:2ms0=0.5ms1=2msDEVCTRL2_REG PWON_LP_OFF0=Turn-off after PWRON long press not1allowed.1=Turn-off after PWRON long press.DEVCTRL2_REG PWON_LP_RST0=No impact01=Reset digital core when device is OFF.DEVCTRL2_REG IT_POL0=INT1signal will be active low.Active low1=INT1signal will be active high.INT_MSK_REG VMBHI_IT_MSK0=Device automatically switches on at NO0=AutomaticSUPPLY-to-OFF or BACKUP-to-OFF switch-on from supplytransition.insertion1=Start-up is reason required beforeswitch-on.INT_MSK3_REG GPIO5_F_IT_MSK0=GPIO5falling edge detection interrupt not Maskedmasked.1=GPIO5falling edge detection interruptmasked.INT_MSK3_REG GPIO5_R_IT_MSK0=GPIO5rising edge detection interrupt not Maskedmasked.1=GPIO5rising edge detection interruptmasked.INT_MSK3_REG GPIO4_F_IT_MSK0=GPIO4falling edge detection interrupt not Maskedmasked.1=GPIO4falling edge detection interruptmasked.6TPS659113Centaurus User Guide SWCU083–August2011Submit Documentation FeedbackCopyright©2011,Texas Instruments Incorporated Power-Up SequencingTable2.EEPROM Configuration for TPS659113(continued)Register Bit Description Option Selected INT_MSK3_REG GPIO4_R_IT_MSK0=GPIO4rising edge detection interrupt not Maskedmasked.1=GPIO4rising edge detection interruptmasked.GPIO0_REG GPIO_ODEN0=GPIO0configured as push-pull output.Push-pull1=GPIO0configured as open-drain output.WATCHDOG_REG WATCHDOG_EN0=Watchdog disabled Disabled1=Watchdog enabled,periodic operation with100sVMBCH_REG VMBBUF_BYPASS0=Enable input buffer for external resistive Enable bufferdivider.1=In single-cell system,disable buffer forlower power consumption.VMBCH_REG VMBCH_SEL[5:1]Select threshold for boot gating comparator 3.1VCOMP1,2.5–3.5V.EEPROM AUTODEV_ON0=PWRHOLD pin is used as PWRHOLD PWRHOLD pin is GPIfeature.1=PWRHOLD pin is GPI.After power-on,DEV_ON is set high internally,no processoraction needed to maintain supplies.EEPROM PWRDN_POL0=PWRDN signal is active low.Active high1=PWRDN signal is active high.7 SWCU083–August2011TPS659113Centaurus User Guide Submit Documentation FeedbackCopyright©2011,Texas Instruments IncorporatedGetting Started With the 4Getting Started With the TPS6591134.1First Initialization4.1.1Power-Down Sequence ConfigurationTo meet processor power-down sequence requirements,select the reverse sequence by setting thePWR_OFF_SEQ bit to1in the DEVCTRL_REG register.4.1.2I/O Polarity/Muxing ConfigurationVoltage scaling for VDD1,VDD2,and VDDCtrl can be done either through the main I2C interface orthrough dedicated interface EN1/EN2.Refer to the processor documentation for information on which one is supported.To enable the dedicated voltage scaling interface,set the SR_CTL_I2C_SEL bit to0inDEVCTRL_REG register.If sleep mode is supported,program the SLEEPSIG_POL bit in the DEVCTRL2_REG register according to the GPIO from the processor.This can be set to active-low or active-high for SLEEP transitions.Software can configure specific power resources to enter the LOW-POWER or OFF state in sleep mode.In the DEVCTRL_REG register,set the DEV_SLP bit to1to allow the SLEEP transition when requested through the SLEEP pin.Update the GPIOx configuration(GPIOx_REG)based on your needs.4.1.3Define Wake Up/Interrupt Event(SLEEP or OFF)Select the appropriate bits in the INT_MSK_REG,INT_MSK2_REG,and INT_MSK3_REG registers to enable an interrupt to the processor on the INT1line.4.1.4Backup Battery ConfigurationIf the system has a backup battery,set the BBCHEN bit to1in the BBCH_REG register to enable backup battery charging.The maximum voltage can be set based on backup battery specifications by using the BBSEL bits in the BBCH_REG register.4.1.5DC-DC Maximum Current CapablityIn VIO_REG,VDD1_REG,and VDD2_REG registers,set ILMAX according to required maximum current.4.1.6Sleep Platform ConfigurationConfigure the state of the LDOs when the SLEEP signal is used.By default,in sleep mode all resources maintain their output voltage and load capability but response to transients(load change)is reduced.Resources that must provide full load capability must be set in the SLEEP_KEEP_LDO_ON_REG and SLEEP_KEEP_RES_ON_REG registers.Resources that can be set off in the SLEEP state to optimize power consumption must be set in theSLEEP_SET_LDO_OFF_REG and SLEEP_SET_RES_OFF_REG registers.4.2Event Management Through Interrupts4.2.1INT_STS_REG.VMBHI_ITINT_STS_REG.VMBHI_IT indicates that a supply has been connected(PMIC leaving the BACKUP or NO SUPPLY state)and the system must be initialized(see Section4.1,First Initialization).8TPS659113Centaurus User Guide SWCU083–August2011Submit Documentation FeedbackCopyright©2011,Texas Instruments Incorporated Getting Started With the TPS659113 4.2.2INT_STS_REG.PWRON_ITINT_STS_REG.PWRON_IT is triggered by pressing the PWRON button.If the device is in the OFF orSLEEP state,then this acts as a wake-up event and resources are reinitialized.4.2.3INT_STS_REG.PWRON_LP_ITINT_STS_REG.PWRON_LP_IT is the PWRON long-press interrupt.This interrupt is generated when the PWRON button is pressed for4seconds.The application processor can make a decision to acknowledge the interrupt.If this interrupt is not acknowledged in the next1second,the device interprets this as apower-down event.4.2.4INT_STS_REG.HOTDIE_ITINT_STS_REG.HOTDIE_IT indicates that the temperature of the die is reaching the limit.The software must take action to decrease the power consumption before automatic shutdown.4.2.5INT_STS_REG.PWRHOLD_R/F_ITINT_STS_REG.PWRHOLD_R/F_IT indicates a GPI interrupt event.4.2.6INT_STS_REG.RTC_ALARM_ITINT_STS_REG.RTC_ALARM_IT is triggered when the RTC alarm set time is reached.4.2.7INT_STS2(3)_REG.GPIO_R/F_ITINT_STS2_REG.GPIO_R/F_IT indicates a GPIO interrupt event.It can be used to wake up the device from the SLEEP state.This can be an interrupt coming from any peripheral device or alike.4.2.8INT_STS_REG3.PWRDN_ITINT_STS_REG.PWRDN_IT is triggered when PWRDN reset is detected.4.2.9INT_STS_REG3.VMBCH2_H/L_ITINT_STS_REG.VMBCH2_H/L_IT is triggered when comparator2input(VCCS)is above or below thethreshold.4.2.10INT_STS_REG3.WATCHDG_ITINT_STS_REG.WATCHDOG_IT is triggered from the watchdog(periodic or interrupt mode).9 SWCU083–August2011TPS659113Centaurus User Guide Submit Documentation FeedbackCopyright©2011,Texas Instruments IncorporatedIMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make 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