cy7c68000中文翻译
CY7C028V中文资料
元器件交易网
CY7C027V/028V CY7C037V/038V
Pin Configurations
100-Pin TQFP (Top View)
BUSYR BUSYL INTR GND INTL A0R A1R A2R A3R A4R A5R A6R A7R A8R 75 74 73 72 71 70 69 68 67 66 65 M/S A8L A7L A6L A5L A4L A3L A2L A1L A0L NC
I/O6R
I/O7R
I/O8R
Selection Guide
CY7C037V/038V CY7C037V/038V CY7C037V/038V -15 -20 -25 Maximum Access Time Typical Operating Current Typical Standby Current for ISB1 (Both ports TTL level) Typical Standby Current for ISB3 (Both ports CMOS level)
Note: 6. This pin is NC for CY7C037V.
I/O9R
GND
GND
VCC
I/O9L
I/O8L
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
I/O1L
I/O0L
VCC
Unit ns mA mA µA
15 125 35 10 µA
20 120 35 10 µA
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A9L A10L A11L A12L A13L A14L [5] A15L NC NC LBL UBL CE0L CE1L SEML VCC R/WL OEL GND GND I/O15L I/O14L I/O13L I/O12L I/O11L I/O10L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A9R A10R A11R A12R A13R A14R A15R [5] NC NC LBR UBR CE0R CE1R SEMR GND R/WR OER GND GND I/O15R I/O14R I/O13R I/O12R I/O11R I/O10R
CY7C1470BV25资料
72-Mbit (2M x 36/4M x 18/1M x 72)Pipelined SRAM with NoBL™ ArchitectureCY7C1470BV25CY7C1472BV25, CY7C1474BV25Features■Pin-compatible and functionally equivalent to ZBT™ ■Supports 250 MHz bus operations with zero wait states ❐Available speed grades are 250, 200, and 167 MHz■Internally self-timed output buffer control to eliminate the need to use asynchronous OE■Fully registered (inputs and outputs) for pipelined operation■Byte Write capability ■Single 2.5V power supply ■2.5V IO supply (V DDQ )■Fast clock-to-output times ❐3.0 ns (for 250-MHz device)■Clock Enable (CEN) pin to suspend operation ■Synchronous self-timed writes■CY7C1470BV25, CY7C1472BV25 available inJEDEC-standard Pb-free 100-pin TQFP , Pb-free and non-Pb-free 165-ball FBGA package. CY7C1474BV25available in Pb-free and non-Pb-free 209-ball FBGA package ■IEEE 1149.1 JTAG Boundary Scan compatible ■Burst capability—linear or interleaved burst order ■“ZZ” Sleep Mode option and Stop Clock optionFunctional DescriptionThe CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25are 2.5V, 2M x 36/4M x 18/1M x 72 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL ™) logic, respectively.They are designed to support unlimited true back-to-back read or write operations with no wait states. The CY7C1470BV25,CY7C1472BV25, and CY7C1474BV25 are equipped with the advanced (NoBL) logic required to enable consecutive read or write operations with data being transferred on every clock cycle.This feature dramatically improves the throughput of data in systems that require frequent read or write transitions. The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 are pin-compatible and functionally equivalent to ZBT devices.All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Write operations are controlled by the Byte Write Selects (BW a –BW d for CY7C1470BV25, BW a –BW b for CY7C1472BV25, and BW a –BW h for CY7C1474BV25) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry.Three synchronous Chip Enables (CE 1, CE 2, CE 3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. To avoid bus contention,the output drivers are synchronously tri-stated during the data portion of a write sequence.Selection GuideDescription250 MHz 200 MHz 167 MHz Unit Maximum Access Time3.0 3.0 3.4ns Maximum Operating Current450450400mA Maximum CMOS Standby Current120120120mALogic Block Diagram – CY7C1470BV25 (2M x 36)Logic Block Diagram – CY7C1472BV25 (4M x 18)Logic Block Diagram – CY7C1474BV25 (1M x 72)Pin ConfigurationsA A A A A 1A 0V S SV D DA A A A A AV DDQ V SSDQb DQb DQb V SS V DDQDQb DQb V SSNCV DDDQaDQa V DDQ V SSDQa DQa V SS V DDQ V DDQV SS DQc DQc V SS V DDQ DQc V DD V SS DQd DQd V DDQ V SS DQd DQd DQd V SS V DDQ A A C E 1C E 2B W aC E 3V D DV S SC L K W E C E N O E A A123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495080797877767574737271706968676665646362616059585756555453525110099989796959493929190898887868584838281A AA D V /L D ZZCY7C1470BV25A A A A A 1A 0V S SV D DA A A A A AA NC NC V DDQ V SS NC DQPa DQa DQa V SS V DDQ DQa DQa V SS NC V DD DQa DQa V DDQ V SS DQa DQa NC NC V SS V DDQ NC NC NCNC NC NC V DDQ V SS NC NC DQb DQb V SS V DDQDQb DQbV DD V SS DQb DQb V DDQV SS DQb DQb DQPbNC V SS V DDQNC NC NCA A C E 1C E 2N C N C B W b B W a C E 3V D DV S SC L K W E C E N O E A A123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495080797877767574737271706968676665646362616059585756555453525110099989796959493929190898887868584838281A AA D V /L D ZZ M O D E CY7C1472BV25B W d M O D E B W c DQc DQc DQc DQc DQPc DQd DQd DQd DQPb DQb DQa DQaDQa DQaDQPa DQb DQb (2M × 36)(4M × 18)B W b NC NC NC DQc NC N C (288)N C (144)N C (288)N C (144)DQPdA A A A A A Figure 1. 100-Pin TQFP PinoutPin Configurations (continued)165-Ball FBGA (15 x 17 x 1.4 mm) PinoutCY7C1470BV25 (2M x 36)CY7C1472BV25 (4M x 18)2345671A B C D E F G H J K L M N P RTDO NC/576M NC/1G DQP c DQ c DQP d NC DQ d A CE 1BW b CE 3BW c CEN A CE2DQ c DQ d DQ d MODENC DQ c DQ c DQ d DQ d DQ d AV DDQ BW d BW a CLKWEV SS V SS V SS V SS V DDQ V SS V DD V SS V SS V SS NC V SS V SS V SS V SS V DDQ V DDQ NC V DDQ V DDQ V DDQ V DDQ A AV DD V SS V DD V SS V SS V DDQ V DD V SS V DD V SS V DD V SS V SS V SS V DD V DD V SS V DD V SS V SS NC TCKA0V SS TDIAA DQ c V SS DQ c V SS DQ c DQ c NC V SS V SS V SS V SS NC V SS A1DQ d DQ d NC/144M NCV DDQ V SS TMS891011NC/288MAA ADV/LDNC OE A A NC V SS V DDQ NC DQP b V DDQ V DD DQ b DQ b DQ b NC DQ b NC DQ a DQ a V DD V DDQ V DD V DDQ DQ b V DD NC V DD DQ a V DD V DDQ DQ a V DDQ V DD V DD V DDQ V DD V DDQ DQ a V DDQ AAV SS AAADQ b DQ b DQ b ZZ DQ a DQ a DQP aDQ a A V DDQ AA 2345671A B C D E F G H J K L M N P RTDO NC/576M NC/1G NC NC DQP b NC DQ b A CE 1CE 3BW b CEN A CE2NC DQ b DQ b MODENC DQ b DQ b NC NC NC AV DDQ BW a CLKWE V SS V SS V SS V SSV DDQ V SS V DD V SS V SS V SS NC V SS V SS V SS V SS V DDQ V DDQ NC V DDQ V DDQ V DDQ V DDQ A AV DD V SS V DD V SS V SS V DDQ V DD V SS V DD V SS V DD V SS V SS V SS V DD V DD V SS V DD V SS V SS NC TCKA0V SS TDIAA DQ b V SS NC V SS DQ b NC NC V SS V SS V SS V SS NC V SS A1DQ b NC NC/144M NCV DDQ V SS TMS891011NC/288MAA ADV/LDA OE A A NC V SSV DDQ NC DQPa V DDQ V DD NC DQ a DQ a NC NC NC DQ a NC V DD V DDQ V DD V DDQ DQ a V DD NC V DD NC V DD V DDQ DQ a V DDQ V DD V DD V DDQ V DD V DDQ NC V DDQ AAV SS AAADQ a NC NC ZZ DQ a NC NCDQ a A V DDQ AA NC NCPin Configurations (continued)CY7C1474BV25 (1M × 72)209-Ball FBGA (14 x 22 x 1.76 mm) PinoutA B C D E F G H J K L M N P R T U V W1234567891110DQgDQgDQgDQgDQgDQgDQgDQgDQcDQcDQcDQcNCDQPgDQhDQhDQhDQhDQdDQdDQdDQdDQPdDQPcDQcDQcDQcDQcNCDQhDQhDQhDQhDQPhDQdDQdDQdDQdDQbDQbDQbDQbDQbDQbDQbDQbDQfDQfDQfDQfNCDQPfDQaDQaDQaDQaDQeDQeDQeDQeDQPaDQPbDQfDQfDQfDQfNCDQaDQaDQaDQaDQPeDQeDQeDQeDQeA A A ANC NCNC/144M A A NC/288MA A AA A A A1A0A A AA AANC/576MNCNCNC NCNCBWS b BWS fBWS e BWS aBWS c BWS gBWS dBWS hTMS TDI TDO TCKNCNC MODE NCCEN V SSNCCLK NC V SSV DD V DD V DDV DDV DDV DDV DDV DDV DDV DDV DDV DDV DDV SS V SSV SSV SSV SSV SS V SSV SSNC/1GV DDNCOECE3CE1CE2ADV/LDWEV SSV SSV SSV SS V SS V SS VSSZZV SS V SS V SS V SSNCV DDQV SSV SS NC V SS V SSV SS V SS VSSV SSNCV SSV DDQ V DDQ V DDQ V DDQV DDQ NC V DDQ VDDQV DDQ V DDQ NC V DDQ V DDQV DDQ V DDQ NC V DDQ VDDQV DDQV DDQV DDQ V DDQV DDQ VDDQV DDQ V DDQTable 1. Pin DefinitionsPin Name IO Type Pin DescriptionA0 A1 AInput-SynchronousAddress Inputs Used to Select One of the Address Locations. Sampled at the rising edge of theCLK.BW a BW b BW c BW d BW e BW f BW g BW hInput-SynchronousByte Write Select Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampledon the rising edge of CLK. BW a controls DQ a and DQP a, BW b controls DQ b and DQP b, BW c controlsDQ c and DQP c, BW d controls DQ d and DQP d, BW e controls DQ e and DQP e, BW f controls DQ f andDQP f, BW g controls DQ g and DQP g, BW h controls DQ h and DQP h.WE Input-Synchronous Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence.ADV/LD Input-Synchronous Advance/Load Input Used to Advance the On-Chip Address Counter or Load a New Address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD must be driven LOW to load a new address.CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW.CE1Input-Synchronous Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device.CE2Input-Synchronous Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device.CE3Input-Synchronous Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device.OE Input-Asynchronous Output Enable, Active LOW. Combined with the synchronous logic block inside the device to control the direction of the IO pins. When LOW, the IO pins can behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected.CEN Input-Synchronous Clock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required.DQ s IO-Synchronous Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[18:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQ a–DQ h are placed in a tri-state condition. The outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE.DQP X IO-Synchronous Bidirectional Data Parity IO Lines. Functionally, these signals are identical to DQ[71:0]. During write sequences, DQP a is controlled by BW a, DQP b is controlled by BW b, DQP c is controlled by BW c, and DQP d is controlled by BW d, DQP e is controlled by BW e, DQP f is controlled by BW f, DQP g is controlled by BW g, DQP h is controlled by BW h.MODE Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.Pulled LOW selects the linear burst order. MODE must not change states during operation. Whenleft floating MODE defaults HIGH, to an interleaved burst order.TDO JTAG SerialOutputSynchronousSerial Data Out to the JTAG Circuit. Delivers data on the negative edge of TCK.TDI JTAG Serial InputSynchronousSerial Data In to the JTAG Circuit. Sampled on the rising edge of TCK.Functional OverviewThe CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 are synchronous-pipelined Burst NoBL SRAMs designed specif-ically to eliminate wait states during read or write transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t CO) is 3.0 ns (250-MHz device).Accesses can be initiated by asserting all three Chip Enables (CE1, CE2, CE3) active at the rising edge of the clock. If CEN is active LOW and ADV/LD is asserted LOW, the address presented to the device is latched. The access can either be a read or write operation, depending on the status of the Write Enable (WE). BW[x] can be used to conduct Byte Write opera-tions.Write operations are qualified by the Write Enable (WE). All writes are simplified with on-chip synchronous self-timed write circuitry.Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (reads, writes, and deselects) are pipelined. ADV/LD must be driven LOW after the device is deselected to load a new address for the next operation.Single Read AccessesA read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, (3) the input signal WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 2.6 ns (250-MHz device) provided OE is active LOW. After the first clock of the read access the output buffers are controlled by OE and the internal control logic. OE must be driven LOW to drive out the requested data. During the second clock, a subsequent operation (read, write, or deselect) can be initiated. Deselecting the device is also pipelined. Therefore, when the SRAM is deselected at clock rise by one of the chip enable signals, its output tri-states following the next clock rise.Burst Read AccessesThe CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 have an on-chip burst counter that enables the user to supply a single address and conduct up to four reads without reasserting the address inputs. ADV/LD must be driven LOW to load a new address into the SRAM, as described in the Single Read Accesses section. The sequence of the burst counter is deter-mined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and wraps around when incremented sufficiently. A HIGH input on ADV/LD increments the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (read or write) is maintained throughout the burst sequence.Single Write AccessesWrite accesses are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, and (3) the signal WE is asserted LOW. The address presented to the address inputs is loaded into the Address Register. The write signals are latched into the Control Logic block.On the subsequent clock rise the data lines are automatically tri-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQ and DQP (DQ a,b,c,d/DQP a,b,c,d for CY7C1470BV25, DQ a,b/DQP a,b for CY7C1472BV25, and DQ a,b,c,d,e,f,g,h/DQP a,b,c,d,e,f,g,h for CY7C1474BV25). In addition, the address for the subsequentTMS Test Mode SelectSynchronousTMS Pin Controls the Test Access Port State Machine. Sampled on the rising edge of TCK. TCK JTAG Clock Clock Input to the JTAG Circuitry.V DD Power Supply Power Supply Inputs to the Core of the Device.V DDQ IO Power Supply Power Supply for the IO Circuitry.V SS Ground Ground for the Device. Must be connected to ground of the system.NC–No Connects. This pin is not connected to the die.NC(144M, 288M, 576M, 1G)–These Pins are Not Connected. They are used for expansion to the 144M, 288M, 576M, and 1G densities.ZZ Input-Asynchronous ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with data integrity preserved. For normal operation, this pin has must be LOW or left floating.ZZ pin has an internal pull down.Table 1. Pin Definitions (continued)Pin Name IO Type Pin Descriptionaccess (read, write, or deselect) is latched into the Address Register (provided the appropriate control signals are asserted). On the next clock rise the data presented to DQ and DQP (DQ a,b,c,d/DQP a,b,c,d for CY7C1470BV25, DQ a,b/DQP a,b for CY7C1472BV25, DQ a,b,c,d,e,f,g,h/DQP a,b,c,d,e,f,g,h for CY7C1474BV25) (or a subset for Byte Write operations, see “Partial Write Cycle Description” on page11 for details) inputs is latched into the device and the Write is complete.The data written during the Write operation is controlled by BW (BW a,b,c,d for CY7C1470BV25, BW a,b for CY7C1472BV25, and BW a,b,c,d,e,f,g,h for CY7C1474BV25) signals. The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 provides Byte Write capability that is described in “Partial Write Cycle Description” on page11. Asserting the WE input with the selected BW input selectively writes to only the desired bytes. Bytes not selected during a Byte Write operation remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte Write capability has been included to greatly simplify read, modify, or write sequences, which can be reduced to simple Byte Write opera-tions.Because the CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 are common IO devices, data must not be driven into the device while the outputs are active. OE can be deasserted HIGH before presenting data to the DQ and DQP (DQ a,b,c,d/DQP a,b,c,d for CY7C1470BV25, DQ a,b/DQP a,b for CY7C1472BV25, and DQ a,b,c,d,e,f,g,h/DQP a,b,c,d,e,f,g,h for CY7C1474BV25) inputs. Doing so tri-states the output drivers. As a safety precaution, DQ and DQP (DQ a,b,c,d/DQP a,b,c,d for CY7C1470BV25, DQ a,b/DQP a,b for CY7C1472BV25, and DQ a,b,c,d,e,f,g,h/DQP a,b,c,d,e,f,g,h for CY7C1474BV25) are automatically tri-stated during the data portion of a write cycle, regardless of the state of OE.Burst Write AccessesThe CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 has an on-chip burst counter that enables the user to supply a single address and conduct up to four write operations without reasserting the address inputs. ADV/LD must be driven LOW to load the initial address, as described in “Single Write Accesses”on page8. When ADV/LD is driven HIGH on the subsequent clock rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BW (BW a,b,c,d for CY7C1470BV25, BW a,b for CY7C1472BV25, and BW a,b,c,d,e,f,g,h for CY7C1474BV25) inputs must be driven in each cycle of the burst write to write the correct bytes of data. Sleep ModeThe ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected before entering the “sleep” mode. CE1, CE2, and CE3, must remain inactive for the duration of t ZZREC after the ZZ input returns LOW.Table 2. Linear Burst Address Table (MODE = GND) FirstAddressSecondAddressThirdAddressFourthAddress A1,A0A1,A0A1,A0A1,A000011011011011001011000111000110Table 3. Interleaved Burst Address Table(MODE = Floating or V DD)FirstAddressSecondAddressThirdAddressFourthAddress A1,A0A1,A0A1,A0A1,A000011011010011101011000111100100ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min Max Unit I DDZZ Sleep mode standby current ZZ > V DD − 0.2V120mA t ZZS Device operation to ZZ ZZ > V DD− 0.2V2t CYC ns t ZZREC ZZ recovery time ZZ < 0.2V2t CYC ns t ZZI ZZ active to sleep current This parameter is sampled2t CYC ns t RZZI ZZ Inactive to exit sleep current This parameter is sampled0nsTable 4. Truth TableThe truth table for CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 follows.[1, 2, 3, 4, 5, 6, 7]Operation AddressUsed CE ZZ ADV/LD WE BW x OE CEN CLK DQ Deselect Cycle None H L L X X X L L-H Tri-State Continue Deselect Cycle None X L H X X X L L-H Tri-StateExternal L L L H X L L L-H Data Out (Q) Read Cycle(Begin Burst)Next X L H X X L L L-H Data Out (Q) Read Cycle(Continue Burst)External L L L H X H L L-H Tri-State NOP/Dummy Read(Begin Burst)Next X L H X X H L L-H Tri-State Dummy Read(Continue Burst)External L L L L L X L L-H Data In (D) Write Cycle(Begin Burst)Next X L H X L X L L-H Data In (D) Write Cycle(Continue Burst)None L L L L H X L L-H Tri-State NOP/Write Abort(Begin Burst)Next X L H X H X L L-H Tri-State Write Abort(Continue Burst)Ignore Clock Edge (Stall)Current X L X X X X H L-H–Sleep Mode None X H X X X X X X Tri-StateNotes1.X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BW x = L signifies at least one Byte Write Select is active, BW x = Validsignifies that the desired Byte Write Selects are asserted, see “Partial Write Cycle Description” on page11 for details.2.[a:d]. See “Partial Write Cycle Description” on page11 for details.3.When a write cycle is detected, all IOs are tri-stated, even during Byte Writes.4.The DQ and DQP pins are controlled by the current cycle and the OE signal.5.6.Device powers up deselected with the IOs in a tri-state condition, regardless of OE.7.OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a Read cycle DQ s and DQP[a:d] = tri-state when OE isinactive or when the device is deselected, and DQ s = data when OE is active.Table 5. Partial Write Cycle DescriptionThe partial write cycle description for CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 follows.[1, 2, 3, 8]Function (CY7C1470BV25)WE BW d BW c BW b BW a Read H X X X X Write – No bytes written L H H H H Write Byte a – (DQ a and DQP a)L H H H L Write Byte b – (DQ b and DQP b)L H H L H Write Bytes b, a L H H L L Write Byte c – (DQ c and DQP c)L H L H H Write Bytes c, a L H L H L Write Bytes c, b L H LL L H Write Bytes c, b, a L H L L L Write Byte d – (DQ d and DQP d)L L H H H Write Bytes d, a L L H H L Write Bytes d, b L L H L H Write Bytes d, b, a L L H L L Write Bytes d, c L L L H H Write Bytes d, c, a L L L H L Write Bytes d, c, b L L L L H Write All Bytes L L L L LFunction (CY7C1472BV25)WE BW b BW aRead H x xWrite – No Bytes Written L H HWrite Byte a – (DQ a and DQP a)L H LWrite Byte b – (DQ b and DQP b)L L HWrite Both Bytes L L LFunction (CY7C1474BV25)WE BW xRead H xWrite – No Bytes Written L HWrite Byte X − (DQ x and DQP x)L LWrite All Bytes L All BW = LNote8.Table lists only a partial listing of the Byte Write combinations. Any combination of BW[a:d] is valid. Appropriate write is based on which Byte Write is active.IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC-standard 2.5V IO logic levels.The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register.Disabling the JTAG FeatureIt is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (V SS) to prevent clocking of the device. TDI and TMS are inter-nally pulled up and may be unconnected. They may alternately be connected to V DD through a pull up resistor. TDO must be left unconnected. During power up, the device comes up in a reset state, which does not interfere with the operation of the device. The 0/1 next to each state represents the value of TMS at therising edge of TCK.Test Access Port (TAP)Test Clock (TCK)The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.Test MODE SELECT (TMS)The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level.Test Data-In (TDI)The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information about loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See TAP Controller Block Diagram.)Test Data-Out (TDO)The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See TAP Controller State Diagram.)Performing a TAP ResetA RESET is performed by forcing TMS HIGH (V DD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. During power up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.TAP RegistersRegisters are connected between the TDI and TDO balls to scan the data in and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK.Figure 2. TAP Controller State DiagramFigure 3. TAP Controller Block DiagramInstruction RegisterThree-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the “TAP Controller Block Diagram”on page12. During power up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section.When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary ‘01’ pattern to enable fault isolation of the board-level serial test data path.Bypass RegisterTo save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This shifts the data through the SRAM with minimal delay. The bypass register is set LOW (V SS) when the BYPASS instruction is executed.Boundary Scan RegisterThe boundary scan register is connected to all the input and bidirectional balls on the SRAM.The boundary scan register is loaded with the contents of the RAM IO ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the IO ring.The Boundary Scan Order tables on page 17 show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI and the LSB is connected to TDO. Identification (ID) RegisterThe ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in “Identification Register Definitions” on page16.TAP Instruction SetOverviewEight different instructions are possible with the three-bit instruction register. All combinations are listed in “Identification Codes” on page17. Three of these instructions are listed as RESERVED and must not be used. The other five instructions are described in this section in detail.The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented.The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the IO buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather, it performs a capture of the IO ring when these instruc-tions are executed.Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction after it is shifted in, the TAP controller must be moved into the Update-IR state.EXTESTEXTEST is a mandatory 1149.1 instruction which is executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1. The TAP controller does recognize an all-0 instruction.When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state.IDCODEThe IDCODE instruction loads a vendor-specific, 32-bit code into the instruction register. It also places the instruction register between the TDI and TDO balls and shifts the IDCODE out of the device when the TAP controller enters the Shift-DR state.The IDCODE instruction is loaded into the instruction register during power up or whenever the TAP controller is in a test logic reset state.SAMPLE ZThe SAMPLE Z instruction connects the boundary scan register between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state.SAMPLE/PRELOADSAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the device TAP controller is not fully 1149.1 compliant.When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register.The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output may undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that is captured. Repeatable results may not be possible.To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold time (t CS plus t CH).The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still。
CY7C68031A固件程序FW.C详解
CY7C68031A固件程序FW.C详解（1）2011-04-01 14:10736人阅读评论(0)收藏举报////本来要一次传上去，百度空间嫌文章太长，只好分为两篇////FW.C文件，我当初看了一个星期，也没看懂的。
这里我们逐字逐句研读，////边理解，边一行一行的注释.////以下是Cypress公司的官方程序，我不做改动，原英文注释保留，只增加注释//简单语句就不说了//// //???//是我不懂得的地方，希望高手补充//// //###//是以后开发可能需要改动的地方//////我加的所有注释都用////四个连斜杠，便于以后不需要的时候屏蔽掉////这是在Keil UV2里编辑的，没有其它格式字符，可以直接编译//-----------------------------------------------------------------------------// File: fw.c// Contents: Firmware frameworks task dispatcher and device request parser //// $Archive: /USB/Examples/FX2LP/bulkext/fw.c $// $Date: 3/23/05 2:53p $// $Revision: 8 $//////-----------------------------------------------------------------------------// Copyright 2003, Cypress Semiconductor Corporation//-----------------------------------------------------------------------------#include "fx2.h"////fx2.h 定义EZUSB的宏、数据类型等的头文件#include "fx2regs.h"////fx2regs.h 定义EZUSB寄存器定义的头文件#include "syncdly.h" // SYNCDELAY macro////syncdly.h同步延时宏定义//-----------------------------------------------------------------------------// Constants//-----------------------------------------------------------------------------#define DELAY_COUNT 0x9248*8L // Delay for 8 sec at 24Mhz, 4 sec at 48 #define _IFREQ 48000 // IFCLK constant for Synchronization Delay#define _CFREQ 48000 // CLKOUT constant for Synchronization Delay////以上设置时钟频率为48MHZ//-----------------------------------------------------------------------------// Random Macros//-----------------------------------------------------------------------------#define min(a,b) (((a)<(b))?(a):(b))#define max(a,b) (((a)>(b))?(a):(b))//-----------------------------------------------------------------------------// Global Variables////全局变量//-----------------------------------------------------------------------------volatile BOOL GotSUD;////GotSUD是令牌包标志，准确的说是“令牌阶段数据到来”，什么是令牌包？////首先，USB一连串的数据传输、处理、响应等就叫做USB事务。
CY7C63723-PC中文资料
元器件交易网CY7C63743CY7C63722/23CY7C63743enCoRe™ USBCombination Low-Speed USB & PS/2Peripheral ControllerTABLE OF CONTENTS1.0 FEATURES (5)2.0 FUNCTIONAL OVERVIEW (6)2.1 enCoRe USB - The New USB Standard (6)3.0 LOGIC BLOCK DIAGRAM (7)4.0 PIN CONFIGURATIONS (7)5.0 PIN ASSIGNMENTS (7)6.0 PROGRAMMING MODEL (8)6.1 Program Counter (PC) (8)6.2 8-bit Accumulator (A) (8)6.3 8-bit Index Register (X) (8)6.4 8-bit Program Stack Pointer (PSP) (8)6.5 8-bit Data Stack Pointer (DSP) (9)6.6 Address Modes (9)6.6.1 Data (9)6.6.2 Direct (9)6.6.3 Indexed (9)7.0 INSTRUCTION SET SUMMARY (10)8.0 MEMORY ORGANIZATION (11)8.1 Program Memory Organization (11)8.2 Data Memory Organization (12)8.3 I/O Register Summary (13)9.0 CLOCKING (14)9.1 Internal/External Oscillator Operation (15)9.2 External Oscillator (16)10.0 RESET (16)10.1 Low-voltage Reset (LVR) (16)10.2 Brown Out Reset (BOR) (16)10.3 Watchdog Reset (WDR) (17)11.0 SUSPEND MODE (17)11.1 Clocking Mode on Wake-up from Suspend (18)11.2 Wake-up Timer (18)12.0 GENERAL PURPOSE I/O PORTS (18)12.1 Auxiliary Input Port (21)13.0 USB SERIAL INTERFACE ENGINE (SIE) (22)13.1 USB Enumeration (22)13.2 USB Port Status and Control (22)14.0 USB DEVICE (24)14.1 USB Address Register (24)14.2 USB Control Endpoint (24)14.3 USB Non-control Endpoints (25)14.4 USB Endpoint Counter Registers (26)15.0 USB REGULATOR OUTPUT (27)16.0 PS/2 OPERATION (27)17.0 SERIAL PERIPHERAL INTERFACE (SPI) (28)17.1 Operation as an SPI Master (29)17.2 Master SCK Selection (29)17.3 Operation as an SPI Slave (29)17.4 SPI Status and Control (30)17.5 SPI Interrupt (31)17.6 SPI Modes for GPIO Pins (31)18.0 12-BIT FREE-RUNNING TIMER (31)19.0 TIMER CAPTURE REGISTERS (32)20.0 PROCESSOR STATUS AND CONTROL REGISTER (35)21.0 INTERRUPTS (36)21.1 Interrupt Vectors (37)21.2 Interrupt Latency (37)21.3 Interrupt Sources (37)22.0 USB MODE TABLES (42)23.0 REGISTER SUMMARY (47)24.0 ABSOLUTE MAXIMUM RATINGS (48)25.0 DC CHARACTERISTICS (48)26.0 SWITCHING CHARACTERISTICS (50)27.0 ORDERING INFORMATION (55)28.0 PACKAGE DIAGRAMS (55)LIST OF FIGURESFigure 8-1. Program Memory Space with Interrupt Vector Table (11)Figure 8-2. Data Memory Organization (12)Figure 9-1. Clock Oscillator On-chip Circuit (14)Figure 9-2. Clock Configuration Register (Address 0xF8) (14)Figure 10-1. Watchdog Reset (WDR, Address 0x26) (17)Figure 12-1. Block Diagram of GPIO Port (one pin shown) (19)Figure 12-2. Port 0 Data (Address 0x00) (19)Figure 12-3. Port 1 Data (Address 0x01) (19)Figure 12-4. GPIO Port 0 Mode0 Register (Address 0x0A) (20)Figure 12-5. GPIO Port 0 Mode1 Register (Address 0x0B) (20)Figure 12-6. GPIO Port 1 Mode0 Register (Address 0x0C) (20)Figure 12-7. GPIO Port 1 Mode1 Register (Address 0x0D) (20)Figure 12-8. Port 2 Data Register (Address 0x02) (21)Figure 13-1. USB Status and Control Register (Address 0x1F) (23)Figure 14-1. USB Device Address Register (Address 0x10) (24)Figure 14-2. Endpoint 0 Mode Register (Address 0x12) (25)Figure 14-3. USB Endpoint EP1, EP2 Mode Registers (Addresses 0x14 and 0x16) (26)Figure 14-4. Endpoint 0,1,2 Counter Registers (Addresses 0x11, 0x13 and 0x15) (26)Figure 17-1. SPI Block Diagram (28)Figure 16-1. Diagram of USB-PS/2 System Connections (28)Figure 17-2. SPI Data Register (Address 0x60) (29)Figure 17-3. SPI Control Register (Address 0x61) (30)Figure 17-4. SPI Data Timing (31)Figure 18-1. Timer LSB Register (Address 0x24) (31)Figure 18-2. Timer MSB Register (Address 0x25) (32)Figure 18-3. Timer Block Diagram (32)Figure 19-1. Capture Timers Block Diagram (33)Figure 19-2. Capture Timer A-Rising, Data Register (Address 0x40) (33)Figure 19-3. Capture Timer A-Falling, Data Register (Address 0x41) (34)Figure 19-4. Capture Timer B-Rising, Data Register (Address 0x42) (34)Figure 19-5. Capture Timer B-Falling, Data Register (Address 0x43) (34)Figure 19-6. Capture Timer Status Register (Address 0x45) (34)Figure 19-7. Capture Timer Configuration Register (Address 0x44) (34)Figure 20-1. Processor Status and Control Register (Address 0xFF) (35)Figure 21-1. Global Interrupt Enable Register (Address 0x20) (38)Figure 21-2. Endpoint Interrupt Enable Register (Address 0x21) (39)Figure 21-3. Interrupt Controller Logic Block Diagram (40)Figure 21-4. Port 0 Interrupt Enable Register (Address 0x04) (40)Figure 21-5. Port 1 Interrupt Enable Register (Address 0x05) (40)Figure 21-6. Port 0 Interrupt Polarity Register (Address 0x06) (41)Figure 21-7. Port 1 Interrupt Polarity Register (Address 0x07) (41)Figure 21-8. GPIO Interrupt Diagram (41)Figure 26-1. Clock Timing (51)Figure 26-2. USB Data Signal Timing (51)Figure 26-3. Receiver Jitter Tolerance (52)Figure 26-4. Differential to EOP Transition Skew and EOP Width (52)Figure 26-5. Differential Data Jitter (52)Figure 26-7. SPI Slave Timing, CPHA = 0 (53)Figure 26-6. SPI Master Timing, CPHA = 0 (53)Figure 26-8. SPI Master Timing, CPHA = 1 (54)Figure 26-9. SPI Slave Timing, CPHA = 1 (54)LIST OF TABLESTable 8-1. I/O Register Summary (13)Table 11-1. Wake-up Timer Adjust Settings (18)Table 12-1. Ports 0 and 1 Output Control Truth Table (21)Table 13-1. Control Modes to Force D+/D– Outputs (24)Table 17-1. SPI Pin Assignments (31)Table 19-1. Capture Timer Prescalar Settings (Step size and range for FCLK = 6 MHz) (35)Table 21-1. Interrupt Vector Assignments (37)Table 22-1. USB Register Mode Encoding for Control and Non-Control Endpoints (42)Table 22-2. Decode table for Table 22-3: “Details of Modes for Differing Traffic Conditions” (44)Table 22-3. Details of Modes for Differing Traffic Conditions (45)Table 28-1. CY7C63722-XC Probe Pad Coordinates in microns ((0,0) to bond pad centers) (57)1.0 Features•enCoRe™ USB - enhanced Component Reduction—Internal oscillator eliminates the need for an external crystal or resonator—Interface can auto-configure to operate as PS/2 or USB without the need for external components to switch between modes (no GPIO pins needed to manage dual mode capability)—Internal 3.3V regulator for USB pull-up resistor—Configurable GPIO for real-world interface without external components•Flexible, cost-effective solution for applications that combine PS/2 and low-speed USB, such as mice, gamepads, joysticks, and many others.•USB Specification Compliance—Conforms to USB Specification, Version 2.0—Conforms to USB HID Specification, Version 1.1—Supports 1 Low-Speed USB device address and 3 data endpoints—Integrated USB transceiver—3.3V regulated output for USB pull-up resistor•8-bit RISC microcontroller—Harvard architecture—6-MHz external ceramic resonator or internal clock mode—12-MHz internal CPU clock—Internal memory—256 bytes of RAM—8 Kbytes of EPROM—Interface can auto-configure to operate as PS/2 or USB—No external components for switching between PS/2 and USB modes—No GPIO pins needed to manage dual mode capability•I/O ports—Up to 16 versatile General Purpose I/O (GPIO) pins, individually configurable—High current drive on any GPIO pin: 50 mA/pin current sink—Each GPIO pin supports high-impedance inputs, internal pull-ups, open drain outputs or traditional CMOS outputs —Maskable interrupts on all I/O pins•SPI serial communication block—Master or slave operation—2 Mbit/s transfers•Four 8-bit Input Capture registers—Two registers each for two input pins—Capture timer setting with 5 prescaler settings—Separate registers for rising and falling edge capture—Simplifies interface to RF inputs for wireless applications•Internal low-power wake-up timer during suspend mode—Periodic wake-up with no external components•Optional 6-MHz internal oscillator mode—Allows fast start-up from suspend mode•Watchdog Reset (WDR)•Low-voltage Reset at 3.75V•Internal brown-out reset for suspend mode•Improved output drivers to reduce EMI•Operating voltage from 4.0V to 5.5VDC•Operating temperature from 0 to 70 degrees Celsius•CY7C63723 available in 18-pin SOIC, 18-pin PDIP•CY7C63743 available in 24-pin SOIC, 24-pin PDIP•CY7C63722 available in DIE form•Industry standard programmer support2.0 Functional Overview2.1enCoRe USB - The New USB StandardCypress has re-invented its leadership position in the low-speed USB market with a new family of innovative microcontrollers. Introducing...enCoRe USB—“enhanced Component Reduction.” Cypress has leveraged its design expertise in USB solutions to create a new family of low-speed USB microcontrollers that enables peripheral developers to design new products with a minimum number of components. At the heart of the enCoRe USB technology is the breakthrough design of a crystal-less oscillator. By integrating the oscillator into our chip, an external crystal or resonator is no longer needed. We have also integrated other external components commonly found in low-speed USB applications such as pull-up resistors, wake-up circuitry, and a 3.3V regulator. All of this adds up to a lower system cost.The CY7C637xx is an 8-bit RISC One Time Programmable (OTP) microcontroller. The instruction set has been optimized specif-ically for USB and PS/2 operations, although the microcontrollers can be used for a variety of other embedded applications. The CY7C637xx features up to 16 general purpose I/O (GPIO) pins to support USB, PS/2 and other applications. The I/O pins are grouped into two ports (Port 0 to 1) where each pin can be individually configured as inputs with internal pull-ups, open drain outputs, or traditional CMOS outputs with programmable drive strength of up to 50 mA output drive. Additionally, each I/O pin can be used to generate a GPIO interrupt to the microcontroller. Note the GPIO interrupts all share the same “GPIO” interrupt vector. The CY7C637xx microcontrollers feature an internal oscillator. With the presence of USB traffic, the internal oscillator can be set to precisely tune to USB timing requirements (6 MHz ±1.5%). Optionally, an external 6-MHz ceramic resonator can be used to provide a higher precision reference for USB operation. This clock generator reduces the clock-related noise emissions (EMI). The clock generator provides the 6- and 12-MHz clocks that remain internal to the microcontroller.The CY7C637xx has 8 Kbytes of EPROM and 256 bytes of data RAM for stack space, user variables, and USB FIFOs.These parts include low-voltage reset logic, a watchdog timer, a vectored interrupt controller, a 12-bit free-running timer, and capture timers. The low-voltage reset (LVR) logic detects when power is applied to the device, resets the logic to a known state, and begins executing instructions at EPROM address 0x0000. LVR will also reset the part when V CC drops below the operating voltage range. The watchdog timer can be used to ensure the firmware never gets stalled for more than approximately 8 ms. The microcontroller supports 10 maskable interrupts in the vectored interrupt controller. Interrupt sources include the USB Bus-Reset, the 128-µs and 1.024-ms outputs from the free-running timer, three USB endpoints, two capture timers, an internal wake-up timer and the GPIO ports. The timers bits cause periodic interrupts when enabled. The USB endpoints interrupt after USB transactions complete on the bus. The capture timers interrupt whenever a new timer value is saved due to a selected GPIO edge event. The GPIO ports have a level of masking to select which GPIO inputs can cause a GPIO interrupt. For additional flexibility, the input transition polarity that causes an interrupt is programmable for each GPIO pin. The interrupt polarity can be either rising or falling edge.The free-running 12-bit timer clocked at 1 MHz provides two interrupt sources as noted above (128 µs and 1.024 ms). The timer can be used to measure the duration of an event under firmware control by reading the timer at the start and end of an event, and subtracting the two values. The four capture timers save a programmable 8 bit range of the free-running timer when a GPIO edge occurs on the two capture pins (P0.0, P0.1).The CY7C637xx includes an integrated USB serial interface engine (SIE) that supports the integrated peripherals. The hardware supports one USB device address with three endpoints. The SIE allows the USB host to communicate with the function integrated into the microcontroller. A 3.3V regulated output pin provides a pull-up source for the external USB resistor on the D– pin.The USB D+ and D– USB pins can alternately be used as PS/2 SCLK and SDATA signals, so that products can be designed to respond to either USB or PS/2 modes of operation. PS/2 operation is supported with internal pull-up resistors on SCLK and SDATA, the ability to disable the regulator output pin, and an interrupt to signal the start of PS/2 activity. No external components are necessary for dual USB and PS/2 systems, and no GPIO pins need to be dedicated to switching between modes. Slow edge rates operate in both modes to reduce EMI.3.0 Logic Block Diagram4.0 Pin Configurations5.0 Pin AssignmentsNameI/O CY7C63723CY7C63743CY7C63722Description18-Pin 24-Pin 25-Pad D–/SDATA,D+/SCLK I/O 121315161617USB differential data lines (D– and D+), or PS/2 clock and data signals (SDATA and SCLK)P0[7:0]I/O1, 2, 3, 4,15, 16, 17, 181, 2, 3, 4,21, 22, 23, 241, 2, 3, 4,22, 23, 24, 25GPIO Port 0 capable of sinking up to 50 mA/pin, or sinking controlled low or high programmable current.Can also source 2 mA current, provide a resistive pull-up, or serve as a high-impedance input. P0.0 and P0.1 provide inputs to Capture Timers A and B, respec-tively.P1[7:0]I/O5, 145, 6, 7, 8,17, 18, 19, 205, 6, 7, 8,18, 19, 20, 21IO Port 1 capable of sinking up to 50 mA/pin, or sinking controlled low or high programmable current. Can alsosource 2 mA current, provide a resistive pull-up, or serve as a high-impedance input.Wake-Up 12-bit Timer USB &D+,D–P1.0–P1.7Interrupt ControllerPort 0P0.0–P0.7GPIO8-bit RISC Xtal RAM 256 Byte EPROM 8K ByteCoreBrown-out Reset XcvrWatch Timer Dog 3.3V Port 1GPIO Capture TimersUSB Engine PS/2Internal Oscillator Oscillator Low ResetVoltage RegulatorTimerSPIXTALOUTXTALIN/P2.1VREG/P2.01234569111516171819202221P0.0P0.1P0.2P0.3P1.0P1.2VSS VREG/P2.0P0.6P1.5P1.1P1.3D+/SCLK P1.7D–/SDATA VCC14P0.710VPPXTALIN/P2.1XTALOUT121378P1.4P1.62423P0.4P0.524-pin SOIC/PDIPCY7C6374312346781011121315161817P0.0P0.1P0.2P0.3VSS VREG/P2.0P0.4P0.6P0.7D+/SCLK D–/SDATA VCC18-pin SOIC/PDIPP0.59VPPXTALIN/P2.1XTALOUTCY7C63723514P1.0P1.1Top View4 5 6 7 8 93 P 0.21 P 0.0 2 P 0.125 P 0.4 24 P 0.523 P 0.622 21 20 19 1811121314151617P0.3P1.0P1.2P1.4P1.6 VSS VSS V P P X T A L I N /P 2.1V R E G X T A L O U T V C C D -/S D A T A D+/SCLK P0.7P1.1P1.3P1.5P1.7CY7C63722-XCDIE106.0 Programming ModelRefer to the CYASM Assembler User’s Guide for more details on firmware operation with the CY7C637xx microcontrollers.6.1Program Counter (PC)The 14-bit program counter (PC) allows access for up to 8 Kbytes of EPROM using the CY7C637xx architecture. The program counter is cleared during reset, such that the first instruction executed after a reset is at address 0x0000. This instruction is typically a jump instruction to a reset handler that initializes the application.The lower 8 bits of the program counter are incremented as instructions are loaded and executed. The upper 6 bits of the program counter are incremented by executing an XPAGE instruction. As a result, the last instruction executed within a 256-byte “page”of sequential code should be an XPAGE instruction. The assembler directive “XPAGEON” will cause the assembler to insert XPAGE instructions automatically. As instructions can be either one or two bytes long, the assembler may occasionally need to insert a NOP followed by an XPAGE for correct execution.The program counter of the next instruction to be executed, carry flag, and zero flag are saved as two bytes on the program stack during an interrupt acknowledge or a CALL instruction. The program counter, carry flag, and zero flag are restored from the program stack only during a RETI instruction.Please note the program counter cannot be accessed directly by the firmware. The program stack can be examined by reading SRAM from location 0x00 and up.6.28-bit Accumulator (A)The accumulator is the general-purpose, do everything register in the architecture where results are usually calculated.6.38-bit Index Register (X)The index register “X” is available to the firmware as an auxiliary accumulator. The X register also allows the processor to perform indexed operations by loading an index value into X.6.48-bit Program Stack Pointer (PSP)During a reset, the program stack pointer (PSP) is set to zero. This means the program “stack” starts at RAM address 0x00 and “grows” upward from there. Note that the program stack pointer is directly addressable under firmware control, using the MOV PSP ,A instruction. The PSP supports interrupt service under hardware control and CALL, RET, and RETI instructions under firmware control.During an interrupt acknowledge, interrupts are disabled and the program counter, carry flag, and zero flag are written as two bytes of data memory. The first byte is stored in the memory addressed by the program stack pointer, then the PSP is incremented.The second byte is stored in memory addressed by the program stack pointer and the PSP is incremented again. The net effect is to store the program counter and flags on the program “stack” and increment the program stack pointer by two.The return from interrupt (RETI) instruction decrements the program stack pointer, then restores the second byte from memory addressed by the PSP . The program stack pointer is decremented again and the first byte is restored from memory addressed by the PSP . After the program counter and flags have been restored from stack, the interrupts are enabled. The effect is to restore the program counter and flags from the program stack, decrement the program stack pointer by two, and re-enable interrupts.The call subroutine (CALL) instruction stores the program counter and flags on the program stack and increments the PSP by two.XTALIN/P2.1IN 912136-MHz ceramic resonator or external clock input, or P2.1 inputXTALOUT OUT1013146-MHz ceramic resonator return pin or internal oscillator outputV PP 71011Programming voltage supply, ground for normal operation V CC111415Voltage supplyVREG/P2.0 81112Voltage supply for 1.3-k Ω USB pull-up resistor (3.3V nominal). Also serves as P2.0 input.V SS699, 10Ground5.0 Pin Assignments (continued)NameI/O CY7C63723CY7C63743CY7C63722Description18-Pin 24-Pin 25-PadThe return from subroutine (RET) instruction restores the program counter, but not the flags, from program stack and decrements the PSP by two.Note that there are restrictions in using the JMP, CALL, and INDEX instructions across the 4-KB boundary of the program memory. Refer to the CYASM Assembler User’s Guide for a detailed description.6.58-bit Data Stack Pointer (DSP)The data stack pointer (DSP) supports PUSH and POP instructions that use the data stack for temporary storage. A PUSH instruction will pre-decrement the DSP, then write data to the memory location addressed by the DSP. A POP instruction will read data from the memory location addressed by the DSP, then post-increment the DSP.During a reset, the Data Stack Pointer will be set to zero. A PUSH instruction when DSP equals zero will write data at the top of the data RAM (address 0xFF). This would write data to the memory area reserved for a FIFO for USB endpoint 0. In non-USB applications, this works fine and is not a problem.For USB applications, the firmware should set the DSP to an appropriate location to avoid a memory conflict with RAM dedicated to USB FIFOs. The memory requirements for the USB endpoints are shown in Section 8.2. For example, assembly instructions to set the DSP to 20h (giving 32 bytes for program and data stack combined) are shown below:MOV A,20h; Move 20 hex into Accumulator (must be D8h or less to avoid USB FIFOs)SWAP A,DSP; swap accumulator value into DSP register6.6Address ModesThe CY7C637xx microcontrollers support three addressing modes for instructions that require data operands: data, direct, and indexed.6.6.1DataThe “Data” address mode refers to a data operand that is actually a constant encoded in the instruction. As an example, consider the instruction that loads A with the constant 0x30:•MOV A, 30hThis instruction will require two bytes of code where the first byte identifies the “MOV A” instruction with a data operand as the second byte. The second byte of the instruction will be the constant “0xE8h”. A constant may be referred to by name if a prior “EQU” statement assigns the constant value to the name. For example, the following code is equivalent to the example shown above:•DSPINIT: EQU 30h•MOV A,DSPINIT6.6.2Direct“Direct” address mode is used when the data operand is a variable stored in SRAM. In that case, the one byte address of the variable is encoded in the instruction. As an example, consider an instruction that loads A with the contents of memory address location 0x10h:•MOV A, [10h]In normal usage, variable names are assigned to variable addresses using “EQU” statements to improve the readability of the assembler source code. As an example, the following code is equivalent to the example shown above:•buttons: EQU 10h•MOV A,[buttons]6.6.3Indexed“Indexed” address mode allows the firmware to manipulate arrays of data stored in SRAM. The address of the data operand is the sum of a constant encoded in the instruction and the contents of the “X” register. In normal usage, the constant will be the “base” address of an array of data and the X register will contain an index that indicates which element of the array is actually addressed:•array: EQU 10h•MOV X,3•MOV A,[x+array]This would have the effect of loading A with the fourth element of the SRAM “array” that begins at address 0x10h. The fourth element would be at address 0x13h.7.0 Instruction Set SummaryRefer to the CYASM Assembler User’s Guide for detailed information on these instructions. Note that conditional jump instructions (i.e., JC, JNC, JZ, JNZ) take 5 cycles if jump is taken, 4 cycles if no jump.MNEMONIC Operand Opcode Cycles MNEMONIC Operand Opcode Cycles HALT 007NOP 204ADD A,expr data014INC A acc214ADD A,[expr] direct026INC X x224ADD A,[X+expr] index037INC [expr] direct237ADC A,expr data044INC [X+expr] index248ADC A,[expr] direct056DEC A acc254ADC A,[X+expr] index067DEC X x264SUB A,expr data074DEC [expr] direct277SUB A,[expr] direct086DEC [X+expr] index288SUB A,[X+expr] index097IORD expr address295SBB A,expr data0A4IOWR expr address2A5SBB A,[expr] direct0B6POP A2B4SBB A,[X+expr] index0C7POP X2C4OR A,expr data0D4PUSH A2D5OR A,[expr] direct0E6PUSH X2E5OR A,[X+expr] index0F7SWAP A,X2F5AND A,expr data104SWAP A,DSP305AND A,[expr] direct116MOV [expr],A direct315AND A,[X+expr] index127MOV [X+expr],A index326XOR A,expr data134OR [expr],A direct337XOR A,[expr] direct146OR [X+expr],A index348XOR A,[X+expr] index157AND [expr],A direct357CMP A,expr data165AND [X+expr],A index368CMP A,[expr] direct177XOR [expr],A direct377CMP A,[X+expr] index188XOR [X+expr],A index388MOV A,expr data194IOWX [X+expr] index396MOV A,[expr] direct1A5CPL 3A4MOV A,[X+expr] index1B6ASL 3B4MOV X,expr data1C4ASR 3C4MOV X,[expr] direct1D5RLC 3D4reserved 1E RRC 3E4XPAGE 1F4RET 3F8MOV A,X404DI 704MOV X,A414EI 724MOV PSP,A604RETI 738CALL addr50 - 5F10JMP addr80-8F5JC addr C0-CF 5 (or 4) CALL addr90-9F10JNC addr D0-DF 5 (or 4)JZ addr A0-AF 5 (or 4)JACC addr E0-EF7JNZ addr B0-BF 5 (or 4)INDEX addr F0-FF148.0 Memory Organization8.1Program Memory Organization[1]After reset Address14 -bit PC0x0000Program execution begins here after a reset.0x0002USB Bus Reset interrupt vector0x0004128-µs timer interrupt vector0x0006 1.024-ms timer interrupt vector0x0008USB endpoint 0 interrupt vector0x000A USB endpoint 1 interrupt vector0x000C USB endpoint 2 interrupt vector0x000E SPI interrupt vector0x0010Capture timer A interrupt Vector0x0012Capture timer B interrupt vector0x0014GPIO interrupt vector0x0016Wake-up interrupt vector0x0018Program Memory begins here0x1FDF8 KB PROM ends here (8K - 32 bytes). See Note below Figure 8-1. Program Memory Space with Interrupt Vector TableNote:1.The upper 32 bytes of the 8K PROM are reserved. Therefore, the user’s program must not overwrite this space.8.2Data Memory OrganizationThe CY7C637xx microcontrollers provide 256 bytes of data RAM. In normal usage, the SRAM is partitioned into four areas: program stack, data stack, user variables and USB endpoint FIFOs as shown below:After reset Address8-bit DSP8-bit PSP0x00Program Stack Growth(User’s firmware movesDSP)8-bit DSP User Selected Data Stack GrowthUser Variables0xE8USB FIFO for Address A endpoint 20xF0USB FIFO for Address A endpoint 10xF8USB FIFO for Address A endpoint 0Top of RAM Memory0xFFFigure 8-2. Data Memory Organization8.3I/O Register SummaryI/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instructions. IORD reads the selected port into the accumulator. IOWR writes data from the accumulator to the selected port. Indexed I/O Write (IOWX) adds the contents of X to the address in the instruction to form the port address and writes data from the accumulator to the specified port. Note that specifying address 0 with IOWX (e.g., IOWX 0h) means the I/O port is selected solely by the contents of X.Note:All bits of all registers are cleared to all zeros on reset, except the Processor Status and Control Register (Figure20-1). All registers not listed are reserved, and should never be written by firmware. All bits marked as reserved should always be written as 0 and be treated as undefined by reads.Table 8-1. I/O Register SummaryRegister Name I/O Address Read/Write Function Fig. Port 0 Data0x00R/W GPIO Port 012-2 Port 1 Data0x01R/W GPIO Port 112-3 Port 2 Data0x02R Auxiliary input register for D+, D–, VREG, XTALIN 12-8 Port 0 Interrupt Enable0x04W Interrupt enable for pins in Port 021-4 Port 1 Interrupt Enable0x05W Interrupt enable for pins in Port 121-5 Port 0 Interrupt Polarity 0x06W Interrupt polarity for pins in Port 021-6 Port 1 Interrupt Polarity 0x07W Interrupt polarity for pins in Port 121-7 Port 0 Mode0 0x0A W Controls output configuration for Port 012-4 Port 0 Mode10x0B W12-5 Port 1 Mode00x0C W Controls output configuration for Port 112-6 Port 1 Mode10x0D W12-7 USB Device Address0x10R/W USB Device Address register14-1 EP0 Counter Register0x11R/W USB Endpoint 0 counter register14-4 EP0 Mode Register0x12R/W USB Endpoint 0 configuration register14-2 EP1 Counter Register0x13R/W USB Endpoint 1 counter register14-4 EP1 Mode Register0x14R/W USB Endpoint 1 configuration register14-3 EP2 Counter Register0x15R/W USB Endpoint 2 counter register14-4 EP2 Mode Register0x16R/W USB Endpoint 2 configuration register14-3 USB Status & Control0x1F R/W USB status and control register13-1 Global Interrupt Enable0x20R/W Global interrupt enable register21-1 Endpoint Interrupt Enable0x21R/W USB endpoint interrupt enables21-2 Timer (LSB)0x24R Lower 8 bits of free-running timer (1 MHz)18-1 Timer (MSB)0x25R Upper 4 bits of free-running timer18-2 WDR Clear0x26W Watchdog Reset clear-Capture Timer A Rising0x40R Rising edge Capture Timer A data register19-2 Capture Timer A Falling0x41R Falling edge Capture Timer A data register19-3 Capture Timer B Rising0x42R Rising edge Capture Timer B data register19-4 Capture Timer B Falling0x43R Falling edge Capture Timer B data register19-5 Capture TImer Configuration0x44R/W Capture Timer configuration register19-7 Capture Timer Status0x45R Capture Timer status register19-6 SPI Data0x60R/W SPI read and write data register17-2 SPI Control0x61R/W SPI status and control register17-3 Clock Configuration0xF8R/W Internal / External Clock configuration register9-2 Processor Status & Control0xFF R/W Processor status and control20-1。
cy7c68000中文翻译
CY7C68000TX2™ USB 2.0 UTMI 收发器Jude 译2009.111.0 EZ-USB TX2性能EZ-USB TX2 是一个符合usb2.0的收发器，把串行的解串成30M的16位或者60M的8位的并行接口。
EZ-USB TX2 提供一个高速的物理层接口，可以工作在usb2.0 允许的最大带宽。
这允许设计者把复杂的高速模拟的usb 部分放在数字ASIC的外面，以减少开发时间和关联两部分的风险。
它提供一个被usb2.0鉴定过的标准的接口，这个接口符合UTMI 1.05（dated 3/29/01）版本的协议。
图1-1 为功能模块，EZ-USB TX2的特性：●作为设备符合usb2.0 UTMI的标准●可作业在usb高速480MBIT/S, 和全速12MBIT/S●串到并，并到串转化●8位单向或者8位双向，或者16位双向外部数据接口●在接受包是检测同步场和EOP●在发送包的时候产生同步场和EOP●从usb 串行数据流恢复数据和时钟●位填充/不填充，为填充错误检测●分段运输寄存器，用来管理在位填充/不填充期间数据速率变化●16位30M ，8位60M的并行接口●全速和高速之间终止和发送信号的转换能力（Ability to switch between FS and HSterminations andsignaling翻译的不准，自己领会）●支持对usb 复位，挂起，回复的检测●支持usb2.0定义的高速的识别和检测●支持恢复信号的发射● 3.3v 工作●两种封装选择56脚QFN,56脚SSOP●所有必要的终止，包括DPLUS上的1.5k 的上拉，都在片内●支持usb2.0测试模式2.0 应用• DSL modems数字模拟语言模型• ATA interface ATA接口• Memory card readers存储卡读卡器• Legacy conversion devices遗产转化设备☺• Cameras照相机• Scanners扫描仪• Home PNA☹• Wireless LAN无线局域网• MP3 players mp3 播放器• Networking网络3.0 功能概述3.1 usb 发信号的速度TX2 工作在两种速率：全速：位时间为12Mbps高速：位时间为480Mbps不支持低速速率1.5Mbps3.2 收发器时钟频率TX2 有一个片上的可用24M晶振的振荡器电路，有以下特性：并行振荡基波模型500uw驱动级27-33pf负载电容片上的pll 把24M的时钟倍频为30M或者60M，作为并行数据传输的时钟，DataBus16_8 引脚决定clk 的频率。
珍贵资料-cy7c68013中文手册
CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A EZ-USB FX2LP (TM) USB 微控制器高速 USB 外设控制器1. 特色 (CY7C68013A/14A/15A/16A)■USB 2.0 USB IF 高速性能且经过认证 (TID # 40460272)■单芯片集成 USB 2.0 收发器、智能串行接口引擎 (SIE) 和增强型 8051 微处理器■适用性、外观和功能均与FX2兼容❐引脚兼容❐目标代码兼容❐功能兼容（FX2LP 是超集）■超低功耗：I CC在任何模式下都不超过 85 mA❐适合总线和电池供电的应用■软件：8051 代码运行介质：❐内部 RAM，通过 USB 下载❐内部 RAM，从 EEPROM 加载❐外部存储设备（128 引脚封装）■16 K 字节片上代码/数据 RAM■四个可编程的 BULK/INTERRUPT/ISOCHRONOUS 端点❐缓冲区大小选项：两倍，三倍，四倍■附加的可编程(BULK/INTERRUPT) 64 位端点■8 位或 16 位外部数据接口■可生成智能介质标准错误校正码 ECC ■通用可编程接口 (General Programmable Interface，GPIF)❐可与大多数并行接口直接连接❐由可编程波形描述符和配置寄存器定义波形❐支持多个 Ready (RDY) 输入和 Control (CTL) 输出■符合行业标准的集成增强型 8051❐48 MHz、24 MHz 或 12 MHz CPU 操作❐每个指令周期四个时钟❐两个 USART❐三个计数器/定时器❐扩展的中断系统❐两个数据指针■3.3V 工作电压，容限输入为 5V■向量化 USB 中断和 GPIF/FIFO 中断■分离的 CONTROL 传输设置部分和数据部分数据缓冲■集成 I2C 控制器，在 100 或 400 kHz 下运行■集成的四个先进先出 (FIFO) 缓冲❐集成胶合逻辑和 FIFO 有助于降低系统成本❐与 16 位总线之间的自动转换❐可主-从操作❐使用外部时钟或异步选通脉冲❐易于与 ASIC 和 DSP IC 相连的接口■有商业和工业温度等级供选择（除 VFBGA 外的所有封装）1.1 特色（仅限 CY7C68013A/14A ）■CY7C68014A ：适合电池供电应用❐挂起电流：100 μA (typ)■CY7C68013A ：适合非电池供电应用❐挂起电流：300 μA (typ)■有五种无铅封装供选择，可包含多达 40 个 GPIO ❐128 引脚 TQFP （40 个 GPIO ）、100 引脚 TQFP （40 个 GPIO ）、56 引脚 QFN （24 个 GPIO ）、56 引脚 SSOP （24 个 GPIO ）和 56 引脚 VFBGA （24 个 GPIO ）1.2 特色（仅限 CY7C68015A/16A ）■CY7C68016A ：适合电池供电应用❐挂起电流：100 μA (typ)■CY7C68015A ：适合非电池供电应用❐挂起电流：300 μA (typ)■采用无铅 56 引脚 QFN 封装（26 个 GPIO ）❐比 CY7C68013A/14A 多 2 个 GPIO ，可在同样的空间内实现额外的功能赛普拉斯半导体公司（赛普拉斯）的 EZ-USB FX2LP ™ (CY7C68013A/14A) 是高集成、低功耗 USB 2.0 微控制器EZ-USB FX2™ (CY7C68013) 的一个低功耗版本。
CY7C008V-15AC中文资料
Document #: 38-06044 Rev. *B
Revised December 27, 2002
元器件交易网
CY7C008V/009V CY7C018V/019V
Functional Description
The CY7C008V/009V and CY7018V/019V are low-power CMOS 64K, 128K x 8/9 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 8/9-bit dual-port static RAMs or multiple devices can be combined in order to function as a 16/18-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 16/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory.
CY7C131中文资料
1K x 8 Dual-Port Static RAMCY7C130/CY7C131CY7C140/CY7C141Features•True Dual-Ported memory cells which allow simulta-neous reads of the same memory location •1K x 8 organization•0.65-micron CMOS for optimum speed/power •High-speed access: 15 ns•Low operating power: I CC = 110 mA (max.)•Fully asynchronous operation •Automatic power-down•Master CY7C130/CY7C131 easily expands data bus width to 16 or more bits using slave CY7C140/CY7C141•BUSY output flag on CY7C130/CY7C131; BUSY input on CY7C140/CY7C141•INT flag for port-to-port communication•Available in 48-pin DIP (CY7C130/140), 52-pin PLCC, 52-Pin TQFP .•Pb-Free packages availableFunctional DescriptionThe CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master dual-port RAM in conjunction with the CY7C140/CY7C141 slave dual-port device in systems requiring 16-bit or greater word widths. It is the solution to applications requiring shared or buffered data, such as cache memory for DSP , bit-slice, or multiprocessor designs.Each port has independent control pins; chip enable (CE), write enable (R/W), and output enable (OE). Two flags are provided on each port, BUSY and INT. BUSY signals that the port is trying to access the same location currently being accessed by the other port. INT is an interrupt flag indicating that data has been placed in a unique location (3FF for the left port and 3FE for the right port). An automatic power-down feature is controlled independently on each port by the chip enable (CE) pins.The CY7C130 and CY7C140 are available in 48-pin DIP . The CY7C131 and CY7C141 are available in 52-pin PLCC, 52-pin Pb-free PLCC, 52-pin PQFP and 52-pin Pb-free PQFP .Note:1.CY7C130/CY7C131 (Master): BUSY is open drain output and requires pull-up resistor2.Open drain outputs: pull-up resistor required.Logic Block DiagramPin Configurations131415161718192021222326272832313029333635342425GND123456789101138394044434241454847461237R/W L CE L BUSY L INT L OE L A 0L A 1L A 2L A 3L A 4L A 5L A 6L A 7L A 8L A 9L I/O 0L I/O 1L I/O 2L I/O 3L I/O 4L I/O 5L I/O 6L I/O 7L CE R R/W R BUSY R INT R OE R A 0R A 1R A 2R A 3R A 4R A 5R A 6R A 7R A 8R A 9R I/O 7R I/O 6R I/O 5R I/O 4R I/O 3R I/O 2R I/O 1R I/O 0RV CCDIP Top View7C1307C140R/W L BUSY LCE L OE LA 9L A 0LA 0RA 9R R/W R CE R OE RCE R OE R CE L OE L R/W LR/W RI/O 7L I/O 0L I/O 7R I/O 0R BUSY RINT LINT RARBITRATIONLOGIC(7C130/7C131ONLY)ANDINTERRUPT LOGICCONTROL I/O CONTROLI/O MEMORY ARRAYADDRESS DECODERADDRESS DECODER[1][2][2]Pin Configuration (continued )1V C CTop ViewPLCC OE R A 0R 8910111213141516171819204645444342414039383736353421222324252627282930313233765432525150494847A 1R A 2R A 3R A 4R A 5R A 6R A 7R A 8R A 9R NC I/O 7RA 1LA 2L A 3L A 4L A 5L A 6L A 7L A 8L A 9L I/O 0L I/O 1L I/O 2L I/O 3LI /O I /O I /O I /O I /O I /O I /O I /O I /O I /O I /O 4L 5L6L 7L0R 1R2R 3R 4R5R 6RN C G N DO E B U S Y I N T A N C R /W C E R /W B U S Y I N T N C0LL L LL L C E R R R R7C1317C14146123456789101112133938373635343332313029282714151617181920212223242526525150494847454443424140Top ViewPQFPV C CO E B U S Y I N T A N C R /W C E R /W B U S Y I N T N C0LL L LL L C E R R R ROE R A 0R A 1R A 2R A 3R A 4R A 5R A 6R A 7R A 8R A 9R NC I/O 7RA 1L A 2L A 3L A 4L A 5L A 6L A 7L A 8L A 9L I/O 0L I/O 1L I/O 2L I/O 3LI /O I /O I /O I /O I /O I /O I /O I /O I /O I /O I /O 4L 5L6L 7L0R 1R2R 3R 4R5R 6RN C G N D 7C1317C141Pin DefinitionsLeft PortRight PortDescriptionCE L CE R Chip Enable R/W L R/W R Read/Write Enable OE LOE ROutput Enable A 0L –A 11/12L A 0R –A 11/12R AddressI/O 0L –I/O 15/17L I/O 0R –I/O 15/17R Data Bus Input/Output INT L INT R Interrupt Flag BUSY L BUSY RBusy Flag V CC Power GNDGroundSelection Guide7C131-15[3]7C141-157C131-25[3]7C141-257C130-307C131-307C140-307C141-307C130-357C131-357C140-357C141-357C130-457C131-457C140-457C141-457C130-557C131-557C140-557C141-55Unit Maximum Access Time 152530354555ns Maximum Operating CurrentCom’l/Ind 190170170120120110mAMilitary 170170120Maximum Standby CurrentCom’l/Ind 756565454535mAMilitary656545Shaded areas contain preliminary information.Note:3.15 and 25-ns version available only in PLCC/PQFP packages.Maximum Ratings[4](Above which the useful life may be impaired. For user guide-lines, not tested.)Storage Temperature .................................–65°C to +150°C Ambient Temperature withPower Applied.............................................–55°C to +125°C Supply Voltage to Ground Potential(Pin 48 to Pin 24)...........................................–0.5V to +7.0V DC Voltage Applied to Outputsin High Z State...............................................–0.5V to +7.0V DC Input Voltage............................................–3.5V to +7.0V Output Current into Outputs (LOW).............................20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015)Latch-Up Current.................................................... >200 mA Operating RangeRangeAmbientTemperature V CC Commercial0°C to +70°C 5V ± 10% Industrial–40°C to +85°C 5V ± 10% Military[5]–55°C to +125°C 5V ± 10%Electrical Characteristics Over the Operating Range[6]Parameter Description Test Conditions 7C131-15[3]7C141-157C130-30[3]7C131-25,307C140-307C141-25,307C130-35,457C131-35,457C140-35,457C141-35,457C130-557C131-557C140-557C141-55Unit Min.Max.Min.Max.Min.Max.Min.Max.V OH Output HIGHVoltageV CC = Min., I OH = –4.0 mA 2.4 2.4 2.4 2.4VV OL Output LOWVoltage I OL = 4.0 mA0.40.40.40.4V I OL = 16.0 mA[7]0.50.50.50.5V IH Input HIGH Voltage 2.2 2.2 2.2 2.2V V IL Input LOW Voltage0.80.80.80.8V I IX Input LeakageCurrentGND < V I < V CC–5+5–5+5–5+5–5+5µAI OZ Output LeakageCurrent GND < V O < V CC,Output Disabled–5+5–5+5–5+5–5+5µAI OS Output ShortCircuit Current[8, 9]V CC = Max.,V OUT = GND–350–350–350–350mAI CC V CC OperatingSupply Current CE = V IL,Outputs Open,f = f MAX[10]Com’l190170120110mAMil170120I SB1Standby CurrentBoth Ports,TTL Inputs CE L and CE R >V IH, f = f MAX[10]Com’l75654535mAMil6545I SB2Standby CurrentOne Port,TTL Inputs CE L or CE R > V IH,Active Port OutputsOpen,f = f MAX[10]Com’l1351159075mAMil11590I SB3Standby CurrentBoth Ports,CMOS Inputs Both Ports CE L andCE R >V CC – 0.2V,V IN > V CC – 0.2Vor V IN < 0.2V, f = 0Com’l15151515mAMil1515Shaded areas contain preliminary information.Note:4.The Voltage on any input or I/O pin cannot exceed the power pin during power-up.5.T A is the “instant on” case temperature6.See the last page of this specification for Group A subgroup testing information.7.BUSY and INT pins only.8.Duration of the short circuit should not exceed 30 seconds.9.This parameter is guaranteed but not tested.10.At f = f MAX, address and data inputs are cycling at the maximum frequency of read cycle of 1/t RC and using AC Test Waveforms input levels of GND to 3V.I SB4Standby Current One Port, CMOS InputsOne Port CE L or CE R > V CC – 0.2V,V IN > V CC – 0.2V or V IN < 0.2V, Active Port Outputs Open, f = f MAX [10]Com’l 1251058570mAMil10585Capacitance [9]Parameter DescriptionTest ConditionsMax.Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V CC = 5.0V15pF C OUTOutput Capacitance10pFElectrical Characteristics Over the Operating Range [6] (continued)Parameter Description Test Conditions 7C131-15[3]7C141-157C130-30[3]7C131-25,307C140-307C141-25,307C130-35,457C131-35,457C140-35,457C141-35,457C130-557C131-557C140-557C141-55Unit Min.Max.Min.Max.Min.Max.Min.Max.AC Test Loads and Waveforms3.0V 5V OUTPUTR1 893ΩR2347Ω30pF INCLUDING JIGAND SCOPEGND90%90%10%≤ 5ns≤5ns5V OUTPUTR1 893ΩR2347Ω5pFINCLUDING JIGAND SCOPE(a)(b)OUTPUT1.40VEquivalent to:THÉVENIN EQUIVALENT5V 281Ω30pFBUSY OR INT(CY7C130/CY7C131ONLY)10%ALL INPUT PULSES 250ΩSwitching Characteristics Over the Operating Range[6, 11]Parameter Description7C131-15[3]7C141-157C130-25[3]7C131-257C140-257C141-257C130-307C131-307C140-307C141-30Unit Min.Max.Min.Max.Min.Max.READ CYCLEt RC Read Cycle Time152530ns t AA Address to Data Valid[12]152530ns t OHA Data Hold from Address Change000ns t ACE CE LOW to Data Valid[12]152530ns t DOE OE LOW to Data Valid[12]101520ns t LZOE OE LOW to Low Z[9, 13, 14]333ns t HZOE OE HIGH to High Z[9, 13, 14]101515ns t LZCE CE LOW to Low Z[9, 13, 14]355ns t HZCE CE HIGH to High Z[9, 13, 14]101515ns t PU CE LOW to Power-Up[9]000ns t PD CE HIGH to Power-Down[9]152525ns WRITE CYCLE[15]t WC Write Cycle Time152530ns t SCE CE LOW to Write End122025ns t AW Address Set-Up to Write End122025ns t HA Address Hold from Write End222ns t SA Address Set-Up to Write Start000ns t PWE R/W Pulse Width121525ns t SD Data Set-Up to Write End101515ns t HD Data Hold from Write End000ns t HZWE R/W LOW to High Z[14]101515ns t LZWE R/W HIGH to Low Z[14]000ns Shaded areas contain preliminary information.Note:11.Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specifiedI OL/I OH, and 30-pF load capacitance.12.AC Test Conditions use V OH = 1.6V and V OL = 1.4V.13.At any given temperature and voltage condition for any given device, t HZCE is less than t LZCE and t HZOE is less than t LZOE.14.t LZCE, t LZWE, t HZOE, t LZOE, t HZCE and t HZWE are tested with C L = 5pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.15.The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be low to initiate a write and either signal canterminate a write by going high. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.BUSY/INTERRUPT TIMING t BLA BUSY LOW from Address Match 152020ns t BHA BUSY HIGH from Address Mismatch [16]152020ns t BLC BUSY LOW from CE LOW 152020ns t BHC BUSY HIGH from CE HIGH [16]152020ns t PS Port Set Up for Priority 555ns t WB [17]R/W LOW after BUSY LOW 000ns t WH R/W HIGH after BUSY HIGH 132030ns t BDD BUSY HIGH to Valid Data152530ns t DDD Write Data Valid to Read Data Valid Note 18Note 18Note 18ns t WDD Write Pulse to Data Delay Note 18Note 18Note 18ns INTERRUPT TIMINGt WINS R/W to INTERRUPT Set Time 152525ns t EINS CE to INTERRUPT Set Time 152525ns t INS Address to INTERRUPT Set Time 152525ns t OINR OE to INTERRUPT Reset Time [16]152525ns t EINR CE to INTERRUPT Reset Time [16]152525ns t INRAddress to INTERRUPT Reset Time [16]152525nsShaded areas contain preliminary information.Note:16.These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.17.CY7C140/CY7C141 only.18.A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:BUSY on Port B goes HIGH. Port B’s address is toggled. CE for Port B is toggled.R/W for Port B is toggled during valid read.Switching Characteristics Over the Operating Range [6, 11] (continued)ParameterDescription7C131-15[3]7C141-157C130-25[3]7C131-257C140-257C141-257C130-307C131-307C140-307C141-30UnitMin.Max.Min.Max.Min.Max.Switching Characteristics Over the Operating Range [6,11]Parameter Description7C130-357C131-357C140-357C141-357C130-457C131-457C140-457C141-457C130-557C131-557C140-557C141-55UnitMin.Max.Min.Max.Min.Max.READ CYCLE t RC Read Cycle Time 354555ns t AA Address to Data Valid [12]354555ns t OHA Data Hold from Address Change 0ns t ACE CE LOW to Data Valid [12]354555ns t DOE OE LOW to Data Valid [12]202525ns t LZOE OE LOW to Low Z [9, 13, 14]333ns t HZOE OE HIGH to High Z [9, 13, 14]202025ns t LZCECE LOW to Low Z [9, 13, 14]555nst HZCE CE HIGH to High Z [9, 13, 14]202025ns t PU CE LOW to Power-Up [9]0ns t PD CE HIGH to Power-Down [9]353535ns WRITE CYCLE [15]t WC Write Cycle Time 354555ns t SCE CE LOW to Write End 303540ns t AW Address Set-Up to Write End 303540ns t HA Address Hold from Write End 222ns t SA Address Set-Up to Write Start 000ns t PWE R/W Pulse Width253030ns t SD Data Set-Up to Write End 152020ns t HD Data Hold from Write End 0ns t HZWE R/W LOW to High Z [14]202025ns t LZWE R/W HIGH to Low Z [14]ns BUSY/INTERRUPT TIMINGt BLA BUSY LOW from Address Match 202530ns t BHA BUSY HIGH from Address Mismatch [16]202530ns t BLC BUSY LOW from CE LOW 202530ns t BHC BUSY HIGH from CE HIGH [16]202530ns t PS Port Set Up for Priority 555ns t WB [17]R/W LOW after BUSY LOW 000ns t WH R/W HIGH after BUSY HIGH 303535ns t BDD BUSY HIGH to Valid Data354545ns t DDD Write Data Valid to Read Data Valid Note 18Note 18Note 18ns t WDDWrite Pulse to Data DelayNote 18Note 18Note 18nsINTERRUPT TIMING t WINS R/W to INTERRUPT Set Time 253545ns t EINS CE to INTERRUPT Set Time 253545ns t INS Address to INTERRUPT Set Time 253545ns t OINR OE to INTERRUPT Reset Time [16]253545ns t EINR CE to INTERRUPT Reset Time [16]253545ns t INRAddress to INTERRUPT Reset Time [16]253545nsSwitching Characteristics Over the Operating Range [6,11] (continued)Parameter Description7C130-357C131-357C140-357C141-357C130-457C131-457C140-457C141-457C130-557C131-557C140-557C141-55Unit Min.Max.Min.Max.Min.Max.Switching WaveformsRead Cycle No. 1[19, 20]Read Cycle No. 2[19, 21]Read Cycle No. 3[20]Notes:19.R/W is HIGH for read cycle.20.Device is continuously selected, CE = V IL and OE = V IL .21.Address valid prior to or coincident with CE transition LOW.t RCt AAt OHADATA VALIDPREVIOUS DATA VALIDDATA OUTADDRESSEither Port Address Accesst ACEt LZOEt DOEt HZOEt HZCEDATA VALIDDATA OUTCE OEt LZCEt PUI CC I SBt PDEither Port CE/OE Accesst BHAt BDDVALIDt DDDt WDDADDRESS MATCHADDRESS MATCHR/W R ADDRESS RD INRADDRESS LBUSY LDOUT Lt PSt BLARead with BUSY , Master: CY7C130 and CY7C131t RCt PWEVALIDt HDWrite Cycle No. 1 (OE Three-States Data I/Os—Either Port [15, 22]Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)[16, 23]Notes:22.PWE or t HZWE + t SD to allow the data I/O pins to enter high impedanceand for data to be placed on the bus for the required t SD .23.If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.Switching Waveforms (continued)t AWt WCDATA VALIDHIGH IMPEDANCEt SCEt SAt PWEt HDt SDt HACER/WADDRESSt HZOEOED OUTDATA INEither Portt AWt WCt SCEt SAt PWEt HDt SDt HZWEt HAHIGH IMPEDANCEDATA VALIDt LZWEADDRESSCER/WDATA OUTDATA INBusy Timing Diagram No. 1 (CE Arbitration)Busy Timing Diagram No. 2 (Address Arbitration)Switching Waveforms (continued)ADDRESS MATCHt PSCE L Valid First:t BLCt BHCADDRESS MATCHt PSt BLCt BHCADDRESS L,RBUSY RCE LCE RBUSY LCE RCE LADDRESS L,RCE R Valid First:Left Address Valid First:ADDRESS MATCHt PSADDRESS LBUSY RADDRESS MISMATCHt RC or t WC t BLA t BHAADDRESS RADDRESS MATCHADDRESS MISMATCHt PSADDRESS LBUSY Lt RC or t WC t BLA t BHAADDRESS RRight Address Valid First:Switching Waveforms (continued)Busy Timing Diagram No. 3Write with BUSY (Slave:CY7C140/CY7C141)CEt PWER/Wt WB t WH BUSYInterrupt Timing Diagrams Switching Waveforms (continued)WRITE 3FFt INSt WCt EINSRight Side Clears INT Rt HAt SAt WINSREAD 3FF t RCt EINRt HAt INTt OINRWRITE 3FEt INSt WCt EINSt HAt SAt WINSRight Side Sets INT LLeft Side Sets INT RLeft Side Clears INT LREAD 3FE t EINRt HAt INRt OINRt RC ADDR RCE LR/W L INT LOE LADDR RR/W R CE RINT LADDR RCE RR/W R INT ROE RADDR LR/W LCE LINT RTypical DC and AC Characteristics1.41.00.44.04.55.05.56.0–55251251.21.01201008060402001.02.03.04.0O U T P U T S O U R C E C U R R E N T (m A )SUPPLY VOLTAGE (V)NORMALIZED SUPPLY CURRENTvs. SUPPLY VOLTAGENORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE AMBIENT TEMPERATURE (°C)OUTPUT VOLTAGE (V)OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 0.00.80.80.60.6N O R M A L I Z E D I C C , I S BV CC = 5.0V V IN = 5.0V V CC = 5.0V T A = 25°C0I CC1.61.41.21.00.8–55125N O R M A L I Z E D t A ANORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE AMBIENT TEMPERATURE (°C)1.41.31.21.00.94.04.55.05.56.0N O R M A L I Z E D t A ASUPPLY VOLTAGE (V)NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 120140*********0.01.02.03.04.0O U T P U T S I N K C U R R E N T (m A )080OUTPUT VOLTAGE (V)OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE0.60.8 1.251.00.751040N O R M A L I Z E D I C C0.50NORMALIZED I CC vs. CYCLE TIME CYCLE FREQUENCY (MHz)3.02.52.01.50.501.02.03.05.0N O R M A L I Z E D t P C25.030.020.010.05.00200400600800D E L T A t A A (n s )015.00.0SUPPLY VOLTAGE (V)TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE CAPACITANCE (pF)TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING4.010001.020300.20.61.2I SB30.20.4251.1V V IN = 0.5VN O R M A L I Z E D I C C , I S BI CCI SB3T A = 25°CV CC = 5.0VV CC = 5.0V T A = 25°CT A = 25°CCC = 4.5V V CC = 4.5V T A = 25°COrdering InformationSpeed(ns)Ordering Code PackageName Package TypeOperatingRange30CY7C130-30PC P2548-Lead (600-Mil) Molded DIP Commercial CY7C130-30PI P2548-Lead (600-Mil) Molded DIP Industrial 35CY7C130-35PC P2548-Lead (600-Mil) Molded DIP Commercial CY7C130-35PI P2548-Lead (600-Mil) Molded DIP Industrial CY7C130-35DMB D2648-Lead (600-Mil) Sidebraze DIP Military45CY7C130-45PC P2548-Lead (600-Mil) Molded DIP Commercial CY7C130-45PI P2548-Lead (600-Mil) Molded DIP Industrial CY7C130-45DMB D2648-Lead (600-Mil) Sidebraze DIP Military55CY7C130-55PC P2548-Lead (600-Mil) Molded DIP Commercial CY7C130-55PI P2548-Lead (600-Mil) Molded DIP Industrial CY7C130-55DMB D2648-Lead (600-Mil) Sidebraze DIP Military15CY7C131-15JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C131-15JXC J6952-Lead Pb-Free Plastic Leaded Chip CarrierCY7C131-15NC N5252-Pin Plastic Quad FlatpackCY7C131-15JI J6952-Lead Plastic Leaded Chip Carrier Industrial CY7C131-15JXI J6952-Lead Pb-Free Plastic Leaded Chip Carrier25CY7C131-25JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C131-25JXC J6952-Lead Pb-Free Plastic Leaded Chip CarrierCY7C131-25NC N5252-Pin Plastic Quad FlatpackCY7C131-25NXC N5252-Pin Pb-Free Plastic Quad FlatpackCY7C131-25JI J6952-Lead Plastic Leaded Chip Carrier Industrial CY7C131-25NI N5252-Pin Plastic Quad Flatpack30CY7C131-30JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C131-30NC N5252-Pin Plastic Quad FlatpackCY7C131-30JI J6952-Lead Plastic Leaded Chip Carrier Industrial 35CY7C131-35JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C131-35NC N5252-Pin Plastic Quad FlatpackCY7C131-35JI J6952-Lead Plastic Leaded Chip Carrier Industrial CY7C131-35NI N5252-Pin Plastic Quad Flatpack45CY7C131-45JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C131-45NC N5252-Pin Plastic Quad FlatpackCY7C131-45JI J6952-Lead Plastic Leaded Chip Carrier Industrial CY7C131-45NI N5252-Pin Plastic Quad Flatpack55CY7C131-55JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C131-55JXC J6952-Lead Pb-Free Plastic Leaded Chip CarrierCY7C131-55NC N5252-Pin Plastic Quad FlatpackCY7C131-55NXC N5252-Pin Pb-Free Plastic Quad FlatpackCY7C131-55JI J6952-Lead Plastic Leaded Chip Carrier Industrial CY7C131-55JXI J6952-Lead Pb-Free Plastic Leaded Chip CarrierCY7C131-55NI N5252-Pin Plastic Quad Flatpack30CY7C140-30PC P2548-Lead (600-Mil) Molded DIP Commercial CY7C140-30PI P2548-Lead (600-Mil) Molded DIP Industrial 35CY7C140-35PC P2548-Lead (600-Mil) Molded DIP Commercial CY7C140-35PI P2548-Lead (600-Mil) Molded DIP Industrial CY7C140-35DMBD2648-Lead (600-Mil) Sidebraze DIP Military 45CY7C140-45PC P2548-Lead (600-Mil) Molded DIP Commercial CY7C140-45PI P2548-Lead (600-Mil) Molded DIP Industrial CY7C140-45DMBD2648-Lead (600-Mil) Sidebraze DIP Military 55CY7C140-55PC P2548-Lead (600-Mil) Molded DIP Commercial CY7C140-55PI P2548-Lead (600-Mil) Molded DIP Industrial CY7C140-55DMBD2648-Lead (600-Mil) Sidebraze DIP Military 15CY7C141-15JC J6952-Lead Plastic Leaded Chip Carrier CommercialCY7C141-15NC N5252-Pin Plastic Quad Flatpack 25CY7C141-25JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C141-25JXC J6952-Lead Pb-Free Plastic Leaded Chip Carrier CY7C141-25NC N5252-Pin Plastic Quad Flatpack CY7C141-25JI J6952-Lead Plastic Leaded Chip Carrier Industrial CY7C141-25NIN5252-Pin Plastic Quad Flatpack 30CY7C141-30JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C141-30NC N5252-Pin Plastic Quad Flatpack CY7C141-30JIJ6952-Lead Plastic Leaded Chip Carrier Industrial 35CY7C141-35JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C141-35NC N5252-Pin Plastic Quad Flatpack CY7C141-35JI J6952-Lead Plastic Leaded Chip Carrier Industrial CY7C141-35NIN5252-Pin Plastic Quad Flatpack 45CY7C141-45JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C141-45NC N5252-Pin Plastic Quad Flatpack CY7C141-45JI J6952-Lead Plastic Leaded Chip Carrier Industrial CY7C141-45NIN5252-Pin Plastic Quad Flatpack 55CY7C141-55JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C141-55NC N5252-Pin Plastic Quad Flatpack CY7C141-55JI J6952-Lead Plastic Leaded Chip Carrier Industrial CY7C141-55NIN5252-Pin Plastic Quad FlatpackOrdering Information (continued)Speed (ns)Ordering Code Package Name Package TypeOperating RangeMILITARY SPECIFICATIONS Group A Subgroup Testing Note:24.CY7C140/CY7C141 only.DC CharacteristicsParameterSubgroups V OH 1, 2, 3V OL 1, 2, 3V IH 1, 2, 3V IL Max.1, 2, 3I IX 1, 2, 3I OZ 1, 2, 3I CC 1, 2, 3I SB11, 2, 3I SB21, 2, 3I SB31, 2, 3I SB41, 2, 3Switching CharacteristicsParameterSubgroups READ CYCLEt RC 7, 8, 9, 10, 11t AA 7, 8, 9, 10, 11t ACE 7, 8, 9, 10, 11t DOE7, 8, 9, 10, 11WRITE CYCLEt WC 7, 8, 9, 10, 11t SCE 7, 8, 9, 10, 11t AW 7, 8, 9, 10, 11t HA 7, 8, 9, 10, 11t SA 7, 8, 9, 10, 11t PWE 7, 8, 9, 10, 11t SD 7, 8, 9, 10, 11t HD7, 8, 9, 10, 11BUSY/INTERRUPT TIMINGt BLA 7, 8, 9, 10, 11t BHA 7, 8, 9, 10, 11t BLC 7, 8, 9, 10, 11t BHC 7, 8, 9, 10, 11t PS 7, 8, 9, 10, 11t WINS 7, 8, 9, 10, 11t EINS 7, 8, 9, 10, 11t INS 7, 8, 9, 10, 11t OINR 7, 8, 9, 10, 11t EINR 7, 8, 9, 10, 11t INR7, 8, 9, 10, 11BUSY TIMINGt WB [24]7, 8, 9, 10, 11t WH 7, 8, 9, 10, 11t BDD7, 8, 9, 10, 11Package Diagrams48-Lead (600-Mil) Sidebraze DIP D26MIL-STD-1835 D-14 Config. C51-80044 **Document #: 38-06002 Rev. *DPage 18 of 19All products and company names mentioned in this document may be the trademarks of their respective holders.Package Diagrams (continued)51-85020-*A48-Lead (600-Mil) Molded DIP P2551-85042-**52-Lead Pb-Free Plastic Quad Flatpack N5252-Lead Plastic Quad Flatpack N52Document History PageDocument Title: CY7C130/CY7C131/CY7C140/CY7C141 1K x 8 Dual-Port Static RAM Document Number: 38-06002REV.ECN NO.IssueDateOrig. ofChange Description of Change**11016909/29/01SZV Change from Spec number: 38-00027 to 38-06002*A12225512/26/02RBI Power up requirements added to Maximum Ratings Information*B236751See ECN YDT Removed cross information from features section*C325936See ECN RUY Added pin definitions table, 52-pin PQFP package diagram and Pb-freeinformation*D393153See ECN YIM Added CY7C131-15JI to ordering informationAdded Pb-Free parts to ordering information:CY7C131-15JXI。
CY7C68013A-128AXC中文资料
• CY7C68016A: Ideal for battery powered applications — Suspend current: 100 µA (typ) • CY7C68015A: Ideal for non-battery powered applications — Suspend current: 300 µA (typ) • Available in lead-free 56-pin QFN package (26 GPIOs) — 2 more GPIOs than CY7C68013A/14A enabling additional features in same footprint Cypress Semiconductor Corporation’s (Cypress’s) EZ-USB FX2LP (CY7C68013A/14A) is a low-power version of the EZ-USB FX2 (CY7C68013), which is a highly integrated, low-power USB 2.0 microcontroller. By integrating the USB 2.0 transceiver, serial interface engine (SIE), enhanced 8051 microcontroller, and a programmable peripheral interface in a single chip, Cypress has created a very cost-effective solution that provides superior time-to-market advantages with low power to enable bus powered applications. The ingenious architecture of FX2LP results in data transfer rates of over 53 Mbytes per second, the maximum-allowable USB 2.0 bandwidth, while still using a low-cost 8051 microcontroller in a package as small as a 56 QFN. Because it incorporates the USB 2.0 transceiver, the FX2LP is more economical, providing a smaller footprint solution than USB 2.0 SIE or external transceiver implementations. With EZ-USB FX2LP, the Cypress Smart SIE handles most of the USB 1.1 and 2.0 protocol in hardware, freeing the embedded microcontroller for application-specific functions and decreasing development time to ensure USB compatibility. The General Programmable Interface (GPIF) and Master/Slave Endpoint FIFO (8- or 16-bit data bus) provides
CY7C67300-100AI资料
CY7C67300 EZ-Host™ Programmable EmbeddedUSB Host/Peripheral ControllerTABLE OF CONTENTS1.0 INTRODUCTION (10)1.1 EZ-Host Features (10)2.0 TYPICAL APPLICATIONS (11)3.0 FUNCTIONAL OVERVIEW (11)3.1 Processor Core (11)3.1.1 Processor (11)3.1.2 Clocking (11)3.1.3 Memory (11)3.1.4 Interrupts (11)3.1.5 General Timers and Watchdog Timer (11)3.1.6 Power Management (11)4.0 INTERFACE DESCRIPTIONS (11)4.1 USB Interface (13)4.1.1 USB Features (13)4.1.2 USB Pins. (14)4.2 OTG Interface (14)4.2.1 OTG Features (14)4.2.2 OTG Pins. (14)4.3 External Memory Interface (14)4.3.1 External Memory Interface Features (14)4.3.2 External Memory Access Strobes (14)4.3.3 Page Registers (15)4.3.4 Merge Mode (15)4.3.5 Program Memory Hole Description (15)4.3.6 DMA to External Memory Prohibited (15)4.3.7 External Memory Interface Pins (16)4.3.8 External Memory Interface Block Diagrams (17)4.4 General Purpose I/O Interface (GPIO) (18)4.4.1 GPIO Description (18)4.4.2 Unused Pin Descriptions (18)4.5 UART Interface (18)4.5.1 UART Features (18)4.5.2 UART Pins. (18)4.6 I2C EEPROM Interface (18)4.6.1 I2C EEPROM Features (18)4.6.2 I2C EEPROM Pins. (18)4.7 Serial Peripheral Interface (18)4.7.1 SPI Features (19)4.7.2 SPI Pins (19)4.8 High-speed Serial Interface (19)4.8.1 HSS Features (19)4.8.2 HSS Pins (20)4.9 Programmable Pulse/PWM Interface (20)4.9.1 Programmable Pulse/PWM Features (20)4.9.2 Programmable Pulse/PWM Pins. (20)4.10 Host Port Interface (20)4.10.1 HPI Features (20)4.10.2 HPI Pins. (21)TABLE OF CONTENTS (continued)4.11 IDE Interface (21)4.11.1 IDE Features (22)4.11.2 IDE Pins (22)4.12 Charge Pump Interface (22)4.12.1 Charge Pump Features (23)4.12.2 Charge Pump Pins. (23)4.13 Booster Interface (23)4.13.1 Booster Pins. (24)4.14 Crystal Interface (25)4.14.1 Crystal Pins (25)4.15 Boot Configuration Interface (25)4.16 Operational Modes (26)4.16.1 Coprocessor Mode (26)4.16.2 Standalone Mode (26)5.0 POWER-SAVINGS AND RESET DESCRIPTION (27)5.1 Power-Savings Mode Description (27)5.2 Sleep (27)5.3 External (Remote) wakeup Source (27)5.4 Power-On-Reset Description (27)5.5 Reset Pin (27)5.6 USB Reset (27)6.0 MEMORY MAP (28)6.1 Mapping (28)6.1.1 Internal Memory (28)6.1.2 External Memory (28)7.0 REGISTERS (30)7.1 Processor Control Registers (30)7.1.1 CPU Flags Register [0xC000] [R] (30)7.1.2 Bank Register [0xC002] [R/W] (31)7.1.3 Hardware Revision Register [0xC004] [R] (31)7.1.4 CPU Speed Register [0xC008] [R/W] (32)7.1.5 Power Control Register [0xC00A] [R/W] (33)7.1.6 Interrupt Enable Register [0xC00E] [R/W] (35)7.1.7 Breakpoint Register [0xC014] [R/W] (36)7.1.8 USB Diagnostic Register [0xC03C] [R/W] (37)7.1.9 Memory Diagnostic Register [0xC03E] [W] (38)7.2 External Memory Registers (39)7.2.1 Extended Page n Map Register [R/W] (39)7.2.2 Upper Address Enable Register [0xC038] [R/W] (39)7.2.3 External Memory Control Register [0xC03A] [R/W] (40)7.3 Timer Registers (41)7.3.1 Watchdog Timer Register [0xC00C] [R/W] (41)7.3.2 Timer n Register [R/W] (42)7.4 General USB Registers (42)7.4.1 USB n Control Register [R/W] (42)7.5 USB Host Only Registers (45)7.5.1 Host n Control Register [R/W] (45)7.5.2 Host n Address Register [R/W] (46)TABLE OF CONTENTS (continued)7.5.3 Host n Count Register [R/W] (46)7.5.4 Host n Endpoint Status Register [R] (47)7.5.5 Host n PID Register [W] (48)7.5.6 Host n Count Result Register [R] (49)7.5.7 Host n Device Address Register [W] (50)7.5.8 Host n Interrupt Enable Register [R/W] (50)7.5.9 Host n Status Register [R/W] (52)7.5.10 Host n SOF/EOP Count Register [R/W] (53)7.5.11 Host n SOF/EOP Counter Register [R] (53)7.5.12 Host n Frame Register [R] (54)7.6 USB Device Only Registers (54)7.6.1 Device n Endpoint n Control Register [R/W] (55)7.6.2 Device n Endpoint n Address Register [R/W] (56)7.6.3 Device n Endpoint n Count Register [R/W] (57)7.6.4 Device n Endpoint n Status Register [R/W] (57)7.6.5 Device n Endpoint n Count Result Register [R/W] (59)7.6.6 Device n Port Select Register [R/W] (60)7.6.7 Device n Interrupt Enable Register [R/W] (60)7.6.8 Device n Address Register [W] (63)7.6.9 Device n Status Register [R/W] (63)7.6.10 Device n Frame Number Register [R] (65)7.6.11 Device n SOF/EOP Count Register [W] (66)7.7 OTG Control Registers (66)7.7.1 OTG Control Register [0xC098] [R/W] (66)7.8 GPIO Registers (68)7.8.1 GPIO Control Register [0xC006] [R/W] (68)7.8.2 GPIO n Output Data Register [R/W] (70)7.8.3 GPIO n Input Data Register [R] (70)7.8.4 GPIO n Direction Register [R/W] (71)7.9 IDE Registers (71)7.9.1 IDE Mode Register [0xC048] [R/W] (71)7.9.2 IDE Start Address Register [0xC04A] [R/W] (72)7.9.3 IDE Stop Address Register [0xC04C] [R/W] (72)7.9.4 IDE Control Register [0xC04E] [R/W] (73)7.9.5 IDE PIO Port Registers [0xC050 - 0xC06F] [R/W] (74)7.10 HSS Registers (74)7.10.1 HSS Control Register [0xC070] [R/W] (75)7.10.2 HSS Baud Rate Register [0xC072] [R/W] (77)7.10.3 HSS Transmit Gap Register [0xC074] [R/W] (77)7.10.4 HSS Data Register [0xC076] [R/W] (78)7.10.5 HSS Receive Address Register [0xC078] [R/W] (78)7.10.6 HSS Receive Counter Register [0xC07A] [R/W] (79)7.10.7 HSS Transmit Address Register [0xC07C] [R/W] (79)7.10.8 HSS Transmit Counter Register [0xC07E] [R/W] (79)7.11 HPI Registers (80)7.11.1 HPI Breakpoint Register [0x0140] [R] (80)7.11.2 Interrupt Routing Register [0x0142] [R] (81)7.11.3 SIEXmsg Register [W] (82)7.11.4 HPI Mailbox Register [0xC0C6] [R/W] (83)7.11.5 HPI Status Port [] [HPI: R] (83)TABLE OF CONTENTS (continued)7.12 SPI Registers (85)7.12.1 SPI Configuration Register [0xC0C8] [R/W] (86)7.12.2 SPI Control Register [0xC0CA] [R/W] (87)7.12.3 SPI Interrupt Enable Register [0xC0CC] [R/W] (89)7.12.4 SPI Status Register [0xC0CE] [R] (89)7.12.5 SPI Interrupt Clear Register [0xC0D0] [W] (90)7.12.6 SPI CRC Control Register [0xC0D2] [R/W] (91)7.12.7 SPI CRC Value Register [0xC0D4] [R/W] (92)7.12.8 SPI Data Register [0xC0D6] [R/W] (92)7.12.9 SPI Transmit Address Register [0xC0D8] [R/W] (93)7.12.10 SPI Transmit Count Register [0xC0DA] [R/W] (93)7.12.11 SPI Receive Address Register [0xC0DC [R/W] (93)7.12.12 SPI Receive Count Register [0xC0DE] [R/W] (94)7.13 UART Registers (94)7.13.1 UART Control Register [0xC0E0] [R/W] (94)7.13.2 UART Status Register [0xC0E2] [R] (95)7.13.3 UART Data Register [0xC0E4] [R/W] (96)7.14 PWM Registers (96)7.14.1 PWM Control Register [0xC0E6] [R/W] (97)7.14.2 PWM Maximum Count Register [0xC0E8] [R/W] (98)7.14.3 PWM n Start Register [R/W] (99)7.14.4 PWM n Stop Register [R/W] (99)7.14.5 PWM Cycle Count Register [0xC0FA] [R/W] (100)8.0 PIN DIAGRAM (101)9.0 PIN DESCRIPTIONS (101)10.0 ABSOLUTE MAXIMUM RATINGS (105)11.0 OPERATING CONDITIONS (105)12.0 CRYSTAL REQUIREMENTS (XTALIN, XTALOUT) (105)13.0 DC CHARACTERISTICS (105)13.1 USB Transceiver (106)14.0 AC TIMING CHARACTERISTICS (107)14.1 Reset Timing (107)14.2 Clock Timing (107)14.3 SRAM Read Cycle (108)14.4 SRAM Write Cycle (109)14.5 I2C EEPROM Timing (110)14.6 HPI (Host Port Interface) Write Cycle Timing (111)14.7 HPI (Host Port Interface) Read Cycle Timing (112)14.8 IDE Timing (113)14.9 HSS BYTE Mode Transmit (113)14.10 HSS Block Mode Transmit (113)14.11 HSS BYTE and BLOCK Mode Receive (113)14.12 Hardware CTS/RTS Handshake (114)15.0 REGISTERS SUMMARY (114)16.0 ORDERING INFORMATION (118)17.0 PACKAGE DIAGRAMS (118)LIST OF FIGURESFigure 1-1. Block Diagram (10)Figure 4-1. Page n Registers External Address Pins Logic (15)Figure 4-2. Interfacing to 64k × 8 Memory Array (17)Figure 4-3. Interfacing up to 256k × 16 for External Code/Data (17)Figure 4-4. Interfacing up to 512k × 8 for External Code/Data (17)Figure 4-5. Charge Pump (23)Figure 4-6. Power Supply Connection With Booster (24)Figure 4-7. Power Supply Connection Without Booster (24)Figure 4-8. Crystal Interface (25)Figure 4-9. Minimum Standalone Hardware Configuration – Peripheral Only (26)Figure 6-1. Memory Map (29)Figure 7-1. Processor Control Registers (30)Figure 7-2. CPU Flags Register (30)Figure 7-3. Bank Register (31)Figure 7-4. Revision Register (31)Figure 7-5. CPU Speed Register (32)Figure 7-6. Power Control Register (33)Figure 7-7. Interrupt Enable Register (35)Figure 7-8. Breakpoint Register (36)Figure 7-9. USB Diagnostic Register (37)Figure 7-10. Memory Diagnostic Register (38)Figure 7-11. External Memory Control Registers (39)Figure 7-12. Extended Page n Map Register (39)Figure 7-13. External Memory Control Register (39)Figure 7-14. External Memory Control Register (40)Figure 7-15. Timer Registers (41)Figure 7-16. Watchdog Timer Register (41)Figure 7-17. Timer n Register (42)Figure 7-18. General USB Registers (42)Figure 7-19. USB n Control Register (43)Figure 7-20. USB Host Only Register (45)Figure 7-21. Host n Control Register (45)Figure 7-22. Host n Address Register (46)Figure 7-23. Host n Count Register (46)Figure 7-24. Host n Endpoint Status Register (47)Figure 7-25. Host n PID Register (49)Figure 7-26. Host n Count Result Register (49)Figure 7-27. Host n Device Address Register (50)Figure 7-28. Host n Interrupt Enable Register (50)Figure 7-29. Host n Status Register (52)Figure 7-30. Host n SOF/EOP Count Register (53)Figure 7-31. Host n SOF/EOP Counter Register (54)Figure 7-32. Host n Frame Register (54)Figure 7-33. USB Device Only Registers (55)Figure 7-34. Device n Endpoint n Control Register (55)Figure 7-35. Device n Endpoint n Address Register (57)Figure 7-36. Device n Endpoint n Count Register (57)Figure 7-37. Device n Endpoint n Status Register (58)Figure 7-38. Device n Endpoint n Count Result Register (60)LIST OF FIGURES (continued)Figure 7-39. Device n Port Select Register (60)Figure 7-40. Device n Interrupt Enable Register (61)Figure 7-41. Device n Address Register (63)Figure 7-42. Device n Status Register (63)Figure 7-43. Device n Frame Number Register (65)Figure 7-44. Device n SOF/EOP Count Register (66)Figure 7-45. OTG Registers (66)Figure 7-46. OTG Control Register (66)Figure 7-47. GPIO Registers (68)Figure 7-48. GPIO Control Register (68)Figure 7-49. GPIO n Output Data Register (70)Figure 7-50. GPIO n Input Data Register (70)Figure 7-51. GPIO n Direction Register (71)Figure 7-52. IDE Registers (71)Figure 7-53. IDE Mode Register (71)Figure 7-54. IDE Start Address Register (72)Figure 7-55. IDE Stop Address Register (72)Figure 7-56. IDE Control Register (73)Figure 7-57. HSS Registers (74)Figure 7-58. HSS Control Register (75)Figure 7-59. HSS Baud Rate Register (77)Figure 7-60. HSS Transmit Gap Register (77)Figure 7-61. HSS Data Register (78)Figure 7-62. HSS Receive Address Register (78)Figure 7-63. HSS Receive Counter Register (79)Figure 7-64. HSS Transmit Address Register (79)Figure 7-65. HSS Transmit Counter Register (79)Figure 7-66. HPI Registers (80)Figure 7-67. HPI Breakpoint Register (80)Figure 7-68. Interrupt Routing Register (81)Figure 7-69. SIEXmsg Register (82)Figure 7-70. HPI Mailbox Register (83)Figure 7-71. HPI Status Port (83)Figure 7-72. SPI Registers (85)Figure 7-73. SPI Configuration Register (86)Figure 7-74. SPI Control Register (87)Figure 7-75. SPI Interrupt Enable Register (89)Figure 7-76. SPI Status Register (89)Figure 7-77. SPI Interrupt Clear Register (90)Figure 7-78. SPI CRC Control Register (91)Figure 7-79. SPI CRC Value Register (92)Figure 7-80. SPI Data Register (92)Figure 7-81. SPI Transmit Address Register (93)Figure 7-82. SPI Transmit Count Register (93)Figure 7-83. SPI Receive Address Register (93)Figure 7-84. SPI Receive Count Register (94)Figure 7-85. UART Registers (94)Figure 7-86. UART Control Register (94)Figure 7-87. UART Status Register (95)LIST OF FIGURES (continued)Figure 7-88. UART Data Register (96)Figure 7-89. PWM Registers (96)Figure 7-90. PWM Control Register (97)Figure 7-91. PWM Maximum Count Register (98)Figure 7-92. PWM n Start Register (99)Figure 7-93. PWM n Stop Register (99)Figure 7-94. PWM Cycle Count Register (100)Figure 8-1. EZ-Host Pin Diagram (101)LIST OF TABLESTable 4-1. Interface Options for GPIO Pins (12)Table 4-2. Interface Options for External Memory Bus Pins (12)Table 4-3. USB Port Configuration Options (13)Table 4-4. USB Interface Pins (14)Table 4-5. OTG Interface Pins (14)Table 4-6. External Memory Interface Pins (16)Table 4-7. UART Interface Pins (18)Table 4-8. I2C EEPROM Interface Pins (18)Table 4-9. SPI Interface Pins (19)Table 4-10. HSS Interface Pins (20)Table 4-11. PWM Interface Pins (20)Table 4-12. HPI Interface Pins (21)Table 4-13. HPI Addressing (21)Table 4-14. IDE Throughput (22)Table 4-15. IDE Interface Pins (22)Table 4-16. Charge Pump Interface Pins (23)Table 4-17. Charge Pump Interface Pins (24)Table 4-18. Crystal Pins (25)Table 4-19. Boot Configuration Interface (25)Table 5-1. Wakeup Sources (27)Table 7-1. Bank Register Example (31)Table 7-2. CPU Speed Definition (32)Table 7-3. Force Select Definition (38)Table 7-4. Memory Arbitration Select (38)Table 7-5. Period Select Definition (41)Table 7-6. USB Data Line Pull-up and Pull-down Resistors (44)Table 7-7. Port A/B Force D± State (44)Table 7-8. Port Select Definition (47)Table 7-9. PID Select Definition (49)Table 7-10. Mode Select Definition (69)Table 7-11. Mode Select Definition (72)Table 7-12. IDE PIO Port Registers (74)Table 7-13. Scale Select Field Definition for SCK Frequency (86)Table 7-14. CRC Mode Definition (91)Table 7-15. UART Baud Select Definition (95)Table 7-16. Prescaler Select Definition (97)Table 9-1. Pin Descriptions (101)Table 12-1. Crystal Requirements (105)Table 13-1. DC Characteristics (105)Table 13-2. DC Characteristics: Charge Pump (106)Table 15-1. Register Summary (114)Table 16-1. Ordering Information (118)1.0 INTRODUCTIONEZ-Host™ (CY7C67300) is Cypress Semiconductor’s first full-speed, low-cost multiport host/peripheral controller. EZ-Host is designed to easily interface to most high-performance CPUs to add USB host functionality. EZ-Host has its own 16-bit RISC processor to act as a coprocessor or operate in standalone mode. EZ-Host also has a programmable I/O interface block allowing a wide range of interface options.Figure 1-1. Block Diagram1.1EZ-Host Features•Single-chip programmable USB dual-role (Host/Peripheral) controller with two configurable Serial Interface Engines (SIEs) and four USB ports•Support for USB On-The-Go (OTG) protocol•On-chip 48-MHz 16-bit processor with dynamically switchable clock speed•Configurable I/O block supporting a variety of I/O options or up to 32 bits of General Purpose I/O (GPIO)•4K x 16 internal masked ROM containing built-in BIOS that supports a communication ready state with access to I2C EEPROM Interface, external ROM, UART, or USB•8K x 16 internal RAM for code and data buffering•Extended memory interface port for external SRAM and ROM•16-bit parallel Host Port Interface (HPI) with a DMA/Mailbox data path for an external processor to directly access all of the on-chip memory and control on-chip SIEs•Fast serial port supports from 9600 baud to 2.0 Mbaud•SPI support in both master and slave•On-chip 16-bit DMA/Mailbox data path interface•Supports 12-MHz external crystal or clock•3.3V operation•Package option — 100-pin TQFP2.0 Typical ApplicationsEZ-Host is a very powerful and flexible dual role USB controller that supports a wide variety of applications. It is primarily intended to enable host capability in applications such as:•Set-top boxes•Printers•KVM switches•Kiosks•Automotive applications•Wireless access points.3.0 Functional Overview3.1Processor Core3.1.1ProcessorEZ-Host has a general-purpose 16-bit embedded RISC processor that runs at 48 MHz.3.1.2ClockingEZ-Host requires a 12-MHz source for clocking. Either an external crystal or TTL level oscillator may be used. EZ-Host has an internal PLL that produces a 48-MHz internal clock from the 12-MHz source.3.1.3MemoryEZ-Host has a built-in 4K × 16 masked ROM and an 8K × 16 internal RAM. The masked ROM contains the EZ-Host BIOS. The internal RAM can be used for program code or data.3.1.4InterruptsEZ-Host provides 128 interrupt vectors. The first 48 vectors are hardware interrupts and the following 80 vectors are software interrupts.3.1.5General Timers and Watchdog TimerEZ-Host has two built-in programmable timers and a Watchdog timer. All three timers can generate an interrupt to the EZ-Host.3.1.6Power ManagementEZ-Host has one main power saving mode, Sleep. Sleep mode pauses all operations and provides the lowest power state.4.0 Interface DescriptionsEZ-Host has a wide variety of interface options for connectivity. With several interface options available, EZ-Host can act as a seamless data transport between many different types of devices.See Table4-1 and Table4-2 to understand how the interfaces share pins and which can coexist. It should be noted that some interfaces have more then one possible port location selectable through the GPIO Control Register [0xC006]. Below are some general guidelines:•HPI and IDE interfaces are mutually exclusive.•If 16-bit external memory is required, then HSS and SPI default locations must be used.•I2C EEPROM and OTG do not conflict with any interfaces.Notes:1.Default interface location.2.Alternate interface location.Table 4-1. Interface Options for GPIO Pins GPIO Pins HPIIDEPWMHSSSPIUARTI2C OTGGPIO31SCL/SDA GPIO30SCL/SDAGPIO29OTGIDGPIO28TX [1]GPIO27RX [1]GPIO26PWM3CTS [1]GPIO25GPIO24INT IOREADY GPIO23nRD IOR GPIO22nWR IOW GPIO21nCS GPIO20A1CS1GPIO19A0CS0GPIO18A2PWM2RTS [1]GPIO17A1PWM1RXD [1]GPIO16A0PWM0TXD [1]GPIO15D15D15GPIO14D14D14GPIO13D13D13GPIO12D12D12GPIO11D11D11MOSI [1]GPIO10D10D10SCK [1]GPIO9D9D9nSSI [1]GPIO8D8D8MISO [1]GPIO7D7D7TX [2]GPIO6D6D6RX [2]GPIO5D5D5GPIO4D4D4GPIO3D3D3GPIO2D2D2GPIO1D1D1GPIO0D0D0Table 4-2. Interface Options for External Memory Bus Pins MEM Pins HPIIDEPWMHSS SPIUARTI2COTGD15CTS [2]D14RTS [2]D13RXD [2]D12TXD [2]D11MOSI [2]D10SCK [2]D9nSSI [2]D8MISO [2]D[7:0]A[18:0]CONTROL4.1USB InterfaceEZ-Host has two built-in Host/Peripheral SIEs and four USB transceivers that meet the USB 2.0 specification requirements for full and low speed (high speed is not supported). In Host mode, EZ-Host supports four downstream ports, each support control, interrupt, bulk, and isochronous transfers. In Peripheral mode, EZ-Host supports one peripheral port with eight endpoints for each of the two SIEs. Endpoint 0 is dedicated as the control endpoint and only supports control transfers. Endpoints 1 though 7 support Interrupt, Bulk (up to 64 Bytes/packet), or Isochronous transfers (up to 1023 Bytes/packet size). EZ-Host also supports a combi-nation of Host and Peripheral ports simultaneously as shown in Table4-3.Table 4-3. USB Port Configuration OptionsPort Configurations Port 1A Port 1B Port 2A Port 2BOTG OTG–––OTG + 2 Hosts OTG–Host HostOTG + 1 Host OTG–Host–OTG + 1 Host OTG––HostOTG + 1 Peripheral OTG–Peripheral–OTG + 1 Peripheral OTG––Peripheral4 Hosts Host Host Host Host3 Hosts Any Combination of Ports2 Hosts Any Combination of Ports1 Host Any Port2 Hosts + 1 Peripheral Host Host Peripheral–2 Hosts + 1 Peripheral Host Host–Peripheral2 Hosts + 1 Peripheral Peripheral–Host Host2 Hosts + 1 Peripheral–Peripheral Host Host1 Host + 1 Peripheral Host–Peripheral–1 Host + 1 Peripheral Host––Peripheral1 Host + 1 Peripheral–Host–Peripheral1 Host + 1 Peripheral–Host Peripheral–1 Host + 1 Peripheral Peripheral–Host–1 Host + 1 Peripheral Peripheral––Host1 Host + 1 Peripheral–Peripheral–Host1 Host + 1 Peripheral–Peripheral Host–2 Peripherals Peripheral–Peripheral–2 Peripherals Peripheral––Peripheral2 Peripherals–Peripheral–Peripheral2 Peripherals–Peripheral Peripheral–1 Peripheral Any Port4.1.1USB Features•USB 2.0-compliant for full and low speed•Up to four downstream USB host ports•Up to two upstream USB peripheral ports•Configurable endpoint buffers (pointer and length), must reside in internal RAM•Up to eight available peripheral endpoints (one control endpoint)•Supports Control, Interrupt, Bulk, and Isochronous transfers•Internal DMA channels for each endpoint•Internal pull-up and pull-down resistors•Internal Series termination resistors on USB data lines4.1.2USB Pins.Table 4-4. USB Interface PinsPin Name Pin NumberDM1A22DP1A23DM1B18DP1B19DM2A9DP2A10DM2B4DP2B54.2OTG InterfaceEZ-Host has one USB port that is compatible with the USB On-The-Go supplement to the USB 2.0 specification. The USB OTG port has a various hardware features to support Session Request Protocol (SRP) and Host Negotiation Protocol (HNP). OTG is only supported on USB PORT 1A.4.2.1OTG Features•Internal Charge Pump to supply and control VBUS•VBUS Valid Status (above 4.4V)•VBUS Status for 2.4V< VBUS <0.8V•ID Pin Status•Switchable 2KΩ internal discharge resistor on VBUS•Switchable 500Ω internal Pull-up resistor on VBUS•Individually switchable internal Pull-up and Pull-down resistors on the USB Data Lines4.2.2OTG Pins.Table 4-5. OTG Interface PinsPin Name Pin NumberDM1A22DP1A23OTGVBUS11OTGID41CSwitchA13CSwitchB124.3External Memory InterfaceEZ-Host provides a robust interface to a wide variety of external memory arrays. All available external memory array locations can contain either code or data. The CY16 RISC processor directly addresses a flat memory space from 0x0000 to 0xFFFF. 4.3.1External Memory Interface Features•Supports 8-bit or 16-bit SRAM or ROM•SRAM or ROM can be used for code or data space•Direct addressing of SRAM or ROM•Two external memory mapped page registers4.3.2External Memory Access StrobesAccess to external memory is sampled asynchronously on the rising edge of strobes with a minimum of one wait state cycle. Up to seven wait state cycles may be inserted for external memory access. Each additional wait state cycle stretches the external memory access time by 21 nsec. An external memory device with 12-nsec access time is necessary to support 48-MHz code execution.4.3.3Page RegistersEZ-Host allows extended data or program code to be stored in external SRAM, or ROM. The total size of extended memory can be up to 512K bytes. The CY16 processor can access extended memory via two address regions of 0x8000-0x9FFF and 0xA000-0xBFFF. The page register 0xC018 can be used to control the address region 0x8000-0x9FFF and the page register 0xC01A controls the address region of 0xA000-0xBFFF.Figure4-1 illustrates that when the nXMEMSEL pin is asserted the upper CPU address pins are driven by the contents of the Page x Registers.Figure 4-1. Page n Registers External Address Pins Logic4.3.4Merge ModeMerge modes enabled through the External Memory Control Register [0xC03] allow combining of external memory regions in accordance with the following:•nXMEMSEL is active from 0x8000 to 0xBFFF•nXRAMSEL is active from 0x4000 to 0x7FFF when RAM Merge is disabled; nXRAMSEL is active from 0x4000 to 0xBFFF when RAM Merge is enabled•nXROMSEL is active from 0xC100 to 0xDFFF when ROM Merge is disabled; nXROMSEL is active from 0x8000 to 0xDFFF (excluding the 0xC000 to 0xC0FF area) when ROM Merge is enabled4.3.5Program Memory Hole DescriptionCode residing in the 0xC000-0xC0FF address space is not accessible by the cpu.4.3.6DMA to External Memory ProhibitedEZ-Host supports an internal DMA engine to rapidly move data between different functional blocks within the chip. This DMA engine is used for SIE1, SIE2, HPI, SPI, HSS, and IDE but it can only transfer data between the specified block and internal RAM or ROM. Setting up the DMA engine to transfer to or from an external memory space might result in internal RAM data corruption because the hardware (i.e HSS/HPI/SIE1/SIE2/IDE) does not explicitly check the address range. For example, setting up a DMA transfer to external address 0x8000 might result in a DMA transfer into address 0x0000.External Memory Related Resource Considerations:•By default A[18:15] are not available for general addressing and are driven high on power up. The Upper Address Enable Register must be written appropriately to enable A[18:15] for general addressing purposes.•47k ohm external pull-up on A15-pin for 12-MHz crystal operation.•During the 3-msec BIOS boot procedure the CPU external memory bus is active.•ROM boot load value 0xC3B6 located at 0xC100.•HPI, HSS, SPI, SIE1, SIE2, and IDE can't DMA to external memory arrays.•Page 1 banking is always enabled and is in effect from 0x8000 to 0x9FFF.•Page 2 banking is always enabled and is in effect from 0xA000 to 0xBFFF.•CPU memory bus strobes may wiggle when chip selects are inactive.4.3.7External Memory Interface PinsTable 4-6. External Memory Interface PinsPin Name Pin Number nWR64nRD62 nXMEMSEL (optional nCS)34nXROMSEL (ROM nCS)35nXRAMSEL (RAM nCS)36A1896A1795A1697A1538A1433A1332A1231A1130A1027A925A824A720A617A58A47A33A22A11nBEL/A099nBEH98D1567D1468D1369D1270D1171D1072D973D874D776D677D578D479D380D281D182D0834.3.8External Memory Interface Block DiagramsFigure4-2 illustrates how to connect a 64k × 8 memory array (SRAM/ROM) to the EZ-Host external memory interface.Figure 4-2. Interfacing to 64k × 8 Memory ArrayFigure4-3 illustrates the interface for connecting a 16-bit ROM or 16-bit RAM to the EZ-Host external memory interface. In 16-bit mode, up to 256K words of external ROM or RAM are supported. Note that the Address lines do not map directly.Figure 4-3. Interfacing up to 256k × 16 for External Code/DataFigure4-4 illustrates the interface for connecting an 8-bit ROM or 8-bit RAM to the EZ-Host external memory interface. In 8-bit mode, up to 512K bytes of external ROM or RAM are supported.Figure 4-4. Interfacing up to 512k × 8 for External Code/Data4.4General Purpose I/O Interface (GPIO)EZ-Host has up to 32 GPIO signals available. Several other optional interfaces use GPIO pins as well and may reduce the overall number of available GPIOs.4.4.1GPIO DescriptionAll Inputs are sampled asynchronously with state changes occurring at a rate of up to two 48-MHZ clock cycles. GPIO pins are latched directly into registers, a single flip-flop.4.4.2Unused Pin DescriptionsUnused USB pins should be three-stated with the D+ line pulled high through the internal pull-up resistor and the D- line pulled low through the internal pull-down resistor.Unused GPIO pins should be configured as outputs and driven low.4.5UART InterfaceEZ-Host has a built-in UART interface. The UART interface supports data rates from 900 to 115.2K baud. It can be used as a development port or for other interface requirements. The UART interface is exposed through GPIO pins.4.5.1UART Features•Supports baud rates of 900 to 115.2K•8-N-14.5.2UART Pins.Table 4-7. UART Interface PinsPin Name Pin NumberTX42RX434.6I2C EEPROM InterfaceEZ-Host provides a master only I2C interface for external serial EEPROMs. The serial EEPROM can be used to store application specific code and data. This I2C interface is only to be used for loading code out of EEPROM, it is not a general I2C interface. The I2C EEPROM interface is a BIOS implementation and is exposed through GPIO pins. Please refer to the BIOS documentation for additional details on this interface.4.6.1I2C EEPROM Features•Supports EEPROMs up to 64KB (512K bit)•Auto-detection of EEPROM size4.6.2I2C EEPROM Pins.Table 4-8. I2C EEPROM Interface PinsPin Name Pin NumberSMALL EEPROMSCK39SDA40LARGE EEPROMSCK40SDA394.7Serial Peripheral InterfaceEZ-Host provides a SPI interface for added connectivity. EZ-Host may be configured as either an SPI master or SPI slave. The SPI interface can be exposed through GPIO pins or the External Memory port.。
cy7c68013中文手册
CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A EZ-USB FX2LP (TM) USB 微控制器高速 USB 外设控制器1. 特色 (CY7C68013A/14A/15A/16A)■USB 2.0 USB IF 高速性能且经过认证 (TID # 40460272)■单芯片集成 USB 2.0 收发器、智能串行接口引擎 (SIE) 和增强型 8051 微处理器■适用性、外观和功能均与FX2兼容❐引脚兼容❐目标代码兼容❐功能兼容（FX2LP 是超集）■超低功耗：I CC在任何模式下都不超过 85 mA❐适合总线和电池供电的应用■软件：8051 代码运行介质：❐内部 RAM，通过 USB 下载❐内部 RAM，从 EEPROM 加载❐外部存储设备（128 引脚封装）■16 K 字节片上代码/数据 RAM■四个可编程的 BULK/INTERRUPT/ISOCHRONOUS 端点❐缓冲区大小选项：两倍，三倍，四倍■附加的可编程(BULK/INTERRUPT) 64 位端点■8 位或 16 位外部数据接口■可生成智能介质标准错误校正码 ECC ■通用可编程接口 (General Programmable Interface，GPIF)❐可与大多数并行接口直接连接❐由可编程波形描述符和配置寄存器定义波形❐支持多个 Ready (RDY) 输入和 Control (CTL) 输出■符合行业标准的集成增强型 8051❐48 MHz、24 MHz 或 12 MHz CPU 操作❐每个指令周期四个时钟❐两个 USART❐三个计数器/定时器❐扩展的中断系统❐两个数据指针■3.3V 工作电压，容限输入为 5V■向量化 USB 中断和 GPIF/FIFO 中断■分离的 CONTROL 传输设置部分和数据部分数据缓冲■集成 I2C 控制器，在 100 或 400 kHz 下运行■集成的四个先进先出 (FIFO) 缓冲❐集成胶合逻辑和 FIFO 有助于降低系统成本❐与 16 位总线之间的自动转换❐可主-从操作❐使用外部时钟或异步选通脉冲❐易于与 ASIC 和 DSP IC 相连的接口■有商业和工业温度等级供选择（除 VFBGA 外的所有封装）1.1 特色（仅限 CY7C68013A/14A ）■CY7C68014A ：适合电池供电应用❐挂起电流：100 μA (typ)■CY7C68013A ：适合非电池供电应用❐挂起电流：300 μA (typ)■有五种无铅封装供选择，可包含多达 40 个 GPIO ❐128 引脚 TQFP （40 个 GPIO ）、100 引脚 TQFP （40 个 GPIO ）、56 引脚 QFN （24 个 GPIO ）、56 引脚 SSOP （24 个 GPIO ）和 56 引脚 VFBGA （24 个 GPIO ）1.2 特色（仅限 CY7C68015A/16A ）■CY7C68016A ：适合电池供电应用❐挂起电流：100 μA (typ)■CY7C68015A ：适合非电池供电应用❐挂起电流：300 μA (typ)■采用无铅 56 引脚 QFN 封装（26 个 GPIO ）❐比 CY7C68013A/14A 多 2 个 GPIO ，可在同样的空间内实现额外的功能赛普拉斯半导体公司（赛普拉斯）的 EZ-USB FX2LP ™ (CY7C68013A/14A) 是高集成、低功耗 USB 2.0 微控制器EZ-USB FX2™ (CY7C68013) 的一个低功耗版本。
CY7C68013A-100AXC中文资料
元器件交易网
CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A
1.2 Features (CY7C68015A/16A only)
an easy and glueless interface to popular interfaces such as ATA, UTOPIA, EPP, PCMCIA, and most DSP/processors. The FX2LP draws considerably less current than the FX2 (CY7C68013), has double the on-chip code/data RAM and is fit, form and function compatible with the 56-, 100-, and 128pin FX2. Four packages are defined for the family: 56 SSOP, 56 QFN, 100 TQFP, and 128 TQFP.
• CY7C68016A: Ideal for battery powered applications — Suspend current: 100 µA (typ) • CY7C68015A: Ideal for non-battery powered applications — Suspend current: 300 µA (typ) • Available in lead-free 56-pin QFN package (26 GPIOs) — 2 more GPIOs than CY7C68013A/14A enabling additional features in same footprint Cypress Semiconductor Corporation’s (Cypress’s) EZ-USB FX2LP (CY7C68013A/14A) is a low-power version of the EZ-USB FX2 (CY7C68013), which is a highly integrated, low-power USB 2.0 microcontroller. By integrating the USB 2.0 transceiver, serial interface engine (SIE), enhanced 8051 microcontroller, and a programmable peripheral interface in a single chip, Cypress has created a very cost-effective solution that provides superior time-to-market advantages with low power to enable bus powered applications. The ingenious architecture of FX2LP results in data transfer rates of over 53 Mbytes per second, the maximum-allowable USB 2.0 bandwidth, while still using a low-cost 8051 microcontroller in a package as small as a 56 QFN. Because it incorporates the USB 2.0 transceiver, the FX2LP is more economical, providing a smaller footprint solution than USB 2.0 SIE or external transceiver implementations. With EZ-USB FX2LP, the Cypress Smart SIE handles most of the USB 1.1 and 2.0 protocol in hardware, freeing the embedded microcontroller for application-specific functions and decreasing development time to ensure USB compatibility. The General Programmable Interface (GPIF) and Master/Slave Endpoint FIFO (8- or 16-bit data bus) provides
apccy7波长
apccy7波长
APCCY7波长是一种短波红外线辐射，其波长约为7微米。
它属于较高能量的红外线，具有许多应用。
一些智能手机和智能手表使用APCCY7传感器来检测人体，从而实现步数计数和睡眠监测等功能。
APCCY7波长也常用于医疗领域中的体温检测和心率监测，以及与假肢相关的工程技术。
此外，在建筑物的能源管理、空气质量监测和人体姿态检测方面，APCCY7波长也有广泛的应用。
通过使用基于APCCY7波长的传感器，可以有效监测和控制室内外温度、湿度和照明等因素，提高用户的舒适度和安全性。
在气象学和环境科学领域，APCCY7波长还可以被用于检测温室气体和污染物质的浓度，以促进环保和可持续发展的进程。
总之，APCCY7波长是一种功能广泛的红外线波长，在多个领域均有应用。
随着技术的不断发展和创新，我们相信它在更多领域中的应用将会有所拓展和深化。
cy7 羧基
Cy7羧基是一种常用的荧光染料，也被称为Cyanine 7 carboxylic acid。
它是一种具有高荧光强度和稳定性的染料，常用于生物医学研究中的荧光标记和成像。
Cy7羧基的荧光波长在近红外区域，其发射波长约为750纳米，这使得它非常适合用于体内荧光成像研究。
与其他荧光染料相比，Cy7羧基具有更高的组织穿透力和较低的背景干扰，因此在生物医学研究中具有广泛的应用前景。
Cy7羧基可以与多种氨基酸残基的羧基进行化学反应，生成稳定的酰胺键连接。
因此，它可以用于抗体、蛋白质、多肽和其他生物分子上的荧光标记。
通过荧光标记，研究人员可以更方便地跟踪和定位这些生物分子在生物体内的分布和行为。
此外，Cy7羧基还可以与其他荧光染料进行组合使用，以实现多重标记和成像。
例如，可以将Cy7羧基与Alexa Fluor系列染料结合使用，以实现近红外和可见光区域的双重荧光成像。
需要注意的是，Cy7羧基是一种有毒的染料，因此在使用过程中需要采取适当的防护措施。
此外，由于其荧光强度较高，可能会对实验结果产生一定的干扰，因此在使用时需要控制染料的浓度和使用时间。
总之，Cy7羧基是一种重要的荧光染料，在生物医学研究中具有广泛的应用前景。
通过荧光标记和成像技术，可以更深入地了解生物体内的生理和病理过程，为疾病诊断和治疗提供更有效的手段。
CY7C0831AV资料
Revised May 10, 2006
Logic Block Diagram[1]
OEL R/WL B0L B1L
CE0L CE1L
CY7C0837AV CY7C0830AV/CY7C0831AV CY7C0832AV/CY7C0833AV
OER R/WR
B0R B1R
CE0R CE1R
DQ9L–DQ17L
True Dual-Ported RAM Array
Address Decode
Address Decode
Interrupt Logic
MRST
Reset Logic
TMS TDI TCK
JTAG
Addr. Read Back
Mask Register
Counter/ Address Register Mirror Reg
1-Mbit (64K x 18)
CY7C0830AV
167
4.0
225
120 TQFP 144 FBGA
2-Mbit (128K x 18)
CY7C0831AV
167
4.0
225
120 TQFP 144 FBGA
4-Mbit (256K 18)
CY7C0832AV
167
4.0
225
120 TQFP 144 FBGA
CY7C093794V CY7C093894V CY7C09289V CY7C09369V CY7C09379V CY7C09389VFLEx18™ 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM
CY7C0837AV CY7C0830AV/CY7C0831AV CY7C0832AV/CY7C0833AV
CY7C68013A的特点及应用
CY7C68013的特点及应用【V1.0】1、USB2.0的主要特点USB协议的2.0版本于2000年4月推出。
支持以下3种速度模式：低速模式（low speed） 1.5Mb/s；全速模式（full speed） 12Mb/s高速模式（high speed） 480Mb/sUSB2.0协议支持现存的所有USB设备，既可以把USB1.1设备插入USB1.1的PC机接口，并且在电气上兼容USB1.1的连接线。
1.1 数据包USB传输的数据包的类型用称之为Packet Ids（PIDs）的特定代码来定义。
USB包中共有4种PID类型，如表1所列。
表1 USB2.0的数据包类型PID类型 PID名称 令牌IN，OUT，SOF，SETUP 数据 DATA0，DATA1，DATA2，MDATA 握手 ACK，NAK，STALL，NYET 特殊类型 PRE，ERR，SPLIT，PIN注：黑体字表示USB2.0增加的PID类型。
在全速模式时，每个OUT传输发送OUT数据包，不考虑外设是否处于“忙”状态而不能接收数据。
针对这种浪费带宽的情况，在高速模式时推荐使用新的 PID类型“PING”。
主机先对OUT端点发出个较短的“PING”令牌，访问当前外设是否有数据文凭间来存放OUT的数据包。
仅仅当外部设备回答 “ACK”时，主机才发送较长OUT数据包。
SETUP邻牌只用于控制传输。
它数据包中的前8个字节。
通过这8个字节，外设对主机的设备请求进行译码。
SOF令牌代表一个USB帧的开始。
ACK（Acknowlegde）表示成功，数据接收无误。
NAK（Negavite Acknowlegde）表示忙，得发。
这并不是出错，USB外设没有应答表示出错。
STALL表示未知错误，外设未能理解主机发出的设备请求，可能是外设端出错，或是主机访问并存在的资源。
USB协议提供了从stall状态恢复的方法。
NYET（Not Yet）类似于ACK，表示数据接收无误，并且指出外设还没准备好接收下一个OUT数据包。
CY7C168A-20资料
C168A-2
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Commercial Military
7C168A-15 15 115 -
7C168A-20 20 90 100
7C168A-25 25 90 100
The input/output pins remain in a high-impedance state when Chip Enable (CE) is HIGH or Write Enable (WE) is LOW.
A die coat is used to insure alpha immunity.
IOS
Output Short Circuit Current[4]
ICC
VCC Operating
Supply Current
ISB1
Automatic CE
Power-Down Current
ISB2
Automatic CE
Power-Down Current
Test Conditions VCC = Min., IOH = −4.0 mA VCC = Min., IOL = 8.0 mA
7C168A-25 7C168A-35 7C168A-45
Min. Max. Min. Max. Min. Max. Unit
2.4
2.4
2.4
V
0.4
0.4
0.4 V
2.2 VCC 2.2 VCC 2.2 VCC V −0.5 0.8 −0.5 0.8 −0.5 0.8 V
−10 +10 −10 10 −10 10 µA
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CY7C68000
TX2™ USB 2.0 UTMI 收发器
Jude 译2009.11
1.0 EZ-USB TX2性能
EZ-USB TX2 是一个符合usb2.0的收发器，把串行的解串成30M的16位或者60M的8位的并行接口。
EZ-USB TX2 提供一个高速的物理层接口，可以工作在usb2.0 允许的最大带宽。
这允许设计者把复杂的高速模拟的usb 部分放在数字ASIC的外面，以减少开发时间和关联两部分的风险。
它提供一个被usb2.0鉴定过的标准的接口，这个接口符合UTMI 1.05（dated 3/29/01）版本的协议。
图1-1 为功能模块，EZ-USB TX2的特性：
●作为设备符合usb2.0 UTMI的标准
●可作业在usb高速480MBIT/S, 和全速12MBIT/S
●串到并，并到串转化
●8位单向或者8位双向，或者16位双向外部数据接口
●在接受包是检测同步场和EOP
●在发送包的时候产生同步场和EOP
●从usb 串行数据流恢复数据和时钟
●位填充/不填充，为填充错误检测
●分段运输寄存器，用来管理在位填充/不填充期间数据速率变化
●16位30M ，8位60M的并行接口
●全速和高速之间终止和发送信号的转换能力（Ability to switch between FS and HS
terminations andsignaling翻译的不准，自己领会）
●支持对usb 复位，挂起，回复的检测
●支持usb2.0定义的高速的识别和检测
●支持恢复信号的发射
● 3.3v 工作
●两种封装选择56脚QFN,56脚SSOP
●所有必要的终止，包括DPLUS上的1.5k 的上拉，都在片内
●支持usb2.0测试模式
2.0 应用
• DSL modems数字模拟语言模型
• ATA interface ATA接口
• Memory card readers存储卡读卡器
• Legacy conversion devices遗产转化设备☺
• Cameras照相机
• Scanners扫描仪
• Home PNA☹
• Wireless LAN无线局域网
• MP3 players mp3 播放器
• Networking网络
3.0 功能概述
3.1 usb 发信号的速度
TX2 工作在两种速率：
全速：位时间为12Mbps
高速：位时间为480Mbps
不支持低速速率1.5Mbps
3.2 收发器时钟频率
TX2 有一个片上的可用24M晶振的振荡器电路，有以下特性：
并行振荡
基波模型
500uw驱动级
27-33pf负载电容
片上的pll 把24M的时钟倍频为30M或者60M，作为并行数据传输的时钟，
DataBus16_8 引脚决定clk 的频率。
3.3 总线
两种封装的8-16位双向数据总线可用来与控制器传输数据
3.4 复位引脚
Reset 引脚复位芯片。
这个引脚有一个迟滞作用，根据UTMI协议高有效，当VCC到达
3.3v 后大约200us内部的pll稳定。
3.5 总线状态
线状态输出引脚linestate被联合逻辑驱动或者是连接在j或者k状态，他们被clk 同步，
在clk 的边沿这些线的状态反应usb数据线的状态，时钟上升沿linestates的0位是
dplus的状态，1位是dminus的状态。
当同步后，linestates的建立时间和保持时间和并
行数据是同样的。
3.6 全速和高速选择
FS vs HS通过XcvrSelect和TermSelect 输入信号完成，TermSelect使能dplus的1.5k
上拉电阻，当TermSelect 被驱动为低，一个SE0被发到总线上，提供HS的停止，在总线
上产生HS的idle 状态。
XcvrSelect信号控制选择高速收发器还是全速收发器，置0选择高
速收发器，置1选择全速收发器。
3.7 操作模式
操作模式被OpMode 信号控制，OpMode 信号有能力约束收发器为正常模式和唤起特殊测
试模式。
这些模式会立即有效，优先于任何未决定的数据传输。
操作模式的数据率取决
于XcvrSelect的输入状态
模式0 允许这个收发器对正常的usb 数据解码编码。
模式1 允许收发器逻辑支持一个软连接特性，三态的全速高速的收发器，移除任何的从usb来的终止，使得它对于一个上游的端口像一个已经断开链接的设备。
模式2 取消位填充和NRZI编码逻辑，使得1s装载数据线成Js，0s 变成Ks
4.0 DPLUS和DMINUS 阻抗
5.0 引脚分配
5.1引脚分配
后面的DC，AC特性==的自己看英文的吧，对应用不太重要。