PCM1774中文资料

FEATURESAPPLICATIONSDESCRIPTION•2(I 2C™)or 3(SPI)Wire Serial Control•Analog Front End:•Programmable Function by Register Control:–Stereo Single-Ended Input–Digital Attenuation:0dB to –62dB –Microphone Amplifier (12dB,20dB)–Digital Gain of DAC:0,6,12,18dB•Analog Back End:–Power Up/Down Control for Each Module –Stereo/Mono Line Output With Volume –6-dB to –70-dB Gain for Analog Outputs –Stereo/Mono Headphone Amplifier With –0/12/20dB for Microphone InputVolume–0-dB to –21-dB Gain for Analog Mixing •Analog Performance:–Three-Band Tone Control and 3D Sound –Dynamic Range:93dB–Analog Mixing Control–40-mW +40-mW Headphone Output at •Pop-Noise Reduction Circuit R L =16Ω•Short Protection Circuit•Power Supply Voltage•Package:4-mm ×4-mm QFN Package– 1.71V to 3.6V for Digital I/O Section •Operation Temperature Range:–40°C to 85°C– 1.71V to 3.6V for Digital Core Section – 2.4V to 3.6V for Analog Section•Portable Audio Player,Cellular Phone – 2.4V to 3.6V for Power Amplifier Section •Video Camcorder,Digital Still Camera •Low Power Dissipation:•PMP/DMB/PND– 6.4mW in Playback,1.8V/2.4V,44.1kHz – 3.3μW in Power Down•Sampling Frequency:5kHz to 50kHzThe PCM1774is a low-power stereo DAC designed •Operation From a Single Clock Input Without for portable digital audio applications.The device PLLintegrates headphone amplifier,line amplifier,line •System Clock:input,boost amplifier,programmable gain control,analog mixing,and sound effects.It is available in a –Common-Audio Clock (256f S /384f S ),12/24,small-footprint,4-mm ×4-mm QFN package.The 13/26,13.5/27,19.2/38.4,19.68/39.36MHzPCM1774supports right-justified,left-justified,I 2S,and DSP formats,providing easy interfacing to audio DSP and decoder/encoder chips.Sampling rates up to 50kHz are supported.The user-programmable functions are accessible through a two-or three-wire serial control port.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.I2C is a trademark of Philips Electronics.PRODUCTION DATA information is current as of publication date.Copyright ©2007,Texas Instruments IncorporatedProducts conform to specifications per the terms of the Texas Instruments standard warranty.Production processing does not necessarily include testing of all parameters. ABSOLUTE MAXIMUM RATINGSRECOMMENDED OPERATING CONDITIONSPCM1774SLAS551–JULY2007This integrated circuit can be damaged by ESD.Texas Instruments recommends that all integrated circuits be handled with appropriate precautions.Failure to observe proper handling and installation procedures can cause damage.ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.over operating free-air temperature range(unless otherwise noted)(1)MAX UNIT Supply voltage V DD,V IO,V CC,V PA–0.3to4V Ground voltage differences:DGND,AGND,PGND±0.1V Input voltage–0.3to4V Input current(any pin except supplies)±10mA Ambient temperature under bias–40to110°C Storage temperature–55to150°C Junction temperature150°C Lead temperature(soldering)260°C,5s Package temperature(reflow,peak)260°C (1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.These are stress ratingsonly,and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.over operating free-air temperature range(unless otherwise noted)MIN NOM MAX UNITAnalog supply voltage,V CC,V PA 2.4 3.3 3.6VV SSDigital supply voltage,V DD,V IO 1.71 3.3 3.6VDigital input logic family CMOSSCKI system clock 3.07218.432MHz Digital input clock frequencyLRCK sampling clock848kHzLOL and LOR10kΩAnalog output load resistanceHPOL and HPOR16ΩAnalog output load capacitance30pFDigital output load capacitance10pFT A Operating free-air temperature–4085°C2Submit Documentation FeedbackELECTRICAL CHARACTERISTICSPCM1774 SLAS551–JULY2007All specifications at T A=25°C,V DD=V IO=V CC=V PA=3.3V,f S=48kHz,system clock=256f S,and16-bit data(unless otherwise noted).PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Audio Data CharacteristicsDATA FORMATResolution16BitsI2S,left-,Audio data interface format right-justified,DSPAudio data bit length16BitsMSB first,2s Audio data formatcomplement Sampling frequency(f S)550kHzV DD<2V27 System clock MHzV DD>2V40Digital Input/OutputCMOSLogic familycompatibleV IH0.7V IOInput logic level VdcV IL0.3V IOI IH V IN=3.3V10Input logic currentμAI IL V IN=0V–10V OH I OH=–2mA0.75V IOOutput logic level VdcV OL I OL=2mA0.25V IODigital Input to Line Output Through DAC(LOL and LOR)R L=10kΩ,volume=0dB,analog mixing=disabledDYNAMIC PERFORMANCE2.828V PPFull-scale output voltage0dB1Vrms Dynamic range EIAJ,A-weighted93dB SNR Signal-to-noise ratio EIAJ,A-weighted8693dB Channel separation91dB THD+N Total harmonic distortion+noise0dB0.008% Load resistance10kΩLine Input to Line Output Through Mixing Path(LOL and LOR)R L=10kΩ,volume=0dB,analog mixing=enabledDYNAMIC PERFORMANCE2.828V PPFull-scale input and output voltage0dB1Vrms SNR Signal-to-noise ratio EIAJ,A-weighted8493dB Digital Input to Headphone Output Through DAC(HPOL and HPOR)R L=16Ωor32Ω,ALC=OFF,volume=0dB,speaker=powered down,analog mixing=disabled,not capless modeDYNAMIC PERFORMANCE2.828V PPFull-scale output voltage0dB1Vrms SNR Signal-to-noise ratio EIAJ,A-weighted8493dB30mW,R L=32Ω,0.1%volume=0dBTHD+N Total harmonic distortion+noise40mW,R L=16Ω,0.03%volume=–1dB3Submit Documentation FeedbackPCM1774SLAS551–JULY 2007ELECTRICAL CHARACTERISTICS (continued)All specifications at T A =25°C,V DD =V IO =V CC =V PA =3.3V,f S =48kHz,system clock =256f S ,and 16-bit data (unless otherwise noted).PARAMETERTEST CONDITIONSMIN TYPMAXUNIT Load resistance16Ω200Hz,140mV PP–40PSRRPower-supply rejection ratio1kHz,140mV PP –45dB20kHz,140mV PP–32Line Input to Headphone Output Through Mixing Path (HPOL and HPOR)R L =16Ωor 32Ω,ALC =OFF,volume =0dB,speaker =powered down,analog mixing =enabled,not capless mode DYNAMIC PERFORMANCE2.828V PP Full-scale output voltage0dB1Vrms SNRSignal-to-noise ratio EIAJ,A-weighted8493dB Load resistance16ΩFilter CharacteristicsINTERPOLATION FILTER FOR DACPass band 0.454f SStop band 0.546f SPass-band ripple ±0.04dB Stop-band attenuation –50dB Group delay 19/f s s De-emphasis error±0.1dBANALOG FILTERFrequency responsef =20kHz±0.2dBPower Supply and Supply Current V IO 1.71 3.3 3.6V DD 1.71 3.3 3.6Voltage rangeVdcV CC 2.4 3.3 3.6V PA2.43.3 3.6BPZ input,all active,no load4.510mA Supply current All inputs are held static 110μA BPZ input14.833mW Power dissipationAll inputs are held static3.333μW Temperature ConditionOperation temperature–4085°C θJAThermal resistance40°C/W4Submit Documentation FeedbackPIN ASSIGNMENTSH P O R /L O RH P O L /L O LV P AP G N DL R C KM O D EM S /A D RM D /S D AD I NM C /S C LV COM AGND V CC AIN1R AIN1LBCK SCKI DGND V DD V IOPCM1774RGP (TOP VIEW)PCM1774SLAS551–JULY 2007Table 1.TERMINAL FUNCTIONSTERMINALI/O DESCRIPTIONNAME NO.AGND 17–Ground for analogAIN1L 20I Analog input 1for L-channel AIN1R 19I Analog input 1for R-channel BCK 10I/O Serial bit clock DGND 8–Digital ground DIN 5I Serial audio data inputHPOL/LOL 15O Headphone/lineout for R-channel HPOR/LOR 14O Headphone/lineout for L-channel LRCK 11I/O Left and right channel clockMC/SCL 4I Mode control clock for three-wire/two-wire interface MD/SDA 3I/O Mode control data for three-wire/two-wire interfaceMODE 1I Two-or three-wire interface selection (LOW:SPI,HIGH:I 2C)MS/ADR 2I Mode control select for three-wire/two-wire interface PGND 12–Ground for speaker power amplifier SCKI 9I System clock V CC 18–Analog power supply V COM 16–Analog common voltage V DD 7–Power supply for digital core V IO 6–Power supply for digital I/O V PA13–Power supply for power amplifier5Submit Documentation FeedbackFUNCTIONAL BLOCK DIAGRAMA I N 1A I N 1V P AP G N DV C CA G N DV D DD G N DV C O P O L /O LP O R /O RV I O M o d u l e o f P o s s i b l e P o w e r U p /D o w nSLAS551–JULY 20076Submit Documentation FeedbackTYPICAL PERFORMANCE CURVES-120-100-80-60-40-201234f - Frequency - xf sA m p l i t u d e - dB-0.2-0.10.10.20.10.20.30.40.5f - Frequency - xf sA m p l i t u d e - dBPCM1774SLAS551–JULY 2007All specifications at T A =25°C,V DD =V IO =V CC =V PA =3.3V,f S =48kHz,system clock =256f S ,and 16-bit data,unlessotherwise noted.INTERPOLATION FILTER,STOP BANDINTERPOLATION FILTER,PASS BANDFigure 1.Figure 2.THREE-BAND TONE CONTROL (BASS,MIDRANGE,TREBLE)THREE-BAND TONE CONTROL (BASS)Figure 3.Figure 4.7Submit Documentation Feedback0.0070.0080.0090.010.0110.01222.533.54909192939495Power Supply - VT H D +N - T o t a l H a r m a n i c D i s t o r t i o n + N o i s e - %S N R - S i g n a l T o N o i s e R a t io22.533.54Power Supply - V909192939495T H D +N - T o t a l H a r m a n i c D i s t o r t i o n + N o i s e - %S N R - S i g n a l T o N o i s e R a t i oPCM1774SLAS551–JULY 2007TYPICAL PERFORMANCE CURVES (continued)All specifications at T A =25°C,V DD =V IO =V CC =V PA =3.3V,f S =48kHz,system clock =256f S ,and 16-bit data,unless otherwise noted.THREE-BAND TONE CONTROL (MIDRANGE)THREE-BAND TONE CONTROL (TREBLE)Figure 5.Figure 6.THD+N/SNR vs POWER SUPPLY THD+N/SNR vs POWER SUPPLY DAC TO HEADPHONE OUTPUT,16-ΩDAC TO LINE OUTPUT,10-k ΩFigure 7.Figure 8.8Submit Documentation Feedback02040608010012022.533.54Power Supply - VP - O u t p u t P o w e r - m WO20406080100120P - Output Power - mWOT H D +N - T o t a l H a r m a n i c D i s t o r t i o n + N o i s e - %-140-120-100-80-60-40-20f - Frequency - kHzA m p l i t u d e - dB20406080P - Output Power - mWO T H D +N - T o t a l H a r m a n i c D i s t o r t i o n + N o i s e - %PCM1774SLAS551–JULY 2007TYPICAL PERFORMANCE CURVES (continued)All specifications at T A =25°C,V DD =V IO =V CC =V PA =3.3V,f S =48kHz,system clock =256f S ,and 16-bit data,unless otherwise noted.OUTPUT POWER vs POWER SUPPLYTHD+N vs OUTPUT POWER(HEADPHONE,16-Ω)(HEADPHONE,16-Ω,VOLUME =6dB)Figure 9.Figure 10.THD+N vs OUTPUT POWEROUTPUT SPECTRUM (DAC TO HEADPHONE OUTPUT,(HEADPHONE,16-Ω,VOLUME =0dB)16-Ω)Figure 11.Figure 12.9Submit Documentation FeedbackDETAILED DESCRIPTIONAnalog InputGain Settings for Analog InputD/A ConverterCommon VoltageLine OutputHeadphone OutputAnalog Mixing and BypassDigital Gain ControlPCM1774SLAS551–JULY 2007The AIN1L and AIN1R pins can be used as microphone or line inputs with selectable 0-,12-,or 20-dB boost and 1-Vrms input.All of these analog inputs have high input impedance (20k Ω),which is not changed by gain settings.One pair of inputs is selected by register 87(AIL0and AIR0).The gain of the analog signals can be adjusted from 0dB to –21dB in 1-dB steps following the 0-,12-,or 20-dB boost amplifier.The gain level can be set for each channel by registers 89(GMR[2:0],GML [2:0].The DAC includes a multilevel delta-sigma modulator and an interpolation filter.These can be used to obtain high PSRR,low jitter sensitivity,and low out-of-band noise quickly and easily.The interpolation filter includes digital attenuator,digital soft mute,three-band tone control (bass,midrange and treble),and 3-D sound controlled by registers 92to 95.The de-emphasis filter (32,44.1and 48kHz)is controlled by registers 68to 70(ATL[5:0],ATR[5:0],PMUL,PMUR,DEM[1:0]).Oversampling rate control can reduce out-of-band noise when operating at low sampling rates by using register 70(OVER).The V COM pin is normally biased to 0.5V CC ,and it provides the common voltage to internal circuitry.It is recommended that a 4.7-μF capacitor be connected between this pin and AGND to provide clean voltage and avoid pop noise.The PCM1774may have a little pop noise on each analog output if a capacitor smaller than 4.7μF is used.The HPOL/LOL and HPOR/LOR pins can drive a 10-k Ωload and be configured by register 74(HPS[1:0])as a monaural single-ended,monaural differential,or stereo single-line output with 1-Vrms output.These outputs include an analog volume amplifier that can be set from 6dB to –70dB and mute in steps of 0.5-,1-,2-or 4-dB.Each output is controlled by registers 64and 65(HLV[5:0],HRV[5:0],HMUL,HMUR).No dc blocking capacitor is required when connecting an external speaker amplifier with monaural differential input.The center voltage is 0.5V CC with zero data input.The HPOL/LOL and HPOR/LOR pins can be configured as a stereo,monaural,or monaural differential headphone output by register 74(HPS[1:0]).These pins have more than 30or 40mWrms output power into a 32-or 16-Ωload,either through a dc blocking capacitor or without a capacitor.These outputs include an analog volume amplifier that can be set from 6dB to –70dB in steps of 0.5,1,2,or 4dB.Each is controlled by registers 64and 65(HLV[5:0],HRV[5:0],HMUL,HMUR).The center voltage is 0.5V CC with zero data input.Mixing amplifiers (MXL,MXR)mix inputs from the AIN pins.The analog inputs are selected by register 87(AIR0,AIL0)and can bypass the DAC and connect the mixed signal to the headphone or speaker outputs by register 88(MXR[2:0],MXL[2:0]).The gain of the analog inputs is controlled by register 89(GMR[2:0],GML[2:0]).These functions are suitable for FM radio,headset,and other analog sources without an ADC.A portable application with small speakers may be require a high sound level when playing back audio data recorded at low level.Digital gain control (DGC)can be used to amplify the digital input data by 0,6,12or 18dB by setting register 70(SPX[1:0]).10Submit Documentation Feedback3-D SoundA3-D sound effect is provided by mixing L-channel and R-channel data with a band-pass filter with two parameters,mixing ratio and band pass filter characteristic,that can be controlled by register95(3DP[3:0], 3FLO).Three-Band Tone ControlTone control has bass,midrange,and treble controls that can be adjusted from12dB to–12dB in1-dB steps by registers92to94(LGA[4:0],MGA[4:0]and HGA[4:0]).Register92(LPAE)attenuates the digital input signal automatically to prevent clipping of the output signal at settings above0dB for bass control.LPAE has no effect on midrange and treble controls.Digital Monaural MixingThe audio data can be converted from stereo digital data to mixed monaural digital data.The conversion occurs in the internal audio interface section and is controlled by register96(MXEN).Zero-Cross DetectionZero-cross detection minimizes audible zipper noise while changing analog volume and digital attenuation.This function applies to the digital input or digital output as defined by register86(ZCRS).Short ProtectionThe short-circuit protection on each headphone output prevents damage to the device while an output is shorted to V PA,an output is shorted to PGND,or any two outputs are shorted together.When the short circuit is detected on the outputs,the PCM1774powers down the shorted amplifier immediately.The short-protection status can be monitored by reading register77(STHC,STHL,SCHR)through the I2C interface.Short-circuit protection operates in any enabled headphone amplifier.Pop-Noise Reduction CircuitThe pop-noise reduction circuit prevents audible noise when turning the power supply on/off and powering the device up/down in portable applications.It is recommended to establish the register settings in the sequence that is shown in Table3and Table4.No particular external parts are required.Power Up/Down for Each ModuleUsing register72(PMXL,PMXR),register73(PBIS,PDAR,PDAL,PHPR,PHPL)and register90(PCOM), unused modules can be powered down to minimize power consumption(7mW during playback only).Digital Audio InterfaceThe PCM1774can receive I2S,right-justified,left-justified,and DSP formats in both master and slave modes. These options can be selected in register70(PFM[1:0]),register81(RFM[1:0])and register84(MSTR).Digital InterfaceAll digital I/O pins can interface at various power supply voltages.V IO pin can be connected to a1.71-V to3.6-V power supply.Power SupplyThe V CC pin and the V PA pin can be connected to2.4V to3.6V.The same voltage must be applied to both pins. The V DD pin and the V IO pin can be connected to1.71V to3.6V.A different voltage can be applied to each of these pins(for example,V DD=1.8V,V IO=3.3V).DESCRIPTION OF OPERATIONSystem Clock InputSCKI0.7 V IO0.3 V IOT0005-12Power-On Reset and System ResetPower On/Off SequenceSLAS551–JULY 2007The PCM1774can accept clocks of various frequencies without a PLL.They are used for clocking the digital filters and automatic level control and delta-sigma modulators and are classified as common-audio and application-specific clocks.Table 2shows frequencies of the common-audio clock and application-specific clock.Figure 13shows the for system clock inputs.The sampling rate and frequency of the are determined by the settings of register 86(MSR[2:0])and register 85(NPR[5:0]).Note that the sampling rate of the application-specific clock has a little sampling error.The details are shown in Table 9.Table 2.System Clock FrequenciesCLOCK FREQUENCIESCommon-audio clock 11.2896,12.288,16.9344,18.432MHzApplication-specific clock12,13,13.5,24,26,27,19.2,19.68,38.4,39.36MHzPARAMETERSSYMBOL MIN UNITS System-clock pulse duration,high t w(SCKH)7ns System-clock pulse duration,lowt w(SCKL)7nsFigure 13.System Clock TimingThe power-on-reset circuit outputs a reset signal,typically at V DD =1.2V,and this circuit does not depend on the voltage of other power supplies (V CC ,V PA ,and V IO ).Internal circuits are cleared to default status,then all analog and digital outputs have no signal.The PCM1774does not require any power supply sequencing.Set Register data after turning all power supplies on.System reset is enabled by setting register 85(SRST =1).After the reset sequence,the register data is reset to SRST =0automatically.All circuits are cleared to their default status at once by the system reset.Note that the PCM1774has audible pop noise on the analog outputs when enabling SRST.To reduce audible pop noise,a sequence of register settings is required after turning all power supplies on when powering up,or before turning the power supplies off when powering down.If some modules are not required for a particular application or operation,they should be placed in the power-down state after performing the power-on sequence.The recommended power-on and power-off sequences are shown in Table 3and Table 4,respectively.Power-Supply Current Table3.Recommended Power-On SequenceREGISTERSTEP NOTESETTINGS1–Turn on all power supplies(1)24027h Headphone amplifier L-ch volume(–6dB)(2)34127h Headphone amplifier R-ch volume(–6dB)(2)64427h Digital attenuator L-ch(–24dB)(2)74527h Digital attenuator R-ch(–24dB)(2)84620h DAC audio interface format(left-justified)(3)1249E0h DAC(DAL,DAR)and analog bias power up135601h Zero-cross detection enable144803h Analog mixer(MXL,MXR)power up155811h Analog mixer input(SW2,SW5)select1649ECh Headphone amplifier(HPL,HPR,HPC)power up184A01h V COM power up195230h Analog front end(D2S,MCB,PG1,2,5,6)power up205711h Analog input(MUX3,MUX4)select.Analog input(MUX1,MUX2)select(1)V DD should be turned on prior to or simultaneously with,the other power supplies.It is recommended to set register data with thesystem clock input after turning all power supplies on.(2)Any level is acceptable for volume or attenuation.Level should be resumed by register data recorded when system powers off.(3)Audio interface format should be set to match the DSP or decoder being used.Table4.Recommended Power-Off SequenceREGISTERSTEP NOTESETTINGS1447Fh DAC L-ch digital soft-mute enable(1)2457Fh DAC R-ch digital soft-mute enable(1)45811h Analog mixer input(SW2,SW5)select549ECh Headphone amplifier(HPL,HPR,HPC)power up(2)65200h Analog front end(D2S,MCB,PG1,2,5,6)power down75A00h PG1,PG2gain control(0dB)84A00h V COM power down9–Wait time(750ms)(3)1049E0h Headphone amplifier(HPL,HPR,HPC)power down,speaker amplifier(SPL,SPR)power down114800h Analog mixer(MXL,MXR)power down124900h DAC(DAL,DAR)and analog bias power down13–Turn off all power supplies.(4)(1)Any level is acceptable for volume or attenuation.(2)The headphone amplifier must be operating during the power-off sequence.(3)PCM1774requires time for V COM to reach the ground level from the common level.The wait time allowed depends on the settings ofregister125PTM[1:0],RES[4:0].The default setting is750ms for V COM=4.7μF.(4)Power supply sequencing is not required.It is recommended to turn off all power supplies after setting the registers with the systemclock input.The current consumption of the PCM1774depends on power up/down status of each circuit module.In order to reduce the power consumption,disabling each module is recommended when it is not used in an application or operation.Table5shows the current consumption in some states.SLAS551–JULY2007Table5.Power Consumption TableOPERATION MODE CONDITION V OL POWER SUPPLY CURRENT[mA]PD[mW][V]VV DD V CC V PA TOTALIOZero Data 1.80.0000.000––0.000f S=44.1kHz 2.80.0000.000––0.000R L=0Ω3.30.0000.000––0.000All Power Down2.4––0.0010.0000.0022.8––0.0010.0000.0033.3––0.0010.0000.003Zero Data 1.800.84–– 1.5f S=44.1kHz 2.80.03 1.47–– 4.2R L=0Ω3.30.04 1.84–– 6.2All Active2.4–– 1.680.38 4.92.8–– 1.810.41 6.23.3–– 1.960.468.0Zero Data 1.800.84–– 1.5f S=44.1kHz 2.80.03 1.47–– 4.2R L=10Ω3.30.04 1.84–– 6.2Line Output2.4–– 1.380.38 4.22.8–– 1.500.41 5.33.3–– 1.640.46 6.9Zero Data 1.800.84–– 1.5f S=44.1kHz 2.80.03 1.47–– 4.2R L=16Ω3.30.04 1.84–– 6.2Headphone Output2.4–– 1.380.38 4.22.8–– 1.500.41 5.33.3–– 1.650.467.0Zero Data 1.80 1.29–– 2.3f S=44.1kHz 2.80.03 2.26–– 6.4R L=16Ω3.30.04 2.82––9.4Headphone Output with SoundEffect 2.4–– 1.380.38 4.22.8–– 1.500.42 5.43.3–– 1.640.46 6.9Zero Data 1.800.84–– 1.5f S=44.1kHz 2.80.03 1.47–– 4.2R L=16Ω3.30.04 1.84–– 6.2Headphone Output with StereoAnalog Mixing 2.4–– 1.680.38 4.92.8–– 1.810.41 6.23.3–– 1.960.468.0Zero Data 1.800.84–– 1.5f S=44.1kHz 2.80.03 1.47–– 4.2R L=16Ω3.30.04 1.84–– 6.2Headphone Output with MonoAnalog Mixing 2.4–– 1.530.38 4.62.8–– 1.660.41 5.83.3–– 1.810.467.5Audio Serial Interface Table5.Power Consumption Table(continued)OPERATION MODE CONDITION V OL POWER SUPPLY CURRENT[mA]PD[mW][V]VIOV DD V CC V PA TOTALZero Data 1.800––0.0f S=44.1kHz 2.800––0.0R L=16Ω3.300––0.0No Digital Input(1)Headphone Output with StereoAnalog Mixing 2.4––0.680.38 2.52.8––0.690.413.13.3––0.710.46 3.9Zero Data 1.800––0.0f S=44.1kHz 2.800––0.0R L=16Ω3.300––0.0No Digital Input(1)Headphone Output with MonoAnalog Mixing 2.4––0.520.38 2.22.8––0.540.42 2.73.3––0.550.46 3.3 (1)All digital inputs are held static.The audio serial interface for the PCM1774comprises LRCK,BCK,DIN,and DOUT.Sampling rate(f S),left and right channel are present on LRCK.DIN receives the serial data for the DAC interpolation filter,and DOUT transmits the serial data from the ADC decimation filter.BCK clocks the transfer of serial audio data on DIN and DOUT in its high-to-low transition.BCK and LRCK should be synchronized with audio system clock.Ideally,it is recommended that they be derived from it.The PCM1774requires LRCK to be synchronized with the system clock.The PCM1774does not require a specific phase relationship between LRCK and the system clock.The PCM1774has both master mode and slave mode interface formats,which can be selected by register84 (MSTR).In master mode,the PCM1774generates LRCK and BCK from the system clock.Audio Data Formats and TimingDINBCKLRCK50% of V IOIOIOSLAS551–JULY 2007The PCM1774supports I 2S,right-justified,left-justified,and DSP formats.The data formats are shown in Figure 16and are selected using registers 70and 81(RFM[1:0],PFM[1:0]).All formats require binary MSB-first audio data.The default format is I 2S.Figure 14shows a detailed timing diagram.PARAMETERSMIN MAX UNITSBCK pulse cycle time (I 2S,left-and right-justified formats)1/(64f S )(1)t (BCY)BCK pulse cycle time (DSP format)1/(256f S )(1)t w(BCH)BCK high-level time 35ns t w(BCL)BCK low-level time35ns t (BL)BCK rising edge to LRCK edge 10ns t (LB)LRCK edge to BCK rising edge 10ns t (DS)DIN set up time 10ns t (DH)DIN hold time10ns t r Rising time of all signals 10ns t f Falling time of all signals 10ns(1)f S is the sampling frequency.Figure 14.Audio Interface Timing (Slave Mode)DINBCK (Output)LRCK (Output)50% of V IOSCKI50% of V IOIO50% of V IOPARAMETERSMINMAX UNIT t (SCY)SCKI pulse cycle time1/(256f S )(1)t (DL)LRCK edge from SCKI rising edge 040ns t (DB)BCK edge from SCKI rising edge 040ns t (BCY)BCK pulse cycle time 1/(64f S )(1)t w(BCH)BCK high level time 146ns t w(BCL)BCK low level time 146ns t (DS)DATA setup time 10ns t (DH)DATA hold time10ns(1)f S is up to 48kHz.f S is the sampling frequency.Figure 15.Audio Interface Timing (Master Mode)(b) I 2(a)(= 32 f S , 48 f S (= 32 f S , 48 f S,LRCK BCKDIN LRCKBCKT0009-07(d)(64 f S LRCKBCK DIN LRCK (= 32 f S , 48 f S,(e)BCKDIN SLAS551–JULY 2007NOTE:All audio interface formats support BCK =64f S in master mode (register 69,MSTR =1).The f S of BCK at settingmulti-sampling rate (register 85and 86,NPR[5:0]and MSR[2:0])is shown in Table 9and Table 10.Figure 16.Audio Data FormatsTHREE-WIRE INTERFACE (SPI,MODE (PIN 28)=LOW)MSB IDX6IDX5IDX4IDX3IDX2IDX1IDX0D7D6D5D4D3D2D1D0LSB Register Index (or Address)Register DataR0001-01MC MS MD(1) Single Write Operation(2) Continuous Write OperationMC MS MDT0012-03All write operations for the serial control port use 16-bit data words.Figure 17shows the control data word format.The most-significant bit must be 0.There are seven bits,that set the register address for the write operation.The least-significant eight bits,D[7:0],contain the data to be written to the register specified by IDX[6:0].Figure 18shows the functional timing diagram for writing to the serial control port.To write the data into the the data is clocked into an internal shift register on the rising edge of the MC clock.The serial data should change on the falling edge of the MC clock,and MS should be LOW during write mode.The rising edge of MS should be aligned with the falling edge of the last MC clock pulse in the 16-bit frame.MC can run continuously between transactions while MS is in the LOW state.Figure 17.Control Data Word Format for MDFigure 18.Register Write Operation。