51单片机的中断优先级及中断嵌套

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MCS-51单片机的中断系统

MCS-51单⽚机的中断系统单⽚机中断技术概述在任何⼀款事件驱动型的CPU⾥⾯都应该会有中断系统，因为中断就是为响应某种事件⽽存在的。

中断的灵活应⽤不仅能够实现想要的功能，⽽且合理的中断安排可以提⾼事件执⾏的效率，因此中断在单⽚机应⽤中的地位是⾮常重要的。

单⽚机中断（Interrupt）是硬件驱动事件，它使得CPU暂停当前的主程序，转⽽去执⾏⼀个中断服务⼦程序。

为了更形象地理解中断，下⾯以学⽣上⾃习时接电话为例阐述⼀下中断的概念。

单⽚机的中断系统有5个中断源、2个中断优先级，可实现两级中断服务程序嵌套。

如果单⽚机没有中断系统，单⽚机的⼤量时间可能会浪费在查询是否有服务请求发⽣的定时査询操作上。

采⽤中断技术完全消除了单⽚机在査询⽅式中的等待现象，⼤⼤地提⾼了单⽚机的⼯作效率和实时性。

单⽚机中断系统结构及中断控制中断系统结构图如图5-2所⽰。

由图5-2可见，MCS-51中断系统共有5个中断请求源：INT0——外部中断请求0，中断请求信号由INT0引脚输⼊。

定时/计数器T0计数溢出发出的中断请求。

INT1——外部中断请求1，中断请求信号由INT1引脚输⼊。

定时/计数器T1计数溢出发出的中断请求。

串⾏⼝中断请求。

中断优先级从⾼到底排列。

单⽚机如何知道有中断请求信号？是否能够响应该中断？若5个中断源请求信号同时到来，单⽚机如何响应？这些问题都可以由中断寄存器来解决。

单⽚机中断寄存器有中断标志寄存器TCON和SCON、中断使能寄存器IE和中断优先级寄存器IP，这些寄存器均为8位。

中断标志寄存器5个中断请求源的中断请求标志分别由TCON和SCON的相应位锁存，单⽚机通过这些中断标志位的状态便能知道具体是哪个中断源正在申请中断。

TCON寄存器TCON寄存器为定时/计数器的控制寄存器，字节地址为88H，可位寻址。

特殊功能寄存器TCON的格式如图5-3所⽰。

TCON各标志位功能如下。

TF1——定时/计数器T1的溢出中断请求标志位。

单片机中的中断优先级与中断嵌套技术研究

单片机中的中断优先级与中断嵌套技术研究中断是单片机中的重要概念之一，它能够在特定条件下打断正常的程序执行流程，跳转到一个处理特定事件的子程序中执行，然后再回到原来的程序继续执行。

中断优先级和中断嵌套技术是单片机中处理中断的两个重要方面，对于中断服务程序的优化和系统性能的提升具有重要意义。

一、中断优先级的基本概念与作用中断优先级是指在多个中断请求同时到达时，根据设定的优先级确定哪个中断请求优先被处理。

单片机中的中断优先级是通过硬件电路实现的，不同的单片机具有不同数量的中断优先级位，即能够支持的中断请求个数。

中断优先级主要用于解决中断冲突问题。

当多个中断请求同时发生时，通过设置不同的中断优先级，可以确保高优先级的中断请求先被响应并进行处理。

这样可以提高系统的响应速度，保证重要事件的及时处理。

在设定中断优先级时，需要根据系统的实际需求来确定各个中断的优先级，一般会根据中断请求的紧急程度、重要性以及处理时间的长短等因素进行判断。

通常，系统关键性的中断请求具有较高的优先级，而次要的中断请求则具有较低的优先级。

二、中断嵌套技术的基本概念与实现中断嵌套是指在一个中断服务程序中，允许发生更高优先级的中断请求，并且暂时挂起当前正在执行的中断程序，转而处理更高优先级的中断请求。

中断嵌套技术在确保高优先级事件得到及时处理的同时，也提高了单片机系统的灵活性和效率。

1. 中断嵌套的实现方式单片机中的中断嵌套可以通过软件或硬件方式实现。

（1）软件方式：在编写中断服务程序时，可以通过设置相关的标志位来控制中断嵌套。

当中断请求到来时，会首先检查标志位，如果允许嵌套，则挂起当前中断程序，跳转到更高优先级的中断服务程序中执行；如果不允许嵌套，则忽略该中断请求。

（2）硬件方式：某些单片机芯片内部集成了硬件中断嵌套功能。

通过设置相应的硬件寄存器，可以实现中断嵌套的功能。

硬件方式能够更好地支持多个中断请求的处理和优先级设置，具有更高的灵活性和效率。

51单片机中断介绍

中断申请源的中断优先级的高低，由中断优先级控制寄存器 IP 的各位控制，
IP 的各位由用户用指令来设定。当系统复位后，IP 低 5 位全部清 0，所有中断源
均设定为低优先级中断。
如果几个同一优先级的中断源同时向 CPU 申请中断，CPU 通过内部硬件查
询逻辑，按自然优先级顺序确定先响应哪个中断请求。自然优先级由硬件形成，
（2） INT1 ：外部中断 1 请求，由 P3.3 脚输入。通过 IT1 脚（TCON.2）来决
定是低电平有效还是下跳变有效。一旦输入信号有效，则向 CPU 申请中断，并建立 IE1 标志。
（3）TF0：定时器 T0 溢出中断请求。当定时器 T0 产生溢出时，定时器 T0 中断请求标志位（TCON.5）置位（由硬件自动执行），请求中断处理。
务程序时，并不清“0”TI，TI 必须由用户的中断服务程序清“0”。
RI(SCON.0)：串行口接收中断标志，RI 为 1 表示串行口接收器正在向 CPU
申请中断，同样 RI 必须由用户的中断服务程序清“0”。
一般情况，以上五个中断源的中断请求标志是由中断机构硬件电路自动置位
的，但也可以人为的通过指令（SETB BIT），对以上两个控制寄存器的中断标志位置位，即“软件代请中断”，这是单片机中断系统的一大特点。
PX1（IP．2）：外部中断 1 中断优先级控制位。
PX1=1，为高优先级中断，PX1=0，为低优先级中断。
PT0（IP．1）：定时器/计数器 T0 中断优先级控制位。
PT0=1，为高优先级中断，PT1=0，为低优先级中断。
PX0（IP．0）：外部中断 0 中断优先级控制位。
PX0=1，为高优先级中断，PX0=0，为低优先级中断。

51单片机中断总结

51单片机中断总结：1. 查询优先级为固定的(外部中断0>定时器0>外部中断1>定时器1>串行中断)。

2. 执行优先级可以通过IP寄存器进行设置(高/低)。

3. CPU同时收到多个中断请求时，首先响应优先级较高者，然后相应优先级较低者；如果优先级相同，则按照查询优先级顺序依次响应。

4. 正在执行的中断服务，不能被同级或更低级的中断请求打断，但会被更高级的中断请求打断。

推论(1)高优先级的中断不能被任何其它中断所打断(2)低优先级的中断只能在没有任何中断服务运行时得到响应。

5. 对于定时器和外部中断，在进入中断服务后，其中断标志位会自动清零；对于串行中断，由于有两个中断源，需要手动查询并清零RI或/和TI。

if (RI) {// processingRI = 0;}if (TI) {// processingTI = 0;}6. 如果是使用汇编写中断服务，需要保护累加器、状态寄存器、寄存器组等8051 Tutorial: Interrupts/tutint.phpAs the name implies, an interrupt is some event which interrupts normal program execution.As stated earlier, program flow is always sequential, being altered only by those instructions which expressly cause program flow to deviate in some way. However, interrupts give us a mechanism to "put on hold" the normal program flow, execute a subroutine, and then resume normal program flow as if we had never left it. This subroutine, called an interrupt handler, is only executed when a certain event (interrupt) occurs. The event may be one of the timers "overflowing," receiving a character via the serial port, transmitting a character via the serialport, or one of two "external events." The 8051 may be configured so that when any of these events occur the main program is temporarily suspended and control passed to a special section of code which presumably would execute some function related to the event that occured. Once complete, control would be returned to the original program. The main program never even knows it was interrupted.The ability to interrupt normal program execution when certain events occur makes it much easier and much more efficient to handle certain conditions. If it were not for interrupts we would have to manually check in our main program whether the timers had overflown, whether we had received another character via the serial port, or if some external event had occured. Besides making the main program ugly and hard to read, such a situation would make our program inefficient since wed be burning precious "instruction cycles" checking for events that usually dont happen.For example, lets say we have a large 16k program executing many subroutines performing many tasks. Lets also suppose that we want our program to automatically toggle the P3.0 port every time timer 0 overflows. The code to do this isnt too difficult:JNB TF0,SKIP_TOGGLECPL P3.0CLR TF0SKIP_TOGGLE: ...Since the TF0 flag is set whenever timer 0 overflows, the above code will toggle P3.0 every time timer 0 overflows. This accomplishes what we want, but is inefficient. The JNB instruction consumes 2 instruction cycles to determine that the flag is not set and jump over the unnecessary code. In the event that timer 0 overflows, the CPL and CLR instruction require 2 instruction cycles to execute. To make the math easy, lets say the rest of the code in the program requires 98 instruction cycles. Thus, in total, our code consumes 100 instruction cycles (98 instruction cycles plus the 2 that are executed every iteration to determine whether or not timer 0 has overflowed). If were in 16-bit timer mode, timer 0 will overflow every 65,536 machine cycles. In that time we would have performed 655 JNB tests for a total of 1310 instruction cycles, plus another 2 instruction cycles to perform the code. So to achieve our goal weve spent 1312 instruction cycles. So 2.002% of our time is being spent just checking when to toggle P3.0. And our code is ugly because we have to make that check every iteration of our main program loop.Luckily, this isnt necessary. Interrupts let us forget about checking for the condition. The microcontroller itself will check for the condition automatically and when the condition is met will jump to a subroutine (called an interrupt handler), execute the code, then return. In this case, our subroutine would be nothing more than:CPL P3.0RETIFirst, youll notice the CLR TF0 command has disappeared. Thats because when the 8051 executes our "timer 0 interrupt routine," it automatically clears the TF0 flag. Youll also notice that instead of a normal RET instruction we have a RETI instruction. The RETI instruction does the same thing as a RET instruction, but tells the 8051 that an interrupt routine has finished. You must always end your interrupt handlers with RETI.Thus, every 65536 instruction cycles we execute the CPL instruction and the RETI instruction. Those two instructions together require 3 instruction cycles, and weve accomplished the same goal as the first example that required 1312 instruction cycles. As far as the toggling of P3.0 goes, our code is 437 times more efficient! Not to mention its much easier to read and understand because we dont have to remember to always check for the timer 0 flag in our main program. We just setup the interrupt and forget about it, secure in the knowledge that the 8051 will execute our code whenever its necessary.The same idea applies to receiving data via the serial port. One way to do it is to continuously check the status of the RI flag in an endless loop. Or we could check the RI flag as part of a larger program loop. However, in the latter case we run the risk of missing characters--what happens if a character is received right after we do the check, the rest of our program executes, and before we even check RI a second character has come in. We will lose the first character. With interrupts, the 8051 will put the main program "on hold" and call our special routine to handle the reception of a character. Thus, we neither have to put an ugly check in our main code nor will we lose characters.What Events Can Trigger Interrupts, and where do they go?We can configure the 8051 so that any of the following events will cause an interrupt:Timer 0 Overflow.Timer 1 Overflow.Reception/Transmission of Serial Character.External Event 0.External Event 1.In other words, we can configure the 8051 so that when Timer 0 Overflows or when a character is sent/received, the appropriate interrupt handler routines are called.Obviously we need to be able to distinguish between various interrupts and executing different code depending on what interrupt was triggered. This is accomplished by jumping to a fixed address when a given interrupt occurs.Interrupt Flag Interrupt Handler AddressExternal 0 IE0 0003hTimer 0 TF0 000BhExternal 1 IE1 0013hTimer 1 TF1 001BhSerial RI/TI 0023hBy consulting the above chart we see that whenever Timer 0 overflows (i.e., the TF0 bit is set), the main program will be temporarily suspended and control will jump to 000BH. It is assumed that we have code at address 000BH that handles the situation of Timer 0 overflowing.Setting Up InterruptsBy default at powerup, all interrupts are disabled. This means that even if, for example, the TF0 bit is set, the 8051 will not execute the interrupt. Your program must specifically tell the 8051 that it wishes to enable interrupts and specifically which interrupts it wishes to enable.Your program may enable and disable interrupts by modifying the IE SFR (A8h):Bit Name Bit Address Explanation of Function7 EA AFh Global Interrupt Enable/Disable6 - AEh Undefined5 - ADh Undefined4 ES ACh Enable Serial Interrupt3 ET1 ABh Enable Timer 1 Interrupt2 EX1 AAh Enable External 1 Interrupt1 ET0 A9h Enable Timer 0 Interrupt0 EX0 A8h Enable External 0 InterruptAs you can see, each of the 8051s interrupts has its own bit in the IE SFR. You enable a given interrupt by setting the corresponding bit. For example, if you wish to enable Timer 1 Interrupt, you would execute either:MOV IE,#08horSETB ET1Both of the above instructions set bit 3 of IE, thus enabling Timer 1 Interrupt. Once Timer 1 Interrupt is enabled, whenever the TF1 bit is set, the 8051 will automatically put "on hold" the main program and execute the Timer 1 Interrupt Handler at address 001Bh.However, before Timer 1 Interrupt (or any other interrupt) is truly enabled, you must also set bit 7 of IE. Bit 7, the Global Interupt Enable/Disable, enables or disables all interrupts simultaneously. That is to say, if bit 7 is cleared then no interrupts will occur, even if all the other bits of IE are set. Setting bit 7 will enable all the interrupts that have been selected by setting other bits in IE. This is useful in program execution if you have time-critical code that needs to execute. In this case, you may need the code to execute from start to finish without any interrupt getting in the way. To accomplish this you can simply clear bit 7 of IE (CLR EA) and then set it after your time-criticial code is done.So, to sum up what has been stated in this section, to enable the Timer 1 Interrupt the most common approach is to execute the following two instructions:SETB ET1SETB EAThereafter, the Timer 1 Interrupt Handler at 01Bh will automatically be called whenever the TF1 bit is set (upon Timer 1 overflow).Polling SequenceThe 8051 automatically evaluates whether an interrupt should occur after every instruction. When checking for interrupt conditions, it checks them in the following order:External 0 InterruptTimer 0 InterruptExternal 1 InterruptTimer 1 InterruptSerial InterruptThis means that if a Serial Interrupt occurs at the exact same instant that an External 0 Interrupt occurs, the External 0 Interrupt will be executed first and the Serial Interrupt will be executed once the External 0 Interrupt has completed.Interrupt PrioritiesThe 8051 offers two levels of interrupt priority: high and low. By using interrupt priorities you may assign higher priority to certain interrupt conditions.For example, you may have enabled Timer 1 Interrupt which is automatically called every time Timer 1 overflows. Additionally, you may have enabled the Serial Interrupt which is called every time a character is received via the serial port. However, you may consider that receiving a character is much more important than the timer interrupt. In this case, if Timer 1 Interrupt is already executing you may wish that the serial interrupt itself interrupts the Timer 1 Interrupt. When the serial interrupt is complete, control passes back to Timer 1 Interrupt and finally back to the main program. You may accomplish this by assigning a high priority to the Serial Interrupt and a low priority to the Timer 1 Interrupt.Interrupt priorities are controlled by the IP SFR (B8h). The IP SFR has the following format:Bit Name Bit Address Explanation of Function7 - - Undefined6 - - Undefined5 - - Undefined4 PS BCh Serial Interrupt Priority3 PT1 BBh Timer 1 Interrupt Priority2 PX1 BAh External 1 Interrupt Priority1 PT0 B9h Timer 0 Interrupt Priority0 PX0 B8h External 0 Interrupt PriorityWhen considering interrupt priorities, the following rules apply:Nothing can interrupt a high-priority interrupt--not even another high priority interrupt.A high-priority interrupt may interrupt a low-priority interrupt.A low-priority interrupt may only occur if no other interrupt is already executing.If two interrupts occur at the same time, the interrupt with higher priority will execute first. If both interrupts are of the same priority the interrupt which is serviced first by polling sequence will be executed first.What Happens When an Interrupt Occurs?When an interrupt is triggered, the following actions are taken automatically by the microcontroller:The current Program Counter is saved on the stack, low-byte first.Interrupts of the same and lower priority are blocked.In the case of Timer and External interrupts, the corresponding interrupt flag is cleared.Program execution transfers to the corresponding interrupt handler vector address.The Interrupt Handler Routine executes.Take special note of the third step: If the interrupt being handled is a Timer or External interrupt, the microcontroller automatically clears the interrupt flag before passing control to your interrupt handler routine. This means it is not necessary that you clear the bit in your code.What Happens When an Interrupt Ends?An interrupt ends when your program executes the RETI (Return from Interrupt) instruction. When the RETI instruction is executed the following actions are taken by the microcontroller:Two bytes are popped off the stack into the Program Counter to restore normal program execution.Interrupt status is restored to its pre-interrupt status.Serial InterruptsSerial Interrupts are slightly different than the rest of the interrupts. This is due to the fact that there are two interrupt flags: RI and TI. If either flag is set, a serial interrupt is triggered. As you will recall from the section on the serial port, the RI bit is set when a byte is received by the serial port and the TI bit is set when a byte has been sent.This means that when your serial interrupt is executed, it may have been triggered because the RI flag was set or because the TI flag was set--or because both flags were set. Thus, your routine must check the status of these flags to determine what action is appropriate. Also, since the 8051 does not automatically clear the RI and TI flags you must clear these bits in your interrupt handler.A brief code example is in order:INT_SERIAL: JNB RI,CHECK_TI ;If the RI flag is not set, we jump to check TIMOV A,SBUF ;If we got to this line, its because the RI bit *was* setCLR RI ;Clear the RI bit after weve processed itCHECK_TI: JNB TI,EXIT_INT ;If the TI flag is not set, we jump to the exit pointCLR TI ;Clear the TI bit before we send another characterMOV SBUF,#A ;Send another character to the serial portEXIT_INT: RETIAs you can see, our code checks the status of both interrupts flags. If both flags were set, both sections of code will be executed. Also note that each section of code clears its corresponding interrupt flag. If you forget to clear the interrupt bits, the serial interrupt will be executed over and over until you clear the bit. Thus it is very important that you always clear the interrupt flags in a serial interrupt.Important Interrupt Consideration: Register ProtectionOne very important rule applies to all interrupt handlers: Interrupts must leave the processor in the same state as it was in when the interrupt initiated.Remember, the idea behind interrupts is that the main program isnt aware that they are executing in the "background." However, consider the following code:CLR C ;Clear carryMOV A,#25h ;Load the accumulator with 25hADDC A,#10h ;Add 10h, with carryAfter the above three instructions are executed, the accumulator will contain a value of 35h.But what would happen if right after the MOV instruction an interrupt occured. During this interrupt, the carry bit was set and the value of the accumulator was changed to 40h. When the interrupt finished and control was passed back to the main program, the ADDC would add 10h to 40h, and additionally add an additional 1h because the carry bit is set. In this case, the accumulator will contain the value 51h at the end of execution.In this case, the main program has seemingly calculated the wrong answer. How can 25h + 10h yield 51h as a result? It doesnt make sense. A programmer that was unfamiliar with interrupts would be convinced that the microcontroller was damaged in some way, provoking problems with mathematical calculations.What has happened, in reality, is the interrupt did not protect the registers it used. Restated: An interrupt must leave the processor in the same state as it was in when the interrupt initiated.What does this mean? It means if your interrupt uses the accumulator, it must insure that the value of the accumulator is the same at the end of the interrupt as it was at the beginning. This is generally accomplished with a PUSH and POP sequence. For example:PUSH ACCPUSH PSWMOV A,#0FFhADD A,#02hPOP PSWPOP ACCThe guts of the interrupt is the MOV instruction and the ADD instruction. However, these two instructions modify the Accumulator (the MOV instruction) and also modify the value of the carry bit (the ADD instruction will cause the carry bit to be set). Since an interrupt routine must guarantee that the registers remain unchanged by the routine, the routine pushes the original values onto the stack using the PUSH instruction. It is then free to use the registers it protected to its hearts content. Once the interrupt has finished its task, it pops the original values back into the registers. When the interrupt exits, the main program will never know the difference because the registers are exactly the same as they were before the interrupt executed.In general, your interrupt routine must protect the following registers:PSWDPTR (DPH/DPL)PSWACCBRegisters R0-R7Remember that PSW consists of many individual bits that are set by various 8051 instructions. Unless you are absolutely sure of what you are doing and have a complete understanding of what instructions set what bits, it is generally a good idea to always protect PSW by pushing and popping it off the stack at the beginning and end of your interrupts.Note also that most assemblers (in fact, ALL assemblers that I know of) will not allow you to execute the instruction:PUSH R0This is due to the fact that depending on which register bank is selected, R0 may refer to either internal ram address 00h, 08h, 10h, or 18h. R0, in and of itself, is not a valid memory address that the PUSH and POP instructions can use.Thus, if you are using any "R" register in your interrupt routine, you will have to push that registers absolute address onto the stack instead of just saying PUSH R0. For example, instead of PUSH R0 you would execute:PUSH 00hOf course, this only works if youve selected the default register set. If you are using an alternate register set, you must PUSH the address which corresponds to the register you are using.Common Problems with InterruptsInterrupts are a very powerful tool available to the 8051 developer, but when used incorrectly they can be a source of a huge number of debugging hours. Errors in interrupt routines are often very difficult to diagnose and correct.If you are using interrupts and your program is crashing or does not seem to be performing as you would expect, always review the following interrupt-related issues:Register Protection: Make sure you are protecting all your registers, as explained above. If you forget to protect a register that your main program is using, very strange results may occur. In our example above we saw how failure to protect registers caused the main program to apparently calculate that 25h + 10h = 51h. If you witness problems with registers changing values unexpectedly or operations producing "incorrect" values, it is very likely that you've forgotten to protect registers. ALWAYS PROTECT YOUR REGISTERS.Forgetting to restore protected values: Another common error is to push registers onto the stack to protect them, and then forget to pop them off the stack before exiting the interrupt. For example, you may push ACC, B, and PSW onto the stack in order to protect them and subsequently pop only ACC and PSW off the stack before exiting. In this case, since you forgot to restore the value of "B", an extra value remains on the stack. When you execute the RETI instruction the 8051 will use that value as the return address instead of the correct value. In this case, your program will almost certainly crash. ALWAYS MAKE SURE YOU POP THE SAME NUMBER OF VALUES OFF THE STACK AS YOU PUSHED ONTO IT.Using RET instead of RETI: Remember that interrupts are always terminated with the RETI instruction. It is easy to inadvertantly use the RET instruction instead. However, the RETinstruction will not end your interrupt. Usually, using a RET instead of a RETI will cause the illusion of your main program running normally, but your interrupt will only be executed once. If it appears that your interrupt mysteriously stops executing, verify that you are exiting with RETI.11。

mcs-51单片机中断系统的结构[整理版]

1．简述中断、中断源、中断源的优先级及中断嵌套的含义。

答: 当CPU 正在处理某项事件的时，如果外界或内部发生了紧急情况，要求CPU 暂停正在处理的工作转而去处理这个紧急情况，待处理完以后再回到原来被中断的地方，继续执行原来被中断了的程序，这样的过程称为中断。

单片机采用中断主要有如下几个优点：①可以提高CPU 工作效率；②具有实时处理能力；③具有故障处理能力；④实现分时操作，可控制多个外设同时工作。

向CPU 提出中断请求的源称为中断源；当系统有多个中断源时，就可能出现同时有几个中断源申请中断，而CPU 在一个时刻只能响应并处理中断优先高的请求；在实际应用系统中，当CPU 正在处理某个中断源，即正在执行中断服务程序时，会出现优先级更高的中断源申请中断。

为了使更紧急的级别高的中断源及时得到服务，需要暂时中断（挂起）当前正在执行的级别较低的中断服务程序，去处理级别更高的中断源，待处理完以后，再返回到被中断了的中断服务程序继续执行，但级别相同或级别低的中断源不能中断级别高的中断服务，这就是所谓的中断嵌套。

3．MCS-51 单片机能提供几个中断源？几个中断优先级？各个中断的源的优先级怎样确定？在同一优先级中各个中断源的优先级怎样确定？答: 51 单片机有5 个中断源，两个中断优先级：INT0 、T0、INT1 、T1、串行口中断（包括串行接收中断RI 和串行发送中断TI）。

这 5 个中断源的中断入口地址分别是0003H、000BH、0013H、001BH、0023H。

中断优先级是由片内的中断优先级寄存器IP（特殊功能寄存器）控制的。

PS：串行口中断优先级控制位。

PS=1，串行口定义为高优先级中断源；PS=0，串行口定义为低优先级中断源；PT1：T1 中断优先级控制位。

PT1=1，定时器/计数器 1 定义为高优先级中断源；PT1=0，定时器/计数器 1 定义为低优先级中断源；PX1：外部中断 1 中断优先级控制位。

51单片机中断优先控制的基本原则

51单片机中断优先控制的基本原则以51单片机中断优先控制的基本原则为标题中断是51单片机中的一种重要的工作模式，它可以在程序运行过程中，根据外部或内部事件的发生而中断正常的程序执行，执行相应的中断服务程序，处理完中断事件后再返回到原来的程序继续执行。

中断优先级控制是指当多个中断同时发生时，系统根据优先级确定中断服务程序的执行顺序。

本文将介绍51单片机中断优先级控制的基本原则。

1. 中断优先级的确定在51单片机中，中断的优先级是由中断源的优先级决定的。

一般来说，硬件中断具有更高的优先级，而软件中断（如定时器中断）具有较低的优先级。

在设计系统时，需要根据实际需求确定中断源的优先级，以确保高优先级中断能够及时响应。

2. 中断嵌套中断嵌套是指当一个中断正在执行时，另一个更高优先级的中断发生，系统会中断当前中断的执行，去执行更高优先级的中断服务程序。

在51单片机中，中断嵌套是默认开启的，可以通过设置中断标志位来禁止中断嵌套。

在设计系统时，需要考虑中断嵌套对系统性能的影响，合理设置中断嵌套的开启与禁止。

3. 中断优先级的编码在51单片机中，中断优先级是通过中断优先级编码来实现的。

中断优先级编码是一个二进制编码，通常使用8位来表示。

在设计系统时，需要根据中断源的优先级确定中断优先级编码，以确保中断优先级的正确设置。

4. 中断服务程序的编写中断服务程序是中断发生时要执行的一段代码，在设计系统时，需要根据实际需求编写相应的中断服务程序。

在编写中断服务程序时，需要注意以下几点：- 中断服务程序的执行时间应尽量短，以免影响其他任务的执行。

- 中断服务程序中的变量应使用关键字volatile进行声明，以确保其在中断和非中断代码之间的一致性。

- 中断服务程序中的关键代码应使用临界区保护，以防止多个中断同时修改共享资源导致数据错误。

5. 中断优先级的配置在51单片机中，中断优先级的配置是通过特定的寄存器来实现的。

具体的配置方法可以参考51单片机的相关资料或开发工具的使用手册。

MCS—51系统中断优先级...

摘要鉴于MCS-51系统只提供“二级中断嵌套”，提出扩展51系统中断优先级的纯软件方法。

其利用51系统内建的中断允许寄存器IE和中断优先级寄存器IP，通过屏蔽字机制来实现；以C51的形式，给出这种扩展方法的函数库实现，为该方法的使用赋予友好、简洁的用户接口。

大家都知道，MCS-51系统只提供“二级中断嵌套”，而大多数嵌入式系统希望有多于两级的优先级别。

因为一般来说，系统都有掉电中断，且应置为最高优先级，这样所有其它中断只能共用一个最低优先级，如此，往往不能满足实际的逻辑需求。

为了使系统具有多于两级的中断优先级别，可以利用8259A之类的中断控制芯片实现中断优先级的硬扩展，但却增加了系统的造价和复杂性。

因复杂性的提高，系统的可靠性将受到影响。

本文提出一种扩展MCS-51系统中断优先级的纯软件方法，不需增加任何硬件，且所需的额外资源消耗也很小。

实际应用表明这种方法是可行的和有效的。

关键词：MCS-51单片机、中断优先级、软扩展、C51Abstract51 - MCS due to provide only "secondary interruption, expand nested" 51 system of pure software interrupt priority. The use of the built-in 51 system allows register interrupt and interrupt priority IE IP, through the shield word registers mechanism to realize, In the form of C51 extension methods for realizing the function of library, the use of this method gives friendly user interface, concise.As is known to all, 51 - MCS provide only "2" and interrupt nested most embedded system is more than two level to priority level. Because in general, systems have power to be interrupted, and the highest priority, so that all the other interrupts can share a lowest priority, so, often cannot meet the practical needs of logic. In order to make the system has more than two levels of interrupt priority level, can use 8259A interrupt control chip realization of hardware interrupt priority, but increased the cost of system and complexity. Because of the complexity of improving the reliability of the system will be affected. This paper proposes a kind of expansion MCS - 51 system software interrupt priority methods of pure, do not need to add any additional hardware, and resource consumption is small. Actual application shows that this method is feasible and effective.Keywords: MCS - 51 SCM、interrupt priority、soft extension、C51目录第一章 MCS-51单片机介绍及中断系统简介 (1)第一节 MCS-51单片机介绍 (1)第二节中断系统简介 (1)第二章中断优先级软扩展的方法 (3)第一节方法一 (3)第二节方法二 (6)第三节方法三 (6)第三章优先级软扩展的函数库实现 (7)结束语 (11)谢辞 (12)参考文献 (13)第一章 MCS-51单片机介绍及中断系统简介第一节 MCS-51单片机介绍MCS-51单片机是指由美国INTEL公司（大名鼎鼎的INTEL）生产的一系列单片机的总称，这一系列单片机包括了好些品种，如8031，8051，8751，8032，8052，8752等，其中8051是最早最典型的产品，该系列其它单片机都是在8051的基础上进行功能的增、减、改变而来的，所以人们习惯于用8051来称呼MCS-51系列单片机，而8031是前些年在我国最流行的单片机，所以很多场合会看到8031的名称。

C51单片机中断(两篇)

引言:C51单片机中断是单片机开发中一个非常重要的概念。

通过中断，程序能够在运行过程中及时响应外部事件，提高系统的实时性和可靠性。

本文将进一步探讨C51单片机中断的相关知识，特别是中断优先级、中断嵌套、中断服务函数等方面的内容。

概述:C51单片机中断机制是通过改变程序的执行流程来实现的。

当中断事件发生时，CPU会暂停当前的执行任务，保存现场后转去执行中断服务程序，待中断服务程序执行完毕后，再恢复到之前的执行状态。

C51单片机中断机制通过这样的方式，有效地实现了对外部事件的及时响应。

正文内容:1. 中断优先级1.1 中断优先级的概念中断优先级是指在多个中断事件同时发生时，CPU按照一定的优先级顺序处理这些中断请求。

在C51单片机中，中断优先级是通过中断控制器来实现的。

中断控制器按照预先设定的优先级进行中断请求的响应，优先级越高的中断请求将被优先处理。

1.2 中断优先级的设置在C51单片机中，中断优先级的设置是通过特殊功能寄存器（SFR）来完成的。

通过设置SFR中的相关位，可以对不同的中断请求进行优先级设置。

具体的设置方法可以参考C51单片机的相关手册和数据手册。

2. 中断嵌套2.1 中断嵌套的概念中断嵌套是指在中断服务程序执行过程中，又发生了其他的中断事件，并且这些中断事件的优先级高于当前正在执行的中断服务程序。

在C51单片机中，中断嵌套是通过中断控制器的中断请求线来实现的。

当一个中断事件发生时，如果其优先级高于当前执行的中断服务程序，CPU会立即切换到新的中断服务程序中去执行。

2.2 中断嵌套的处理方法在C51单片机中，中断嵌套的处理是通过中断服务程序的堆栈来实现的。

当发生中断嵌套时，CPU将当前的现场信息保存到堆栈中，然后切换到新的中断服务程序中执行。

当新的中断服务程序执行完毕后，CPU会从堆栈中恢复之前的现场信息，并回到原来的中断服务程序继续执行。

3. 中断服务函数3.1 中断服务函数的概念中断服务函数是指用来处理中断事件的函数。

51单片机中断系统详解

51单片机中断系统详解51 单片机中断系统详解(定时器、计数器)51 单片机中断级别中断源INT0---外部中断0/P3.2 T0---定时器/计数器0 中断/P3.4 INT1---外部中断1/P3.3 T1----定时器/计数器1 中断/P3.5 TX/RX---串行口中断T2---定时器/计数器 2 中断第5 最低4 5 默认中断级别最高第2 第3 第4 序号(C 语言用) 0 1 2 3 intrrupt 0中断允许寄存器IE位序号符号位EA/0 ------ET2/1 ES ET1 EX1 ET0 EX0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 EA---全局中允许位。

EA=1,打开全局中断控制，在此条件下，由各个中断控制位确定相应中断的打开或关闭。

EA=0,关闭全部中断。

-------,无效位。

ET2---定时器/计数器2 中断允许位。

ET2=1, 打开T2 中断。

ET2=0,关闭T2 中断。

关，。

ES---串行口中断允许位。

关，。

ES=1,打开串行口中断。

关，。

ES=0,关闭串行口中断。

关，。

ET1---定时器/计数器1 中断允许位。

关，。

ET1=1,打开T1 中断。

ET1=0,关闭T1 中断。

EX1---外部中断1 中断允许位。

EX1=1,打开外部中断1 中断。

EX1=0,关闭外部中断1 中断。

ET0---定时器/计数器0 中断允许位。

ET0=1,打开T0 中断。

EA 总中断开关，置1 为开；EX0 为外部中断0 (INT0) 开关，。

ET0 为定时器/计数器0(T0)开EX1 为外部中断1(INT1)开ET1 为定时器/计数器1(T1)开ES 为串行口(TX/RX)中断开ET2 为定时器/计数器2(T2)开ET0=0,关闭T0 中断。

EX0---外部中断0 中断允许位。

EX0=1,打开外部中断0 中断。

EX0=0,关闭外部中断0 中断。

中断优先级寄存器IP位序号位地址------PS/0 PT1/0 PX1/0 PT0/0 PX0/0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 -------,无效位。

51单片机中的中断优先级总结

51单片机中的中断优先级总结这段时间编写51的控制板程序，两个大牛技术指导对51中断嵌套问题的看法不一样，后来亲自验证了一下，得到了一下的一些结论，发上来大家参考，表达不清的地方还望理解，呵呵。

51单片机的中断可嵌套，但至多支持二级嵌套。

51单片机的默认（此时的IP寄存器不做设置）中断优先级为：外部中断0 > 定时/计数器0 > 外部中断1 > 定时/计数器1 > 串行中断；但这种优先级只是逻辑上的优先级，当同时有几种中断到达时，高优先级中断会先得到服务。

这种优先级实际上是中断同时到达的情况下，谁先得到服务的优先级，而不是可提供中断嵌套能力的优先级。

这种优先级被称为逻辑优先级。

例如：当计数器0中断和外部中断1（优先级计数器0中断>外部中断1）同时到达时，会进入计时器0的中断服务函数；但是在外部中断1的中断服务函数正在服务的情况下，这时候任何中断都是打断不了它的，包括逻辑优先级比它高的外部中断0计数器0中断。

要实现真正的嵌套形式的优先级，也即高优先级中断服务可以打断低优先级中断服务的情况，必须通过设置中断优先级寄存器IP来实现；这种优先级被称为物理优先级。

例如：设置IP = 0x10，即设置串口中断为最高优先级，则串口中断可以打断任何其他的中断服务函数实现嵌套，且只有串口中断能打断其他中断的服务函数。

若串口中断没有触发，则其他几个中断之间还是保持逻辑优先级，相互之间无法嵌套。

回复于：2009-10-26 16:09:35只要硬件堆栈足够.嵌套没有级数限制。

#4楼得分：0回复于：2009-10-28 10:57:5851只有两个优先级所以只能有两级嵌套！SEI是AVR单片机的，他没有分优先级，所以支持这种嵌套！C51中interrupt和using的用法void INT0（）interrupt 0 using 1{.........}interrupt 0 指明是外部中断0；interrupt 1 指明是定时器中断0；interrupt 2 指明是外部中断1；interrupt 3 指明是定时器中断1；interrupt 4 指明是串行口中断；using 0 是第0组寄存器；using 1 是第1组寄存器；using 2 是第2组寄存器；using 3 是第3组寄存器；51单片机内的寄存器是R0--R7（不是R0-R3）R0-R7在数据存储器里的实际地址是由特殊功能寄存器PSW里的RS1、RS0位决定的。

c51单片机中断详解

响应中断请求的条件
一、一个中断请求被响应，需满足以下必要条件：
（1）IE寄存器中的中断总允许位EA=1。
（2）该中断源发出中断请求，即该中断源对应的中断请求标志为“1”。
（3）该中断源的中断允许位=1，即该中断没有被屏蔽。
（4）无同级或更高级中断正在被服务。
二、中断响应的主要过程
中断源
或者用： MOV 0A8H，#8AH ；A8H为IE寄存器字节地址
三、中断优先级寄存器IP 两个中断优先级，可实现两级中断嵌套。如图所示：
每个中断源的中断优先级都是由中断优先级寄存器IP中的相应位的状态来控制的。中断优先级寄存器IP，其字节地址为B8H。
IP各个位的含义：（1）PS——串行口中断优先级
控制位 1：高优先级中断； 0：低优先级中断。
（2）PT1——定时器T1中断优先级控制位 1：高优先级中断； 0：低优先级中断。
（3）PX1——外部中断1中断优先级控制位 1：高优先级中断； 0：低优先级中断。
（4）PT0——定时器T0中断优先级控制位 1：高优先级中断； 0：低优先级中断。
（5）PX0——外部中断0中断优先级控制位 1：高优先级中断； 0：低优先级中断。
地址是固定的，不能改动。
例
三、中断处理编写中断中断服务程序即可
四、中断返回
▪中断返回由专门的中断返回指令 RETI来实现。
五、中断请求的撤消 2．外部中断请求的撤消（1）跳沿方式外部中断请求的撤消是自动撤消的。（2）电平方式外部中断请求的撤消。
六、外部中断的响应时间外部中断的最短的响应时间为3
二、中断允许控制
中断允许控制寄存器IE
CPU对中断源的开放或屏蔽，由片内的中断允许寄存器IE控制（两级控制）。字节地址为A8H，可位寻址。格式如下：

51单片机的中断系统

51单片机的中断系统8031单片机的中断系统简单实用，其基本特点是：有5个固定的可屏蔽中断源，3个在片内，2个在片外，它们在程序存储器中各有固定的中断入口地址，由此进入中断服务程序；5个中断源有两级中断优先级，可形成中断嵌套；2个特殊功能寄存器用于中断控制和条件设置的编程。

中断系统的结构：5个中断源的符号、名称及产生的条件如下。

INT0：外部中断0，由P3．2端口线引入，低电平或下跳沿引起。

INT1：外部中断1，由P3．3端口线引入，低电平或下跳沿引起。

T0：定时器／计数器0中断，由T0计满回零引起。

T1：定时器／计数器l中断，由T1计满回零引起。

TI／RI：串行I／O中断，串行端口完成一帧字符发送／接收后引起。

整个中断系统的结构框图见下图一所示。

由图一可见，外部中断有下跳沿引起和低电平引起的选择；串行中断有发送(TI)相接收(R1)的区别；各个中断源打开与否，受中断自身的允许位和全局允许位的控制，并具有高优先级和低优先级的选择。

中断系统的控制寄存器：中断系统有两个控制寄存器IE和IP，它们分别用来设定各个中断源的打开／关闭和中断优先级。

此外，在TCON中另有4位用于选择引起外部中断的条件并作为标志位。

IE在特殊功能寄存器中，字节地址为A8H，位地址(由低位到高位)分别是A8H-AFH。

IE用来打开或关断各中断源的中断请求，基本格式如下图二所示：EA：全局中断允许位。

EA＝0，关闭全部中断；EA＝1，打开全局中断控制，在此条件下，由各个中断控制位确定相应中断的打开或关闭。

×：无效位。

ES：串行I／O中断允许位。

ES＝1，打开串行I／O中断；ES＝0，关闭串行I ／O中断。

ETl；定时器／计数器1中断允许位。

ETl＝1，打开T1中断；ETl＝O，关闭T1中断。

EXl：外部中断l中断允许位。

EXl＝1，打开INT1；EXl＝0，关闭INT1。

ET0：定时器／计数器0中断允许位。

ET0＝1，打开T0中断；ET0＝0，关闭TO中断。

MCS51单片机中断系统

中断程序入口地址
五个中断程序的入口地址为：五个中断程序的入口地址为：外中断0 INT0）外中断0（INT0）：0003H 定时器0 T0）定时器0（T0）：000BH 外中断1 INT1）外中断1（INT1）：0013H 定时器1 T1）定时器1（T1）：001BH 串行口（RI/TI）串行口（RI/TI）：0023H
可归纳为下面两条基本规则：可归纳为下面两条基本规则：（1）低优先级可被高优先级中断，反之则不能。低优先级可被高优先级中断，反之则不能。（2）同级中断不会被它的同级中断源所中断。）同级中断不会被它的同级中断源所中断。
CPU正在执行高优先级的中断正在执行高优先级的中断，若 CPU 正在执行高优先级的中断，则不能被任何中断源所中断。源所中断。中断优先级寄存器IP 其字节地址为B IP，中断优先级寄存器IP，其字节地址为B8H。
寄存器名称 D7 定时器控制 TCON(88H TF1 寄存器 ) 位地址 8FH 串行口控制 SCON(98H) 寄存器位地址 9FH 中断允许 IE(A8H) EA 寄存器位地址 AFH 中断优先级 IP(B8H) 寄存器位地址 D6 D5 TF0 8DH 9DH D4 D3 IE1 8BH D2 IT1 8AH D1 IE0 89H TI 99H ET0 A9H PT0 B9H D0 IT0 88H RI 98H EX0 A8H PX0 B8H
MCS-51复位后，IE清 MCS-51复位后，IE清0，所有中断请求被禁止。复位后所有中断请求被禁止。若使某一个中断源被允许中断，除了IE IE相应的位的被若使某一个中断源被允许中断，除了IE相应的位的被还必须使EA =1。 EA位置“1” ，还必须使EA位=1。改变IE的内容，可由位操作指令来实现， IE的内容改变IE的内容，可由位操作指令来实现，即： bit； SETB bit； bit。 CLR bit。若允许片内2个定时器/计数器中断，例5-1 若允许片内2个定时器/计数器中断，禁止其它中断源的中断请求。编写设置IE IE的相应程序段中断源的中断请求。编写设置IE的相应程序段用位操作指令来编写如下程序段：（1）用位操作指令来编写如下程序段： CLR ES ；禁止串行口中断 EX1 禁止外部中断1 CLR EX1 ；禁止外部中断1中断 EX0 禁止外部中断0 CLR EX0 ；禁止外部中断0中断

C51单片机的中断解析

对同时发生多个中断申请时： ☞不同优先级的中断同时申请(很难遇到) ——先高后低 ☞相同优先级的中断同时申请(很难遇到) ——按序执行 ☞正处理低优先级中断又接到高级别中断 ——高打断低 ☞正处理高优先级中断又接到低级别中断 ——高不理低
自然优先级:

INT0 T0 INT1 T1 RI/TI
中断源

入口地址
0003H 000BH 0013H 001BH 0023H

INT0 T0 INT1 T1 RI/TI
特别注意：这些工作是硬件自动完成的！
5.中断入口地址安排跳转指令：如：ORG 0003H LJMP INTT0 INTT0: 中断服务子程序 RETI
二、中断处理
IP B8H
7
6
5
4 PS
3 2 1 0 PT1 PX1 PT0 PX0
51单片机有两个中断优先级——高级和低级
专用寄存器IP为中断优先级寄存器，用户可用软件设定
相应位为1，对应的中断源被设置为高优先级，相应位为0，对应的中断源被设置为低优先级系统复位时，均为低优先级
中断优先级处理原则
高
CPU正在执行低中断源
高中断源
低
RETI
RETI
中断控制寄存器汇总
寄存器名称定时器控制 TCON(88H) 寄存器位地址串行口控制 SCON(98H) 寄存器位地址中断允许 IE(A8H) 寄存器位地址中断优先级 IP(B8H) 寄存器位地址 D7 D6 D5 D4 TF1 TF0 8FH 8EH 8DH 8CH 9FH 9EH EA AFH 9DH D3 IE1 8BH D2 IT1 8AH D1 IE0 89H TI 99H ET0 A9H PT0 B9H D0 IT0 88H RI 98H EX0 A8H PX0 B8H

MCS51的中断系统有几个中断源

．MCS51的中断系统有几个中断源？几个中断优先级？中断优先级是如何控制的？在出现同级中断申请时，CPU按什么顺序响应（按由高级到低级的顺序写出各个中断源）？各个中断源的入口地址是多少？答：MCS51单片机有5个中断源，2个中断优先级，中断优先级由特殊功能寄存器IP控制，在出现同级中断申请时，CPU按如下顺序响应各个中断源的请求：INT0、T0、INT1、T1、串口，各个中断源的入口地址分别是0003H、000BH、0013H、001BH、0023H。

3．MCS51系列单片机的内部资源有哪些？说出8031、8051和8751的区别。

答：MCS51系列单片机上有1个8位CPU、128B的RAM、21个SFR、4个并行口、1个串行口、2个定时计数器和中断系统等资源。

8031、8051和8751的区别是8031内无ROM；8051内有4KB的掩膜ROM；8751内有4KB的EPROM。

五、作图题（10分）用6264（8K*8）构成16K的数据存储系统。

要求采用线选法产生片选信号，并计算6264的地址范围答：WR接6264的WERD接6264的OEAB0---AB12接6264的A0---A12DB0—DB7接6264的D0—D7AB15、AB14分别接Y0和Y1地址：0000H---1FFFH；2000H---3FFFH六、设计题（1题13分；2题12分，共25分）1．某单片机控制系统有8个发光二极管。

试画出89C51与外设的连接图并编程使它们由左向右轮流点亮。

2．某控制系统有2个开关K1和K2，1个数码管，当K1按下时数码管加1，K2按下时数码管减1。

试画出8051与外设的连接图并编程实现上述要求1．某单片机控制系统有8个发光二极管。

试画出89C51与外设的连接图并编程使它们由右向左轮流点亮。

答：图 (5分) 构思 (3分)MOV A，#80H (1分)UP：MOV P1，A (1分)RR A (2分)SJMP UP (1分2．某控制系统有2个开关K1和K2，1个数码管，当K1按下时数码管加1，K2按下时数码管减1。

51单片机的中断系统

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4）多个同级的中断源同时产生中断请求时，系统按照默认的顺序先后予以响应，5个中断默认优先级见表4-1。
表4-1 中断入口地址及优先级排列表
中断源
入口地址
中断级别
外部中断0
0003H
最高
T0溢出中断
000BH
外部中断1
0013H
T1溢出中断串行口中断
001BH 0023H
最低
应；
EA ＝ 1时，CPU开放中断，但每个中断源的中断请
求是允许还是被禁止，还需由各自的控制位确定。
ES，串行口的中断控制位。ES＝1，允许串行口中
断；ES＝0，禁止串行口中断。
ET1：定时器/计数器1的溢出中断控制位。ET1＝1，
T1的中断开放，ET1＝0，T1的中断被关闭。
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嵌入式单片机方向—单片机C语言程序项目设计
单片机的中断系统
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4.1 任务说明
本节为理论内容，重点掌握单片机的中断类型、控制方式以及应用，单片机共有5个中断源，两级优先级控制，在以后的项目实践中，我们要用到定时器中断、外部中断和串行中断。
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4.2 中断系统的结构
IE0，外部中断0的中断请求标志位。如果IT0置1，则当P3.2上的电平由1变为0时，由硬件置位IE0，向CPU申
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请中断。如果CPU响应该中断，在转向中断服务时，由硬件将IE0复位。可见，IT0用于设定INT0中断请求的信号形式。设定了IT0后，如果INT0产生了有效的中断请求信号（P3.2出现脉冲后沿或低电平），则由中断系统的硬件电路自动将IE0置位。单片机系统在工作过程的每一个机器周期的特定时刻（即S5P2），通过检测INT0的中断请求标志位IE0是1还是0来确定INT0是否有中断请求，而不是通过检测P3.2上的中断请求信号来确定INT0的中断请求。

如何设置51单片机的中断优先级

如何设置 51 单片机的中断优先级
在 MCS－51 单片机中断优先级中由中断优先级寄存器 IP 来高置的，IP 中某位设为 1，相应的中断就是高优先级，否则就是低优先级。 PS PT1 PX1 PT0 PX0 IP 优先级别寄存器各位介绍如下：
PS PT1 PX1 PT0 PX0
0 0 0 0 0 1 1 0
因此，最终，IP 的值就是 06H。例：在上例中，如果 5 个中断请求同时发生，求中断响应的次序。响应次序为：定时器 0－＞外中断 1－＞外中断 0－＞实时器 1－＞串行中断。
Байду номын сангаас
PS：串行口中断优先级控制位。PS=1 设定串行口为高优先级中断；PS=0 为低优先级中断。 PT1：T1 中断优先级控制位。PT1=1 设定定时器 T1 为高优先级中断； PT1=0 为低优先级中断。 PX1：外部中断 1 优先级控制位。PX1=1 设定定时器外部中断 1 为高优先级中断；PX1=0 为低优先级中断。 PT0：T0 中断优先级控制位。PT0=1 设定定时器 T0 为高优先级中断； PT0=0 为低优先级中断。 PX0：外部中断 0 优先级控制位。PX0=1 设定定时器外部中断 0 为高优先级中断；PX0=0 为低优先级中断。例：设有如下要求，将 T0、外中断 1 设为高优先级，其它为低优先级，求 IP 的值。 IP 的首 3 位没用，可任意取值，设为 000，后面根据要求写就可以了