苏州大学VLSICHAP5

Modern VLSI Design 3e: Chapter 5 Sequential Machines
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Master-slave flip-flop
Φ’ Φ
Q
Φ φ Φ’ Φ’
Φ’
Modern VLSI Design 3e: Chapter 5 Sequential Machines
φ
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Master-slave flip-flop

clock data
Modern VLSI Design 3e: Chapter 5 Sequential Machines
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Dynamic latch
Stores charge on inverter gate capacitance:
Modern VLSI Design 3e: Chapter 5 Sequential Machines

Modern VLSI Design 3e: Chapter 5 Sequential Machines
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Flip-flops
Not transparent—use multiple storage elements to isolate output from input. Major varieties:

Modern VLSI Design 3e: Chapter 5 Sequential Machines 3
Memory element terminology
Latch: transparent when internal memory is being set from input. Flip-flop: not transparent—reading input and changing output are separate events.
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Latch characteristics
Uses complementary transmission gate to ensure that storage node is always strongly driven. Latch is transparent when transmission gate is closed. Storage capacitance comes primarily from inverter gate capacitance.
Master-slave operation
= 1: master latch is enabled, loading value from input; slave latch is disabled, maintaining old output value. = 0: master latch is disabled; slave latch is enabled, but master latch output is stable, so output does not change.

– capacitance (dynamic); – feedback (static).
Modern VLSI Design 3e: Chapter 5 Sequential Machines
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Variations in memory elements
Form of required clock signal. How behavior of data input around clock affects the stored value. When the stored value is presented to the output. Whether there is ever a combinational path from input to output.
φ
D master
Φ’
slave Q
Φ’
Φ’
φ
φ
φ
Modern VLSI Design 3e: Chapter 5 Sequential Machines
Φ’
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Master-slave DFF timing diagrams
Modern VLSI Design 3e: Chapter 5 Sequential Machines

Modern VLSI Design 3e: Chapter 5 Sequential Machines 10
Stick diagram
VDD
D
Q’
VSS ’
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Modern VLSI Design 3e: Chapter 5 Sequential Machines
Layout
VDD
D
Q’

Modern VLSI Design 3e: Chapter 5 Sequential Mterminology
Clock edge: rising or falling transition. Duty cycle: fraction of clock period for which clock is active (e.g., for active-low clock, fraction of time clock is 0).
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Problems of latch-base systems
Hard to debug—can’t stop the system. Hard to initialize system state. More sensitive to process variations.
Topics






Memory elements. Basics of sequential machines. Clocking disciplines Sequential machine implementation: clocking Sequential machine design. State assignment. Power optimization of sequential machines. Design validation. Sequential testing.

Modern VLSI Design 3e: Chapter 5 Sequential Machines 9
Stored charge leakage
Stored charge leaks away due to reversebias leakage current. Stored value is good for about 1 ms. Value must be rewritten to be valid. If not loaded every cycle, must ensure that latch is loaded often enough to keep data valid.

– master-slave; – edge-triggered.
Modern VLSI Design 3e: Chapter 5 Sequential Machines
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Master-slave flip-flop
master D
slave Q

Modern VLSI Design 3e: Chapter 5 Sequential Machines 22

Modern VLSI Design 3e: Chapter 5 Sequential Machines
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Clocked inverter latch
Modern VLSI Design 3e: Chapter 5 Sequential Machines
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Regenerative latch

Modern VLSI Design 3e: Chapter 5 Sequential Machines
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Memory element parameters
Setup time: time before clock during which data input must be stable. Hold time: time after clock event for which data input must remain stable.

Modern VLSI Design 3e: Chapter 5 Sequential Machines 8
Latch operation
= 0: transmission gate is off, inverter output is determined by storage node. = 1: transmission gate is on, inverter output follows D input. Setup and hold times determined by transmission gate—must ensure that value stored on transmission gate is solid.
VSS
Modern VLSI Design 3e: Chapter 5 Sequential Machines

’
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Multiplexer dynamic latch
Modern VLSI Design 3e: Chapter 5 Sequential Machines
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Non-dynamic latches
1
Modern VLSI Design 3e: Chapter 5 Sequential Machines
Memory elements
Stores a value as controlled by clock. May have load signal, etc. In CMOS, memory is created by: