veriloghdl程序大全

1.简单门电路的设计
二输入与非门
module nand_2(y,a,b);
output y;
input a,b;
nand(y,a,b);
endmodule
二输入异或门
module nand_2(y,a,b);
output y;
input a,b;
reg y;
always @(a,b)
begin
case({a,b})
2’b00:y=1;
2’b01:y=1;
2’b10:y=1;
2’b11:y=0;
default:y=’bx;
endcase
end
endmodule
二输入三态门
module eda_santai(dout,din,en); output dout;
input din,en;
reg dout;
always
if (en) dout<=din;
else dout<=’bz;
endmodule
3-8译码器的设计
module yimaqi(S1,S2,S3,A,Y); input S1;
wire S1;
input S2;
wire S2;
input S3;
wire S3;
input [2:0]A;
wire [2:0]A;
output[7:0]Y;
reg [7:0]Y;
reg s;
always@(S,S1,S2,S3)
begin
s<=S2|S3;
Y <=8'b1111_1111;
else if(S)
Y <=8'b1111_1111;
else
case(A)
3'b000:Y<=11111110;
3'b001:Y<=11111101;
3'b010:Y<=11111011;
3'b011:Y<=11110111;
3'b100:Y<=11101111;
3'b101:Y<=11011111;
3'b110:Y<=10111111;
3'b111:Y<=01111111;
endcase
end
endmodule
2.8-3编码器的设计
module banjiaqi(a,b,count,sum);
input a;
wire a;
input b;
wire b;
output count;
wire count;
output sum;
wire sum;
assign {count,sum}=a+b;
endmodule
4. D触发器的设计
module Dchufaqi ( Q ,CLK ,RESET ,SET ,D ,Qn ); input CLK ;
wire CLK ;
input RESET ;
wire RESET ;
input SET ;
wire SET ;
input D ;
wire D ;
output Q ;
reg Q ;
output Qn ;
wire Qn ;
assign Qn = ~Q ;
always @ ( posedge CLK or negedge SET or negedge RESET ) begin
if ( !RESET)
Q <= 0 ;
else if ( ! SET)
Q <= 1;
else Q <= D;
end
endmodule
5. 1位半加法器的设计
module banjiafaqi(a,b,sum,count);
input a;
wire a;
input b;
wire b;
output sum;
wire sum;
output count;
wire count;
assign {count,sum}=a+b;
endmodule
6. 4位计数器的设计
module sihisjishuqi(CLK,RESET,out);
input CLK;
wire CLK;
input RESET;
wire RESET;
output[3:0] out;
reg[3:0] out;
always @ ( posedge CLK or negedge RESET )
begin
if(!RESET)
out<=4'b0000;
else
begin
out<=out+1;
if(out==4'b1010)
out<=4'b0000;
end
end
endmodule
7.分频时序逻辑电路的设计module eda_fp_even(clk_out,clk_in,rst); input clk_in;
input rst;
wire rst;
output clk_out;
reg clk_out;
reg [1:0]cnt;
parameter N=6;
always @(posedge clk_in or negedge rst) begin
if(!rst)
begin
clk_out<=0;
cnt<=0;
end
else
begin
cnt<=cnt+1;
if(cnt==N/2-1)
begin
clk_out=!clk_out;
cnt<=0;
end
end
end
endmodule
8.7段显示译码器的设计
module eda_scan_seven(clk,dig,y,rst); input clk;
wire clk;
input rst;
wire rst;
output[7:0] dig;
wire[7:0] dig;
output [7:0]y;
wire [7:0]y;
reg clkout;
reg [19:0]cnt;
reg [2:0]wei;
reg [3:0]duan;
reg [6:0]Y_r;
reg [7:0]dig_r;
assign y = {1'b1,(~Y_r[6:0])};
assign dig =~dig_r;
parameter period= 1000000;
always@(posedge clk or negedge rst) begin
if(!rst)
cnt<=0;
else begin
cnt<=cnt+1;
if(cnt==(period>>1)-1)
clkout<=#1 1'b1;
else if(cnt==period-1)
begin
clkout<=#1 1'b0;
cnt<=#1 1'b0;
end
end
end
always@(posedge clkout or negedge rst ) begin
if(!rst)
wei<=0;
else
wei<=wei+1;
end
always @(wei) //数码管选择
begin
case ( wei )
3'b000 :
begin
dig_r <= 8'b0000_0001;
duan <= 1;
end
3'b001 :
begin
dig_r <= 8'b0000_0010;
duan<= 3;
end
3'b010 :
begin
dig_r <= 8'b0000_0100;
duan<= 5;
end
3'b011 :
begin
dig_r <= 8'b0000_1000;
duan <= 7;
end
3'b100 :
begin
dig_r <= 8'b0001_0000;
duan<= 9;
end
3'b101 :
begin
dig_r <= 8'b0010_0000;
duan<= 11;
end
3'b110 :
begin
dig_r <= 8'b0100_0000;
duan <= 13;
end
3'b111 :
begin
dig_r <= 8'b1000_0000;
duan<= 15;
end
endcase
end
always @ ( duan ) //译码begin
case ( duan )
0: Y_r = 7'b0111111; // 0
1: Y_r = 7'b0000110; // 1
2: Y_r = 7'b1011011; // 2
3: Y_r = 7'b1001111; // 3
4: Y_r = 7'b1100110; // 4
5: Y_r = 7'b1101101; // 5
6: Y_r = 7'b1111101; // 6
7: Y_r = 7'b0100111; // 7
8: Y_r = 7'b1111111; // 8
9: Y_r = 7'b1100111; // 9
10: Y_r = 7'b1110111; // A
11: Y_r = 7'b1111100; // b
12: Y_r = 7'b0111001; // c
13: Y_r = 7'b1011110; // d
14: Y_r = 7'b1111001; // E
15: Y_r = 7'b1110001; // F
default: Y_r = 7'b0000000;
endcase
end
endmodule
9.数据选择器的设计
module eda_8xuanyi (A,D0,D1,D2,D3,D4,D5,D6,D7,G,Y); input D0,D1,D2,D3,D4,D5,D6,D7,G;
input [2:0]A;
wire [2:0]A;
output Y;
reg Y;
always @(A, G)
begin
if (G==0)
Y<=0;
else
case(A)
3'b000:Y=D0;
3'b001:Y=D1;
3'b010:Y=D2;
3'b011:Y=D3;
3'b100:Y=D4;
3'b101:Y=D5;
3'b110:Y=D6;
3'b111:Y=D7;
endcase
end
endmodule
10.数据锁存器的设计
module e da_suocunqi(q,d,oen,g); output[7:0] q;//数据输出端
input[7:0] d;//数据输入端
input oen,g;//三态控制端
reg[7:0] q;
always @(*)
begin
if (oen)
begin
q<="z";
end
else
begin
if(g)
q<=d;
else
q<=q;
end
end
endmodule
11.数据寄存器的设计
module eda_jicunqi(r,clk,d,y); input r,clk;
input [7:0]d;
wire [7:0]d;
output [7:0]y;
reg [7:0]y;
always @ (posedge clk or negedge r) begin
if(!r)
y<=8'b00000000;
else
y<=d;
end
endmodule
12.顺序脉冲发生器的设计
module eda_shunxu(clk,clr,q);
input clk,clr;
output [7:0]q;
reg [7:0]q;
always @ ( posedge clk or posedge clr ) begin
if ( clr==1)
begin
q<=8'b00000000; //赋初值
end
else
begin
if(q==0)
q<=8'b00000001;
else
q<=q<<1; //给初值进行移位
end
end
endmodule
13.1位全加法器的设计
module quanjiaqi(a,b,sum,count,cin); input a;
wire a;
input b;
wire b;
input cin;
wire cin;
output sum;
wire sum;
output count;
wire count;
assign{sum,count}=a+b+cin; endmodule
15.键控Led灯的设计
module eda_led(led,key);
input key;
output led;
reg led_out;
assign led<=led_out;
always@(key)
begin
if(key)
led_out<=1;
else if(!key)
led_out<=0;
end
endmodule
16．双向移位寄存器的设计
module eda_yiweijicunqi( left_right ,load ,clr ,clk ,DIN ,DOUT );
input left_right ;
wire left_right ;
input load ;
wire load ;
input clr ;
wire clr ;
input clk ;
wire clk ;
input [3:0] DIN ;
wire [3:0] DIN ;
output [3:0] DOUT ;
wire [3:0] DOUT ;
reg [3:0] data_r;
assign DOUT = data_r ;
always @ (posedge clk or posedge clr or posedge load)//敏感变量，看真值表begin
if(clr==1)
data_r <= 0;//判断是否清零
else if (load )
data_r<=DIN;
//判断是否装载数据
//判断进行左移位还是右移位
else
begin
if(left_right)
data_r<=DIN<<1;
else
data_r<=DIN>>1;
end
end
endmodule
17.8-3优先编码器的设计
module youxianbianma( A ,I ,GS ,EO ,EI ); input [7:0] I ;
wire [7:0] I ;
input EI ;
wire EI ;
output [2:0] A ;
reg [2:0] A ;
output GS ;
reg GS ;
output EO ;
reg EO ;
always @ ( I or EI )
if ( EI )
begin
A <= 3'b111;
GS <= 1;
EO <= 1;
end
else if (I==8'b11111111)
begin
A <= 3'b111;
GS <= 1;
EO <= 0;
end
else if ( I==8'b11111110 )
begin
A <= 3'b111;
GS <= 0;
EO <= 1;
end
else if ( I==8'b1111110x )
begin
A <= 3'b110;
GS <= 0;
EO <= 1;
end
else if ( I==8'b111110xx )
begin
A <= 3'b101;
GS <= 0;
EO <= 1;
end
else if ( I==8'b11110xxx )
begin
A <= 3'b100;
GS <= 0;
EO <= 1;
end
else if ( I==8'b1110xxxx )
begin
A <= 3'b011;
GS <= 0;
EO <= 1;
end
else if ( I==8'b110xxxxx )
begin
A <= 3'b010;
GS <= 0;
EO <= 1;
end
else if ( I==8'b10xxxxxx )
begin
A <= 3'b001;
GS <= 0;
EO <= 1;
end
else if ( I==8'b0xxxxxxx )
begin
A <= 3'b000;
GS <= 0;
EO <= 1;
end
endmodule
18.数据分配器的设计
module shujufenpeiqi(y0,y1,y2,y3,din,a); output y0,y1,y2,y3;//4??êy?Yí¨μà
input din;//êy?Yê?è?
input [1:0] a;
reg y0,y1,y2,y3;
always @(din,a)
begin
y0=0;y1=0;y2=0;y3=0; //3?ê??ˉ￡á?
case(a)
00:y0=din;
01:y1=din;
02:y2=din;
03:y3=din;
endcase end endmodule。