FPGA可编程逻辑器件芯片EP1C20F324C8N中文规格书

MXVR Registers
ADSP-BF54x Blackfin Processor Hardware Reference
the MXVR PLLs enabled and at frequency. Also note that all synchronous data DMA channels should be disabled (by setting MDMAENx = 0) and soft-ware should wait until all synchronous data DMA channels are inactive (DMAACTIVEx == 0 and DMAPMENx == 0) before disabling the MXVR.The MXVR Master Mode/Slave Mode Select (MMSM ) bit determines whether the MXVR is the network timing master or is a network slave node. If the MMSM bit is set to 1, the MXVR will be in Master Mode. When in Master Mode, the transmit clock is supplied by the MXVR FMPLL. The transmit clock is then used to generate the data stream transmitted on the MTX pin. In addition, MXVR CDRPLL recovers the receive clock from the incoming data stream received on the MRX pin. The receive clock is then used by the MXVR to sample the incoming data stream.
If the MMSM bit is set to 0, the MXVR will be in Slave Mode. When in Slave Mode, MXVR CDRPLL recovers the receive clock from the incoming data stream received on the MRX pin. The receive clock is then used by the MXVR to sample the incoming data stream. In addition, the receive clock is used to generate the data stream transmitted on the MTX pin.The Active Mode (ACTIVE ) bit determines whether the MXVR will operate in Active Mode or in All Bypass - MXVR Enabled Mode once the MXVR is enabled. When in Active Mode the MXVR can transmit and receive data. When in All Bypass - MXVR Enabled Mode, the MRX input pin is directly connected to MTX and the MXVR can only receive data. When the MXVREN bit is set to 1 and the ACTIVE bit is set to 1, the MXVR will operate in Active Mode. When the MXVREN bit is set to 1 and the ACTIVE bit is set to 0, the MXVR will operate in All Bypass - MXVR Enabled Mode. When the MXVREN bit is set to 0, the ACTIVE bit has no meaning.
The Synchronous Data Delay (SDELAY ) bit determines whether the syn-chronous data field will be delayed by two frames (SDELAY =1) or zero frames (SDELAY =0) passing through the MXVR. In the zero frame delay case the synchronous data will only be delayed by a few bit periods passing through the MXVR. If the MXVR is in All Bypass - MXVR Disabled Mode (MXVREN = 0) or in All Bypass - MXVR Enabled Mode (MXVREN = 1
MXVR Registers
ADSP-BF54x Blackfin Processor Hardware Reference
The Synchronous Boundary (MSB ) field is writable if the MXVR is in Mas-ter Mode (MMSM = 1) and is read-only if the MXVR is in Slave Mode (MMSM = 0). Writes to the MSB while in Slave Mode will be ignored and the MSB value will not be effected. Note that a particular procedure must be fol-lowed to dynamically change the synchronous boundary for the network to ensure that no data is corrupted and the asynchronous packet channel does not hang.
The Asynchronous Packet Receive Enable (APRXEN ) bit determines whether the MXVR is enabled to receive Asynchronous Packets. If the MXVR receives an Asynchronous Packet and the APRXEN bit is set to 1, the MXVR will write the received data into the Asynchronous Packet Receive Buffer. If the MXVR receives an Asynchronous Packet when the APRXEN bit is set to 0, the MXVR will not write the packet to the Asynchronous Packet Receive Buffer. The APRXEN bit is reset to 0.
The Wake-Up (WAKEUP ) bit is used to trigger the MXVR when in Master Mode to send the wake-up preamble which will indicate to any node in low-power mode to wake-up. If the MMSM bit is set to 1, writing a 1 to the WAKEUP bit will trigger the MXVR to send the wake-up preamble on the network. If MMSM is set to 0, writing a 1 to the WAKEUP bit will have no effect. Writing a 0 to the WAKEUP bit will have no effect. The WAKEUP bit will always read as 0.
The Lock Mechanism Select (LMECH ) bit determines in what order the MXVR Master will send network preambles while locking the network. Lock Mechanism 0 provides the fastest lock time from the completely unlocked state to the super block locked state in a network with only MXVR nodes. Lock Mechanism 1 takes longer than Lock Mechanism 0 to go from the completely unlocked state to the super block locked state; however, if a node in the ring causes an unlock (for example, a node going from All Bypass to Active or vice-versa), only nodes downstream from that node will go unlocked while upstream nodes will remain at their same lock level. Lock Mechanism 1 is generally a better choice for mixed networks which include transceivers other than the MXVR. If the LMECH bit is set to。