22-16-2030;中文规格书,Datasheet资料

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PSD4235G2-70U;PSD4235G2-90U;PSD4235G2-90UI;中文规格书,Datasheet资料

February 2009 Rev 41/129PSD4235G2Flash in-system programmable (ISP)for 16-bit MCUs (5 V supply)Features■Dual bank Flash memories– 4 Mbit of Primary Flash memory (8 uniform sectors, 32K x 16)–256 Kbit Secondary Flash memory with 4 sectors–Concurrent operation: read from onememory while erasing and writing the other ■64 Kbit SRAM■PLD with macrocells–Over 3000 gates of PLD: CPLD and DPLD –CPLD with 16 output macrocells (OMCs) and 24 input macrocells (IMCs)–DPLD - user defined internal chip select decoding ■7 L/O ports with 52 I/O pins–52 individually configurable I/O port pins that can be used for the following functions:–MCU I/Os –PLD I/Os–Latched MCU address output –Special function l/Os–l/O ports may be configured as open-drain outputs ■In-system programming (ISP) with JTAG –Built-in JTAG compliant serial port allows full-chip In-System Programmability–Efficient manufacturing allow easy product testing and programmingUse low cost FlashLINK cable with PC■Page register–Internal page register that can be used to expand the microcontroller address space by a factor of 256–Programmable power management ●High endurance–100,000 Erase/write c ycles of Flash memory–1,000 Erase/WRITE Cycles of PLD –15 Y ear Data Retention ■Single supply voltage –5V ±10%■Memory speed–70ns Flash memory and SRAM access time ■Packages are ECOPACK ®Contents PSD4235G2Contents1Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121.1In-system programming (ISP) via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . 121.1.1First time programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121.1.2Inventory build-up of pre-programmed devices . . . . . . . . . . . . . . . . . . . 121.1.3Expensive sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121.2In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121.2.1Simultaneous READ and WRITE to Flash memory . . . . . . . . . . . . . . . . 131.2.2Complex memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131.2.3Separate Program and Data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131.3PSDsoft™ Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163PSD architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213.1Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213.2PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213.3I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213.4MCU bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.5ISP via JTAG port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.6In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.7In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.8Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.9Power management unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4Development system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5PSD register description and address offsets . . . . . . . . . . . . . . . . . . . 266Register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286.1Data-In registers - port A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . . 286.2Data-out registers - port A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . 286.3Direction registers - ports A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . 286.4Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2/129PSD4235G2Contents6.5Drive registers - Ports A, B, D, E, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296.6Drive registers - Ports C and F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296.7Enable-Out registers - Ports A, B, C, F . . . . . . . . . . . . . . . . . . . . . . . . . . 296.8Input macrocells registers- ports A, B, C . . . . . . . . . . . . . . . . . . . . . . . . . 296.9Output macrocells A/B registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306.10Mask macrocells A/B registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306.11Flash Memory Protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306.12Flash Boot Protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316.13JTAG Enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316.14Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316.15PMMR0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316.16PMMR2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326.17VM register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336.18Memory_ID0 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346.19Memory_ID1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347Detailed operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357.1Memory blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357.2Primary Flash memory and Secondary Flash memory description . . . . . 367.2.1Memory block Select signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367.2.2Ready/Busy (PE4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367.3Memory operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398.1Power-up condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398.2Reading Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408.3Read memory contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408.4Read Primary Flash identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408.5Read Memory Sector Protection status . . . . . . . . . . . . . . . . . . . . . . . . . . 408.6Reading the Erase/Program status bits . . . . . . . . . . . . . . . . . . . . . . . . . . 408.7Data Polling (DQ7) - DQ15 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . 418.8Toggle flag (DQ6) - DQ14 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . 418.9Error flag (DQ5) - DQ13 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428.10Erase timeout flag (DQ3) - DQ11 for Motorola . . . . . . . . . . . . . . . . . . . . . 423/129Contents PSD4235G29Programming Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439.1Data polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439.2Data toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449.3Unlock Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4510Erasing Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4710.1Flash Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4710.2Suspend Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4810.3Resume Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4811Specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4911.1Flash Memory Sector Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4911.2Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4911.3Reset (RESET) pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5013Memory Select signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5113.1Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5113.2Memory Select configuration for MCUs with separateProgram and Data spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5113.3Separate space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5213.4Combined space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5213.580C51XA memory map example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 14Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 15Memory ID registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 16PLDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 17Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5918Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6118.1Output macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6218.2Product Term Allocator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4/129PSD4235G2Contents18.3Loading and Reading the output macrocells (OMC) . . . . . . . . . . . . . . . . 6418.4The OMC Mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6418.5The output Enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6418.6Input macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6518.7External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6719MCU bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6919.1PSD interface to a multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7019.2PSD interface to a non-multiplexed 8-bit bus . . . . . . . . . . . . . . . . . . . . . . 7119.3Data Byte Enable reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7119.4MCU bus interface examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7219.580C196 and 80C186 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7319.6MC683xx and MC68HC16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7419.780C51XA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7519.8H8/300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7619.9MMC2001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7719.10C16x family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7720I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8020.1General port architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8020.2Port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8120.3MCU I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8220.4PLD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8220.5Address Out mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8220.6Address In mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8420.7Data Port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8420.8Peripheral I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8420.9JTAG in-system programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8520.10MCU Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8520.11Port Configuration registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8620.12Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8620.13Direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8620.14Port Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8820.15Data In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885/129Contents PSD4235G26/12920.16Data Out register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 20.17Output macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 20.18Mask macrocell register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 20.19Input macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 20.20Enable Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 20.21Ports A, B and C - functionality and structure . . . . . . . . . . . . . . . . . . . . . 89 20.22Port D - functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 20.23Port E - functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 20.24Port F - functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 20.25Port G - functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9221Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9421.1Automatic Power-down (APD) Unit and Power-down mode . . . . . . . . . . . 9521.2Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9521.3Other power saving options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9621.4PLD power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9621.5PSD Chip Select input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9721.6Input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9721.7Input control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9822Power-on Reset, Warm Reset and Power-down . . . . . . . . . . . . . . . . . . 9922.1Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9922.2Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9922.3I/O pin, register and PLD status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . 9922.4Reset of Flash Memory Erase and Program cycles . . . . . . . . . . . . . . . . . 9923Programming in-circuit using the JTAG serial interface . . . . . . . . . . 10123.1Standard JTAG signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10123.2JTAG extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10223.3Security and Flash memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . 102 24Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 25Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105PSD4235G2Contents 26DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 27Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 28Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Appendix A Pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 29Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1287/129List of tables PSD4235G2 List of tablesTable 1.Pin names. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 2.Pin description (for the LQFP package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 3.PLD I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 4.JTAG signals on port E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 5.Methods of programming different functional blocks of the PSD . . . . . . . . . . . . . . . . . . . . 23 Table 6.Register address offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 7.Data-In registers - Ports A, B, C, D, E, F, G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 8.Data-Out registers - Ports A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 9.Direction registers - Ports A, B, C, D, E, F, G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 10.Control registers - Ports E, F, G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 11.Drive registers - Ports A, B, D, E, G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 12.Drive registers - Ports C, F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 13.Enable-Out registers - Ports A, B, C, F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 14.Input macrocell registers - Port A, B, C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 15.Output macrocells A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 16.Output macrocells B register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 17.Mask macrocells A register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 18.Mask macrocells B register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 19.Flash Memory Protection register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 20.Flash Boot Protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 21.JTAG Enable register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 22.Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 23.PMMR0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 24.PMMR2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 25.VM register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 26.Memory_ID0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 27.Memory_ID1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 28.Memory block size and organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 29.Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 30.Status bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 31.Status bits for Motorola. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 32.DPLD and CPLD inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 33.Output macrocell Port and Data bit Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 34.MCUs and their control signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 35.16-bit data bus with BHE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 36.16-bit data bus with WRH and WRL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 37.16-bit data bus with SIZ0, A0 (Motorola MCU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 38.16-bit data bus with LDS, UDS (Motorola MCU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 39.Port operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 40.Port operating mode settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 41.I/O port latched address output assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 42.Port Configuration registers (PCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 43.Port Pin Direction Control, output Enable P.T. not defined. . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 44.Port Pin Direction Control, output Enable P.T. defined. . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 45.Port direction assignment example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 46.Drive register pin assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 47.Port Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 48.Effect of Power-down mode on ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8/129PSD4235G2List of tables Table 49.PSD timing and standby current during Power-down mode. . . . . . . . . . . . . . . . . . . . . . . . 96 Table 50.APD counter operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 51.Status During Power-On Reset, Warm Reset and Power-down mode. . . . . . . . . . . . . . . . 99 Table 52.JTAG port signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 53.Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 54.Example of PSD typical power calculation at V CC = 5.0V (with Turbo mode on). . . . . . . 107 Table 55.Example of PSD typical power calculation at V CC = 5.0V (with Turbo mode off). . . . . . . 108 Table 56.Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 57.AC signal letters for PLD timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 58.AC signal behavior symbols for PLD timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 59.AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 60.Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 61.DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 62.CPLD Combinatorial timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Table 63.CPLD macrocell Synchronous clock mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Table 64.CPLD macrocell Asynchronous clock mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 65.Input macrocell timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 66.Program, WRITE and Erase times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 67.READ timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 68.WRITE timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 69.Port F Peripheral Data Mode Read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 70.Port F Peripheral Data Mode Write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 71.Reset (RESET) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 72.Power-down timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Table 73.ISC timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Table 74.LQFP80 - 80-lead plastic thin, quad, flat package mechanical data. . . . . . . . . . . . . . . . . 124 Table 75.Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Table 76.PSD4235G2 LQFP80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table 77.Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1289/129。

TCST2103;中文规格书,Datasheet资料

Transmissive Optical Sensor with Phototransistor OutputTCST2103, TCST2202, TCST2300Vishay SemiconductorsDESCRIPTIONThe TCST2103, TCST2202, and TCST2300 are transmissive sensors that include an infrared emitter and phototransistor, located face-to-face on the optical axes in a leaded package which blocks visible light. These part numbers include options for aperture width.FEATURES•Package type: leaded •Detector type: phototransistor•Dimensions (L x W x H in mm): 24.5 x 6.3 x 10.8•Gap (in mm): 3.1•Typical output current under test: C = 4 mA (TCST2103)•Typical output current under test: I C = 2 mA (TCST2202)•Typical output current under test: I C = 0.5 mA (TCST2300)•Daylight blocking filter •Emitter wavelength: 950 nm •Lead (Pb)-free soldering released•Compliant to RoHS directive 2002/95/EC and in accordance to WEEE 2002/96/ECAPPLICATIONS•Optical switch •Photo interrupter •Counter •EncoderNote(1)Conditions like in table basic characteristics/couplerNote(1)MOQ: minimum order quantity19180_4PRODUCT SUMMARYPART NUMBER GAP WIDTH(mm)APERTURE WIDTH(mm)TYPICAL OUTPUT CURRENTUNDER TEST (1)(mA)DAYLIGHTBLOCKING FILTER INTEGRATEDTCST2103 3.114Yes TCST2202 3.10.52Yes TCST23003.10.250.5YesORDERING INFORMATIONORDERING CODE PACKAGINGVOLUME (1)REMARKS TCST2103Tube MOQ: 1020 pcs, 85 pcs/tube With mounting flange TCST2202Tube MOQ: 1020 pcs, 85 pcs/tube With mounting flange TCST2300TubeMOQ: 1020 pcs, 85 pcs/tubeWith mounting flangeABSOLUTE MAXIMUM RATINGS (1)PARAMETER TEST CONDITIONSYMBOLVALUEUNITCOUPLERTotal power dissipation T amb ≤ 25 °CP tot 250mW Ambient temperature range T amb - 55 to + 85°C Storage temperature range T stg - 55 to + 100°C Soldering temperatureDistance to package: 2 mm; t ≤ 5 sT sd260°CTCST2103, TCST2202, TCST2300Vishay SemiconductorsTransmissive Optical Sensor withPhototransistor OutputNote (1)T amb = 25 °C, unless otherwise specifiedABSOLUTE MAXIMUM RATINGSFig. 1 - Power Dissipation Limit vs. Ambient TemperatureINPUT (EMITTER)Reverse voltage V R 6V Forward current I F 60mA Forward surge current t p ≤ 10 µs I FSM 3A Power dissipation T amb ≤ 25 °CP V 100mW Junction temperature T j100°COUTPUT (DETECTOR)Collector emitter voltage V CEO 70V Emitter collector voltage V ECO 7V Collector peak current t p /T = 0.5, t p≤ 10 msI CM 200mA Power dissipation T amb ≤ 25 °CP V 150mW Junction temperatureT j100°CABSOLUTE MAXIMUM RATINGS (1)PARAMETER TEST CONDITIONSYMBOLVALUEUNITBASIC CHARACTERISTICS (1)PARAMETER TEST CONDITIONPARTSYMBOLMIN.TYP.MAX.UNITCOUPLERCurrent transfer ratioV CE = 5 V, I F = 20 mATCST2103CTR 1020%TCST2202CTR 510%TCST2300CTR 1.25 2.5%Collector currentV CE = 5 V, I F = 20 mA TCST2103I C 24mA TCST2202I C 12mA TCST2300I C 0.250.5mA Collector emitter saturationvoltageI F = 20 mA, I C = 1 mA TCST2103V CEsat 0.4V I F = 20 mA, I C = 0.5 mA TCST2202V CEsat 0.4V I F = 20 mA, I C = 0.1 mA TCST2300V CEsat 0.4V Resolution, path of the shutter crossing the radiant sensitive zoneI Crel = 10 % to 90 %TCST2103s 0.6mm TCST2202s 0.4mm TCST2300s0.2mmTCST2103, TCST2202, TCST2300T ransmissive Optical Sensor withPhototransistor OutputVishay SemiconductorsNote (1)T amb = 25 °C, unless otherwise specifiedFig. 2 - Test Circuit for t on and t offFig. 3 - Switching TimesBASIC CHARACTERISTICST amb = 25°C, unless otherwise specifiedFig. 4 - Forward Current vs. Forward Voltage Fig. 5 - Relative Current Transfer Ratio vs. Ambient TemperatureINPUT (EMITTER)Forward voltage I F = 60 mA V F 1.25 1.6V Junction capacitance V R = 0 V, f = 1 MHzC j50pFOUTPUT (DETECTOR)Collector emitter voltage I C = 1 mA V CEO 70V Emitter collector voltage I E = 10 µAV ECO 7V Collector dark currentV CE = 25 V, I F = 0 A, E = 0 lxI CEO100nASWITCHING CHARACTERISTICS Turn-on time I C = 2 mA, V S = 5 V,R L = 100 Ω (see figure 2)t on 10µs Turn-off timeI C = 2 mA, V S = 5 V,R L = 100 Ω (see figure 2)t off8µsBASIC CHARACTERISTICS (1)PARAMETER TEST CONDITIONPARTSYMBOLMIN.TYP.MAX.UNIT10 %90 %100 %I FI C t p P u lse d u ration t d Delay time t rRise time t on (= t d + t r ) T u rn-on timet s Storage time t fFall time t off (= t s + t f )T u rn-off time96 11698TCST2103, TCST2202, TCST2300Vishay Semiconductors Transmissive Optical Sensor withPhototransistor OutputFig. 6 - Collector Dark Current vs. Ambient Temperature Fig. 7 - Collector Current vs. Forward Current Fig. 8 - Collector Current vs. Collector Emitter VoltageFig. 9 - Current Transfer Ratio vs. Forward Current Fig. 10 - Turn-off/Turn-on Time vs. Collector Current Fig. 11 - Relative Collector Current vs. DisplacementTCST2103, TCST2202, TCST2300T ransmissive Optical Sensor withPhototransistor OutputVishay SemiconductorsFig. 12 - Relative Collector Current vs. Displacement Fig. 13 - Relative Collector Current vs. DisplacementPACKAGE DIMENSIONS in millimetersTCST2103, TCST2202, TCST2300Vishay Semiconductors Transmissive Optical Sensor withPhototransistor Output TUBE DIMENSIONS in millimetersPackaging and Ordering InformationPackaging and Ordering InformationVishay SemiconductorsNotes(1)MOQ: minimum order quantity (2)Please refer to datasheetsTUBE SPECIFICATION FIGURESFig. 1PART NUMBER MOQ (1)PCS PER TUBETUBE SPEC.(FIGURE)CONSTITUENTS(FORMS)CNY70400080128TCPT1300X012000Reel (2)29TCRT10001000Bulk -26TCRT10101000Bulk -26TCRT5000450050227TCRT5000L 240048327TCST1030520065524TCST1030L 260065624TCST1103102085424TCST1202102085424TCST1230480060724TCST1300102085424TCST2103102085424TCST2202102085424TCST2300102085424TCST5250486030824TCUT1300X012000Reel (2)29TCZT8020-PAER2500Bulk-22Packaging and Ordering InformationVishay Semiconductors Packaging and Ordering InformationFig. 2Fig. 3Packaging and Ordering Information Packaging and Ordering Information Vishay SemiconductorsFig. 4Fig. 5Packaging and Ordering InformationVishay Semiconductors Packaging and Ordering InformationFig. 6Fig. 7分销商库存信息: VISHAYTCST2103。

BSS64;中文规格书,Datasheet资料

50
100
1
10 100 I C - COLLECTOR CURRE NT (mA)
200
/
BSS64
NPN General Purpose Amplifier
(continued)
Typical Characteristics
1 0.8
β = 10
V BEON - BASE EMITTER ON VOLTAGE (V)
SMALL SIGNAL CHARACTERISTICS
fT Cob Current Gain - Bandwidth Product Output Capacitance IC = 4.0 mA, VCE = 10, f = 35 MHz VCB = 10 V, f = 1.0 MHz 60 5.0 MHz pF
Absolute Maximum Ratings*
Symbol
VCEO VCBO VEBO IC TJ, Tstg Collector-Emitter Voltage Collector-Base Voltage Emitter-Base Voltage Collector Current - Continuous
TA = 25°C unless otherwise noted
Parameter
Value
80 120 5.0 200 -55 to +150
Units
V V V mA °C
Operating and Storage Junction Temperature Range
*These ratings are limiting values above which the serviceability of any semiconductor device may be impaired.

ORD9216-2030;中文规格书,Datasheet资料

ORD9216 l
n MECHANICAL CHARACTERISTICS
(1) Lead tensile test (static load)
2.27kg-10sec
(2) Lead tensile strength
99.9
AT 60
Cumulative frequency percent (%)
99 95 90 80 70 60 50 40 30 20 10 5 1 0.1 0 2 4 6 8 10kg Breaking load
Pull-in Value • Drop-out Value
50
40
PI
30
20
DO
10
0 Contact resistance
80
CR
60
40
Before test After test
0.4 Operate time
0.3
0.2
0.1
0
10
20
30 Pull-in Value
40
50
0.1
AT
0
0.1
0.2
0.3
0.4
ms
Bounce time
(3) Release time
(4) Resonant frequency
99.9
Cumulative frequency percent (%)
n ENVIRONMENTAL CHARACTERISTICS
(1) Temperature characteristics
40 CR 30
Rate of change percent
20 DO 10 PI 0
10

QSD2030;中文规格书,Datasheet资料

QSD2030 — Plastic Silicon PhotodiodePlastic Silicon PhotodiodeFeatures■ PIN photodiode■ Package type: T-1 3/4 (5mm lens diameter) ■ Wide reception angle, 40°■ Package material and color: clear epoxy■ High sensitivity■ Peak sensitivity λ = 880nm■ Radiant sensitive area: 1.245mm x 1.245mmPackage Dimensions0.195 (4.95)0.040 (1.02)NOM0.100 (2.54) NOM0.050 (1.25)0.800 (20.3)MIN0.305 (7.75)0.240 (6.10)0.215 (5.45)0.020 (0.51)SQ. (2X)REFERENCE SURFACECATHODECATHODEANODENotes:SchematicQSD2030 — Plastic Silicon PhotodiodeNotes:1. Derate power dissipation linearly 1.33mW/°C above 25°C.2. RMA flux is recommended.3. Methanol or isopropyl alcohols are recommended as cleaning agents.4. Soldering iron 1/16” (1.6mm) minimum from housing.Electrical/Optical Characteristics (T A =25°C)T OPR Operating Temperature -40 to +100°C T STG Storage Temperature-40 to +100°C T SOL-I Soldering Temperature (Iron)(2,3,4) 240 for 5 sec °C T SOL-F Soldering Temperature (Flow)(2,3) 260 for 10 sec°C V BR Reverse Breakdown Voltage 50V P DPower Dissipation (1)100mWSymbolParameterTest Conditions Min.Typ.Max.UnitsλPS Peak Sensitivity Wavelength 880nm λSR Wavelength Sensitivity Range 4001100nm Θ Reception Angle ±20°V F Forward Voltage I F = 80mA 1.3VI D Reverse Dark Current V R = 10V , Ee = 010nA I L Reverse Light Current Ee = 0.5mW/cm 2 , V R = 5V , λ = 950nm1525µA V O Open Circuit VoltageEe = 0.5mW/cm 2 , λ = 880nm 420mV TC V Temperature Coefﬁcient of V O +0.6mV / K I SC Short Circuit CurrentEe = 0.5mW/cm 2 , λ = 880nm 50µA TC I Temperature Coefﬁcient of I SC +0.3% / K C Capacitance V R = 0, f = 1MHz, Ee = 060pF t r Rise Time V R = 5V , R L = 50 Ω , λ = 950nm5nst fFall Time5QSD2030 — Plastic Silicon PhotodiodeFigure 4. Dark Current vs. Reverse VoltageFigure 3. Capacitance vs. Reverse VoltageVR–Break Down Voltage (V)I D –D a r k C u r r e n t (n A )Vr–Reverse Voltage (V)C j –C a p a c i t a n c e (p F )51015202530350.30.40.50.60.70.80.91.01.11.21.3T A = 25°C246810121416182014121086420Ee–Emitter output power (mw/cm 2)0.00.10.20.30.40.50.60.70.80.940°50°60°70°80°90°1.00.90.80.7I L –R e v e r s e L i g h t C u r r e n t V o l t 0510152025303540subsidiaries,and is notAccuPower™Auto-SPM™Build it Now™CorePLUS™CorePOWER™CROSSVOLT™CTL™Current Transfer Logic™DEUXPEED®Dual Cool™EcoSPARK®EfficientMax™ESBC™®Fairchild®Fairchild Semiconductor®FACT Quiet Series™FACT®FAST®FastvCore™FETBench™FlashWriter®*FPS™F-PFS™FRFET®Global Power Resource SMGreen FPS™Green FPS™e-Series™G max™GTO™IntelliMAX™ISOPLANAR™MegaBuck™MICROCOUPLER™MicroFET™MicroPak™MicroPak2™MillerDrive™MotionMax™Motion-SPM™OptoHiT™OPTOLOGIC®OPTOPLANAR®®PDP SPM™Power-SPM™PowerTrench®PowerXS™Programmable Active Droop™QFET®QS™Quiet Series™RapidConfigure™™Saving our world,1mW/W/kW at a time™SignalWise™SmartMax™SMART START™SPM®STEALTH™SuperFET™SuperSOT™-3SuperSOT™-6SuperSOT™-8SupreMOS®SyncFET™Sync-Lock™®*The Power Franchise®TinyBoost™TinyBuck™TinyCalc™TinyLogic®TINYOPTO™TinyPower™TinyPWM™TinyWire™TriFault Detect™TRUECURRENT™*"SerDes™UHC®Ultra FRFET™UniFET™VCX™VisualMax™XS™*Trademarks of System General Corporation,used under license by Fairchild Semiconductor.DISCLAIMERFAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY,FUNCTION,OR DESIGN.FAIRCHILD DOES NOT ASSUME ANYLIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS,NOR THE RIGHTS OF OTHERS.THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWID E TERMS AND CONDITIONS,SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.LIFE SUPPORT POLICYFAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.As used herein:1.Life support devices or systems are devices or systems which,(a)are intended for surgical implant into the body or(b)support or sustain life,and(c)whose failure to perform when properly used in accordance with instructions for use provided in the labeling,can be reasonably expected to result in a significant injury of the user.2.A critical component in any component of a life support,device,orsystem whose failure to perform can be reasonably expected to cause the failure of the life support device or system,or to affect its safety or effectiveness.ANTI-COUNTERFEITING POLICYFairchild Semiconductor Corporation's Anti-Counterfeiting Policy.Fairchild's Anti-Counterfeiting Policy is also stated on ourexternal website,, under Sales Support.Counterfeiting of semiconductor parts is a growing problem in the industry.All manufacturers of semiconductor products are experiencing counterfeiting of their parts.Customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation,substa ndard performance,failed applications,and increased cost of production and manufacturing delays.Fairchild is taking strong measures to protect ourselv es and our customers from the proliferation of counterfeit parts.Fairchild strongly encourages customers to purchase Fairchild parts either directly from Fa irchild or from Authorized Fairchild Distributors who are listed by country on our web page cited above.Products customers buy either from Fairchild directly or from Authorized Fairchild Distributors are genuine parts,have full traceability,meet Fairchild's quality standards for handling and storage and provide access to Fa irchild's full range of up-to-date technical and product information.Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately addr ess any warranty issues that may arise. Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources.Fairchild is c ommitted to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors.PRODUCT STATUS DEFINITIONSDefinition of TermsDatasheet Identification Product Status Definitionn QSD2030 — Plastic Silicon Photodiode分销商库存信息: FAIRCHILDQSD2030。

IRMCK203;中文规格书,Datasheet资料

Data Sheet No. PD60225 Rev BIRMCK203High Performance Sensorless Motion Control ICFeaturesComplete Sensorless control IC for PermanentMagnet AC motorsNo phase voltage feedback sensing required Sinusoidal current waveform with SynchronouslyRotating Frame closed loop current control High starting torque and smooth speed ramping Direct interface to IR2175 current sensing highvoltage IC Auto Retry at startup with configurable startingtorque Versatile loss minimization Space Vector PWM Serial communication interface (RS232C, RS422,SPI) I 2C serial interface to 1k bit serial EEPROM forparameter storage for stand alone operation Phase loss/Overcurrent/Overvoltage protection 7-bit discrete I/O for sequencing and statusmonitorIntegrated brake IGBT control for dc bus voltage limitation ServoDesigner TM tool for easy operationParallel interface for microcontroller expansionProduct SummaryMax Clock input33.3 MHz Sensorless control computation time 10 µsec max Speed operating range (typical) 5% to 100% Speed control resolution15 bit full range Adjustable current limit at start-up 15 bit full range Programmable retry on start-upmax 16 trialsOver current, speed, phase loss, dc bus fault protection PWM carrier frequency16 bit/33MHzIR2175 Current feedback data resolution 10bit Inverter leg current sensing (optional) 12bitRS232C speedup to 57.6 Kbps Optional RS422 communication up to 1 MbpsMax SPI Clock 8 MHzPackage: QFP80DescriptionIRMCK203 is a high performance digital motion control IC for Sensorless AC permanent magnet motor application. Control is based on closed loop vector control for sinusoidal Back EMF motors. With IRMCK203, the users can readily build a high performance Sensorless drive system without any programming effort and minimum start-up time. Built-in unique start-up and ramping algorithm enables wide application. This IC is versatile enough that the users can configure and optimize system performance according to the needs of each application. With International Rectifier iMOTION products including high voltage ICs such as IR2175 current sensing IC and IRAM series of Intelligent IGBT module in combination with IRMCK203, the end result is a fully optimized system with reduced electronics component counts. This simplifies the design for low cost Sensorless drive modules. IRMCK203 can be easily adapted to various permanent magnet motors through ServoDesigner TM tool, which is the fully configurable graphic user interface tool.OverviewIRMCK203 is a new International Rectifier integrated circuit device designed for one-chip solution for complete closed loop current and velocity control of a high performance Sensorless drive for PM motors. Unlike a traditional microcontroller or DSP, IRMCK203 does not require any programming to complete complex Sensorless algorithm development. Combined with International Rectifier's high voltage gate drive and current sensing IC, the user can implement complete speed control of PM motors with minimum component count and virtually no design effort. In addition to Sensorless closed loop speed control operation, features such as Start-up retry, Phase Loss detection, Low Loss PWM, Regeneration Braking control and various drive protections are all implemented inside IRMCK203. Analog and digital I/Os can also be configured. Host communication logic contains Asynchronous Communication Interface for RS232C or RS422 communication interface, a fast slave SPI interface and an 8 bit wide Host Parallel Interface. All communication ports have the same access capability to the host register set. The users can write to, and read from the predefined registers to configure and monitor the drive through these communication ports.IRMCK203 Main functions• Complete closed loop current control based on Synchronously Rotating Frame Field Orientation (using Rotor Angle Observer)• Closed loop velocity control based on estimated speed• Configurable parameters (PI controller gains, PI output limit range, current feedbackscaling, PWM carrier frequency) provide adaptation to various PM motors• Built-in Sensorless control logic for start-up, ramping, and running conditions• Auto Retry (programmable) on start-up with configurable torque current limit• Analog reference input (can be used for speed reference)• RS232C/RS422 reference input• Full dynamic braking control for DC bus voltage limitation• Cycle-by-cycle on/off Control for Brake IGBT• Loss minimization Space Vector PWM with deadtime insertion• Build-in two IR2175 current sensing IC interfaces• Phase Loss, Overcurrent (GATEKILL input), Overvoltage, Undervoltage, Overspeed protection• Low cost serial 12bit A/D interface with multiplexer and sample/hold circuit• Optional Inverter Leg (low side) current sensing in lieu of IR2175 IC• 4 channel analog output (PWM)• Local EEPROM for startup initialization of internal data/parameters through host register interface AT24C01A, 128X8• Versatile host communication interfaceRS232C or RS422 host interfaceFast SPI slave host interface with multi-drop capabilityParallel Host interface (total 12 pins)• Multiplexed data/address busAddress EnableRD/WR• Discrete I/Os for Standalone mode operationSTARTSTOP (Input)ESTOP (Input)DIR (Input) FLTCLR (Input) FAULT (Output) SYNC (Output) REDLED (Output)GREENLED (Output)Table of Contents Overview (2)IRMCK203 Main functions (2)IRMCK203 Block Diagrams (7)Basic Block Diagram (7)Input/Output of IRMCK203 (8)Application Connections (12)IC Crystal Clock Circuitry (13)PLL Clock Circuitry (14)Low Pass Filter (14)Implementing the Low Pass Filter Shield (15)Cp Rp and Cs Component Values (15)PLL Reset (15)DC Electrical Characteristics and Operating Conditions (16)Absolute Maximum Ratings (16)Recommended Operating Conditions (16)DC Characteristics (17)Common Quiescent and Leakage Current (17)Input Characteristics – Non Schmitt Inputs (17)Input Characteristics – Schmitt Inputs (17)Output Characteristics (17)Output Characteristics OSC2CLK (18)Pin and I/O Characteristic Table (19)Power Consumption (21)AC Electrical Characteristics and Operating Conditions (22)System Level AC Characteristics (22)Sync Pulse to Sync Pulse Timing (22)FAULT and REDLED Response to GATEKILL (23)Host Interface AC Characteristics (24)SPI Timing (24)Host Parallel Timing (25)Host Parallel Read Cycle (25)Host Parallel Write Cycle (26)Discrete I/O Electrical Characteristics (27)Motion Peripheral Electrical Characteristics (28)PWM Electrical Characteristics (28)IR2175 Interface (28)Analog Interface Electrical Characteristics (29)ADC Timing (29)PLL Interface Electrical Characteristics (30)Appendix A Host Register Map (31)Register Access (31)Host Parallel Access (31)SPI Register Access (31)RS-232 Register Access (31)Write Register Definitions (36)PwmConfig Register Group (Write Registers) (36)CurrentFeedbackConfig Register Group (Write Registers) (37)SystemControl Register Group (Write Registers) (38)TorqueLoopConfig Register Group (Write Registers) (38)VelocityControl Register Group (Write Registers) (39)IRMCK203 FaultControl Register Group (Write Registers) (40)SystemConfig Register Group (Write Registers) (41)EepromControl Registers (Write Registers) (42)ClosedLoopAngleEstimator Registers (Write Registers) (43)OpenLoopAngleEstimator Registers (Write Registers) (44)StartupAngleEstimator Registers (Write Registers) (44)StartupRetrial Registers (Write Registers) (45)PhaseLossDetect Registers (Write Registers) (47)D/AConverter Registers (Write Registers) (47)Factory Test Register (Write Register) (48)Read Register Definitions (49)SystemStatus Register Group (Read Registers) (49)DcBusVoltage Register Group (Read Registers) (49)FocDiagnosticData Register Group (Read Registers) (50)FaultStatus Register Group (Read Registers) (51)VelocityStatus Register Group (Read Registers) (52)CurrentFeedbackOffset Register Group (Read Registers) (53)EepromStatus Registers (Read Registers) (53)FOCDiagnosticDataSupplement Register Group (Read Registers) (54)ProductIdentification Registers (Read Registers) (55)Factory Register (Read Register) (55)Appendix B Package (56)Table of FiguresFigure 1: IRMCS2031 Simplified Blocks (7)Figure 2: Input/Output of IRMCK203 (8)Figure 3: Application Connection of IRMCK203 (12)Figure 4: Oscillator Circuit (13)Figure 5: PLL Low Pass Filter Shielding (14)Figure 6: System Level SYNC To SYNC Timing (22)Figure 7: FAULT and REDLED Response to GATEKILL (23)Figure 8: SPI Timing (24)Figure 9: Host Parallel Read Cycle (25)Figure 10: Host Parallel Write Cycle (26)Figure 11: Discrete I/O Timing (27)Figure 12: PWM Timing (28)Figure 13: IR2175 Interface (28)Figure 14: Top Level ADC Timing (29)Table of TablesTable 1: Typical Values for the Clock Circuit (13)Table 2: PLL Test Pin Assignments (14)Table 3: PLL Low Pass Filter Values (15)Table 4: Absolute Maximum Ratings (16)Table 5: Recommended Operating Conditions (16)Table 6: DC Characteristics (17)Table 7: Non Schmitt Input Characteristics (17)Table 8: Schmitt Input Characteristics (17)Table 9: Output Characteristics (17)Table 10: Output Characteristics OSC2CLK (18)Table 11: Pin and I/O Characteristics (21)Table 12: IRMCK203 Power Consumption (21)Table 13: System Level SYNC to SYNC Timing (22)Table 14: FAULT and REDLED Response to GATEKILL (23)Table 15: SPI Timing (24)Table 16: Host Parallel Read Cycle Timing (25)Table 17: Host Parallel Write Cycle Timing (26)IRMCK203 Block DiagramsBasic Block DiagramFigure 1 shows the basic block diagram of the IRMCK203 surrounded by International Rectifiers’ ICs. Host communications are provided over SPI, RS-232C or Host parallel ports. Two current sensing ICs (IR2175) and a three phase high voltage gate drive typically implement the high voltage / current interface between the IRMCK203 IC and motor.The IRMCK203 can operate in a “stand-alone” mode without the host controller. A serial EEPROM would be utilized to load motor-specific parameters into the IC.AC PowerConfigurable parameters are provided to tailor design to various applications (motor and load). These configurable parameters can be modified via the host register interface through the communication interface. In the IRMCK203 product, a design spread sheet is provided to aid the user for ease of drive start-up, the spread sheet will input high level application data such as motor name plate information, max speed, current limit, speed and current regulator bandwidth, base on this information the program will generate the required configurable parameters. Detail on Drive commissioning is described in the IRMCK203 Application Developer’s Guide.All logic and algorithms are pre-programmed, and the user does not need to make any effort to develop code, alleviating the tedious design process. If needed, the user can configure the drive to tailor the control per specificneeds to meet the required specification. This configuration can be easily done by accessing the host register interface through the communication interface.Input/Output of IRMCK203The I/O signals are shown in Figure 2. The interface signals are divided into sub-groups. For detailed pin assignment, please refer to appendix (Pin definition).PWMUH PWMUL PWMVL BRAKEGATEKILLIFB[0-1]ADCLK ADOUT ADCONVST ADMUX[0-2]RESSAMPLEPWM gate signalInterfaceIR2175 Interface A/D InterfaceSPI Interface Parallel InterfaceLED/StatusPLL Clock ControlCrystalDAC[0-3]D/A Interface (PWM output)RESETNSystem ResetFLTCLROUT Figure 2: Input/Output of IRMCK203Host Interface GroupSignal Input (I) /Output (O)Low (L) /High (H) TrueAsserted FunctionSPICLK IPositive edgesensitiveSPI clockSPIMISO O - Master input and slave output SPIMOSI I - Master output and slave input SPICSN I L SPI chip selectHP_nOE I LParallel data output enable HP_nWE I LParallel data write cycleidentificationHP_D [7:0] I/O - Parallel dataHP_A I HParallel data address cycleidentificationHP_nCS I L Chip select TX O - RS-232 data out RX I - RS-232 data inBAUDSEL[1:0] I H RS-232 baud rate: 00 = 19.3K bps;01 = 38.4K bps10 = 57.6K bps;11 = 1.031250M bpsSYNC O L Start of PWM cycleCLK1XOUT O -33.333 MHz output of PLL. This signal has no phase relationshipwith the OSC1CLK or OSC2CLK inputs.Discrete I/O GroupSignalInput (I) / Output (O)Low (L) / High (H) True AssertedFunctionSTARTSTOP I HStart / Stop command edgesensitiveDIR I HForward/Reverse Directioncommand, level sensitiveFAULTCLR I H Fault ClearESTOP I HEmergency Stop, statesensitivePWEN O H PWM enable/disable state SYNC O H SYNC pulse FAULT O H Fault stateMotion Peripheral GroupSignalInput (I) / Output (O)Low (L) / High (H) True AssertedFunctionPWMUH O PWM phase U high side PWMUL O PWM phase U low side PWMVH O PWM phase V high sidePWHVL O PWM phase V low side PWMWH O PWM phase W high side PWMWL O -PWM phase W low side BRAKE O L IGBT gateGATEKILL I Varies, Based onWrite Register0x0C Bit 7When asserted, negates all sixPWM signals, host writeableIFB0 I - Channel 0 (phase V) IFB1 I - Channel 1 (phase W)Analog Interface GroupSignal Input (I) /Output (O)Low (L) /High (H) TrueAsserted FunctionADCLK ONegative EdgeSensitiveClock to ADS7818ADOUT I - Serial data from ADS7818 DAC [3:0] O - Diagnostic DACADCONVST O LConversion start to ADS7818 RESSAMPLE OSample/hold control signalchannel 0 A/D converterADMUX0 O H Analog input MUX select ADMUX1 O H Analog input MUX selectPLL Interface GroupSignal Input (I) /Output (O)Low (L) /High (H) True AssertedFunctionXPD I L PLL reset RESETN I L Digital logic resetBYPASSCLK I HInternal test pin – force to logiclowBYPASSMODE I HInternal test pin – force to logiclowOSC1CLK I - 33.33 MHz crystal input OSC2CLK I - 33.33 MHz crystal inputPLLTEST I HInternal test pin – force to logiclowCHGO I/O - Low pass filter LPVSS I/O - Low pass filter ground分销商库存信息: IRIRMCK203。

20263;中文规格书,Datasheet资料

BDCCA 4.52.461.800 3.600R.0212 PLCS.2056PLCS2.122.00±.02.066 PLCSFULL RAD 6 PLCSR.134 PLCSAASEE NOTE 4.188.188.007SEE DETAILSECTION A-ANOTES:1. MATERIAL: MAKE FROM HENKEL AL-2-45H-212.2. THICKNESS: .007±.001.3. SEE DETAIL FOR ASSY ORDER.4. FOR ARTWORK SHOWN HERE SEE DWG# 20200.5. DENOTE CRITICAL CHARACTERISTIC FOR LOT INSPECTION.6. RoHS COMPLIANT PER CST-0001 LATEST REVISION.7. PRIOR TO ASSEMBLY, PRODUCTS SHALL BE STORED IN A COOL, DRY LOCATION IN ORIGINAL PACKAGING AT TEMPERATURES BELOW 40°C (104°F). UNDER THESE CONDITIONS THE SHELF LIFE IS INDEFINITE. THERMMATE PADS CAN BE PRE-APPLIED TO BASEPLATES OR HEAT SINKS WHICH ARE THEN SHIPPED TO A FINAL ASSEMBLY LOCATION, AS LONG AS THE TEMPERATURE DOES NOT EXCEED THE LEVEL INDICATED ABOVE.FEDETAIL :A. SPLIT RELEASE LINER.B. ADHESIVE STRIP; .0025 THICK .188 WIDE.C. ALUMINUM ALLOY 1145-0; .002 THICK.D. ROLL CARRIER WITH ADHESIVE STRIP BONDING.E. PHASE CHANGE THERMAL COMPOUND.F. ADHESIVE STRIPS ON ROLL CARRIER.(VERTICAL THICKNESS IS NOT SHOWN TO SCALE).188.007PEI AABBCCDDEEFF1122334455667788SWDTHERMAL INTERFACE PADTHERMATE (MAXI)P/N 202632/13/97J. RENAUDDATE DRAWN REV5DWG NO16188CAGE CODE67131SIZEBSHEET 1 OF 1SCALE 1: 1RELEASED PER E0430434VICORUNLESS OTHERWISE SPECIFIED DIMENSIONS ARE INCH [MM]TOLERANCES ARE:DECIMALS ANGLES X.XX [X.X] = ±0.01 [0.25] ±1°X.XXX [X.XX] = ±0.005 [0.127]FN 2REVISED PER E101310b KUK 09/16/04REVISED PER E090673C REVISED PER E091595a AR JS 3404/22/0909/10/09REJH REJH DO NOT SCALE DRAWINGTHIRD ANGLE PROJECTIONVICOR CONFIDENTIALTHIS DOCUMENT AND THE DATA DISCLOSED HEREIN OR HEREWITH IS NOT TO BE REPRODUCED, USED ORDISCLOSED IN WHOLE OR IN PART TO ANYONE WITHOUT THE PERMISSION OF VICOR CORP.DATE 1DESCRIPTIONFINISHREVISIONSREV MATERIALAPPROVED10/22/10AR 11/07/11KUKREVISED PER E1110905REJH/分销商库存信息: VICOR20263。

CSPEMI202AG;中文规格书,Datasheet资料

Publication Order Number: CSPEMI202AG/D
MIC_OUT2
MIC_OUT1
CSPEMI202AG
Table 1. PIN DESCRIPTIONS
5−bump CSP Package
Pin
Name
Description
A1 MIC_IN1 Microphone Input 1 (from microphone)
பைடு நூலகம்
Table 3. STANDARD OPERATING CONDITIONS Parameter
Operating Temperature Range
Rating −40 to +85
Units °C
Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 1)
(IEC 61000−4−2 Level 4, Contact Discharge)
• ±15 kV ESD Protection on each Channel (HBM) • Supports Bipolar Signals − Ideal for Audio Applications • Chip Scale Package Features Extremely Low Lead Inductance for
68 W
A1
C1
47 pF
47 pF
68 W
A3
C3
47 pF
47 pF
B2
MARKING DIAGRAM
+ AD
AD = CSPEMI202AG
ORDERING INFORMATION

DSI30-12AS;DSI30-08AS;DSI30-16AS;DSI30-08A;DSI30-12A;中文规格书,Datasheet资料

Tamb
0 0 20 40 60 80 100 120 140 °C TC
Fig. 4 Power dissipation versus direct output current and ambient temperature, sine 180°
1.2 K/W 1.0
ZthJC
Fig. 5 Max. forward current versus case temperature
Nm

A
C (TAB)
TO-220 AC
C A C (TAB)
Conditions TC = 95°C; 180° sine t = 10 ms (50 Hz), sine t = 8.3 ms (60 Hz), sine t = 10 ms (50 Hz), sine t = 8.3 ms (60 Hz), sine t = 10 ms (50 Hz), sine t = 8.3 ms (60 Hz), sine t = 10 ms (50 Hz), sine t = 8.3 ms (60 Hz), sine
50
TVJ = 150°C
10
0 0.0
0.4
0.8 VF
1.2 V
1.6
0 0.001
102 0.01 0.1 t s 1 1 2 3 4 5 6 7 ms 8 910 t
Fig. 1 Forward current versus voltage drop per diode
60 W
Fig. 2 Surge overload current
Inches Min. Max. .160 .080 .020 .045 .018 .045 .340 .280 .380 .270 .100 .575 .090 .040 .050 0 .018 .190 .110 .039 .055 .029 .055 .380 .320 .405 .320 BSC .625 .110 .055 .070 .015 .029

CS5532-BSZR;CS5534-BSZR;CDB5532U;中文规格书,Datasheet资料

Copyright © Cirrus Logic, Inc. 2008CS5532/34-BS24-bit ∆Σ ADCs with Ultra-low-noise PGIAFeaturesChopper-stabilized PGIA (ProgrammableGain Instrumentation Amplifier, 1x to 64x)– 6 nV/√Hz @ 0.1 Hz (No 1/f noise) at 64x –1200pA Input Current with Gains >1 Delta-sigma Analog-to-digital Converter –Linearity Error: 0.0007% FS–Noise-free Resolution: Up to 23 bits Two- or Four-channel Differential MUX Scalable Input Span via Calibration –±5 mV to differential ±2.5VScalable V REF Input: Up to Analog Supply Simple Three-wire Serial Interface –SPI™ and Microwire™ Compatible –Schmitt Trigger on Serial Clock (SCLK) R/W Calibration Registers Per Channel Selectable Word Rates: 6.25 to 3,840 Sps Selectable 50 or 60 Hz RejectionPower Supply Configurations–VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V–VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V –VA+ = +3 V; VA- = -3 V; VD+ = +3 VGeneral DescriptionThe CS5532/34 are highly integrated ∆Σ Analog-to-Digi-tal Converters (ADCs) which use charge-balance techniques to achieve 24-bit performance. The ADCs are optimized for measuring low-level unipolar or bipolar signals in weigh scale, process control, scientific, and medical applications.To accommodate these applications, the ADCs come as either two-channel (CS5532) or four-channel (CS5534)devices and include a very low-noise, chopper-stabilized instrumentation amplifier (6 nV/√Hz @ 0.1 Hz) with se-lectable gains of 1×, 2×, 4×, 8×, 16×, 32×, and 64×.These ADCs also include a fourth-order ∆Σ modulator followed by a digital filter which provides twenty selectable output word rates of 6.25, 7.5, 12.5, 15, 25, 30, 50, 60, 100,120, 200, 240, 400, 480, 800, 960, 1600, 1920, 3200, and 3840 Sps (MCLK =4.9152MHz).To ease communication between the ADCs and a micro-controller, the converters include a simple three-wire se-rial interface which is SPI™ and Microwire™ compatible with a Schmitt-trigger input on the serial clock (SCLK).High dynamic range, programmable output rates, and flexible power supply options makes these ADCs ideal solutions for weigh scale and process control applications.ORDERING INFORMATIONSee page 47VA+C1C2VREF+VREF-VD+DIFFERENTIAL 4TH ORDER ∆ΣMODULATORPGIA 1,2,4,8,16PROGRAMMABLE SINC FIR FILTERMUX(CS5534SHOWN)AIN1+AIN1-AIN2+AIN2-AIN3+AIN3-AIN4+AIN4-SERIAL INTERFACELATCHCLOCK GENERATORCALIBRATION SRAM/CONTROLLOGICDGNDCSSDI SDO SCLKOSC2OSC1A1A0/GUARD VA-32,64OCT ‘08TABLE OF CONTENTS1.CHARACTERISTICS AND SPECIFICATIONS (4)ANALOG CHARACTERISTICS (4)TYPICAL RMS NOISE (NV) (7)TYPICAL NOISE-FREE RESOLUTION(BITS) (7)5 V DIGITAL CHARACTERISTICS (8)3 V DIGITAL CHARACTERISTICS (8)DYNAMIC CHARACTERISTICS (9)ABSOLUTE MAXIMUM RATINGS (9)SWITCHING CHARACTERISTICS (10)2.GENERAL DESCRIPTION (12)2.1.Analog Input (12)2.1.1. Analog Input Span (13)2.1.2. Multiplexed Settling Limitations (13)2.1.3. Voltage Noise Density Performance (13)2.1.4. No Offset DAC (14)2.2.Overview of ADC Register Structure and Operating Modes (14)2.2.1. System Initialization (15)2.2.2. Serial Port Interface (22)2.2.3. Reading/Writing On-Chip Registers (23)2.3.Configuration Register (23)2.3.1. Power Consumption (23)2.3.2. System Reset Sequence (23)2.3.3. Input Short (24)2.3.4. Guard Signal (24)2.3.5. Voltage Reference Select (24)2.3.6. Output Latch Pins (24)2.3.7. Offset and Gain Select (25)2.3.8. Filter Rate Select (25)2.4.Setting up the CSRs for a Measurement (27)2.5.Calibration (30)2.5.1. Calibration Registers (30)2.5.2. Performing Calibrations (31)2.5.3. Self Calibration (31)2.5.4. System Calibration (32)2.5.5. Calibration Tips (32)2.5.6. Limitations in Calibration Range (33)2.6.Performing Conversions (33)2.6.1. Single Conversion Mode (33)2.6.2. Continuous Conversion Mode (34)2.6.3. Examples of Using CSRs to Perform Conversions and Calibrations (35)ing Multiple ADCs Synchronously (36)2.8.Conversion Output Coding (36)2.9.Digital Filter (38)2.10.Clock Generator (39)2.11.Power Supply Arrangements (39)2.12.Getting Started (43)2.13.PCB Layout (43)3.PIN DESCRIPTIONS (44)4.SPECIFICATION DEFINITIONS (46)5.ORDERING INFORMATION (47)6.ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION (47)7.PACKAGE DRAWINGS (48)LIST OF FIGURESFigure 1. SDI Write Timing (Not to Scale) (11)Figure 2. SDO Read Timing (Not to Scale) (11)Figure 3. Multiplexer Configuration (12)Figure 4. Input models for AIN+ and AIN- pins (13)Figure 5. Measured Voltage Noise Density (13)Figure 6. CS5532/34 Register Diagram (14)Figure 7. Command and Data Word Timing (22)Figure 8. Guard Signal Shielding Scheme (24)Figure 9. Input Reference Model when VRS = 1 (25)Figure 10. Input Reference Model when VRS = 0 (25)Figure 11. Self Calibration of Offset (32)Figure 12. Self Calibration of Gain (32)Figure 13. System Calibration of Offset (32)Figure 14. System Calibration of Gain (32)Figure 15. Synchronizing Multiple ADCs (36)Figure 16. Digital Filter Response (WR = 60 Sps) (38)Figure 18. 120 Sps Filter Phase Plot to 120 Hz (38)Figure 17. 120 Sps Filter Magnitude Plot to 120 Hz (38)Figure 19. Z-Transforms of Digital Filters (38)Figure 20. On-chip Oscillator Model (39)Figure 21. CS5532 Configured with a Single +5 V Supply (40)Figure 22. CS5532 Configured with ±2.5 V Analog Supplies (41)Figure 23. CS5532 Configured with ±3 V Analog Supplies (41)Figure 24. CS5532 Configured for Thermocouple Measurement (42)Figure 25. Bridge with Series Resistors (42)LIST OF TABLESTable 1. Conversion Timing – Single Mode (34)Table 2. Conversion Timing – Continuous Mode (35)Table 3. Command Byte Pointer (35)Table 4. Output Coding for 24-bit CS5532 and CS5534 (37)1. CHARACTERISTICS AND SPECIFICATIONSANALOG CHARACTERISTICS(VA+, VD+ = 5 V ±5%; VREF+ = 5 V; VA-, VREF-, DGND = 0 V; MCLK = 4.9152 MHz; OWR (Output Word Rate) = 60 Sps; Bipolar Mode; Gain = 32)(See Notes 1 and 2.)Notes: 1.Applies after system calibration at any temperature within -40 °C ~ +85 °C.2.Specifications guaranteed by design, characterization, and/or test. LSB is 24 bits.3. This specification applies to the device only and does not include any effects by external parasiticthermocouples. The PGIA contributes 5 nV of offset drift, and the modulator contributes 640/G nV of offset drift, where G is the amplifier gain setting.4.Drift over specified temperature range after calibration at power-up at 25 °C.ParameterMin Typ Max Unit Accuracy Linearity Error -±0.0007±0.0015%FS No Missing Codes 24--Bits Bipolar Offset -±16±32LSB 24Unipolar Offset-±32±64LSB 24Offset Drift(Notes 3 and 4)-640/G +5-nV/°C Bipolar Full-scale Error -±8±31ppm Unipolar Full-scale Error -±16±62ppm Full-scale Drift(Note 4)-2-ppm/°CANALOG CHARACTERISTICS (Continued)(See Notes 1 and 2.)Notes: 5.The voltage on the analog inputs is amplified by the PGIA, and becomes V CM ± Gain*(AIN+ - AIN-)/2 atthe differential outputs of the amplifier. In addition to the input common mode + signal requirements for the analog input pins, the differential outputs of the amplifier must remain between (VA- + 0.1 V) and (VA+ - 0.1 V) to avoid saturation of the output stage.6.See the section of the data sheet which discusses input models.7.Input current on AIN+ or AIN- (with Gain =1), or VREF+ or VREF- may increase to 250nA if operatedwithin 50mV of VA+ or VA-. This is due to the rough charge buffer being saturated under these conditions.ParameterMin TypMaxUnitAnalog InputCommon Mode + Signal on AIN+ or AIN-Bipolar/Unipolar ModeGain = 1 Gain = 2, 4, 8, 16, 32, 64(Note 5)VA-VA- + 0.7--VA+VA+ - 1.7V V CVF Current on AIN+ or AIN-Gain = 1 (Note 6, 7)Gain = 2, 4, 8, 16, 32, 64--501200--nA pA Input Current Noise Gain = 1 Gain = 2, 4, 8, 16, 32, 64--2001--pA/√Hz pA/√Hz Input Leakage for Mux when Off (at 25 °C)-10-pA Off-channel Mux Isolation -120-dB Open Circuit Detect Current 100300-nA Common Mode Rejection dc, Gain = 1dc, Gain = 6450, 60 Hz ---90130120---dB dB dB Input Capacitance -60-pF Guard Drive Output -20-µA Voltage Reference Input Range (VREF+) - (VREF-)1 2.5(VA+)-(VA-)V CVF Current (Note 6, 7)-50-nA Common Mode Rejection dc 50, 60 Hz --120120--dB dB Input Capacitance 11-22pF System Calibration Specifications Full-scale Calibration Range Bipolar/Unipolar Mode 3-110%FS Offset Calibration Range Bipolar Mode -100-100%FS Offset Calibration Range Unipolar Mode -90-90%FSANALOG CHARACTERISTICS (Continued)(See Notes 1 and 2.)8.All outputs unloaded. All input CMOS levels.9.Power is specified when the instrumentation amplifier (Gain ≥ 2) is on. Analog supply current is reducedby approximately 1/2 when the instrumentation amplifier is off (Gain = 1).10.Tested with 100 mV change on VA+ or VA-.ParameterMinTypMaxUnitPower SuppliesDC Power Supply Currents (Normal Mode)I A+, I A-I D+- - 130.5151mA mA Power ConsumptionNormal Mode (Notes 8 and 9)Standby Sleep---70450080--mW mW µW Power Supply Rejection (Note 10)dc Positive Supplies dc Negative Supply--115115--dB dBTYPICAL RMS NOISE (nV)(See notes 11, 12, 13 and 14)Notes:11.The -B devices provide the best noise specifications.12.Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25 °C.13.For Peak-to-Peak Noise multiply by 6.6 for all ranges and output rates.14.Word rates and -3dB points with FRS = 0. When FRS = 1, word rates and -3dB points scale by 5/6.TYPICAL NOISE-FREE RESOLUTION(BITS)(See Notes 15 and 16)15.Noise-free resolution listed is for bipolar operation, and is calculated as LOG((Input Span)/(6.6xRMSNoise))/LOG(2) rounded to the nearest bit. For unipolar operation, the input span is 1/2 as large, so one bit is lost. The input span is calculated in the analog input span section of the data sheet. The noise-free resolution table is computed with a value of 1.0 in the gain register. Values other than 1.0 will scale the noise, and change the noise-free resolution accordingly.16.“Noise-free resolution” is not the same as “effective resolution”. Effective resolution is based on theRMS noise value, while noise-free resolution is based on a peak-to-peak noise value specified as 6.6 times the RMS noise value. Effective resolution is calculated as LOG((Input Span)/(RMS Noise))/LOG(2).Specifications are subject to change without notice.Output Word Rate (Sps)-3 dB Filter Frequency (Hz)Instrumentation Amplifier Gain x64x32x16x8x4x2x17.5 1.948.59101526509915 3.88121315213770139307.751718213052991966015.524252942731402771203134364259103198392240628013626051410202050409048012211319436973014502900581096023015927452310302060411082301,920390260470912181036207230145003,84078013602690538010800215004300086000Output Word Rate (Sps)-3 dB Filter Frequency (Hz)Instrumentation Amplifier Gainx64x32x16x8x4x2x17.5 1.942021222323232315 3.8820212222222222307.75192021222222226015.5192021212121211203118192021212121240621717181818181848012217171717171717960230161617171717171,920390161616161616163,840780131313131313135 V DIGITAL CHARACTERISTICS(VA+, VD+ = 5 V ±5%; VA-, DGND = 0 V; See Notes 2 and 17.)3 V DIGITAL CHARACTERISTICS(T A = 25 °C; VA+ = 5V ±5%; VD+ = 3.0V±10%; VA-, DGND = 0V; See Notes 2 and 17.)17.All measurements performed under static conditions.ParameterSymbol Min Typ Max Unit High-level Input Voltage All Pins Except SCLKSCLK V IH 0.6 VD+(VD+) - 0.45--VD+VD+V Low-level Input Voltage All Pins Except SCLKSCLK V IL 0.00.0-0.80.6V High-level Output Voltage A0 and A1, I out = -1.0 mASDO, I out = -5.0 mA V OH (VA+) - 1.0(VD+) - 1.0--V Low-level Output Voltage A0 and A1, I out = 1.0 mASDO, I out = 5.0 mAV OL --(VA-) + 0.40.4V Input Leakage Current I in -±1±10µA SDO Tri-State Leakage Current I OZ --±10µA Digital Output Pin CapacitanceC out-9-pFParameterSymbol Min Typ Max Unit High-level Input Voltage All Pins Except SCLKSCLK V IH 0.6 VD+(VD+) - 0.45-VD+VD+V Low-level Input Voltage All Pins Except SCLKSCLK V IL 0.00.0-0.80.6V High-level Output Voltage A0 and A1, I out = -1.0 mASDO, I out = -5.0 mA V OH (VA+) - 1.0(VD+) - 1.0--V Low-level Output Voltage A0 and A1, I out = 1.0 mASDO, I out = 5.0 mAV OL --(VA-) + 0.40.4V Input Leakage Current I in -±1±10µA SDO Tri-State Leakage Current I OZ --±10µA Digital Output Pin CapacitanceC out-9-pFDYNAMIC CHARACTERISTICS18.The ADCs use a Sinc 5 filter for the 3200 Sps and 3840 Sps output word rate (OWR) and a Sinc 5 filterfollowed by a Sinc 3 filter for the other OWRs. OWR sinc5 refers to the 3200 Sps (FRS = 1) or 3840 Sps (FRS = 0) word rate associated with the Sinc 5 filter.19.The single conversion mode only outputs fully settled conversions. See Table 1 for more details aboutsingle conversion mode timing. OWR SC is used here to designate the different conversion time associated with single conversions.20.The continuous conversion mode outputs every conversion. This means that the filter’s settling timewith a full scale step input in the continuous conversion mode is dictated by the OWR.ABSOLUTE MAXIMUM RATINGS(DGND = 0 V; See Note 21.)Notes:21.All voltages with respect to ground.22.VA+ and VA- must satisfy {(VA+) - (VA-)} ≤ +6.6 V.23.VD+ and VA- must satisfy {(VD+) - (VA-)} ≤ +7.5 V.24.Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pins.25.Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power supply pin is ±50 mA.26.Total power dissipation, including all input currents and output currents.WARNING:Operation at or beyond these limits may result in permanent damage to the device.Normal operation is not guaranteed at these extremes.ParameterSymbol Ratio Unit Modulator Sampling Ratef s MCLK/16Sps Filter Settling Time to 1/2 LSB (Full Scale Step Input)Single Conversion mode (Notes 18, 19, and 20)Continuous Conversion mode, OWR < 3200 Sps Continuous Conversion mode, OWR ≥ 3200 Spst s t s t s1/OWR SC5/OWR sinc5 + 3/OWR5/OWRs s sParameterSymbol Min Typ Max Unit DC Power Supplies(Notes 22 and 23)Positive Digital Positive Analog Negative Analog VD+VA+VA--0.3-0.3+0.3---+6.0+6.0-3.75V V V Input Current, Any Pin Except Supplies (Notes 24 and 25)I IN --±10mA Output Current I OUT--±25mA Power Dissipation (Note 26)PDN --500mW Analog Input Voltage VREF pins AIN PinsV INR V INA (VA-) -0.3(VA-) -0.3--(VA+) + 0.3(VA+) + 0.3V V Digital Input VoltageV IND -0.3-(VD+) + 0.3V Ambient Operating Temperature T A -40-85°C Storage Temperature T stg-65-150°CSWITCHING CHARACTERISTICS(VA+ = 2.5 V or 5 V ±5%; VA- = -2.5V±5% or 0 V; VD+ = 3.0 V ±10% or 5 V ±5%;DGND = 0 V; Levels: Logic 0 = 0 V, Logic 1 = VD+; C L = 50 pF; See Figures 1 and 2.)Notes:27.Device parameters are specified with a 4.9152 MHz clock.28.Specified using 10% and 90% points on waveform of interest. Output loaded with 50pF.29.Oscillator start-up time varies with crystal parameters. This specification does not apply when using anexternal clock source.ParameterSymbol Min Typ MaxUnitMaster Clock Frequency (Note 27)External Clock or Crystal OscillatorMCLK1 4.91525MHz Master Clock Duty Cycle 40-60%Rise Times(Note 28)Any Digital Input Except SCLKSCLKAny Digital Output t rise-----50 1.0100-µs µs ns Fall Times(Note 28)Any Digital Input Except SCLKSCLKAny Digital Output t fall-----50 1.0100-µs µs ns Start-upOscillator Start-up Time XTAL = 4.9152 MHz(Note 29)t ost-20-ms Serial Port Timing Serial Clock Frequency SCLK 0-2MHz Serial Clock Pulse Width High Pulse Width Lowt 1t 2250250----ns nsSDI Write TimingCS Enable to Valid Latch Clock t 350--ns Data Set-up Time prior to SCLK rising t 450--ns Data Hold Time After SCLK Rising t 5100--ns SCLK Falling Prior to CS Disable t 6100--nsSDO Read Timing CS to Data Validt 7--150ns SCLK Falling to New Data Bit t 8--150ns CS Rising to SDO Hi-Zt 9--150ns分销商库存信息:CIRRUS-LOGICCS5532-BSZR CS5534-BSZR CDB5532U。

W9412G6JH-5I;中文规格书,Datasheet资料

Read Operation............................................................................................................. 12 Write Operation ............................................................................................................. 13 Precharge ..................................................................................................................... 13 Burst Termination ......................................................................................................... 13 Refresh Operation ........................................................................................................ 13 Power Down Mode ....................................................................................................... 14 Input Clock Frequency Change during Precharge Power Down Mode ........................ 14 Mode Register Operation .............................................................................................. 14 Publication Release Date: Nov. 29, 2011 Revision A03

DS1603;中文规格书,Datasheet资料

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: /errata .FEATURES§ Two 32-bit counters keep track of real -time and elapsed time§ Counters keep track of seconds for over 125 years§ Battery powered counter counts seconds from the time battery is attached until V BAT is less than 2.5V§ V CC powered counter counts seconds while V CC is above V TP and retains the count in the absence of V CC under battery backup power § Clear function resets selected counter to 0 § Read/write serial port affords low pin count § Powered internally by a lithium energy cell that provides over 10 years of operation§ One-byte protocol defines read/write, counter address and software clear function§ Self-contained crystal provides an accuracy of ±2 min per month§ Operating temperature range of 0°C to +70°C § Low-profile SIP module§ Underwriters Laboratory (UL) recognized PIN ASSIGNMENTPIN DESCRIPTIONRST- Reset CLK - ClockDQ - Data Input/Output GND - Ground V CC - +5VOSC - 1Hz Oscillator Output NC- No ConnectDESCRIPTIONThe DS1603 is a real -time clock/elapsed time counter designed to count seconds when V CC power is applied and continually count seconds under battery backup power with an additional counter regardless of the condition of V CC . The continuous counter can be used to derive time of day, week, month, and year by using a software algorithm. The V CC powered counter will automatically record the amount of time that V CC power is applied. This function is particularly useful in determining the operational time of equipment in which the DS1603 is used. Alternatively, this counter can also be used under software control to record real -time events. Communication to and from the DS1603 takes place via a 3-wire serial port. A 1-byte protocol selects read/ write functions, counter clear functions and oscillator trim. The device contains a 32.768kHz crystal that will keep track of time to within ±2 min/mo. An internal lithium energy source contains enough energy to power the continuous seconds counter for over 10 years.OPERATIONThe main elements of the DS1603 are shown in Figure 1. As shown, communications to and from the elapsed time counter occur over a 3-wire serial port. The port is activated by driving RST to a high state.V CC RST DQ NC CLK OSC GND DS1603Elapsed Time Counter Moduleselect, register clear, and oscillator trim information. Each bit is serially input on the rising edge of the clock input. After the first eight clock cycles have loaded the protocol register with a valid protocol additional clocks will output data for a read or input data for a w rite. V CC must be present to access the DS1603. If V CC < V TP, the DS1603 will switch to internal power and disable the serial port to conserve energy. When running off of the internal power supply, only the continuous counter will continue to count and the counter powered by V CC will stop, but retain the count, which had accumulated when V CC power was lost. The 32-bit V CC counter is gated by V CC and the internal 1Hz signal.PROTOCOL REGISTERThe protocol bit definition is shown in Figure 2. Valid protocols and the resulting actions are shown in Table 1. Each data transfer to the protocol register designates what action is to occur. As defined, the MSB (bit 7 which is designated ACC) selects the 32-bit continuous counter for access. If ACC is a logical 1 the continuous counter is selected and the 32 clock cycles that follow the protocol will either read or write this counter. If the counter is being read, the contents will be latched into a different register at the end of protocol and the latched contents will be read out on the next 32 clock cycles. This avoids reading garbled data if the counter is clocked by the oscillator during a read. Similarly, if the counter is to be written, the data is buffered in a register and all 32 bits are jammed into the counter simultaneously on the rising edge of the 32nd clock. The next bit (bit 6 which is designated AVC) selects the 32–bit V CC active counter for access. If AVC is a logical 1 this counter is selected and the 32 clock cycles that follow will either read or write this counter. If both bit 7 and bit 6 are written to a logic high, all clock cycles beyond the protocol are ignored and bit 5, 4, and 3 are loaded into the oscillator trim register. A value of binary 3 (011) will give a clock accuracy of ±120 seconds per month at +25°C. Increasing the binary number towards 7 will cause the real-time clock to run faster. Conversely, lowering the binary number towards 0 will cause the clock to run slower. Binary 000 will stop the oscillator completely. This feature can be used to conserve battery life during storage. In this mode the internal power supply current is reduced to 100 nA maximum. In applications where oscillator trimming is not practical or not needed, a default setting of 011 is recommended. Bit 2 of protocol (designated CCC) is used to clear the continuous counter. When set to logic 1, the continuous counter will reset to 0 when RST is taken low. Bit 1 of protocol (designated CVC) is used to clear the V CC active counter. When set to logical 1, the V CC active counter will reset to 0 when RST is taken low. Both counters can be reset simultaneously by setting CCC and CVC both to a logical 1. Bit 0 of the protocol (designated RD) determines whether the 32 clocks to follow w ill write a counter or read a counter. When RD is set to a logical 0 a write action will follow when RD is set to a logical 1 a read action will follow. When sending the protocol, 8 bits should always be sent. Sending less than 8 bits can produce erroneous results. If clearing the counters or trimming the oscillator, the data transfer can be terminated after the 8-bit protocol is sent. However, when reading or writing the counters, 32 clock cycles should always follow the protocol.RESET AND CLOCK CONTROLAll data transfers are initiated by driving the RST input high. The RST input has two functions. First, RST turns on the serial port logic, which allows access to the protocol register for the protocol data entry. Second, the RST signal provides a method of terminating the protocol transfer or the 32-bit counter transfer. A clock cycle is a sequence of a rising edge followed by a falling edge. For write inputs, data must be valid during the rising edge of the clock. Data bits are output on the falling edge of the clock when data is being read. All data transfers terminate if the RST input is transitioned low and the DQ pin goes to a high-impedance state. RST should only be transitioned low while the clock is high to avoid disturbing the last bit of data. All data transfers must consist of 8 bits when transferring protocol only or 8 + 32 bits when reading or writing either counter. Data tran sfer is illustrated in Figure 3.DATA INPUTFollowing the 8-bit protocol that inputs write mode, 32 bits of data are written to the selected counter on the rising edge of the next 32 CLK cycles. After 32 bits have been entered any additional CLK cycles will be ignored until RST is transitioned low to end data transfer and then high again to begin new data transfer.DATA OUTPUTFollowing the eight CLK cycles that input read mode protocol, 32 bits of data will be output from the selected counter on the next 32 CLK cycles. The first data bit to be transmitted from the selected 32-bit counter occurs on the falling edge after the last bit of protocol is written. When transmitting data from the selected 32-bit counter, RST must remain at high level as a transition to low level will terminate data transfer. Data is driven out the DQ pin as long as CLK is low. When CLK is high the DQ pin is tristated. OSCILLATOR OUTPUTPin 6 of the DS1603 module is a 1Hz output signal. This signal is present only when V CC is applied and greater than the internal power supply. However, the output is guaranteed to meet TTL requirement only while V CC is within normal limits. This output can be used as a 1-second interrupt or time tick needed in some applications.INTERNAL POWERThe internal battery of the DS1603 module provides 35mAh and will run the elapsed time counter for over 10 years in the absence of power.PIN DESCRIPTIONSV CC, GND – DC power is provided to the device on these pins. V CC is the +5V input. When 5V is applied within normal limits, the device is fully accessible and data can be written and read. When a 3V battery is connected to the device and V CC is below 1.25 x V BAT, reads and writes are inhibited. As V CC falls below V BAT the continuous counter is switched over to the internal battery.CLK (Serial Clock Input) – CLK is used to synchronize data movement on the serial interface.DQ (Data Input/Output) – The DQ pin is the bi-directional data pin for the 3-wire interface.RST (Reset) – The reset signal must be asserted high during a read or a write.OSC (One Hertz Output Signal) – This signal is only present when Vcc is at a valid level and the oscillator is enabled.Figure 1. ELAPSED TIME COUNTER BLOCK DIAGRAMFigure 2. PROTOCOL BIT MAP7 6 5 4 3 2 1 0ACC AVC OSC2 OSC1 OSC0 CCC CVC RDTable 1. VALID PROTOCOLSPROTOCOLACTIONACC AVC OSC2 OSC1 OSC0 CCC CVC RDFUNCTION ReadContinuous Counter 1 0 X X X X X 1Output continuouscounter on the 32 clocksfollowing protocol.Oscillator trim registeris not updated. Countersare not reset.WriteContinuous Counter 1 0 X X X X X 0Input data to continuouscounter on the 32 clocksfollowing protocol.Oscillator trim registeris not updated. Countersare not reset.Read V CCActive Counter 0 1 X X X X X 1Output V CC activecounter on the 32 clocksfollowing protocol,oscillator trim registeris not updated. Countersare not reset.Write V CCActive Counter 0 1 X X X X X 0Input data to continuouscounter on the 32 clocksfollowing protocol.Oscillator trim registeris not updated. Countersare not reset.ClearContinuous Counter 0 0 X X X 1 X XResets the continuouscounter to all zeros atthe end of protocol.Oscillator trim registeris not updated.Clear V CCActive Counter 0 0 X X X X 1 XResets the V CC activecounter to all zeros atthe end of protocol.Oscillator trim registeris not updated.Set Oscillator Trim Bits 1 1 A B C X X 0Sets the oscillator trimregister to a value ofABC. Counters areunaffected.X = Don’t CareFigure 3. DATA TRANSFERTIMING DIAGRAM: READ/WRITE DATA TRANSFERNote: t CL, t CH, t R, and t F apply to both read and write data transfer.ABSOLUTE MAXIMUM RATINGSVoltage Range on Any Pin Relative to Ground -0.3V to +7.0VOperating Temperature Range 0°C to +70°CStorage Temperature Range -40°C to +70°CSoldering Temperature Range See IPC/JEDEC J-STD-020A (See Note 11)This is a stress rating only and functional operation of the device at these or any other conditions beyond t h ose indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability.RECOMMENDED DC OPERATING CONDITIONS (0°C to +70°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Supply Voltage V CC 4.5 5.0 5.5 V 1 Logic 1 Input V IH 2.0 V CC + 0.3 V 1 Logic 0 Input V IL-0.3 0.8 V 1DC ELECTRICAL CHARACTERISTICS (0°C to +70°C; V CC = 5V ±10%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Leakage I LI-1 +1 µAI/O Leakage I LO-1 +1 µALogic 1 Output V OH 2.4 V 2 Logic 0 Output V OL0.4 V 3 Active Supply Current I CC 1 mA 4 Timekeeping Current I CC150 µA 5 Battery Trip Point V TP 3.0 4.5 V 9 CAPACITANCE (T A = +25°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Capacitance C I 5 pFI/O Capacitance C I/O10 pF(T A = +25°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Expected Datat DR10 years 10 Retention TimeNOTES:1) All voltages are referenced to ground.2) Logic 1 voltages are specified at a source current of 1mA.3) Logic 0 voltages are specified at a sink current of 4mA.4) I CC is specified with the DQ pin open.5) I CC1 is specified with V CC at 5.0V and RST = GND.6) Measured at V IH= 2.0V or V IL = 0.8V.7) Measured at V OH = 2.4V or V OL - 0.4V.8) Load capacitance = 50pF.9) Battery trip point is the point at which the V CC powered counter and the serial port stops operation.The battery trip point drops below the minimum once the internal lithium energy cell is exhausted. 10) The expected t D R is defined as accumulative time in the absence of V CC with the clock oscillatorrunning.11) Real-time clock modules can be successfully processed through conventional wave-solderingtechniques as long as temperature exposure to the lithium energy source contained within does not exceed +85°C. Post-solder cleaning with water-washing techniques is acceptable, provided that ultrasonic vibration is not used.DS1603DS1603 7-PIN MODULEPKG7-PIN DIM MIN MAX A IN. MM 0.830 21.08 0.850 21.59 B IN. MM 0.650 16.51 0.670 17.02 C IN. MM 0.310 7.87 0.330 8.38 D IN. MM 0.015 0.38 0.030 0.76 E IN. MM 0.110 2.79 0.140 3.56 F IN. MM 0.015 0.38 0.021 0.53 G IN. MM 0.090 2.29 0.110 2.79 H IN. MM 0.105 2.67 0.135 3.43 J IN. MM 0.360 9.14 0.390 9.91分销商库存信息: MAXIMDS1603。

L3GD20TR;L3GD20;中文规格书,Datasheet资料

August 2011Doc ID 022116 Rev 11/44L3GD20MEMS motion sensor:three-axis digital output gyroscopeFeatures■Three selectable full scales (250/500/2000 dps)■I 2C/SPI digital output interface ■16 bit-rate value data output ■8-bit temperature data output■Two digital output lines (interrupt and data ready)■Integrated low- and high-pass filters with user-selectable bandwidth■Wide supply voltage: 2.4 V to 3.6 V ■Low voltage-compatible IOs (1.8 V)■Embedded power-down and sleep mode ■Embedded temperature sensor ■Embedded FIFO ■High shock survivability■Extended operating temperature range (-40 °C to +85 °C)■ECOPACK ® RoHS and “Green” compliantApplications■Gaming and virtual reality input devices ■Motion control with MMI (man-machine interface)■GPS navigation systems ■Appliances and roboticsDescriptionThe L3GD20 is a low-power three-axis angular rate sensor.It includes a sensing element and an IC interface capable of providing the measured angular rate to the external world through a digital interface (I 2C/SPI).The sensing element is manufactured using a dedicated micro-machining process developed by STMicroelectronics to produce inertial sensors and actuators on silicon wafers.The IC interface is manufactured using a CMOS process that allows a high level of integration to design a dedicated circuit which is trimmed to better match the sensing element characteristics.The L3GD20 has a full scale of ±250/±500/ ±2000 dps and is capable of measuring rates with a user-selectable bandwidth.The L3GD20 is available in a plastic land grid array (LGA) package and can operate within a temperature range of -40 °C to +85 °C.Table 1. Device summaryOrder code Temperature range (°C)Package Packing L3GD20-40 to +85LGA-16 (4x4x1 mm)Tray L3GD20TR-40 to +85LGA-16 (4x4x1 mm)T ape and reelContents L3GD20Contents1Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.1Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 92.1Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.2Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.3Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.4Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 112.4.1SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.4.2I2C - Inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.5Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.6Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.6.1Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.6.2Zero-rate level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.7Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154Digital main blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164.1Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164.2FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164.2.1Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174.2.2FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174.2.3Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184.2.4Bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204.2.5Stream-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204.2.6Retrieve data from FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225.1I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225.1.1I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235.2SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245.2.1SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2/44Doc ID 022116 Rev 1L3GD20Contents5.2.2SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275.2.3SPI read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276Output register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317.1WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317.2CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317.3CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327.4CTRL_REG3 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337.5CTRL_REG4 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347.6CTRL_REG5 (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347.7REFERENCE/DAT ACAPTURE (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357.8OUT_TEMP (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357.9STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367.10OUT_X_L (28h), OUT_X_H (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367.11OUT_Y_L (2Ah), OUT_Y_H (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367.12OUT_Z_L (2Ch), OUT_Z_H (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367.13FIFO_CTRL_REG (2Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367.14FIFO_SRC_REG (2Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377.15INT1_CFG (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377.16INT1_SRC (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387.17INT1_THS_XH (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397.18INT1_THS_XL (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397.19INT1_THS_YH (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397.20INT1_THS_YL (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397.21INT1_THS_ZH (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407.22INT1_THS_ZL (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407.23INT1_DURA TION (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Doc ID 022116 Rev 13/44List of tables L3GD20 List of tablesTable 2.Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 3.Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 4.Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 5.Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 6.SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 7.I2C slave timing values (TBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 8.Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 9.Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 10.I2C terminology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 11.SAD+read/write patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 12.Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 13.Transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 14.Transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 24 Table 15.Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 24 Table 16.Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 17.WHO_AM_I register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 18.CTRL_REG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 19.CTRL_REG1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 20.DR and BW configuration setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 21.Power mode selection configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 22.CTRL_REG2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 23.CTRL_REG2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 24.High-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 25.High-pass filter cut off frequency configuration [Hz]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 26.CTRL_REG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 27.CTRL_REG3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 28.CTRL_REG4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 29.CTRL_REG4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 30.CTRL_REG5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 31.CTRL_REG5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 32.REFERENCE register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 33.REFERENCE register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 34.OUT_TEMP register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 35.OUT_TEMP register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 36.STATUS_REG register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 37.STATUS_REG description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 38.REFERENCE register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 39.REFERENCE register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 40.FIFO mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 41.FIFO_SRC register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 42.FIFO_SRC register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 43.INT1_CFG register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 44.INT1_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 45.INT1_SRC register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 46.INT1_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 47.INT1_THS_XH register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 48.INT1_THS_XH description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 49.INT1_THS_XL register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4/44Doc ID 022116 Rev 1L3GD20List of tables Table 50.INT1_THS_XL description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 51.INT1_THS_YH register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 52.INT1_THS_YH description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 53.INT1_THS_YL register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 54.INT1_THS_YL description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 55.INT1_THS_ZH register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 56.INT1_THS_ZH description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 57.INT1_THS_ZL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 58.INT1_THS_ZL description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 59.INT1_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 60.INT1_DURATION description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 61.Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Doc ID 022116 Rev 15/44List of figures L3GD20 List of figuresFigure 1.Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2.Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3.SPI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 4.I2C slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5.L3GD20 electrical connections and external component values . . . . . . . . . . . . . . . . . . . . 15 Figure 6.Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 7.Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 8.FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 9.Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 10.Bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 11.Trigger stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 12.Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 13.SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 14.Multiple byte SPI read protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 15.SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 16.Multiple byte SPI write protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 17.SPI read protocol in 3-wire mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 18.INT1_Sel and Out_Sel configuration block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 19.Wait disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 20.Wait enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 21.LGA-16: mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6/44Doc ID 022116 Rev 1Doc ID 022116 Rev 17/441 Block diagram and pin descriptionFigure 1.Block diagramNote:The vibration of the structure is maintained by drive circuitry in a feedback loop. The sensing signal is filtered and appears as a digital signal at the output.1.1 Pin descriptionFigure 2.Pin connectionFIFOTRIMMING CIRCUITSREFERENCEMIXERCHARGE AMPCLOCK LOW-PASS FILTER+Ωx,y,zI2C SPICSSCL/SPCSDA/SDO/SDI SDOY+Z+Y-Z-X+X-DRIVING MASSFeedback loopM U XA D D C I G I T A LF I L T E R I N GCONTROL LOGIC&INTERRUPT GEN.INT1DRDY/INT2A D C T E M P E R A T U R ES E N S O R12&PHASE GENERATORAM10126V1(TOP VIEW)DIRECTION S OF THE DETECTABLE ANGULAR RATE SXVdd_IO S CL/S PC S DA/S DI/S DOS DO/S A0RE S RE S RE S RE SI N T 1D R D Y /I N T 2C SR E SR E SR E SV d dG N D18125491316+ΩZ+ΩXBOTTOMVIEW+ΩYAM10127V18/44Doc ID 022116 Rev 1Table 2.Pin descriptionPin#Name Function1Vdd_IO (1)1.100 nF filter capacitor recommended.Power supply for I/O pins 2SCL SPC I 2C serial clock (SCL)SPI serial port clock (SPC)3SDA SDI SDO I 2C serial data (SDA)SPI serial data input (SDI)3-wire interface serial data output (SDO)4SDO SA0SPI serial data output (SDO)I 2C less significant bit of the device address (SA0)5CS I 2C/SPI mode selection (1: SPI idle mode / I 2C communication enabled; 0: SPI communication mode / I 2C disabled)6DRDY/INT2Data ready/FIFO interrupt (Watermark/Overrun/Empty)7INT1Programmable interrupt 8Reserved Connect to GND 9Reserved Connect to GND 10Reserved Connect to GND 11Reserved Connect to GND 12Reserved Connect to GND 13GND 0 V supply14Reserved Connect to GND with ceramic capacitor (2)2. 1 nF min value must be guaranteed under 11 V bias condition.15Reserved Connect to Vdd 16Vdd (3)3.100 nF plus 10 µF capacitors recommended.Power supply2 Mechanical and electrical specifications2.1 Mechanicalcharacteristics@ Vdd = 3.0 V, T = 25 °C unless otherwise noted.Table 3.Mechanical characteristics(1)Symbol Parameter Test condition Min. Typ.(2)Max.UnitFS Measurement range User-selectable±250dps ±500±2000So Sensitivity FS = 250 dps8.75mdps/digit FS = 500 dps17.50FS = 2000 dps70SoDr Sensitivity change vs.temperatureFrom -40 °C to +85 °C±2%DVoff Digital zero-rate level FS = 250 dps±10dps FS = 500 dps±15FS = 2000 dps±75OffDr Zero-rate level changevs. temperatureFS = 250 dps±0.03dps/°CFS = 2000 dps±0.04dps/°CNL Non linearity Best fit straight line0.2% FS Rn Rate noise density0.03ODR Digital output data rate 95/190/380/760HzTop Operating temperaturerange-40+85°C1.The product is factory calibrated at 3.0 V. The operational power supply range is specified in Table4.2.Typical specifications are not guaranteed.dps Hz(⁄Doc ID 022116 Rev 19/4410/44Doc ID 022116 Rev 12.2 Electrical characteristics@ Vdd =3.0 V , T=25 °C unless otherwise noted.2.3 Temperature sensor characteristics@ Vdd =3.0 V , T=25 °C unless otherwise noted.Table 4.Electrical characteristics (1)Symbol ParameterTest conditionMin.Typ.(2)Max.Unit Vdd Supply voltage2.43.03.6V Vdd_IO I/O pins supply voltage (3) 1.71Vdd+0.1V Idd Supply current 6.1mA IddSL Supply currentin sleep mode (4)Selectable by digital interface2mA IddPdn Supply current in power-down mode Selectable by digital interface5µA VIH Digital high level input voltage0.8*Vdd_IOV VIL Digital low level input voltage0.2*Vdd_IO V T opOperating temperature range-40+85°C1.The product is factory calibrated at 3.0 V.2.Typical specifications are not guaranteed.3.It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses; in this condition themeasurement chain is powered off.4.Sleep mode introduces a faster turn-on time relative to power-down mode.Table 5.Electrical characteristics (1)Symbol ParameterTest conditionMin.Typ.(2)Max.Unit TSDr T emperature sensor output change vs. temperature--1°C/digit TODR T emperature refresh rate 1Hz T opOperating temperature range-40+85°C1.The product is factory calibrated at 3.0 V.2.Typical specifications are not guaranteed.分销商库存信息:STML3GD20TR L3GD20。

0191150022;中文规格书,Datasheet资料

This document was generated on 08/31/2012PLEASE CHECK FOR LATEST PART INFORMATIONPart Number:19115-0022Status:ActiveOverview:Ring Tongue - Spade TerminalsDescription:Avikrimp™ Snap Spade Terminal for 14-16 AWG WireDocuments:Drawing (PDF)Product Specification PS-19902-013 (PDF)Product Specification PS-19902-011 (PDF)RoHS Certificate of Compliance (PDF)Agency CertificationCSA LR18689ULE32244GeneralProduct Family Ring and Spade Terminals Series19115Crimp Quality Equipment Yes Mil-Spec N/AOverviewRing Tongue - Spade Terminals Product Name Avikrimp™Type Spade Snap UPC800753092082PhysicalBarrel Type Closed Flammability 94V-2InsulationNylon (PA)Material - Plating Mating Tin Net Weight0.904/g Packaging Type BagPlating min - Mating4.064µm Plating min - Termination 4.064µm Stud Size5 (M3)Wire Insulation Diameter 4.30mm max.Wire Size AWG14, 16Material InfoOld Part NumberBB-8707-05Reference - Drawing NumbersProduct Specification PS-19902-011, PS-19902-013Sales DrawingBBCD80502Seriesimage - Reference onlyEU RoHSChina RoHSELV and RoHS Compliant REACH SVHCContains SVHC: No Low-Halogen Status Not ReviewedNeed more information on product environmental compliance?Email productcompliance@For a multiple part number RoHS Certificate of Compliance, click herePlease visit the Contact Us section for any non-product compliance questions.Search Parts in this Series 19115SeriesApplication Tooling | FAQTooling specifications and manuals are found by selecting the products below.Crimp Height Specifications are then contained in the Application Tooling Specification document.GlobalDescription Product #PremiumGrade™Hand Crimp Tool0640010100Crimp Head for the AT-200™ Pneumatic Hand Tool0640050100This document was generated on 08/31/2012PLEASE CHECK FOR LATEST PART INFORMATION/分销商库存信息: MOLEX 0191150022。

0192210399;中文规格书,Datasheet资料

This document was generated on 08/09/2012PLEASE CHECK FOR LATEST PART INFORMATIONPart Number:19221-0399Status:ActiveOverview:Battery Cable LugsDescription:Compression Style Ring Tongue Terminal for 2 AWG Wire, Stud Size 1/2" (M12), Un-Plated, Wide PadDocuments:Drawing (PDF)Product Specification PS-19902-013 (PDF)Product Specification PS-19902-011 (PDF)RoHS Certificate of Compliance (PDF)Agency CertificationCSA LR18689ULE32244GeneralProduct Family Ring and Spade Terminals Series19221CommentsHeavy Duty Crimp Quality Equipment Yes Mil-Spec N/AOverviewBattery Cable Lugs Product Name Battery Cable Lug Type RingUPC800753064836PhysicalBarrel Type Closed InsulationNone Material - Plating Mating TinNet Weight14.116/g Packaging Type BagStud Size1/2" (M12)Termination Interface: Style Crimp or Compression Wire Insulation Diameter N/A Wire Size AWG 2Wire Size mm²26.60 - 42.40Material InfoOld Part NumberBCL-212-WPReference - Drawing NumbersProduct Specification PS-19902-011, PS-19902-013Sales DrawingSD-19221-010Seriesimage - Reference onlyEU RoHSChina RoHSELV and RoHS Compliant REACH SVHCContains SVHC: No Low-Halogen Status Low-HalogenNeed more information on product environmental compliance?Email productcompliance@For a multiple part number RoHS Certificate of Compliance, click herePlease visit the Contact Us section for any non-product compliance questions.Search Parts in this Series 19221SeriesApplication Tooling | FAQTooling specifications and manuals are found by selecting the products below.Crimp Height Specifications are then contained in the Application Tooling Specification document.GlobalDescription Product #Hand Crimp Tool 0192840034Putt Pump Dieless Head System0192860065Manual Putt Pump Hydraulic System,Die set required 0192860117Die Set (large) for the HHLS Hydraulic Crimper0192900010Manual tool for Crimping non-insulated 8AWG thru 4/0 Terminals0192940008This document was generated on 08/09/2012PLEASE CHECK FOR LATEST PART INFORMATION分销商库存信息: MOLEX 0192210399。

AS5045-ASST;AS5045-ASSU;AS5045 PB;AS5045 DB V2;AS5045 AB;中文规格书,Datasheet资料

1 General DescriptionThe AS5045 is a contactless magnetic rotary encoder for accurate angular measurement over a full turn of 360°. It is a system-on-chip, combining integrated Hall elements, analog front end and digital signal processing in a single device.To measure the angle, only a simple two-pole magnet, rotating over the center of the chip, is required. The magnet may be placed above or below the IC.The absolute angle measurement provides instant indication of the magnet’s angular position with a resolution of 0.0879° = 4096 positions per revolution. This digital data is available as a serial bit stream and as a PWM signal.An internal voltage regulator allows the AS5045 to operate at either 3.3 V or 5 V supplies.2 BenefitsComplete system-on-chipFlexible system solution provides absolute andPWM outputs simultaneously Ideal for applications in harsh environments due tocontactless position sensing No calibration required3 Key FeaturesContactless high resolution rotational positionencoding over a full turn of 360 degrees Two digital 12bit absolute outputs:- Serial interface and- Pulse width modulated (PWM) output User programmable zero positionFailure detection mode for magnet placementmonitoring and loss of power supply “red-yellow-green” indicators display placement ofmagnet in Z-axis Serial read-out of multiple interconnected AS5045devices using Daisy Chain mode Tolerant to magnet misalignment and airgapvariations Wide temperature range: - 40°C to + 125°CSmall Pb-free package: SSOP 16 (5.3mm x 6.2mm)4 ApplicationsIndustrial applications:- Contactless rotary position sensing - Robotics Automotive applications:- Steering wheel position sensing - Transmission gearbox encoder - Headlight position control - Torque sensing- Valve position sensing Replacement of high end potentiometersFigure 1. Typical Arrangement of AS5045 and MagnetAS504512 Bit Programmable Magnetic Rotary Encoder Data SheetTable of Contents1General Description (1)2Benefits (1)3Key Features (1)4Applications (1)5Pinout (4)5.1Pin Configuration (4)5.2Pin Description (4)6Electrical Characteristics (5)6.1AS5045 Differences to AS5040 (5)6.2Absolute Maximum Ratings (non operating) (6)6.3Operating Conditions (6)6.4DC Characteristics for Digital Inputs and Outputs (7)6.4.1CMOS Schmitt-Trigger Inputs: CLK, CSn. (CSn = internal Pull-up) (7)6.4.2CMOS / Program Input: Prog (7)6.4.3CMOS Output Open Drain: MagINCn, MagDECn (7)6.4.4CMOS Output: PWM (7)6.4.5Tristate CMOS Output: DO (8)6.5Magnetic Input Specification (8)6.6Electrical System Specifications (9)6.7Timing Characteristics (10)6.7.1Synchronous Serial Interface (SSI) (10)6.7.2Pulse Width Modulation Output (11)6.8Programming Conditions (11)7Functional Description (12)8Mode Input Pin (13)8.1Synchronous Serial Interface (SSI) (13)8.1.1Data Content (14)8.1.2Z-axis Range Indication (Push Button Feature, Red/Yellow/Green Indicator) (14)8.2Daisy Chain Mode (15)9Pulse Width Modulation (PWM) Output (16)9.1Changing the PWM Frequency (17)10Analog Output (17)11Programming the AS5045 (18)11.1Zero Position Programming (18)11.2Repeated OTP Programming (18)11.3Non-permanent Programming (19)11.4Analog Readback Mode (20)12Alignment Mode (21)13 3.3V / 5V Operation (22)14Choosing the Proper Magnet (23)14.1Physical Placement of the Magnet (24)15Simulation Modeling (25)16Failure Diagnostics (26)16.1Magnetic Field Strength Diagnosis (26)16.2Power Supply Failure Detection (26)17Angular Output Tolerances (26)17.1Accuracy (26)17.2Transition Noise (28)17.3High Speed Operation (28)17.3.1Sampling Rate (28)17.4Propagation Delays (29)17.4.1Angular Error Caused by Propagation Delay (29)17.5Internal Timing Tolerance (29)17.6Temperature (30)17.6.1Magnetic Temperature Coefficient (30)17.7Accuracy over Temperature (30)17.7.1Timing Tolerance over Temperature (30)18Package Drawings and Markings (31)19Ordering Information (31)20Recommended PCB Footprint (32)5 Pinout5.1 Pin ConfigurationFigure 2. Pin Configuration SSOP165.2 Pin DescriptionTable 1 shows the description of each pin of the standard SSOP16 package (Shrink Small Outline Package, 16 leads, body size: 5.3mm x 6.2mmm; see Figure 2).Pins 7, 15 and 16 supply pins, pins 3, 4, 5, 6, 13 and 14 are for internal use and must not be connected.Pins 1 and 2 MagINCn and MagDECn are the magnetic field change indicators (magnetic field strength increase or decrease through variation of the distance between the magnet and the device). These outputs can be used to detect the valid magnetic field range. Furthermore those indicators can also be used for contact-less push-button functionality.Pin 6 Mode allows switching between filtered (slow) and unfiltered (fast mode). This pin must be tied to VSS or VDD5V, and must not be switched after power up. See chapter 8 Mode Input Pin.Pin 8 Prog is used to program the zero-position into the OTP (see chapter 11.1 Zero Position Programming).This pin is also used as digital input to shift serial data through the device in Daisy Chain configuration, (see chapter 8.2 Daisy Chain Mode).Pin 11 Chip Select (CSn; active low) selects a device within a network of AS5045 encoders and initiates serial data transfer. A logic high at CSn puts the data output pin (DO) to tri-state and terminates serial data transfer. This pin is also used for alignment mode (Figure 14) and programming mode (Figure 10).Pin 12 PWM allows a single wire output of the 10-bit absolute position value. The value is encoded into a pulse width modulated signal with 1µs pulse width per step (1µs to 4096µs over a full turn). By using an external low pass filter, the digital PWM signal is converted into an analog voltage, making a direct replacement of potentiometers possible.Table 1. Pin DescriptionPin Symbol Type Description1MagINCn DO_OD Magnet Field Mag nitude INC rease; active low, indicates a distance reduction between the magnet and the device surface. See Table 52MagDECn DO_OD Magnet Field Mag nitude DEC rease; active low, indicates a distance increase between the device and the magnet. See Table 53 NC - Must be left unconnected4 NC - Must be left unconnectedPin Symbol Type Description 5 NC - Must be left unconnected6Mode - Select between slow (low, VSS) and fast (high, VDD5V) mode. Internal pull-down resistor.7 VSS S Negative Supply Voltage (GND)8Prog_DI DI_PD OTP Prog ramming Input and Data Input for Daisy Chain mode. Internal pull-down resistor (~74kΩ). Connect to VSS if not used9 DO DO_TD ata O utput of Synchronous Serial Interface10 CLK DI,ST Cl oc k Input of Synchronous Serial Interface; Schmitt-Trigger input11 CSn DI_PU,STC hip S elect, active low; Schmitt-Trigger input, internal pull-up resistor (~50kΩ)12 PWM DO P ulse W idth M odulation of approx. 244Hz; 1µs/step (opt. 122Hz; 2µs/step)13 NC - Must be left unconnected14 NC - Must be left unconnected15VDD3V3 S 3V-Regulator Output, internally regulated from VDD5V. Connect to VDD5V for 3V supply voltage. Do not load externally.16 VDD5V S Positive Supply Voltage, 3.0 to 5.5 VDO_OD digital output open drain S supply pinDO digital output DI digital inputDI_PD digital input pull-down DO_T digital output /tri-stateDI_PU digital input pull-up ST Schmitt-Trigger input6 Electrical Characteristics6.1 AS5045 Differences to AS5040All parameters are according to AS5040 datasheet except for the parameters shown below: Building Block AS5045 AS5040Resolution 12bits, 0.088°/step. 10bit, 0.35°/stepData length Read: 18bits(12bits data + 6 bits status)OTP write: 18 bits(12bits zero position + 6 bits mode selection) Read: 16bits(10bits data + 6 bits status)OTP write: 16 bits(10bits zero position + 6 bits mode selection)Incremental encoder Not usedPin 3: not usedPin 4:not usedQuadrature, step/direction and BLDC motorcommutation modesPin 3:incremental output A_LSB_UPin 4:incremental output B_DIR_VPins 1 and 2 MagINCn, MagDECn: same feature asAS5040, additional OTP option for red-yellow-green magnetic range MagINCn, MagDECn indicate in-range or out-of-range magnetic field plus movement of magnet in z-axisPin 6 MODE pin, switch between fast and slowmodePin 6:Index outputPin 12 PWM output: frequency selectable by OTP:1µs / step, 4096 steps per revolution,f=244Hz 2µs/ step, 4096 steps perrevolution, f=122Hz PWM output:1µs / step, 1024 steps per revolution, 976Hz PWM frequencySampling frequency Selectable by MODE input pin:2.5kHz, 10kHzFixed at 10kHz @10bit resolutionBuilding Block AS5045AS5040 Propagation delay 384µs (slow mode) 96µs (fast mode)48µs Transition noise (rms; 1sigma) 0.03 degrees max. (slow mode) 0.06 degrees max. (fast mode)0.12 degreesOTP programming options Zero position, rotational direction, PWMdisable, 2 Magnetic Field indicator modes, 2 PWM frequenciesZero position, rotational direction, incremental modes, index bit width6.2 Absolute Maximum Ratings (non operating)Stresses beyond those listed under “Absolute Maximum Ratings“ may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under “Operating Conditions” is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ParameterSymbol Min Max Unit Note DC supply voltage at pin VDD5V VDD5V -0.3 7 V DC supply voltage at pin VDD3V3 VDD3V35VInput pin voltageV in -0.3VDD5V+0.3 V Except VDD3V3 Input current (latchup immunity) I scr -100 100 mA Norm: JEDEC 78Electrostatic discharge ESD ± 2 kV Norm: MIL 883 E method 3015 Storage temperature T strg-55125°CMin – 67°F ; Max +257°FBody temperature (Lead-free package)T Body 260°C t=20 to 40s,Norm: IPC/JEDEC J-Std-020 Lead finish 100% Sn “matte tin” Humidity non-condensing H585%6.3 Operating ConditionsParameterSymbol Min Typ Max UnitNoteAmbient temperature T amb -40125 °C -40°F…+257°FSupply currentI supp 1621 mA Supply voltage at pin VDD5V Voltage regulator output voltage at pin VDD3V3VDD5V VDD3V3 4.53.0 5.03.3 5.5 3.6 V 5V operationSupply voltage at pin VDD5V Supply voltage at pin VDD3V3 VDD5V VDD3V33.03.03.33.33.6 3.6V3.3V operation(pin VDD5V and VDD3V3 connected)6.4 DC Characteristics for Digital Inputs and Outputs6.4.1 CMOS Schmitt-Trigger Inputs: CLK, CSn. (CSn = internal Pull-up)(operating conditions: T amb = -40 to +125°C, VDD5V = 3.0-3.6V (3V operation) VDD5V = 4.5-5.5V (5V operation) unless otherwise noted) ParameterSymbol Min Max Unit NoteHigh level input voltage V IH 0.7 * VDD5VV Normal operation Low level input voltage V IL0.3 * VDD5VVSchmitt Trigger hysteresis V Ion- V Ioff 1V-1 1 CLK only Input leakage current Pull-up low level input current I LEAK I iL-30 -100µA µA CSn only, VDD5V: 5.0V6.4.2 CMOS / Program Input: Prog(operating conditions: T amb = -40 to +125°C, VDD5V = 3.0-3.6V (3V operation) VDD5V = 4.5-5.5V (5V operation)unless otherwise noted) ParameterSymbol Min Max Unit Note High level input voltage VIH 0.7 * VDD5VVDD5VVHigh level input voltage VPROG See Programming ConditionsV During programming Low level input voltage VIL 0.3 * VDD5VVHigh level input current IiL30100µAVDD5V: 5.5V6.4.3 CMOS Output Open Drain: MagINCn, MagDECn(operating conditions: T amb = -40 to +125°C, VDD5V = 3.0-3.6V (3V operation) VDD5V = 4.5-5.5V (5V operation)unless otherwise noted) ParameterSymbolMinMax UnitNote Low level output voltage V OL VSS+0.4 V Output currentI O4 2mAVDD5V: 4.5V VDD5V: 3VOpen drain leakage current I OZ 1 µA6.4.4 CMOS Output: PWM(operating conditions: T amb = -40 to +125°C, VDD5V = 3.0-3.6V (3V operation) VDD5V = 4.5-5.5V (5V operation)unless otherwise noted) ParameterSymbolMinMax UnitNoteHigh level output voltage V OH VDD5V-0.5 V Low level output voltage V OL VSS+0.4 V Output current I O4 2mA mAVDD5V: 4.5V VDD5V: 3V6.4.5 Tristate CMOS Output: DO(operating conditions: T amb = -40 to +125°C, VDD5V = 3.0-3.6V (3V operation) VDD5V = 4.5-5.5V (5V operation) unless otherwise noted) ParameterSymbolMinMax UnitNoteHigh level output voltage V OH VDD5V –0.5VLow level output voltage V OL VSS+0.4 VOutput currentI O4 2mAmAVDD5V: 4.5V VDD5V: 3VTri-state leakage current I OZ 1 µA6.5 Magnetic Input Specification(operating conditions: T amb = -40 to +125°C, VDD5V = 3.0-3.6V (3V operation) VDD5V = 4.5-5.5V (5V operation)unless otherwise noted)Two-pole cylindrical diametrically magnetised source: ParameterSymbolMinTypMaxUnitNoteDiameter d mag 4 6 mm Thickness t mag 2.5 mm Recommended magnet: Ø 6mm x 2.5mm forcylindrical magnets Magnetic input fieldamplitude B pk 4575 mTRequired vertical component of the magnetic field strength on the die’s surface, measured along a concentric circle with a radius of 1.1mm Magnetic offset B off ± 10mT Constant magnetic stray field Field non-linearity5 %Including offset gradient2.44146 rpm @ 4096 positions/rev.; fast modeInput frequency (rotational speed of magnet)f mag_abs0.61Hz36.6rpm @ 4096 positions/rev.; slow mode Displacement radiusDisp0.25mmMax. offset between defined device center and magnet axis (see Figure 18) Eccentricity Ecc 100µm Eccentricity of magnet center to rotational axis-0.12NdFeB (Neodymium Iron Boron) Recommended magnetmaterial andtemperature drift -0.035%/KSmCo (Samarium Cobalt)6.6 Electrical System Specifications(operating conditions: T amb = -40 to +125°C, VDD5V = 3.0~3.6V (3V operation) VDD5V = 4.5~5.5V (5V operation) unless otherwise noted) ParameterSymbolMinTypMaxUnitNoteResolution RES 12 bit 0.088 deg Integral non-linearity (optimum)INL opt± 0.5 deg Maximum error with respect to the best line fit. Centered magnet without calibration, T amb =25 °C. Integral non-linearity (optimum)INL temp± 0.9 degMaximum error with respect to the best line fit. Centered magnetwithout calibration, T amb = -40 to +125°CIntegral non-linearity INL ± 1.4 degBest line fit =(Err max – Err min ) / 2Over displacement tolerance with 6mm diameter magnet, without calibration,T amb = -40 to +125°C Differential non-linearity DNL ±0.044 deg 12bit, no missing codes 0.06 1 sigma, fast mode (MODE = 1)Transition noiseTN0.03deg RMS1 sigma, slow mode (MODE=0 or open)Power-on reset thresholds On voltage; 300mV typ. hysteresisOff voltage; 300mV typ. hysteresisV on V off 1.37 1.08 2.2 1.9 2.9 2.6VDC supply voltage 3.3V (VDD3V3)DC supply voltage 3.3V (VDD3V3)20Fast mode (Mode = 1); until status bit OCF = 1Power-up timet PwrUp80msSlow mode (Mode = 0 or open); until OCF = 196Fast mode (MODE=1)System propagation delay absolute output : delay of ADC, DSP and absolute interfacet delay384µsSlow mode (MODE=0 or open) 2.48 2.61 2.74T amb = 25°C, slow mode (MODE=0 or open)Internal sampling rate for absolute output:f S2.35 2.61 2.87 kHzT amb = -40 to +125°C, slow mode (MODE=0 or open) 9.90 10.42 10.94T amb = 25°C, fast mode (MODE = 1)Internal sampling rate forabsolute outputf S9.38 10.42 11.46kHz T amb = -40 to +125°C, : fast mode (MODE = 1)Read-out frequency CLK1MHz Max. clock frequency to read out serial dataFigure 3. Integral and Differential Non-linearity (example)Integral Non-Linearity (INL) is the maximum deviation between actual position and indicated position. Differential Non-Linearity (DNL) is the maximum deviation of the step length from one position to the next. Transition Noise (TN) is the repeatability of an indicated position6.7 Timing Characteristics6.7.1Synchronous Serial Interface (SSI)(operating conditions: T amb = -40 to +125°C, VDD5V = 3.0~3.6V (3V operation) VDD5V = 4.5~5.5V (5V operation) unless otherwise noted) ParameterSymbol MinTypMaxUnitNoteData output activated (logic high)t DO active 100 nsTime between falling edge of CSn and dataoutput activated First data shifted to output registert CLK FE500 nsTime between falling edge of CSn and firstfalling edge of CLKStart of data output T CLK / 2 500nsRising edge of CLK shifts out one bit at a timeData output valid t DO valid357 375 394 nsTime between rising edge of CLK and dataoutput validData output tristate t DO tristate100 nsAfter the last bit DO changes back to“tristate”Pulse width of CSn t CSn 500ns CSn = high; To initiate read-out of next angular position Read-out frequencyf CLK>01MHzClock frequency to read out serial data分销商库存信息:AMSAS5045-ASST AS5045-ASSU AS5045 PB AS5045 DB V2AS5045 AB。

VN5E160S-E;VN5E160STR-E;中文规格书,Datasheet资料

February 2008Rev 21/34VN5E160S-ESingle channel high side driver for automotive applicationsFeatures■General–Inrush current active management by power limitation–Very low stand-by current– 3.0V CMOS compatible inputs–Optimized electromagnetic emissions –Very low electromagnetic susceptibility –In compliance with the 2002/95/EC european directive ■Diagnostic functions–Open Drain status output –On-state open load detection –Off-state open load detection –Output short to V CC detection–Overload and short to ground (power limitation) indication–Thermal shutdown indication■Protections–Undervoltage shutdown –Overvoltage clamp –Load current limitation–Self limiting of fast thermal transients–Protection against loss of ground and loss of V CC–Over-temperature shutdown with autorestart (thermal shutdown)–Reverse battery protected (a)–Electrostatic discharge protectionApplication■All types of resistive, inductive and capacitive loadsDescriptionThe VN5E160S-E is a single channel high-side driver manufactured in the ST proprietaryVIPower M0-5 technology and housed in the tiny SO-8 package.The VN5E160S-E is designed to drive automotive grounded loads delivering protection, diagnostics and easy 3V and 5V CMOS-compatible interface with any microcontroller.The device integrates advanced protectivefunctions such as load current limitation, inrush and overload active management by power limitation, over-temperature shut-off with auto-restart and over-voltage active clamp.A dedicated active low digital status pin isassociated with every output channel in order to provide Enhanced diagnostic functions including fast detection of overload and short-circuit to ground, over-temperature indication, short-circuit to V CC diagnosis and ON & OFF state open-load detection.The diagnostic feedback of the whole device can be disabled by pulling the STAT_DIS pin up, thus allowing wired-ORing with other similar devices.Max transient supply voltage V CC41VOperating voltage rangeV CC 4.5 to 28V Max On-state resistance (per ch.)R ON 160 m ΩCurrent limitation (typ)I LIMH 10A Off state supply currentI S2 µA (1)1.Typical value with all loads connected. a.See Figure 32: Application schematic .Contents VN5E160S-EContents1Block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.1Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.2Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.3Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152.4Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.1GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 223.1.1Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 223.1.2Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 233.2Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233.3MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233.4Open load detection in Off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243.5Maximum demagnetization energy (VCC=13.5V) . . . . . . . . . . . . . . . . . 254Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264.1SO-8 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295.1ECOP ACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295.2Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295.3Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332/34VN5E160S-E List of tables List of tablesTable 1.Pin function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 2.Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3.Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 4.Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 5.Power section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 6.Switching (VCC=13V; Tj=25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 7.Status pin (V SD=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 8.Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 9.Open load detection (8V<V CC<18V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 10.Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 11.Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 12.Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 13.Thermal parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 14.SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 15.Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 16.Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333/34List of figures VN5E160S-E List of figuresFigure 1.Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2.Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3.Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4.Status timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5.Output voltage drop limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6.Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 7.Normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 8.Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 9.Overload or Short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 10.Intermittent Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 11.Open Load with external pull-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 12.Open Load without external pull-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 13.Short to V CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 14.T J evolution in Overload or Short to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 15.Off state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 16.High level input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 17.Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 18.Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 19.Input low level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 20.Low level STAT_DIS current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 21.On state resistance vs T case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 22.High level STAT_DIS current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 23.On state resistance vs V CC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 24.Low level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 25.I LIM vs T case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 26.Turn-On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 27.Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 28.Turn-Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 29.STAT_DIS clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 30.High level STAT_DIS voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 31.Low level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 32.Application schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 33.Open load detection in Off state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 34.Maximum turn-Off current versus inductance (for each channel). . . . . . . . . . . . . . . . . . . . 25 Figure 35.SO-8 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 36.Rthj-amb Vs. PCB copper area in open box free air condition. . . . . . . . . . . . . . . . . . . . . . 26 Figure 37.SO-8 thermal impedance junction ambient single pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 38.Thermal fitting model of a single channel HSD in SO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 39.SO-8 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 40.SO-8 tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 41.SO-8 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4/34VN5E160S-E Block diagram and pin configuration5/341 Block diagram and pin configurationTable 1.Pin functionName FunctionV CCBattery connection.OUTPUT Power output.GND Ground connection. Must be reverse battery protected by an external diode/resistor network.INPUT Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state.STA TUS Open Drain digital diagnostic pin.ST A T_DISActive high CMOS compatible pin, to disable the ST A TUS pin.Block diagram and pin configuration VN5E160S-E6/34Figure 2.Configuration diagram (top view)Table 2.Suggested connections for unused and not connected pins Connection / pin Status N.C.Output Input STAT_DIS Floating X X X X XT o groundNotallowedXNotallowedThrough 10KΩresistorThrough 10KΩresistorV CCV CCOUTPUTOUTPUTSTAT_DISGNDSTATUSINPUT14586723SO-8VN5E160S-E Electrical specifications7/342 Electrical specificationsNote:V F = V OUT - V CC during reverse battery condition.2.1 Absolute maximum ratingsStressing the device above the ratings listed in the “Absolute maximum ratings” tables maycause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions in the “Absolute maximum ratings” tables for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and others relevant quality documents.Table 3.Absolute maximum ratingsSymbol ParameterValue Unit V CC DC supply voltage 41V - V CC Reverse DC supply voltage 0.3V - I GND DC reverse ground pin current 200mA I OUT DC output currentInternally limitedA - I OUT Reverse DC output current 6A I IN DC input current +10 / -1mA I STATDC status current+10 / -1mA I STAT_DIS DC status disable current +10 / -1mA E MAXMaximum switching energy (single pulse)(L=8 mH; R L =0Ω; V bat =13.5V; T jstart =150ºC; I OUT = I limL (Typ.) )36mJElectrical specifications VN5E160S-E8/34Symbol Parameter Value Unit V ESDElectrostatic discharge (Human body model: R=1.5KΩ;C=100pF)–INPUT–ST A TUS–ST A T_DIS–OUTPUT–V CC40004000400050005000VVVVV V ESD Charge device model (CDM-AEC-Q100-011)750V T j Junction operating temperature-40 to 150°C T stg Storage temperature- 55 to 150°CTable 4.Thermal dataSymbol Parameter Max. value Unit R thj-pins Thermal resistance junction-pins30°C/W R thj-amb Thermal resistance junction-ambient See Figure 36.°C/W Table 3.Absolute maximum ratings (continued)VN5E160S-E Electrical specifications9/342.2 Electrical characteristicsValues specified in this section are for 8V<V CC <28V; -40°C< Tj <150°C, unless otherwisestated.Table 5.Power sectionSymbol ParameterTest conditionsMin.Typ.Max.Unit V CC Operating supply voltage 4.51328V V USD Undervoltage shutdown 3.5 4.5V V USDhystUndervoltage shutdown hysteresis0.5V R ON On state resistance I OUT =1A; T j =25°C I OUT =1A; T j =150°CI OUT =1A; V CC =5V; T j =25°C 160320210m Ωm Ωm ΩV clampClamp voltageI S =20 mA414652V I SSupply currentOff State; V CC =13V; V IN =V OUT =0V; T j =25°COn State; V IN =5V; V CC =13V; I OUT =0A2(1)1.91.PowerMOS leakage included.5(1)3.5µA mA I L(off1)Off state output current V IN =V OUT =0V; V CC =13V; T j =25°C V IN =V OUT =0V; V CC =13V; T j =125°C 000.0135µA µA V FOutput - V CC diode voltage-I OUT =0.6A; T j =150°C0.7VTable 6.Switching (V CC =13V;T j =25°C)Symbol Parameter Test conditions Min.Typ.Max.Unit t d(on)T urn-On delay time R L =13Ω (see Figure 6.)10µs t d(off)T urn-Off delay timeR L =13Ω (see Figure 6.)15µs dV OUT /dt (on)T urn-On voltage slope R L =13Ω See Figure 26.V/µs dV OUT /dt (off)T urn-Off voltage slopeR L =13Ω See Figure 28.V/µs W ON Switching energy losses during t wonR L =13Ω (see Figure 6.)70µJ W OFFSwitching energy losses during t woffR L =13Ω (see Figure 6.)40µJElectrical specifications VN5E160S-E10/34Table 7.Status pin (V SD=0)Symbol Parameter Test conditions Min.Typ.Max.Unit V STA TStatus low outputvoltageI STA T= 1.6 mA, V SD=0V0.5VI LSTA T Status leakage currentNormal operation or V SD=5V,V STAT= 5V10µAC STA TStatus pin inputcapacitanceNormal operation or V SD=5V,V STAT= 5V100pF V SCL Status clamp voltageI STA T= 1mAI STA T= - 1mA5.5-0.77VV Table 8.Protection (1)1.To ensure long term reliability under heavy overload or short circuit conditions, protection and relateddiagnostic signals must be used together with a proper software strategy. If the device is subjected toabnormal conditions, this software must limit the duration and number of activation cycles.Symbol Parameter Test conditions Min.Typ.Max.UnitI limHDC short circuitcurrentV CC=13V; 5V<V CC<28V7101414AAI limLShort circuit currentduring thermal cyclingV CC=13V; T R<T j<T TSD 2.5A T TSDShutdowntemperature150175200°C T R Reset temperature T RS + 1T RS + 5°C T RSThermal reset ofSTA TUS135°C T HYSTThermal hysteresis(T TSD-T R)7°C t SDLStatus delay inoverload conditionsT j>T TSD (see Figure4)20µs V DEMAGT urn-off output voltageclampI OUT=1A; V IN=0; L=20mH V CC-41V CC-46V CC-52VV ONOutput voltage droplimitationI OUT=0.03A (see Figure 5.)T j= -40°C...+150°C25mV分销商库存信息:STMVN5E160S-E VN5E160STR-E。

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Assy Proc: Hooks Cut: Housing No: Terminal No: Dim C: Plating: Packaging: Voids: Material No
22-14-2024 22-14-2034 22-14-2044 22-14-2054 22-14-2064 22-14-2074 22-14-2084 22-14-2094 22-14-2104 22-14-2114 22-14-2124 22-14-2134 22-14-2144 22-14-2154 22-14-2164 22-14-2174 22-14-2184 22-14-2194 22-14-2204 22-14-2214 22-14-2224 22-14-2234 22-14-2244 22-14-2254
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RIGHT ANGLE NO 4455-N 4316-4(P909) 3.35 / .132 P909 PK-44646-001 NONE Engineer Number A-4455-AZ02A(P909) A-4455-AZ03A(P909) A-4455-AZ04A(P909) A-4455-AZ05A(P909) A-4455-AZ06A(P909) A-4455-AZ07A(P909) A-4455-AZ08A(P909) A-4455-AZ09A(P909) A-4455-AZ10A(P909) A-4455-AZ11A(P909) A-4455-AZ12A(P909) A-4455-AZ13A(P909) A-4455-AZ14A(P909) A-4455-AZ15A(P909) A-4455-AZ16A(P909) A-4455-AZ17A(P909) A-4455-AZ18A(P909) A-4455-AZ19A(P909) A-4455-AZ20A(P909) A-4455-AZ21A(P909) A-4455-AZ22A(P909) A-4455-AZ23A(P909) A-4455-AZ24A(P909) A-4455-AZ25A(P909)
Assy Proc: Hooks Cut: Housing No: Terminal No: Dim C: Plating: Packaging: Voids: Ckts 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Material No 22-15-2026 22-15-2036 22-15-2046 22-15-2056 22-15-2066 22-15-2076 22-15-2086 22-15-2096 22-15-2106 22-15-2116 22-15-2126 22-15-2136 22-15-2146 22-15-2156 22-15-2166 22-15-2176 22-15-2186 22-15-2196 22-15-2206 22-15-2216 22-15-2226 22-15-2236 22-15-2246 22-15-2256
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KK 100 PCB ASSY 2-25 CKT
4455 SERIES
A-4455- *
ASSY PROCEDURE A=RIGHT ANGLE B=BOTTOM ENTRY C=TOP ENTRY
STANDARD PRODUCT
*
N
*
*-*
HOUSING TYPE A=4455-AN B=4455-BN E=4455-NHH H=4455-N2 P=4455-NR (HOOKS CUT OFF) R=4455-NR W=4455-N-2 (HOOKS CUT OFF) Y=4455-N (HOOKS CUT OFF) Z=4455-N NO OF CIRCUITS TERMINAL TYPE Code A B C D F G J L M T Number 4316-4 6516-4 6516-5C 4316-3B 6516-6C 4316-3 6516-3B 6516-3C 6516-4A 4316-4A Material Brass Phos Bronze Phos Bronze Brass Phos Bronze Brass Phos Bronze Phos Bronze Phos Bronze Brass Form Standard Standard Cat Ear / V Std / V Cat Ear / V Standard Std / V Cat Ear / V Cat Ear Cat Ear VOID LOCATION NUMBER = CIRCUIT VOIDED MULTIPLE VOIDS START WITH 51 BLANK = NONE
PLATING (SEE SHEET 1)
REV:
ECR/ECN INFORMATION:
EC No.: DATE:
TITLE:
D9
UCP2013-0145 8/30/2012
CREATED / REVISED BY:
KK 100 PCB ASSY 4455 SERIES DWG
CHECKED BY:
Assy Proc: Hooks Cut: Housing No: Terminal No: Dim C: Plating: Packaging: Voids: Material No 22-16-2021 22-16-2031 22-16-2041 22-16-2051 22-16-2061 22-16-2071 22-16-2081 22-16-2091 22-16-2101 22-16-2111 22-16-2121 22-16-2131 22-16-2141 22-16-2151 22-16-2161 22-16-2171 22-16-2181 22-16-2191 22-16-2201 22-16-2211 22-16-2221 22-16-2231 22-16-2241 22-16-2251
Assy Proc: Hooks Cut: Housing No: Terminal No: Dim C: Plating: Packaging: Voids: Material No
22-17-2022 22-17-2032 22-17-2042 22-17-2052 22-17-2062 22-17-2072 22-17-2082 22-17-2092 22-17-2102 22-17-2112 22-17-2122 22-17-2132 22-17-2142 22-17-2152 22-17-2162 22-17-2172 22-17-2182 22-17-2192 22-17-2202 22-17-2212 22-17-2222 22-17-2232 22-17-2242 22-17-2252
RIGHT ANGLE NO 4455-N 4316-4(565) 3.35 / .132 565 PK-44646-001 NONE Engineer Number A-4455-AZ02A(565) A-4455-AZ03A(565) A-4455-AZ04A(565) A-4455-AZ05A(565) A-4455-AZ06A(565) A-4455-AZ07A(565) A-4455-AZ08A(565) A-4455-AZ09A(565) A-4455-AZ10A(565) A-4455-AZ11A(565) A-4455-AZ12A(565) A-4455-AZ13A(565) A-4455-AZ14A(565) A-4455-AZ15A(565) A-4455-AZ16A(565) A-4455-AZ17A(565) A-4455-AZ18A(565) A-4455-AZ19A(565) A-4455-AZ20A(565) A-4455-AZ21A(565) A-4455-AZ22A(565) A-4455-AZ23A(565) A-4455-AZ24A(565) A-4455-AZ25A(565)
4455 SERIES
Assy Proc: Hooks Cut: Housing No: Terminal No: Dim C: Plating: Packaging: Voids: Ckts 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 REV: Material No
STANDARD455-N 4316-4(208) 3.35 / .132 208 PK-44646-001 NONE Engineer Number
A-4455-AZ02A(208) A-4455-AZ 03 A(208) A-4455-AZ 04 A(208) A-4455-AZ 05 A(208) A-4455-AZ 06 A(208) A-4455-AZ 07 A(208) A-4455-AZ 08 A(208) A-4455-AZ 09 A(208) A-4455-AZ 10 A(208) A-4455-AZ 11 A(208) A-4455-AZ 12 A(208) A-4455-AZ 13 A(208) A-4455-AZ 14 A(208) A-4455-AZ 15 A(208) A-4455-AZ 16 A(208) A-4455-AZ 17 A(208) A-4455-AZ 18 A(208) A-4455-AZ 19 A(208) A-4455-AZ 20 A(208) A-4455-AZ 21 A(208) A-4455-AZ 22 A(208) A-4455-AZ 23 A(208) A-4455-AZ 24 A(208) A-4455-AZ 25 A(208)