180纳米逻辑芯片制造流程
合集下载
- 1、下载文档前请自行甄别文档内容的完整性，平台不提供额外的编辑、内容补充、找答案等附加服务。
- 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
- 3、如文档侵犯您的权益，请联系客服反馈,我们会尽快为您处理(人工客服工作时间：9:00-18:30)。
• NLDD1 Photo (116 layer) – Implant: • N Pocket implant (D130K25E3T30R445) • NLDD implant (A003K80E4T00) – NLDD1 Asher & Wet Strip (21+ SPM) PLDD1 Photo (113 layer) – Implant: • P Pocket implant: (A130K30E3T30R445) • PLDD implant (F005K20E4T00) – PLDD1 Asher & Wet Strip (21+ SPM)
To better shallow trench filling
1000RTA020S (1000C, 20sec ,N2)
For damage reduction by HDP and HDP ox densification
5800Å HDP 1625Å Nitride 110Å PAD Oxide
018LG Process Introduction (1P6M)
1
Logic Circuit: 能够 展现 精确的模拟特性， 精确的模拟特性， ASIC: 为了满足消费者特定需求而专门设计的半导体
电路
• SOC与IC组成的系统相比，由于SOC能够综合并全盘考虑整个系统 的各种情况，可以在同样的工艺技术条件下实现更高性能的系统指 标 – 若采用IS方法和0.35µm工艺设计系统芯片，在相同的系统复杂 度和处理速率下，能够相当于采用0.25 ~ 0.18µm工艺制作的IC 所实现的同样系统的性能 – 与采用常规IC方法设计的芯片相比，采用SOC完成同样功能所 需要的晶体管数目可以有数量级的降低
2
VDD
VDD
IN
OUT Y A1 A2
CMOS反相器 反相器
与非门： 与非门：Y=A1A2
3
基本电路结构： 基本电路结构：MOS器件结构 器件结构
基本电路结构： 基本电路结构：CMOS
4
0.18um Process Features
18LG adopt 27 Photo mask , if include ESD layer AA/Poly/CT/ M1~M5/ V1~V5 use DUV scanner (13 layer) “ DARC” Cap on Critical layer and Top M6 Poly & M1~M5 adopt OPC (optical proximity correction) for line-end shorting & island missing Composite Spacer (ONO) PSM method apply on CT layer Cobalt salicide process Low K IMD layer (FSG) 5
6
Wafer Start
• • WAFER START & RS CHECK
P type 8 ~ 12 ohm-cm, non-EPI wafer
Wafer Mark (For Wafer alignment) • Scrubber Clean (TJBB) • Start oxide RM NLH320A (50:1 HF 350 sec) • Meas: Ox RM THK (25~35A) • AA OX Pre-cln
P-VT P-pthru N-Well P-Well
• • • •
12
P-Well and Vt_N adjustment
• • P_Well Photo (191 layer) Implant: • P WELL IMP • N CHANNEL IMP • N_VT IMP PWELL Asher PWELL Wet Strip
As implant screen oxide
110Å SAC Oxide
11
N-Well and Vt_P adjustment
• • N_Well Photo(192 layer) Implant: • N WELL IMP P440K15E3T00 WELL IMP注入的位置最深，用以调节井的浓度防止Latch-up效应。 • P CHANNEL IMP P140K50E2T00 CHANNEL IMP位置较浅，加大LDD之下部位的WELL浓度，使器件工 作时该位置的耗尽层更窄，防止器件PUNCH THROUGH。 VTP IMP A130K90E2T00 VT注入，靠近器件表面，调节器件的开启电压 NWELL Asher Mattson: 21 NWELL Wet Strip SPM only NWELL Anneal Precln MRCAM (SC1+SC2) IMPLANT DAMAGE ANNEAL 1000RTA010S (1000C; 10sec N2(PVD)
ZERO Photo
For ASML stepper system global Wafer alignment
ZERO Fully dry etch
(OX 100A + SI 1200+-200 A)
• Pad oxide
110+-7A/ 920oC dry O2
ZERO Strip
1625Å Nitride 110Å PAD Oxide
STI Pre-CMP THK-PO PAD (3600+-250 A) , SIN (1050+-50) AA NIT RM NLH90AHPO2450A (50:1 HF + H3PO4) THIN OXIDE THK-P PAD ( 82+-17) STI PAD OX RM NLH60A (50:1 HF 65 sec) SAC OX PRECLN NCR1DH100ARCAM (100:1 HF 240sec) SAC OX 110+-7A/ 920oC 45min dry O2
9
AA Reverse
• • • • AAR Photo (121 layer) AAR Etch AAR Asher AAR wet strip AAR= [ (AA-0.4) +0.4) ] -0.2 Stop on SiN Mattson (Rcp: 1) NPRRM (SPM only)
1. Better surface flatness 2. Improved throughput by OX removing
Outline
1. STI/Trench Isolation 2. Well Definition/Vt Adjust 3. Gate Formation 4. N/PMOS Formation 5. Salicide Formation 6. ILD Layer / Contact CT 7. Metal / VIA 8. Top Meta l Via 9. Passivation (BEOL: interconnect) (FEOL: device)
ADI = 0.23+-0.02
•
SiON DEP(CVD)
FE DARC320 (w/I scrubber )
To reduce SIN reflection and improve PR resolution as an ARC wk.baidu.comayer
• • • • •
AA Photo (120 layer) AA Etch (5800A)
NCR1DH75ARCAM
Start OX 100A dry
1. PR isolation 2. Prevent the laser mark Si recast 3. Surface cleanness 4. Backside oxidation & trap the metal ion
• • •
2000A poly
50Å thick gate oxide Final 70 A 32Å thin gate oxide
Thin gate
Thick gate
14
Poly Gate Definition
• • • • • • • • • • POLY DEPOSITION POLY 2000A, 620C SiON DEP FEDARC320 ADI 0.18+-0.015um POLY PHOTO (130layer) AEI 0.18+-0.015um Poly ARC etch + Poly etch GATE Asher Mattson (Rcp: 1) GATE Wet Strip NDH5APRRM (100:1 HF 10sec +SPM) THICK GATE OXIDE THK-P PAD (25+-5 A) SION RM GATE RE-Oxidation PreCln Poly Re_Oxidation NLH5AHP0550A 50:1 HF +H3PO4 NRCA (SC1+SC2) 1015C,21A RTO ( T ↑ 1C, THK ↑ 0.8 A )
能够展现精确的模拟特性soc与ic组成的系统相比由于soc能够综合并全盘考虑整个系统的各种情况可以在同样的工艺技术条件下实现更高性能的系统指若采用is方法和035m工艺设计系统芯片在相同的系统复杂度和处理速率下能够相当于采用025018m工艺制作的ic所实现的同样系统的性能与采用常规ic方法设计的芯片相比采用soc完成同样功能所需要的晶体管数目可以有数量级的降低asic
SiN/Ox+Si etch ( 80 +-2degree)
AA Asher Mattson ( Rcp: 1 ) Polymer & Wet Strip NDH15APRRMSC1M ( 100:1 HF 30sec) AA THK STI-PO PAD (5400+-160 A)
AEI = 0.25+-0.02
Mattson & Wet Rcp
16250Å Nitride 110Å PAD Oxide
8
HDP Deposition
• • • • • • • STI PadOX PreCln NCR1DH75ARCAM (100:1 HF 180sec) STI Liner OX 1000 C,DRY OX(200+-12A) Anneal(Diff) HDP Fill RTA PRECLN HDPCVD OX RTA 1100 C, 2 hrs (Furnace ann.) HDPCVD OX 5.8KA W/O AR sputter NRCAM (SC1+ SC2)
AA SiN Pad oxide
P Substrate
AA SiN Pad oxide
P Substrate
P Substrate
10
STI CMP & NIT RM
• • • • • • • • • STI Pre-CMP THK-PO PAD (6100+-225 A) STI Polish & in-situ Cln (STI_XXXX) ? CMP 是磨到 是磨到NIT上。 上
• •
B160K15E3T00 B025K44E2T00 D170K70E2T00 Mattson: 21 SPM only
N_VT N pthru P WELL
13
Thick/ Thin Gate oxide define
• • • • • • • • • • SAC OX RM NLH60A (50:1 HF 65sec) SAC OX THK-PO PAD (3200+-400 A) GATE1_OX PreCln NCR1DH100ARCAM GATE1_OX 800C,48A+-4 A, wet Dual GATE Photo (131layer) (0.45+/-0.05um) GATE1 ETCH N(NLB75A) GATE1 Strip SPM only STI THK-PO PAD ( 3150+-180 A) GATE2_OX PreCln NCRRCAM GATE2 OX 750 C, 27+-2 A, wet
a.Recover ETCH damage to GOX. b. Prevent native-oxide For thermal budget&good oxide profile around poly gate
N-Well P-Well
15
LDD1 Definition (Core device, 1.8V)
As buffer layer to release stress, due to SIN and Si different lattice constant
•Nitride DEP (w/I scrubber )
1625+- 100A / 760oC STOP LAYER of STI CMP
7
STI ETCH
To better shallow trench filling
1000RTA020S (1000C, 20sec ,N2)
For damage reduction by HDP and HDP ox densification
5800Å HDP 1625Å Nitride 110Å PAD Oxide
018LG Process Introduction (1P6M)
1
Logic Circuit: 能够 展现 精确的模拟特性， 精确的模拟特性， ASIC: 为了满足消费者特定需求而专门设计的半导体
电路
• SOC与IC组成的系统相比，由于SOC能够综合并全盘考虑整个系统 的各种情况，可以在同样的工艺技术条件下实现更高性能的系统指 标 – 若采用IS方法和0.35µm工艺设计系统芯片，在相同的系统复杂 度和处理速率下，能够相当于采用0.25 ~ 0.18µm工艺制作的IC 所实现的同样系统的性能 – 与采用常规IC方法设计的芯片相比，采用SOC完成同样功能所 需要的晶体管数目可以有数量级的降低
2
VDD
VDD
IN
OUT Y A1 A2
CMOS反相器 反相器
与非门： 与非门：Y=A1A2
3
基本电路结构： 基本电路结构：MOS器件结构 器件结构
基本电路结构： 基本电路结构：CMOS
4
0.18um Process Features
18LG adopt 27 Photo mask , if include ESD layer AA/Poly/CT/ M1~M5/ V1~V5 use DUV scanner (13 layer) “ DARC” Cap on Critical layer and Top M6 Poly & M1~M5 adopt OPC (optical proximity correction) for line-end shorting & island missing Composite Spacer (ONO) PSM method apply on CT layer Cobalt salicide process Low K IMD layer (FSG) 5
6
Wafer Start
• • WAFER START & RS CHECK
P type 8 ~ 12 ohm-cm, non-EPI wafer
Wafer Mark (For Wafer alignment) • Scrubber Clean (TJBB) • Start oxide RM NLH320A (50:1 HF 350 sec) • Meas: Ox RM THK (25~35A) • AA OX Pre-cln
P-VT P-pthru N-Well P-Well
• • • •
12
P-Well and Vt_N adjustment
• • P_Well Photo (191 layer) Implant: • P WELL IMP • N CHANNEL IMP • N_VT IMP PWELL Asher PWELL Wet Strip
As implant screen oxide
110Å SAC Oxide
11
N-Well and Vt_P adjustment
• • N_Well Photo(192 layer) Implant: • N WELL IMP P440K15E3T00 WELL IMP注入的位置最深，用以调节井的浓度防止Latch-up效应。 • P CHANNEL IMP P140K50E2T00 CHANNEL IMP位置较浅，加大LDD之下部位的WELL浓度，使器件工 作时该位置的耗尽层更窄，防止器件PUNCH THROUGH。 VTP IMP A130K90E2T00 VT注入，靠近器件表面，调节器件的开启电压 NWELL Asher Mattson: 21 NWELL Wet Strip SPM only NWELL Anneal Precln MRCAM (SC1+SC2) IMPLANT DAMAGE ANNEAL 1000RTA010S (1000C; 10sec N2(PVD)
ZERO Photo
For ASML stepper system global Wafer alignment
ZERO Fully dry etch
(OX 100A + SI 1200+-200 A)
• Pad oxide
110+-7A/ 920oC dry O2
ZERO Strip
1625Å Nitride 110Å PAD Oxide
STI Pre-CMP THK-PO PAD (3600+-250 A) , SIN (1050+-50) AA NIT RM NLH90AHPO2450A (50:1 HF + H3PO4) THIN OXIDE THK-P PAD ( 82+-17) STI PAD OX RM NLH60A (50:1 HF 65 sec) SAC OX PRECLN NCR1DH100ARCAM (100:1 HF 240sec) SAC OX 110+-7A/ 920oC 45min dry O2
9
AA Reverse
• • • • AAR Photo (121 layer) AAR Etch AAR Asher AAR wet strip AAR= [ (AA-0.4) +0.4) ] -0.2 Stop on SiN Mattson (Rcp: 1) NPRRM (SPM only)
1. Better surface flatness 2. Improved throughput by OX removing
Outline
1. STI/Trench Isolation 2. Well Definition/Vt Adjust 3. Gate Formation 4. N/PMOS Formation 5. Salicide Formation 6. ILD Layer / Contact CT 7. Metal / VIA 8. Top Meta l Via 9. Passivation (BEOL: interconnect) (FEOL: device)
ADI = 0.23+-0.02
•
SiON DEP(CVD)
FE DARC320 (w/I scrubber )
To reduce SIN reflection and improve PR resolution as an ARC wk.baidu.comayer
• • • • •
AA Photo (120 layer) AA Etch (5800A)
NCR1DH75ARCAM
Start OX 100A dry
1. PR isolation 2. Prevent the laser mark Si recast 3. Surface cleanness 4. Backside oxidation & trap the metal ion
• • •
2000A poly
50Å thick gate oxide Final 70 A 32Å thin gate oxide
Thin gate
Thick gate
14
Poly Gate Definition
• • • • • • • • • • POLY DEPOSITION POLY 2000A, 620C SiON DEP FEDARC320 ADI 0.18+-0.015um POLY PHOTO (130layer) AEI 0.18+-0.015um Poly ARC etch + Poly etch GATE Asher Mattson (Rcp: 1) GATE Wet Strip NDH5APRRM (100:1 HF 10sec +SPM) THICK GATE OXIDE THK-P PAD (25+-5 A) SION RM GATE RE-Oxidation PreCln Poly Re_Oxidation NLH5AHP0550A 50:1 HF +H3PO4 NRCA (SC1+SC2) 1015C,21A RTO ( T ↑ 1C, THK ↑ 0.8 A )
能够展现精确的模拟特性soc与ic组成的系统相比由于soc能够综合并全盘考虑整个系统的各种情况可以在同样的工艺技术条件下实现更高性能的系统指若采用is方法和035m工艺设计系统芯片在相同的系统复杂度和处理速率下能够相当于采用025018m工艺制作的ic所实现的同样系统的性能与采用常规ic方法设计的芯片相比采用soc完成同样功能所需要的晶体管数目可以有数量级的降低asic
SiN/Ox+Si etch ( 80 +-2degree)
AA Asher Mattson ( Rcp: 1 ) Polymer & Wet Strip NDH15APRRMSC1M ( 100:1 HF 30sec) AA THK STI-PO PAD (5400+-160 A)
AEI = 0.25+-0.02
Mattson & Wet Rcp
16250Å Nitride 110Å PAD Oxide
8
HDP Deposition
• • • • • • • STI PadOX PreCln NCR1DH75ARCAM (100:1 HF 180sec) STI Liner OX 1000 C,DRY OX(200+-12A) Anneal(Diff) HDP Fill RTA PRECLN HDPCVD OX RTA 1100 C, 2 hrs (Furnace ann.) HDPCVD OX 5.8KA W/O AR sputter NRCAM (SC1+ SC2)
AA SiN Pad oxide
P Substrate
AA SiN Pad oxide
P Substrate
P Substrate
10
STI CMP & NIT RM
• • • • • • • • • STI Pre-CMP THK-PO PAD (6100+-225 A) STI Polish & in-situ Cln (STI_XXXX) ? CMP 是磨到 是磨到NIT上。 上
• •
B160K15E3T00 B025K44E2T00 D170K70E2T00 Mattson: 21 SPM only
N_VT N pthru P WELL
13
Thick/ Thin Gate oxide define
• • • • • • • • • • SAC OX RM NLH60A (50:1 HF 65sec) SAC OX THK-PO PAD (3200+-400 A) GATE1_OX PreCln NCR1DH100ARCAM GATE1_OX 800C,48A+-4 A, wet Dual GATE Photo (131layer) (0.45+/-0.05um) GATE1 ETCH N(NLB75A) GATE1 Strip SPM only STI THK-PO PAD ( 3150+-180 A) GATE2_OX PreCln NCRRCAM GATE2 OX 750 C, 27+-2 A, wet
a.Recover ETCH damage to GOX. b. Prevent native-oxide For thermal budget&good oxide profile around poly gate
N-Well P-Well
15
LDD1 Definition (Core device, 1.8V)
As buffer layer to release stress, due to SIN and Si different lattice constant
•Nitride DEP (w/I scrubber )
1625+- 100A / 760oC STOP LAYER of STI CMP
7
STI ETCH