10外文翻译封面 草稿
2、英文翻译封面格式范例
(3)英文原著若为纸质复印件或不可更改的pdf格式文件，则英文原著与中文翻译单独编制页码；除上述情况外，英文原著与中文翻译整体编制页码。
（4）建议在英文原著首页以页脚的形式注明英文原著的来源，如本页下题注所示，书写格式同正文中的参考文献格式要求。
英文翻译
题目:
Development of LCD Telephone Alarm System
专业班级:
2010电子信息工程01
学号:
XБайду номын сангаасX
姓名:
XXX
指导教师:
XXX教授
XXX高工(校外)
学院名称:
电气信息学院
201年月日
说明：(1)翻译内容的正文格式同毕业设计(论文)格式，也应该有“武汉工程大学毕业设计(论文)说明书”字样的页眉；
毕业设计(论文)外文文献译文格式及装订要求
“毕业设计（论文）外文文献译文”格式及装订要求
全校所有专业的学生在完成毕业设计（论文）的同时，必须完成一篇专业外文文献翻译工作（将外文文献翻译成中文），要求译出3000汉字以上的有关技术资料或专业外文文献，内容要与毕业设计（论文）内容相关。
书写时具体格式要求参考“毕业论文（设计说明书）缩写稿格式、版面要求”，装订时按以下顺序独立装订：1、封面；2、外文文献译文；3、外文文献原文。
附件：毕业设计（论文）外文文献译文封面
毕业设计（论文）
外文文献译文及原文
学生：
学号：
院（系）：
专业：
指导教师：
20 年月日。
2、英文翻译封面格式范例
(2)英文原著字数实词不小于3000；
(3)英文原著若为纸质复印件或不可更改的pdf格式文件，则英文原著与中文翻译单独编制页码；除上述情况外，英文原著与中文翻译整体编制页码。
（4）建议在英文原著首页以页脚的形式注明英文原著的来源，如本页下题注所示，书写格式同正文中的参考文献格式要求。
英文翻译
题目:
Development of LCD Telephone Alarm System
专业班级:
2010电子信息工程01
学号:
XXX
姓名:
XXX
指导教师:
XXX教授
XXX高工(校外)
学院：(1)翻译内容的正文格式同毕业设计(论文)格式，也应该有“武汉工程大学毕业设计(论文)说明书”字样的页眉；
外文翻译排版格式参考
毕业设计(论文)外文资料翻译系别：电子信息系专业：通信工程班级：B100309姓名：张杨学号： B外文出处：附件： 1. 原文； 2. 译文2014年03月An Introduction to the ARM 7 ArchitectureTrevor Martin CEng, MIEETechnical DirectorThis article gives an overview of the ARM 7 architecture and a description of its major features for a developer new to the device. Future articles will examine other aspects of the ARM architecture.Basic CharacteristicsThe principle feature of the ARM 7 microcontroller is that it is a register based load-and-store architecture with a number of operating modes. While the ARM7 is a 32 bit microcontroller, it is also capable of running a 16-bit instruction set, known as "THUMB". This helps it achieve a greater code density and enhanced power saving. While all of the register-to-register data processing instructions are single-cycle, other instructions such as data transfer instructions, are multi-cycle. To increase the performance of these instructions, the ARM 7 has a three-stage pipeline. Due to the inherent simplicity of the design and low gate count, ARM 7 is the industry leader in low-power processing on a watts per MIP basis. Finally, to assist the developer, the ARM core has a built-in JTAG debug port and on-chip "embedded ICE" that allows programs to be downloaded and fully debugged in-system.In order to keep the ARM 7 both simple and cost-effective, the code and data regions are accessed via a single data bus. Thus while the ARM 7 is capable of single-cycle execution of all data processing instructions, data transfer instructions may take several cycles since they will require at least two accesses onto the bus (one for the instruction one for the data). In order to improve performance, a three stage pipeline is used that allows multiple instructions to be processed simultaneously.The pipeline has three stages; FETCH, DECODE and EXECUTE. The hardware of each stage is designed to be independent so up to three instructions can be processed simultaneously. The pipeline is most effective in speeding up sequential code. However a branch instruction will cause the pipeline to be flushed marring its performance. As we shall see later the ARM 7 designers had some clever ideas to solve this problem.InstructionFig 1 ARM 3- Stage pipelineARM7 Programming ModelThe programmer's model of the ARM 7 consists of 15 user registers, as shown in Fig. 3, with R15 being used as the Program Counter (PC). Since the ARM 7 is a load-and- store architecture, an user program must load data from memory into the CPU registers, process this data and then store the result back into memory. Unlike other processors no memory to memory instructions are available.M1M2M34,R 1,R 2 (R 4=R 0+R 2)3Fig 2 Load And Store ArchitectureAs stated above R15 is the Program Counter. R13 and R14 also have special functions; R13 is used as the stack pointer, though this has only been defined as a programming convention. Unusually the ARM instruction set does not have PUSH and POP instructions so stack handling is done via a set of instructions that allow loading and storing of multiple registers in a single operation. Thus it is possible to PUSH or POP the entire register set onto the stack in a single instruction. R14 has special significance and is called the "link register". When a call is made to a procedure, the return address is automatically placed into R14, rather than onto a stack, as might be expected. A return can then be implemented by moving the contents of R14 into R15, the PC. For multiple calling trees, the contents of R14 (the link register) must be placed onto the stack.15 User registers +PCR13 is used as the stack pointer R14 is the link registerR14 is the Program Counter Current Program Status RegisterFig 3 User Mode Register ModelIn addition to the 16 CPU registers, there is a current program status register (CPSR). This contains a set of condition code flags in the upper four bits that record the result of a previous instruction, as shown in Fig 4. In addition to the condition code flags, the CPSR contains a number of user-configurable bits that can be used to change the processor mode, enter Thumb processing and enable/disable interrupts.31 30 29 28 27Negative Carry OverflowIRQ System UserUndefined instruction AbortThumb instruction setFig 4 Current Program Status Register and Flags Exception And Interrupt ModesThe ARM 7 architecture has a total of six different operating modes, as shown below. These modes are protected or exception modes which have associated interrupt sources and their own register sets.User: This mode is used to run the application code. Once in user mode the CPSR cannot be written to and modes can only be changed when an exception is generated.FIQ: (Fast Interrupt reQuest) This supports high speed interrupt handling. Generally it is used for a single critical interrupt source in a systemIRQ: (Interrupt ReQuest) This supports all other interrupt sources in a system Supervisor: A "protected" mode for running system level code to access hardware or run OS calls. The ARM 7 enters this mode after resetAbort: If an instruction or data is fetched from an invalid memory region, an abort exception will be generatedUndefined Instruction: If a FETCHED opcode is not an ARM instruction, an undefined instruction exception will be generated.The User registers R0-R7 are common to all operating modes. However FIQ mode has its own R8 -R14 that replace the user registers when FIQ is entered. Similarly, each of the other modes have their own R13 and R14 so that each operating mode has its own unique Stack pointer and Link register. The CPSR is also common to all modes. However in each of the exception modes, an additional register一the saved program status register (SPSR)，is added. When the processor changes the current value of the CPSR stored in the SPSR，this can be restored on exiting the exception mode.System&User FIQ Supervisor Abort IRQ Undefined Fig 5 Full Register Set For ARM 7Entry to the Exception modes is through the interrupt vector table. Exceptions in the ARM processor can be split into three distinct types.(i) Exceptions caused by executing an instruction, these include software interrupts, undefined instruction exceptions and memory abort exceptions(ii) Exceptions caused as a side effect of an instruction such as a abort caused by trying to fetch data from an invalid memory region.(iii) Exceptions unrelated to instruction execution, this includes reset, FIQ and IRQ interrupts.In each case entry into the exception mode uses the same mechanism. On generation of the exception, the processor switches to the privileged mode, thecurrent value of the PC+4 is saved into the Link register (R14) of the privileged mode and the current value of CPSR is saved into the privileged mode's SPSR. The IRQ interrupts are also disabled and if the FIQ mode is entered, the FIQ interrupts are also disabled, Finally the Program Counter is forced to the exception vector address and processing of the exception can start. Usually the first action of the exception routine will be to push some or all of the user registers onto the stack.Prefetch Abort(instruction fetch memory abort)Software interrupt (SWI)Undefined instruction ResetData Abort (data access momory abort)IRQ (interrupt)FIQ (fast interrupt)Supervisor Undefined Supervisor Abort Abort IRQ FIQ0x000000000x0000001C0x000000040x0000000C 0x000000080x000000100x00000018Fig 6 ARM 7 Vector TableA couple of things are worth noting on the vector table. Firstly, there is a missing vector at 0x000000014. This was used on an earlier ARM architecture and is left empty on ARM 7 to allow backward compatibility. Secondly, the FIQ interrupt is at the highest address so the FIQ routines could start from this address, removing the need for a jump instruction to reach the routine. It helps make entry into the FIQ routine as fast as possible.Once processing of the exception has finished, the processor can leave the privileged mode and return to the user mode. Firstly the contents of any registers previously saved onto the stack must be restored. Next the CSPR must be restored from the SPSR and finally the Program Counter is restored by moving the contents of the link register to R15, . the Program Counter). The interrupted program flow can then restart.Data TypesThe ARM instruction set supports six data types namely 8 bit signed and unsigned, 16 bit signed and unsigned plus 32 bit signed and unsigned. The ARM processor instruction set has been designed to support these data types in Little or Big-endian formats. However most ARM silicon implementations use the Little-endian format. ARM instructions typically have a three-operand format, as shown below ADD Rl ，R2, R3 ; Rl=R2+R3ARM7 Program Flow ControlIn all processors there is a small group of instructions that are conditionally executeddepending on a group of processor flags. These are branch instructions such as branch not equal. Within the ARM instruction set, all instructions are conditionally executable.31 28CONDFig. 7 Instruction Condition Code BitsThe top four bits of each instruction contain a condition code that must be satisfied if the instruction is to be executed. This goes a long way to eliminating small branches in the program code and eliminating stalls in the pipeline so increasing the overall program performance. Thus for small conditional branches of three instructions or less, conditional execution of instructions should be used. For larger jumps, normal branching instructions should be used.Fig. 8 Instruction Condition CodesThus our ADD instruction below could be prefixed with a condition code, as shown. This adds no overhead to instruction executionEQADD R1，R2，R3 ;If(Zero flag = 1)then R1 = R2+R3The ARM7 processor also has a 32-bit barrel shifter that allows it to shift or rotate one of the operands in a data processing instruction. This takes place in the same cycle as the instruction. The ADD instruction could be expanded as followsEQADD R1，R2 R3，LSL #2 ; If ( Zero flag = 1) then R1 = R2+ (R3 x 4)Finally the programmer may decide if a particular instruction can set the condition code flags in the CPSR.EQADDS R1，R2 R3，LSL #2; If (Zero flag = 1) then R1 = R2 + (R3 x4)and set condition code flagsIn the ARM instruction set there are no dedicated call or return instructions. Instead these functions are created out of a small group of branching instructions.The standard branch (B) instruction allows a jump of around+-32Mb. A conditional branch can be formed by use of the condition codes. For example, a "branch not equal" would be the branching instruction B and the condition code "NE" for not equal giving "BNE". The next form of the branch instruction is the branch with link. This is the branch instruction but the current value of the PC +4 is saved into R14, the link register. This acts as a CALL instruction by saving the return address into R14. A return instruction is not necessary since a return can be implemented by moving R14 into the PC. The return is more complicated in the case of an interrupt routine. Depending on the type of exception, it may be necessary to modify the contents of the link register to get the correct return address. For example, in the case of an IRQ or FIQ interrupt, the processor will finish its current instruction, increment the PC to the next instruction and then jumping to the vector table. This means that the value in the link register is PC+4 or one instruction ahead of the return address. This means we need to subtract 4 from the value in the link register to get the correct return address.This can be done in a single instruction thus:SUBS pc, r14,#40x80000x400PC=0x80000x4000x8000Both thebranch and branch-with-link may perform an exchange between 32-bit and 16-bit instruction sets and vice versa .The Branch exchange will jump to a location and start to execute 16-bit Thumb instructions. Branch link exchange will jump to a location, save PC+4 into the linkregister and start execution of 16-bit Thumb instructions. In both cases, the T bit is set in the CPSR. An equivalent instruction is implemented in the Thumb instruction set to return to 32-bit ARM instruction processing.0x8000T=1Y=10x4000x4000x8000Fig. 10 Branch Exchange and Branch Link Exchange Instruction OperationSoftware InterruptsThe ARM instruction set has a software interrupt instruction. Execution of this instruction forces an exception as described above; the processor willenter supervisor mode and jump to the SWI vector at 0x00000008.Fig. 11 Software Interrupt InstructionThe bit field 0-23 of the SWI instruction is empty and can be used to hold an ordinal. On execution of an SWI instruction, this ordinal can be examined to determine which SWI procedure to run and gives over 16 million possible SWI functions.…Swi_ #1 . call swi function one…Tn the swi handlerregister unsigned*link ptr asm ("r14")；In order to access OS calls or SFR registers, the user code must make a SWI call . All these functions are the running in a supervisor mode, with a separate stack and link register.As well as instructions to transfer data to and from memory and to CPU registers, the ARM 7 has instructions to save and load multiple registers. It is possible to load or save all 16 CPU registers or a selection of registers in a single instruction. Needless to say, this is extremely useful when entering or exiting a procedure.M0Fig. 12 Load and Store Multiple Instruction OperationThe CPSR and SPSR are only accessed by two special instructions to move their contents to and from a CPU register. No other instruction can act on them directly.MSRR15R15Fig. 13 Programming The SPSR And CPSR RegistersTHUMB SupportThe ARM processor is capable of executing both 32-bit (ARM) instructions and 16- Bit (Thumb instructions). The Thumb instruction set must always be entered by running a Branch exchange or branch link exchange instruction and NOT by setting the T bit in the CPSR. Thumb instructions are essentially a mapping of their 32 bit cousins but unlike the ARM instructions, they are unconditionally executed except though for branch instructions.Fig. 14 Thumb Instruction ProcessingThumb instructions reduced number of only have unlimited access to registers RO-R7 and R13一Rl5. A instructions can access the full register set.Thumb programmers modelThe Thumb instruction set has the same load and store multiple instructions as ARM and in addition, has a modified version of these instructions in the form of PUSH and POP that implement a full descending stack in the conventional manner. The Thumb instruction set also supports the SWI instruction, except that the ordinal field is only 8 bits long to support 256 different SWI calls. When the processor is executing Thumb code and an exception occurs, it will switch to ARM mode in order to process the exception. When the CPSR is restored the, Thumb bit will be reset and the processor continues to run Thumb instructions.BCXBXThumb Exception ProcessingThumb has a much higher code density than ARM code, needing some 70% of the space of the latter. However in a 32-bit memory, ARM code is some 40% faster than Thumb. However it should be noted that if you only have 16-bit wide memory then Thumb code will be faster than ARM code by about 45%. Finally the other important aspect of Thumb is that it can use up to 30% less power than ARM code.ARM7的体系结构介绍 特里沃马丁曾，鼠技术总监本文给出了ARM 7架构的概述和开发新的设备，以及主要功能的描述，未来将研究ARM 体系结构的其他方面。
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山东理工大学毕业设计（外文翻译材料）学院：专业：学生姓名：指导教师：电气与电子工程学院自动化于小涵季画外文翻译材料格式要求：1.页边距：上3.8磅；下3.8磅；左3.2，右3.2；页眉距边界2.8，页脚距边界32.原文题目：Arial，小三；间距：段前18磅，段后12磅，间距21磅3.原文正文：Times New Roman，小四；间距：段前0磅，段后6磅，间距21磅4.译文题目：黑体，小三；间距：同原文题目5.译文正文：宋体，小四；间距同原文正文6.页眉页脚：原文页眉处写：外文翻译（原文），宋体，五号。
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Plant Model Generation for PLC SimulationHyeong-Tae ParkAbstract:This paper reports an automated procedure for constructing a plant model for PLC simulation. Since PLC programs contain only the control logic without information on the plant model, it is necessary to build the corresponding plant model to perform the simulation. Conventionally, a plant model for PLC simulation has been constructed manually, which requires much effort and indepth knowledge of the simulation. As a remedy for this problem, we propose an automated procedure for generating a plant model from the symbol table of a PLC program. To do so, we propose a naming rule for PLC symbols so that the symbol names include sufficient information on the plant model. By analysing such symbol names, we extract a plant model automatically. The proposed methodology has been implemented and test runs performed.Keywords: agile manufacturing; CAD/CAM; CAPP; simulation1. IntroductionTo survive and prosper in the modern manufacturing era, manufacturers need to continuously improve their products, as well as their production systems. A modern manufacturing line is a highly integrated system composed of automated workstations, such as robots with tool-changing capabilities, a hardware handling system and storage system, and a computer control system that controls the operations of the- 1 -entire system.Since the implementation of a manufacturing line requires heavy investment, proper verification of a line’s operational status sho uld be performed to ensure that the highly automated manufacturing system will successfully achieve the intended benefits. Simulation technology is considered to be an essential tool in the design and analysis of complex systems that cannot be easily described by analytical or mathematical models . Simulation is useful for calculating utilisation statistics, finding bottlenecks, pointing out scheduling errors, and even for creating manufacturing schedules. Traditionally, various simulation languages, including ARENA and AutoMod, have been used for the simulation of manufacturing systems. These simulation languages have been widely accepted both by industry and by academia; however, they remain as analysis tools for the rough design stage of a production line, because their simulation models are not sufficiently realistic to be utilised for a detailed design or for implementation purposes. For example, real production lines are usually controlled by PLC (Programmable Logic Controller) programs (Rullan 1997), but conventional simulation languages roughly describe the control logic with independent entity flows (job flows) between processes.- 2 -Production systems typically consist of simultaneously operating machines, which are controlled by PLCs, currently the most suitable and widely employed industrial control technology. A PLC emulates the behaviour of an electric ladder diagram. As they are sequential machines, to emulate the workings of parallel circuits that respond instantaneously, PLCs use an input/output symbol table and a scanning cycle. When a program is being run in a PLC it is continuously executing a scanning cycle. The program scan solves the Boolean logic related to the information in the input table with that in the output and internal relay tables. In addition, the information in the output and internal relay tables is updated during the program scan. In a PLC, this Boolean logic is typically represented using a graphical language known as a ladder diagram (IEC 2003).Since the abstraction levels of conventional simulators and PLC programs are quite different, the control logic of conventional simulators cannot be reused for the generation of PLC programs. Usually, electrical engineers manually write PLC programs by referring to the rough control logic of conventional simulators, as shown in Figure 1. Since PLC programming is a very tedious and error-prone job, it is essential to verify the PLC programs offline to reduce the stabilisation time of a production system.Previous approaches to a PLC program can be categorised into two groups:- 3 -(1) verification of a given PLC programand (2) generation of a dependable PLC program. In the first group, various software tools have been developed for the verification of PLC based systems via the use of timed automata, such as UPPAAL2k, KRONOS, Supremica and HyTech, mainly for programs written in a statement list language, also termed Boolean (Manesis and Akantziotis 2005). Such software tools verify PLC programs to a certain extent; however, they remain limited. Since they mainly focus on the checking of theoretical attributes (safety, liveness, and reachability), it is not easy for users to determine whether the PLC programs actually achieve the intended control objectives. In the second group, many researchers have focused on the automatic generation of PLC programs from various formalisms including state diagrams, Petri nets, and IDEF0. These formalisms can help the design process of control logics; however, it is still difficult to find hidden errors, which is the most difficult part of verifying a control program.Figure 2. The concept of PLC simulation.To overcome the aforementioned problems, it is necessary to utilise simulation techniques for PLC program verification. By simulating PLC programs, it is possible to analyse the control logic in various ways and recognise hidden errors more intuitively (David 1998). Although PLC simulation can be a very powerful tool for the detailed verification of a production system, the accompanying construction of a plant model is a major obstacle (the counterpart model of a control program). Since PLC programs only contain the control information, without device models, it is necessary to build a corresponding plant model to perform simulation, as shown in- 4 -Figure 2. However, constructing a plant model requires an excessive amount of time and effort. Sometimes, the plant model construction requires much more time than the PLC programming. This serves as the motivation for exploring the possibility of finding an automatic procedure for generating a plant model from a given PLC program.Figure3.Symbol table of a PLC program.Although the objective of a PLC program is not to describe a plant model (device models), the symbol table of a PLC program can provide a glimpse of the plant model. As shown in Figure 3, symbols in a PLC program usually contain some information related to the plant. For example, ‘EXLINE_MB_AGV_P1’ means that the symbol is a signal that is related to the control of an ‘AGV’ (Auto Guided Vehicl e) belonging to the ‘MB’ station of ‘EXLINE’ line. The above scenario reveals the key idea of the present study. If we can develop a proper naming rule for PLC symbols, then it might be possible to extract a plant model by analysing the symbol names.This paper has two major objectives: (1) to propose a proper naming rule for PLC symbols and (2) to develop a procedure for generating a plant model by analysing the symbol names. The application area of the proposed methodology includes all types of automated manufacturing systems controlled by PLC programs, such as automotive production lines, FMSs (flexible manufacturing systems), and ASRSs (automatic storage and retrieval systems). The overall structure of the paper is as follows. Section 2 addresses the specifications of a plant model for PLC simulation. Section 3 describes a naming rule for PLC symbols, which enables the automatic generation of a plant model. Finally, concluding remarks are given in Section 4.2. Plant model for PLC simulationBefore explaining the specification of a plant model enabling PLC simulation, we want to address the importance of the PLC simulation. Chuang et al. (1999) proposed a procedure for the development of an industrial automated production system that- 5 -- 6 -consists of nine steps, as follows: (1) define the process to be controlled; (2) make a sketch of the process operation; (3) create a written sequence of the process; (4) on the sketch, add the sensors needed to carry out the control sequence; (5) add the manual controls needed for the process setup or for operational checks; (6) consider the safety of the operating personnel and make additions and adjustments as needed;(7) add the master stop switches required for a safe shutdown; (8) create a ladder logic diagram that will be used as a basis for thePLC program; and (9) consider the possible points where the process sequence may go astray. The most time-consuming task for the control logic designers is the eighth step, which is usually done by the repetitive method of code writing, testing, and debugging until the control objectives are achieved (Manesis and Akantziotis 2005). This is the reason why conventional PLC programming is often inefficient and prone to human error. As the configurations of production lines and their control programs become more complicated, there is a strong need for a more efficient PLC simulation environment. It is hoped that this paper will take positive steps in this direction.A PLC can be considered as a dedicated computer system having input and output signals. To run a PLC, the corresponding plant model (the counterpart system) is required to interact with the input and output of the PLC. The behaviour of the plant model should be the same as that of the actual system to achieve PLC verification. Since a production line consists of various devices, including robots, transporters, jigs, solenoids, proximity sensors, and light sensors (Groover 2006), we can consider a plant model as a set of device models. To build such a device model, this paper em ploys Zeigler’s DEVS (Discrete Event Systems Specifications) formalism (Zeigler 1984, Kim 1994), which supports the specification of discrete event models in a hierarchical, modular manner. The semantics of the formalism are highly compatible with object-oriented specifications for simulation models. We use the atomic model of the DEVS formalism to represent the behavior of a device model. Formally, an atomic model M is specified by a 7-tuple:M =〈X, S,Y, sin δ,ext δ,λ ,t a 〉X input events setS sequential states setY output events setsin δ S→S: internal transition functionext δQ*X→S: external transition functionQ={(s, e)∣s ∈S, 0≤e ≤t a (s)}: total state of MλS →Y: output function- 7 -t a S →Real: time advance functionThe four elements in the 7-tuple, namely sin δ,ext δ,λand t a , are called the characteristic functions of an atomic model. The atomic model of the DEVS formalism can be considered as a timed-FSA (finite state automata), and it is suitable for describing the behaviour of a device model. Once the device models (plant model) are obtained, it becomes possible to perform the PLC simulation. Currently, device models should be construed manually, which takes much time and effort. To cope with the problem, the objective of the paper is to propose an automated generation procedure for device models.Before explaining the automatic generation procedure of a plant model, let us take a look at the manual procedure to construct device models. To construct a device model, first it is necessary to identify the set of tasks that are assigned to the device. The activation of each task is normally triggered by an external signal from PLC programs. Once the set of tasks is identified for a device, it is then possible to extract the state transition diagram, which defines an atomic model of the DEVS formalism. Figure 4(a) shows a simple example of an AGV (Automatic Guided Vehicle) with two tasks, T1 (movement from p1 to p2) and T2 (movement from p2 to p1). As the two tasks should be triggered by external events, the shell part of the AGV must have two input ports, termed here as Signal_1 and Signal_2, as shown in Figure 4(b).From the set of tasks, it is possible to instantiate the state transition diagram. For this example, there are four states, P1, DoT1, P2 and DoT2. While P1 and P2 take external events from the input ports (Signal_1, Signal_2) for state transitions, DoT1 and DoT2 take internal events that are the end events of the two tasks (T1 and T2). The DEVS atomic model of the virtual device, corresponding to the AGV, can be described as follows:- 8 -Shell of a virtual device:M=〈X,S,Y,sin δ,ext δ,λ ,t a 〉}2_,1_{Signal Signal =X S={P1,DOT1,P2,DOT2} Y={T1Done,T2Done}sin δ(DOT1)=P2 s i nδ(DOT2)=P1 ext δ(P1,Signal_1)=DOT1 ext δ(P2,Signal_2)=DOT2λ(DOT1)=T1Done λ(DOT2)=T2Donet a (DOT1)=Time_1 t a (DOT2)=Time_2Once a plant model has been constructed, it is possible to perform the PLC simulation, which enables the intuitive verification of a PLC program. Figure 5 shows the connections between a PLC program and a plant model. The plant model includes all device models of a production system, and the PLC program contains the control logic for the plant model. To integrate the plant model and the PLC program, it is necessary to define the mapping between the plant model and the PLC program, which is described by I/O mapping. To enable the visual verification of a PLC program, it is necessary to import 3D graphic models, which are controlled by the logical device models (the state transition diagrams). Since 3D graphic models are not always necessary, they are optional for PLC simulation. As mentioned already, the objective of this paper is to extract device models from the symbol names of PLC programs. To do so, it is necessary to develop a proper naming rule for PLC symbols. The naming rule will be addressed in the next section.3. Symbol naming for plant model generationAlthough IEC 61131-3 provides various standard specifications for a PLC, the naming rules of PLC symbols have rarely been brought into focus. Since there have been no standard rules for the naming of PLC symbols, it has been fully dependent on individual PLC programmers.To generate device models from PLC symbols, it is necessary to make PLC symbols that include enough information concerning the plant model. To achieve this objective, we interviewed many PLC programmers and analysed various conventional rules. As a result, we came up with a naming structure consisting of five fields: (1) line name, (2) process number, (3) device name, (4) input or output, and (5) task name (or state name). Figure 6 shows the naming structure for PLC symbols.If the PLC symbols are named according to the proposed naming structure, then it becomes possible to extract device models (atomic models of DEVS formalism) by simply analysing the symbol names. There are two types of symbols (signals), input or output, which are specified by the fourth field. The purpose of the output signal is to trigger a task that is specified by the fifth field. Thus, it is possible to identify the set of tasks of a device by analysing the output symbols. As mentioned already, once the set of tasks is identified for a device, it is then possible to extract the state transition diagram for the device model, which defines an atomic model of the DEVS formalism. While an output signal (symbol) is issued by a PLC to trigger a task, an input signal (symbol) is issued by a device to report the completion of the task to theδand internal transition functions PLC. This means that external transition functionsextδof a device model can be automatically extracted from the output and input sinsymbols, respectively. We demonstrate the generation procedure of a plant modelfrom PLC symbols using an example, as shown in Figure 7.- 9 -- 10 -In the example cell, we assume a part is loaded manually on the AGV by a worker. When the AGV senses the existence of a part, it moves to transfer the part to the machine. After the transfer, the machine performs machining to convert the part into a finished product. In this case, the plant model consists of two device models: an AGV model and a machine model. The PLC program to control the simple manufacturing cell is shown in Figure 8(a), and its symbol table is shown in Figure 8(b).As shown in Figure 8(b), the AGV model has two output symbols and two input symbols. From the output symbols (EX_OP_AGV_O_GOP1, EX_OP_AGV_O_GOP2), we can intuitively recognise that the AGV has two tasks- 11 -(movement from P2 to P1, and movement from P1 to P2). By using the output symbols, we can extract the state transition diagram, as well as the external transitionfunctions, as shown in Figure 9(a).As mentioned already, an output symbol triggers a task of a device model, and an input symbol is made by the device to notify the completion of the task. Since the execution of a task is performed internally by the device, the internal transition functions of a device model can easily be extracted from the input symbols(EX_OP_AGV_I_DONEGOP1, EX_OP_AGV_I_DONEGOP2). In this way, the device model of the machine can be extracted from the related symbols(EX_OP_MC_, etc.), as shown in Figure 9(b). The procedure for the construction of a device model can be described as follows.- 12 -(1) Identify all corresponding pairs between output symbols and input symbols. While an output symbol triggers a task, the corresponding input symbol reports the completion of the task. For example, EX_OP_AGV_O_GOP1 corresponds toEX_OP_AGV_I_DONEGOP1. (2) Define the states of a device mode using the last naming fields of input/output symbols. In the case of the AGV, we can define four states, GoP1, DoneGoP1, GoP2, and DoneGoP2. (3) Define external (internal) transition functions using output (input) symbols. Once a plant model has been obtained, it becomes possible to perform the PLC simulation by defining the I/O mapping relations between the plant model and the PLC symbols. Through the PLC simulation, we can efficiently check whether the PLC program achieves the control objectives or not.The proposed methodology was implemented in C++language, and test runs were made on a personal computer, as shown in Figure 10. The PLC program shown in Figure 8(a) was written using GX IEC developer version 7.0 provided byMitsubishi Electric Corporation. The GX IEC developer can export a symbol table in the form of an Excel file, as shown in Figure 8(b). The exported symbol table becomes the input for the generation of a plant model. Figure 10 shows that the generated device models by analysing the exported symbol table.4. Discussion and conclusionsThrough PLC simulation, it is possible to analyse control logic in various ways and recognise hidden errors more intuitively. Although PLC simulation can be a very powerful tool for the detailed verification of a production system, the accompanying construction of a plant model requires too much time and effort. To remedy this problem, we have proposed an automated procedure to generate a plant model from the symbol table of a PLC program. To do so, we have also proposed a naming rule for PLC symbols so that the symbol names include sufficient information on the plant model. By analysing the symbol names, a plant model can be extracted automatically. Since a plant consists of various manufacturing devices, we can consider a plant model as a set of device models. To represent such a device model, the proposed method employs Zeigler’s DEVS formalism. We use the atomic model of the DEVS formalism to describe the logical behavior of a device model. In other words, it is necessary to extract the device models from the symbol table in the form of an atomic model of the DEVS formalism. Although the proposed methodology only deals with the local verification of PLC programs, it is also possible to extend the methodologyto include the verification of mechanical aspects of the plant .- 13 -工厂模型生成PLC仿真Hyeong-Tae Park摘要 :本文介绍一个自动程序可编程序控制器(PLC)生成工厂模型仿真。
2010届英语专业毕业论文外文翻译原文格式 范文
2010届英语专业毕业论文外文翻译原文格式范文Main Types of Word MeaningWord meaning is made up of various components which are interrelated and interdependent. These components are commonly described as types of meanings. Two main types of word meaning are grammatical and lexical.A. Grammatical meaning:Grammatical meaning consists of word-class and inflectional paradigm.1. Word-class:When a dictionary lists the function of a word, the definition doesat least two things: it describes the word?s lexical meaning and also gives what is traditionally known as the part ofspeech of the word, which modern linguists call the word-class; e.g.: modern will be markedas an adjective, modernize an a verb, and modernization as a noun.The word-class is essential,for when we use a word in a sentence, we have to take into consideration two factors: its specific lexical meaning and the positionit normally occupies in a sentence, which is determined by the word-class to which the word belongs.As already discussed in the section on “Content words and function words” in Chapter 1,lexical meaning is dominant in content words, whereas grammatical meaning is dominant in function words, but in neither is grammaticalmeaning absent. The two kinds of meaning can be demonstrated by nonsense verse. Nonsense sentences of verses are not strings of random words put together. The words are combined according to regular rules of syntax with grammatical signals, i.e. function words, except that the content words are arbitrarily invented without lexical meaning and what is left is only grammatical meaning. Lewis Carroll?s“ Jabberwocky”, which appears in his book Through the Looking Glass, 1871, is probably themost famous poem in which most of the content words have no meaning—they do not exist inthe vocabulary of the English language. Yet all the sentences “sound” as if they should be English sentences.2. Inflectional paradigm:When used in actual speech, words appear in different forms; e.g.: cat-cats, mouse-mice;to walk, walks walked, to write, writes, wrote, written, etc. Theset of grammatical forms of aword is called its paradigm. Nouns are declined, verbs are conjugated, and gradable adjectives have degrees of comparison. The lexical meaning of a word is the same throughout the paradigm the paradigm; that is, all the word-forms of one and the same word have the same lexical meaning, yet the grammatical meaning varies from one word-form to another, e.g.: catis grammatically singular in meaning while cats is plural; writes denotes third person, singular,present tense, whereas wrote denotes past tense.On the other hand the grammatical meaning is the same in identical sets of individual forms of different words, for example, the past-tense meaning in the word-forms of different verbs(played, sang, worked, etc.), or the grammatical meaning of plurality in the word-forms of various nouns(desks, data, boxes, etc.).B. Lexical meaningAnother component of word meaning is lexical meaning, which is different from grammatical meaning in two aspects: first, the lexical meaning of a word is the same in all the forms of one and the same word while the grammatical meaning varies from one word-form to another; second, every word has a different lexical meaning, whereas the grammatical meaning is the same in identical sets of individual forms of different word. Hence we may describe lexical meaning as that component of meaning proper to the word as a lexical item. Lexical meaning may be subdivided into denotative meaning, connotative meaning, social meaning and affective meaning.1. Denotative meaning:Denotative meaning is sometimes called the conceptual meaning. It is the central factor in linguistic communication. One of the functions of words is to designate or describe something, such as an object, a property, a process or a state of affairs. Users of a language cannottalk about their knowledge of a physical object or a natural phenomenon, unless this knowledge is expressed in words which have the same meaningfor all speakers of a given community. This is the denotative meaning ofa word.“Denotative meaning involves the relationship between a linguisticunit and the non-linguistic entities to which it refers...” (Crystal 1980:104) For instance, if we talk about a “chair”, and there is no actual chair around for us to see, we can give the denotative definition: “it is a piece of furniture for one person to sit on, having a back and, usually, four legs”. This denotative meaning of the word chair can readily be understood by all English-speakingpeople. Denotative meaning is used when the emphasis is on the relationship between languages, on the one hand, and the thing, events,or processes, which are external to the speaker and his language, on the other.The denotative meaning of a word is its definition given in a dictionary. It is that aspect of lexical meaning which makes communication possible. There is no doubt that a chemist knows moreabout water than a layman, or that a physician possesses a much deeper knowledge of what edema implies than a patient. Nevertheless, alayman and a chemist or a physician and his patient can both use the words water and edema, and understand each other.Therefore, denotative meaning is the central factor in linguistic communication.2. Connotative meaning:Connotative meaning refers to the emotional association which a word or a phrase suggests in one?s mind; it is the supplementary value whichis added to the purely denotative meaning of a word. For instance, the denotative meaning of the word m other is “femaleparent”, but it generally connotes love, care, and tenderness. The word January denotes” the first month of the year”, but the connotations of the word may include cold weather, a biting north wind, snow, central heating, skating or the New Year.Connotations may be considered on two levels: connotationspertaining to individualsand connotations pertaining to a group.Each individual has his own sphere of experience, and hisconnotations of words ma well be based on personal experience with the referent. For example, father will have differentconnotations for different people because of their individual experiences. Tradition, physical environment, education, and a common cultural background link people into a whole. And the people who from such an entity share much in the way of outlook and attitudes. So the same word or expression may not possess the same connotation to peopleof different countries. Take the word communist for example, it isalmost a term of abuse in some countries but a term of praise in others.Sometimes the connotative meaning is not limited to one speech community;semanticists write about “semantic universals”. For example, white, to most Chinese andWesterners, has certain similar favorable connotations: “mo rally or spiritually pure; spotless, innocent”. In most cases, however, connotations are apt to vary considerably not only fromage to age. A significant example is the word radioactivity:“...Actually, until the bombardment of Hiroshima and Nagasaki in 1945 the idea of radioactivity was associated in the public mind withthe treatment of cancer and was therefore beneficent in tone. Metaphorically it implied a sort of admirable energy. In 1927 Logan Pearsall wrote of …this radioactive quality of popular i diom? and C.E. Montague?s Disenchantment mentioned …the radioactivity of gifted teaching?. It is clear that the whole concept of radioactivity has changed since these days and now stands chiefly for a fearful threat hanging over mankind.”(Foster 1971:126) Hence connotation is relatively unstable, as compared with denotation, which changes too, but not so quickly.3. Social or stylistic meaning:Language must be adjusted to fit different contexts or situations where it is used for a specific purpose; one adjusts one?s language soas to make it appropriate in various situationsin terms of(1)social relationship between the speakers or correspondents which may be that of friend to friend, or professor to student; (2) the occasion which may be a class reunion or an officialreception; (3) subject matter which may be about serious politicalissues or about films, swimming or food; (4) the mode of discourse spoken or written. We have a scale of speech styles as shown in the following quotation:“Martin Joos (1967) provided one of the most common classifications of speech styles using criterion of formality; this criterion tends to subsume subject matter, the audience, the mode of discourse, and the occasion. Joos recognized five different levels of formality, each implying different forms of speech to fit separate functions: (1) oratorical or “frozen”, (2) deliberate or formal, (3) consultative, (4) casual, (5) intimate”. The frozen and deliberate styles generally occur in written report or in dignified public speech prepared beforehand with a written draft. Words marked in dictionaries as formal, literary,poetic or archaic are to be used in these two styles. Consultative and casual styles occur in everyday use. Consultativestyle is a polite and fairly neutral style; it is used when we are talking to a person whom we do not know well, or to someone who issenior to ourselves in terms of age or social position. Common words are used in this style. Casual style is used in conversation between friends or in personal letters, when the language is informal, familiar, relaxed, warm and friendly. A word or meaning labeled colloquial of informal is appropriate in the casual or intimate style.The frozen and intimate styles do not have much practical use for us. We may further simplify the style into three levels: formal, neutral andinformal. None of these styles is better than any other; appropriateness is the key to the good use of the various styles.3. Affective meaning:Affective meaning is concerned with the expression of feelings and attitudes of the speaker or writer. There are a small number of words in English whose main function is to express emotion. Some words are used not as a mere statement of fact, but to express the speaker?s approval of the person or thing he I talking about. They are purr words. On the other hand, words like gang, niggardly, and to boast always show disapproval or contempt onthe part of the speaker. They are snarl words. Such words are permanently charged with emotion, even when they appear in isolation. Therefore affective meaning is one of the objective semantic features proper to words as lexical items, and forms part of the word meaning, independent of the associations of the individual.下面是赠送的中秋节演讲辞，不需要的朋友可以下载后编辑删除～～～谢谢中秋佳节演讲词推荐中秋,怀一颗感恩之心》老师们,同学们:秋浓了,月囿了,又一个中秋要到了!本周日,农历癿八月十亐,我国癿传统节日——中秋节。
外文翻译及外文原文(参考格式)
外文翻译要求：1、外文资料与毕业设计（论文）选题密切相关，译文准确、质量好。
2、阅读2篇幅以上（10000字符左右）的外文资料，完成2篇不同文章的共2000汉字以上的英译汉翻译3、外文资料可以由指导教师提供，外文资料原则上应是外国作者。
严禁采用专业外语教材文章。
4、排序：“一篇中文译文、一篇外文原文、一篇中文译文、一篇外文原文”。
插图内文字及图名也译成中文。
5、标题与译文格式（字体、字号、行距、页边距等）与论文格式要求相同。
下页附：外文翻译与原文参考格式2英文翻译 (黑体、四号、顶格)外文原文出处：(译文前列出外文原文出处、作者、国籍，译文后附上外文原文)《ASHRAE Handbook —Refrigeration 》.CHAPTER3 .SYSTEM Practices for ammonia 3.1 System Selection 3.2 Equipment3.10 Reciprocating Compressors第3章 氨制冷系统的实施3.1 系统选择在选择一个氨制冷系统设计时，须要考虑一些设计决策要素，包括是否采用（1）单级压缩（2）带经济器的压缩（3）多级压缩（4）直接蒸发（5）满液式（6）液体再循环（7）载冷剂。
单级压缩系统基本的单级压缩系统由蒸发器、压缩机、冷凝器、储液器（假如用的话）和制冷剂控制装置（膨胀阀、浮球阀等）。
1997 ASHRAE 手册——“原理篇”中的第一章讨论了压缩制冷循环。
图1.壳管式经济器的布置外文翻译的标题与译文中的字体、字号、行距、页边距等与论文格式相同。
英文原文(黑体、四号、顶格)英文翻译2（黑体，四号，顶格）外文原文出处：（黑体，四号，顶格）P. Fanning. Nonlinear Models of Reinforced and Post-tensioned Concrete Beams. Lecturer, Department of Civil Engineering, University College Dublin. Received 16 Jul 2001.非线形模型钢筋和后张法预应力混凝土梁摘要:商业有限元软件一般包括混凝土在荷载做用下非线性反应的专用数值模型。
外文文献原稿和译文模板
（空一行）原□□稿（空一行） IntroductionThe "jumping off" point for this paper is Reengineering the Corporation, by Michael Hammer and James Champy. The paper goes on to review the literature on BPR. It explores the principles and assumptions behind reengineering, looks for commonfactors behind its successes or failures, examines case studies, and presents alternatives to "classical" reengineering theory. The paper pays particular attention to the role of information technology in BPR. In conclusion, the paper offers somespecific recommendations regarding reengineering. Old Wine in New BottlesThe concept of reengineering traces its origins back to management theories developed as early as the nineteenth century. The purpose of reengineering is to "make all your processes the best-in-class." Frederick Taylor suggested in the 1880's that managers use process reengineering methods to discover the best processes for performing work, and that these processes be reengineered to optimize productivity. BPR echoes the classical belief that there is one best way to conduct tasks. In Taylor's time, technology did not allow large companies to design processes in across-functional or cross-departmental manner. Specialization was the state-of-theart method to improve efficiency given the technology of the time.（下略）正文内容：新罗马“TimesNewRoman ”字体，小四号字。
外文翻译参考样板
重庆科技学院学生毕业设计（论文）外文译文学院建筑工程学院专业班级工程管理工管2009-02 学生姓名饶建林学号2009442232译文要求1. 外文翻译必须使用签字笔，手工工整书写，或用A4纸打印。
2. 所选的原文不少于10000印刷字符，其内容必须与课题或专业方向紧密相关，由指导教师提供，并注明详细出处。
3. 外文翻译书文本后附原文（或复印件）。
选自：《建筑防火设计》，第6章：新建及现有建筑物的消防安全，作者Jane I. Lataille，ISBN 9781220147935，阳光出版社2003年出版建筑防火设计第6章：新建及现有建筑物的消防安全6-1设计过程建筑物的设计用以满足不同的需求。
建筑物必须有一个特定的空间，容纳特定数量的居住者，拥有特定的服务功能。
还必须有电气，机械和通风系统，用来支持建筑设计功能的使用。
建筑结构，电气和机械系统的设计，需要满足这些需求，以及满足各类法规。
每门学科相互协调设计，以满足该设计项目的设计使用目标。
防火设计同样需要协调。
防火必须融入设计过程，并在整个施工过程中协调。
无论是规划一个新的建筑物或是更改现有的建筑物这都是真实必要的。
作为设计团队的一员，防火工程师需要帮助发现和解决消防问题，让消防问题不在项目中产生负面影响。
有些时候新的建筑和现有建筑物的防火设计方法是不同的，但是基本设计原理是相同的。
有效整合消防的建设、布局和建设的占用需要非常熟悉和了解消防系统的功能。
（详见第2章）。
新建项目的防火设计通常比涉及改变现有建筑物的防火设计更直接。
最合适的消防设计是适应每一个已经存在的工程，而不是被确认的最合适的设计。
优化设计往往是切实可行的，因此通常都容易发展不同的设计。
对现有建筑物进行设计更改，可以说是对所有工程学科的一项挑战。
任何建议的更改都将影响到所有其它领域。
这就是为什么涉及到改变现有建筑物时协调是非常重要的。
有时当前的建筑规范对现有的建筑物无法适用。
这是可以使用备选设计方案来保证当前的设计规范能适用这个设计。
外文译文模板
毕业论文（设计）外文译文题目外商直接投资与投资环境学院经济学院专业经济学年级2010级学生姓名彭雅娟学号*********指导教师李宏伟外商直接投资与投资环境Nihal BayraktarProcedia Economics and Finance 5 (2013) 83 – 92【摘要】外国直接投资(FDI)从发达国家向发展中国家转移，特别是在金融危机之后，引起了更多专家的关注。
在本文中，外商直接投资和“经商容易度”指标之间的联系，被视为外国直接投资方向变化的一个可能因素，本文对此进行了研究。
数据来源是世界银行的营商环境数据库。
这项研究的时间跨度从2004年至2010年，由于本文涵盖了全球金融危机前几年的经济状况，以及在危机时期，外国直接投资的变化方向可以更好地评估对发展中国家“经商容易度”的影响。
初步的研究结果表明，那些在“做生意”时有好记录的国家往往会吸引更多的外国直接投资。
发展中国家“经商容易度”指标的提高,在决定更高的外国直接投资流入这些国家可以有部分解释权。
【关键词】外商直接投资全球营商环境指标发展中国家投资环境1 引言外国直接投资(FDI)，尤其是流入，一直被视为技术外溢，提高效率和经济增长的重要来源。
因此，外国直接投资已经被作了广泛研究。
不同的因素被列为外商直接投资的决定因素如受援国的劳动力成本，人力资本水平，再投资，贸易开放程度，金融开放，国家的规模，自然资源禀赋，宏观经济和政治因素，税收，以及投资环境。
外商直接投资的变化方向从发达国家向发展中国家，特别是在危机之后，已经开始吸引更多的关注。
在本文中，外国直接投资和“经商容易度”之间的联系，作为外国直接投资的变化方向的一种可能来源进行了研究。
数据来源是世界银行的营商环境数据库。
这项研究涵盖了从2004年至2011年，由于本文包括几年的经济和金融全球危机前的经济，以及在危机时期，外国直接投资的变化可以更好地评估对发展中国家“经商容易度”的影响。
外文翻译规范要求及模版格式
(二)外文翻译
每位学生必须阅读2篇以上(10000字符左右)的外文材料，应完成5000汉字以上的英译汉翻译。
加“外文翻译”封面，全文1.5倍行距。
原文可用A4纸复印,每篇原文后附译文(即中文不要直接翻译在原文的同一页)。
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外 文 翻 译
毕业设计题目：
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封面
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(原文1)Headaches: A slowdown in traditional newspaper advertising. The proliferation of media choices, especially the Internet, threaten to cannibalize both readership and prestige.
出处：
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另起一页(译文标题)
(译文1)最头痛的事：传统报纸广告量下降。
随着越来越多的媒体出现在人们面前，
出处：
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