伪随机数产生器

-- The following information has been generated by Exemplar Logic and-- may be freely distributed and modified.---- Design name : pseudorandom---- Purpose : This design is a pseudorandom number generator. This design -- will generate an 8-bit random number using the polynomial p(x) = x + 1. -- This system has a seed generator and will generate 2**8 - 1 unique-- vectors in pseudorandom order. These vectors are stored in a ram which -- samples the random number every 32 clock cycles. This variance of a-- priority encoded seed plus a fixed sampling frequency provides a truely -- random number.---- This design used VHDL-1993 methods for coding VHDL.------------------------------------------------------------------------------Library IEEE ;use IEEE.std_logic_1164.all ;use IEEE.std_logic_arith.all ;entity divide_by_n isgeneric (data_width : natural := 8 );port (data_in : in UNSIGNED(data_width - 1 downto 0) ;load : in std_logic ;clk : in std_logic ;reset : in std_logic ;divide : out std_logic);end divide_by_n ;architecture rtl of divide_by_n issignal count_reg : UNSIGNED(data_width - 1 downto 0) ;constant max_count : UNSIGNED(data_width - 1 downto 0) := (others => '1') ; begincont_it : process(clk,reset)beginif (reset = '1') thencount_reg <= (others => '0') ;elsif (clk = '1' and clk'event) thenif (load = '1') thencount_reg <= data_in ;elsecount_reg <= count_reg + "01" ;end if ;end if;end process ;divide <= '1' when count_reg = max_count else '0' ; end RTL ;Library IEEE ;use IEEE.std_logic_1164.all ;use IEEE.std_logic_arith.all ;entity dlatrg isgeneric (data_width : natural := 16 );port (data_in : in UNSIGNED(data_width - 1 downto 0) ;clk : in std_logic ;reset : in std_logic ;data_out : out UNSIGNED(data_width - 1 downto 0));end dlatrg ;architecture rtl of dlatrg isbeginlatch_it : process(data_in,clk,reset)beginif (reset = '1') thendata_out <= (others => '0') ;elsif (clk = '1') thendata_out <= data_in ;end if;end process ;end RTL ;Library IEEE ;use IEEE.std_logic_1164.all ;use IEEE.std_logic_arith.all ;entity lfsr isgeneric (data_width : natural := 8 ); port (clk : in std_logic ;reset : in std_logic ;data_out : out UNSIGNED(data_width - 1 downto 0));end lfsr ;architecture rtl of lfsr issignal feedback : std_logic ;signal lfsr_reg : UNSIGNED(data_width - 1 downto 0) ;beginfeedback <= lfsr_reg(7) xor lfsr_reg(0) ;latch_it : process(clk,reset)beginif (reset = '1') thenlfsr_reg <= (others => '0') ;elsif (clk = '1' and clk'event) thenlfsr_reg <= lfsr_reg(lfsr_reg'high - 1 downto 0) & feedback ;end if;end process ;data_out <= lfsr_reg ;end RTL ;Library IEEE ;use IEEE.std_logic_1164.all ;use IEEE.std_logic_arith.all ;entity priority_encoder isgeneric (data_width : natural := 25 ;address_width : natural := 5 ) ;port (data : in UNSIGNED(data_width - 1 downto 0) ;address : out UNSIGNED(address_width - 1 downto 0) ;none : out STD_LOGIC);end priority_encoder ;architecture rtl of priority_encoder isattribute SYNTHESIS_RETURN : STRING ;FUNCTION to_stdlogic (arg1:BOOLEAN) RETURN STD_LOGIC IS BEGINIF(arg1) THENRETURN('1') ;ELSERETURN('0') ;END IF ;END ;function to_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) return UNSIGNED is variable result: UNSIGNED(SIZE-1 downto 0);variable temp: integer;attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ; begintemp := ARG;for i in 0 to SIZE-1 loopif (temp mod 2) = 1 thenresult(i) := '1';elseresult(i) := '0';end if;if temp > 0 thentemp := temp / 2;elsetemp := (temp - 1) / 2;end if;end loop;return result;end;constant zero : UNSIGNED(data_width downto 1) := (others => '0') ; beginPRIO : process(data)variable temp_address : UNSIGNED(address_width - 1 downto 0) ;begintemp_address := (others => '0') ;for i in data_width - 1 downto 0 loopif (data(i) = '1') thentemp_address := to_unsigned(i,address_width) ;exit ;end if ;end loop ;address <= temp_address ;none <= to_stdlogic(data = zero) ;end process ;end RTL ;Library IEEE ;use IEEE.std_logic_1164.all ;use IEEE.std_logic_arith.all ;use IEEE.std_logic_unsigned.all ;entity ram isgeneric (data_width : natural := 8 ;address_width : natural := 8);port (data_in : in UNSIGNED(data_width - 1 downto 0) ;address : in UNSIGNED(address_width - 1 downto 0) ;we : in std_logic ;clk : in std_logic;data_out : out UNSIGNED(data_width - 1 downto 0));end ram ;architecture rtl of ram istype mem_type is array (2**address_width downto 0) of UNSIGNED(data_width - 1 downto 0) ;signal mem : mem_type ;signal addr_reg : unsigned (address_width -1 downto 0);begindata_out <= mem(conv_integer(addr_reg)) ;I0 : processbeginwait until clk'event and clk = '1';if (we = '1') thenmem(conv_integer(address)) <= data_in ;end if ;addr_reg <= address;end process ;end RTL ;Library IEEE ;use IEEE.std_logic_1164.all ;use IEEE.std_logic_arith.all ;entity tbuf isgeneric (data_width : natural := 16 );port (data_in : in UNSIGNED(data_width - 1 downto 0) ;en : in std_logic ;data_out : out UNSIGNED(data_width - 1 downto 0));end tbuf ;architecture rtl of tbuf isbeginthree_state : process(data_in,en)beginif (en = '1') thendata_out <= data_in ;elsedata_out <= (others => 'Z') ;end if;end process ;end RTL ;Library IEEE ;use IEEE.std_logic_1164.all ;use IEEE.std_logic_arith.all ;entity pseudorandom isgeneric (data_width : natural := 8 );port (seed : in UNSIGNED (24 downto 0) ;init : in UNSIGNED (4 downto 0) ;load : in std_logic ;clk : in std_logic ;reset : in std_logic ;read : in std_logic ;write : in std_logic ;rand : out UNSIGNED (7 downto 0) ;none : out std_logic);end pseudorandom ;architecture rtl of pseudorandom issignal latch_seed : UNSIGNED(24 downto 0) ; signal encoder_address : UNSIGNED(4 downto 0) ; signal random_data : UNSIGNED(7 downto 0) ; signal write_enable : std_logic ;signal ram_data : UNSIGNED(7 downto 0) ;beginI0 : entity work.dlatrg(rtl)generic map (25)port map (seed,read,reset,latch_seed) ;I1 : entity work.priority_encoder(rtl)generic map (25,5)port map (latch_seed,encoder_address,none) ;I2 : entity work.ram(rtl)generic map (8,5)port map (random_data,encoder_address,write_enable,clk,ram_data) ;I3 : entity work.tbuf(rtl)generic map (8)port map (ram_data,write,rand) ;I4 : entity work.lfsr(rtl)generic map (8)port map (clk,reset,random_data) ;I5 : entity work.divide_by_n(rtl)generic map (5)port map (init,load,clk,reset,write_enable) ;end rtl ;。