FPGA可编程逻辑器件芯片EP2S15F672C6N中文规格书

(5) We recommend use of ALTMEMPHY AFI mode to achieve these quoted maximum clock rate due to lower performance of Non-AFI mode.
External Memory I/O Timing Specifications
Stratix III Device Handbook, Volume 2
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics I/O Timing
Figure 1–5. Output Register Clock to Output Timing Diagram
Datain Clock
Clock pad to output Register delay
Output Register micro tCO
Output Register to output pin delay
Output
Simulation using IBIS models is required to determine the delays on the PCB traces in addition to the output pin delay timing reported by the Quartus II software and the timing model in the device handbook.
DDR2 SDRAM Single-ended DQS
DDR SDRAM Single-ended DQS
1.8V SSTL
1.8V SSTL
2.5V SSTL
×4, ×8 181 306 234 326 257 326 257 326 257 326 ×4, ×8 231 256 284 276 307 276 307 276 307 276 ×4, ×8 231 256 284 261 307 261 307 261 307 261
VCCL = 1.1V SW (ps)
VCCL = 1.1V SW (ps)
VCCL = 0.9V SW (ps)
DDR3 SDRAM (with 8 or 10 tap phase offset, 300MHz–400MHz)
DDR3 SDRAM (with Deskew circuitry, 401MHz–533MHz)
Figure 1–6. Output Delay Timing Reporting Setup Modeled by Quartus II Software for Single-Ended Outputs and Dedicated Differential Outputs (Note 1)
VCCIO
Memory Standards DDR2 SDRAM (5)
C2 VCCL = 1.1V
300
C3, I3 VCCL = 1.1V
267
C4, I4 VCCL = 1.1V
233
C4L, I4L
VCCL = 1.1V 233
VCCL = 0.9V 167
Unit MHz
DDR SDRAM
200
200
.
Table 1–30. Sampling Window (SW) - Read Side (Note 1) (Part 1 of 2)
C2
C3, I3
C4, I4
C4L, I4L
C4L, I4L
Memory Type
I/O Standard
Width
VCCL = 1.1V SW (ps)
VCCL = 1.1V SW (ps)
1. Simulate the output driver of choice into the generalized test setup, using values from Table 1–39.
2. Record the time to VMEAS at the far end of the PCB trace.
Stratix III Device Handbook, Volume 2
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics I/O Timing
Figure 1–7 and Figure 1–8 show the model of the circuit that is represented by the output timing of the Quartus II software for differential outputs with single and multiple external resistors.
Figure 1–7. Output Delay Timing Reporting Setup Modeled by Quartus II Software for Differential Outputs with Single External Resistor
3. Simulate the output driver of choice into the actual PCB trace and load, using the appropriate IBIS model or capacitance value to represent the load.
Table 1–30 and Table 1–31 list Stratix III device timing uncertainties on the read and write data paths. Use these specifications to determine timing margins for source synchronous paths between the Stratix III FPGA and the external memory device. Refer to the figure for “SW (sampling window)” in “Glossary”
QDRII/II+ SRAM
QDRII/II+ SRAM Emulation (2)
1.5 V HSTL
1.5 V HSTL
×9, ×18, 261 286 314 291 337 291 337 291 337 291 ×36
×36
261 328 314 337 337 350 337 350 337 350
The Quartus II software reports the timing with the conditions shown in Table 1–39 using the above equation. Figure 1–6 shows the model of the circuit that is represented by the output timing of the Quartus II software.
1.5V SSTL
1.5V SSTL
×4, ×8
Setup Hold Setup Hold Setup Hold Setup Hold Setup Hold 172 296 234 296 257 311 257 311 257 311
×4, ×8 300 213 — — — — — — — —
DDR2 SDRAM Differential DQto Table 1–29:
(1) The supported operating frequencies listed here are memory interface maximums for the FPGA device family. Your design’s actual achievable performance is based on design- and system-specific factors, as well as static timing analysis of the completed design.
(3) The values apply to column I/Os, Rows I/Os and Hybrid mode interface. Column I/Os refers to Top and Bottom I/Os. Row I/Os refers to Left and Right I/Os. Hybrid mode refers to DQ/DQS groups wrapping over Column I/Os and Row I/Os of the device.
4. Record the time to VMEAS at the far end of the PCB trace.
5. Compare the results of steps 2 and 4. The increase or decrease in delay should be added to or subtracted from the I/O Standard Output Adder delays to yield the actual worst-case propagation delay (clock-to-output) of the PCB trace.
(4) It may be possible to close timing at up to 33MHz higher, depending on your design and the Quartus setting used. Refer to the section on advanced settings in External Memory PHY Interface (ALTMEMPHY) Megafunction User Guide.