CD4031 CMOS 64级静态移位寄存器

TL F 5962
CD4031BM CD4031BC 64-Stage Static Shift Register
February 1988
CD4031BM CD4031BC
64-Stage Static Shift Register
General Description
The CD4031BM CD4031BC is an integrated complemen-tary MOS (CMOS) 64-stage fully static shift register Two data inputs DATA IN and RECIRCULATE IN and a MODE CONTROL input are provided Data at the DATA input (when MODE CONTROL is low)or data at the RECIRCU-LATE input (when MODE CONTROL is high) which meets the setup and hold time requirements is entered into the first stage of the register and is shifted one stage at each positive transition of the CLOCK
Data output is available in both true and complement forms from the 64th stage Both the DATA OUT (Q)AND DATA OUT (Q)outputs are fully buffered
The CLOCK input of the CD4031BM CD4031BC is fully buffered and present only a standard input load capaci-tance However a DELAYED CLOCK OUTPUT (CL D )has been provided to allow reduced clock drive fan-out and tran-sition time requirements when cascading packages
Features
Y Wide supply voltage range 3 0V to 15V Y High noise immunity 0 45V DD (typ )
Y
Low power TTL fan out of 2driving 74L
compatibility
or 1driving 74LS
Y
Fully static operation
DC to 8MHz V DD e 10V (typ )
Y
Fully buffered clock input 5pF (typ )
input capacitance
Y Single phase clocking requirements
Y
Delayed clock output for reduced clock drive require-ments
Y Fully buffered outputs
Y High current sinking capability 1 6mA
Y
Q output V DD e 5V and 25 C
Logic and Connection Diagrams
TL F 5962–1
Dual-In-Line Package
TL F 5962–2
Top View
Order Number CD4031B
C 1995National Semiconductor Corporation
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Notes 1and 2)
If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (V DD )
b 0 5V to a 18V Input Voltage (V IN )
b 0 5V to V DD a 0 5V Storage Temperature Range (T S )b 65 C to a 150 C
Power Dissipation (P D )Dual-In-Line 700mW Small Outline 500mW Lead Temp (T L )(Soldering 10sec )
260 C
Recommended Operating Conditions (Note 2)
Supply Voltage (V DD )3V to 15V Input Voltage (V IN )
0V to V DD
Operating Temperature Range (T A )CD4031BM b 55 C to a 125 C CD4031BC
b 40 C to a 85 C
DC Electrical Characteristics (Note 2)CD4031BM
Symbol Parameter Conditions
b 55 C
a 25 C
a 125 C
Units Min Max Min Typ Max Min Max I DD
Quiescent Device V DD e 5V V IN e V DD or V SS 50 015150m A Current
V DD e 10V V IN e V DD or V SS 100 0110300m A V DD e 15V V IN e V DD or V SS 20
0 0220600m A V OL
Low Level Output V DD e 5V 0 0500 050 05V Voltage
V DD e 10V V IH e V DD V IL e 0V l I O l k 1m A
0 0500 050 05V V DD e 15V (0 05
0 05
0 05
V V OH
High Level Output V DD e 5V 4 954 9554 95V Voltage V DD e 10V V IH e V DD V IL e 0V l I O l
k 1m A
9 959 95109 95V V DD e 15V
(
14 95
14 951514 95
V
V IL
Low Level Input V DD e 5V V O e 0 5V or 4 5V 1 52 251 51 5V Voltage V DD e 10V V O e 1 0V or 9 0V l I O l k 1m A
3 04 53 03 0V V DD e 15V V O e 1 5V or 13 5V (4 0
6 75
4 0
4 0
V V IH
High Level Input V DD e 5V V O e 0 5V or 4 5V 3 53 52 753 5V Voltage
V DD e 10V V O e 1 0V or 9 0V l I O l
k 1m A
7 07 05 57 0V V DD e 15V V O e 1 5V or 13 5V (11 011 08 2511 0V I OL
Low Level Output V DD e 5V V O e 0 4V V IH e V DD 2 31 93 81 3mA Current Q Output V DD e 10V V O e 0 5V V IL e 0V 5 14 28 42 8mA (Note 3)
V DD e 15V V O e 1 5V
(10 58 8176 1mA I OL
Low Level Output V DD e 5V V O e 0 4V V IH e V DD 0 640 510 880 36mA Current Q and CL D V DD e 10V V O e 0 5V V IL e 0V 1 61 32 250 9mA Outputs (Note 3)V D e 15V V O e 1 5V (4 2
3 4
8 8
2 4
mA I OH
High Level Output V DD e 5V V O e 4 6V V IH e V DD b 0 64b 0 51b 0 88b 0 36mA Current All Outputs V DD e 10V V O e 9 5V V IL e 0V
b 1 6b 1 3b 2 25b 0 9mA (Note 3)V DD e 15V V O e 13 5V (
b 4 2
b 3 4b 8 8
b 2 4
mA
I IN
Input Current
V DD e 15V V IN e 0V b 0 1
b 10b 5b 0 1
b 1 0m A
V DD e 15V V IN e 15V
0 1
10b 5
0 11 0m A
Truth Tables
Mode Control (Data Selection)Mode Data Recirculate
Data Into Control
In In
First Stage
00X 001X 11X 001
X
1
1
Each Stage
D n CL Q n 0L 01L 1X
K
NC
X e irrelevant
NC e no change L e Low to High level transition
K e High to Low level transition
2
DC Electrical Characteristics (Note 2)CD4031BC
Symbol Parameter Conditions
b 40 C
a 25 C
a 85 C
Units Min Max Min Typ Max Min Max I DD
Quiescent Device V DD e 5V V IN e V DD or V SS 200 0120150m A Current
V DD e 10V V IN e V DD or V SS 400 0140300m A V DD e 15V V IN e V DD or V SS 800 0280600m A V OL
Low Level Output V DD e 5V
0 0500 050 05V Voltage
V DD e 10V V IH e V DD V IL e 0V l I O l k 1m A 0 0500 050 05V V DD e 15V (0 05
0 05
0 05
V V OH
High Level Output V DD e 5V 4 95
4 9554 95V Voltage V DD e 10V V IH e V DD V IL e 0V l I O l k 1m A 9 95
9 95109 95V V DD e 15V
(
14 9514 951514 95
V
V IL
Low Level Input V DD e 5V V O e 0 5V or 4 5V 1 52 251 51 5V Voltage V DD e 10V V O e 1 0V or 9 0V l I O l k 1m A
3 04 53 03 0V V DD e 15V V O e 1 5V or 13 5V (4 0
6 75
4 0
4 0
V V IH
High Level Input V DD e 5V V O e 0 5V or 4 5V 3 53 52 753 5V Voltage
V DD e 10V V O e 1 0V or 9 0V l
I O l k 1m A
7 07 05 57 0V V DD e 15V V O e 1 5V or 13 5V (11 011 08 2511 0V I OL
Low Level Output V DD e 5V V O e 0 4V V IH e V DD 1 81 63 81 3mA Current Q Output V DD e 10V V O e 0 5V V IL e 0V 4 03 58 42 8mA (Note 3)
V DD e 15V V O e 1 5V
(8 77 5176 1mA I OL
Low Level Output V DD e 5V V O e 0 4V V IH e V DD 0 520 440 880 36mA Current Q and CL D V DD e 10V V O e 0 5V V IL e 0V
1 31 1
2 250 9mA Outputs V DD e 15V V O e 1 5V (
3 6
3 0
8 8
2 4
mA (Note 3)
I OH
High Level Output V DD e 5V V O e 4 6V V IH e V DD b 0 52b 0 44b 0 88b 0 36mA Current All Outputs V DD e 10V V O e 9 5V V IL e 0V
b 1 3b 1 1b 2 25b 0 9mA (Note 3)V DD e 15V V O e 13 5V (
b 3 0
b 3 0b 8 8b 2 4
mA
I IN
Input Current
V DD e 15V V IN e 0V
b 0 3
b 10b 5b 0 3
b 1 0m A
V DD e 15V V IN e 15V
0 3
10b 5
0 31 0m A
Note 1 ‘‘Absolute Maximum Ratings’’are those values beyond which the safety of the device cannot be guaranteed They are not meant to imply that the devices should be operated at these limits The tables of ‘Recommended Operating Conditions’’and ‘‘Electrical Characteristics’’provide conditions for actual device operation
Note 2 V SS e 0V unless otherwise specified Note 3 I OH and I OL are tested one output at a time
Switching Time Waveforms
TL F 5962–3
3
AC Electrical Characteristics
T A e25 C C L e50pF R L e200k Input t r e t f e20ns unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
t PHL t PLH Propagation Delay Time Clock to Q and Q V CC e5V300600ns
V CC e10V125250ns
V CC e15V100200ns
t PHL t PLH Propagation Delay Time Clock to CL D V CC e5V125250ns
V CC e10V60125ns
V CC e15V50100ns
t THL t TLH Output Transition Time All Outputs V CC e5V100200ns
V CC e10V50100ns
V CC e15V4080ns
t SU
0Minimum Data Setup Time DATA IN or V CC e5V100200ns
t SU
1RECIRCULATE IN to Clock V CC e10V50100ns
V CC e15V4080ns
t H 0Minimum Data Hold Time Clock to DATA IN V CC e5V100200ns
t H 1or RECIRCULATE IN V CC e10V50100ns
V CC e15V4080ns
t WL t WH Minimum Clock Pulse Width V CC e5V15030ns
V CC e10V60125ns
V CC e15V50100ns
f CL Maximum Clock Frequency V CC e5V1 63 2MHz
V CC e10V4 08 0MHz
V CC e15V5 010MHz
t RCL t FCL Maximum Clock Input Rise and Fall Times V CC e5V15m s (Note4)V CC e10V10m s
V CC e15V5m s
C IN Input Capacitance Any Input57 5pF
AC Parameters are guaranteed by DC correlated testing
Note4 When clocking cascaded packages in parallel one should insure that t r CL s2(t PD b t H)where t PD e the propagation delay of the driving stage and t H e the hold time of the driven stage
Block Diagram
cascading packages using DELAYED CLOCK(CL D)output
TL F 5962–4
4
Physical Dimensions inches(millimeters)
Ceramic Dual-In-Line Package(J)
Order Number CD4031BMJ or CD4031BCJ
NS Package Number J16A
5
C D 4031B M C D 4031B C 64-S t a g e S t a t i c S h i f t R e g i s t e r
Physical Dimensions inches (millimeters)(Continued)
Molded Dual-In-Line Package (N)
Order Number CD4031BMN or CD4031BCN
NS Package Number N16E
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be reasonably expected to result in a significant injury to the user
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