FPGA可编程逻辑器件芯片XC2V4000-6FG456C中文规格书

Chapter 1:Introduction to the RocketIO GTX Transceiver
Table 1-3 lists alphabetically the signal names, clock domains, directions, and descriptions for the GTX_DUAL ports, and provides links to their detailed descriptions.
MGTRREF_R In (Pad)TXT only: Reference resistor input for the X1 column. Analog Design Guidelines (page 254)MGTRREF_L In (Pad)
TXT only: Reference resistor input for the X0 column. Analog Design Guidelines (page 254)
MGTRXN0MGTRXP0MGTRXN1MGTRXP1In (Pad)Differential complements forming a
differential receiver input pair for
each transceiver.
RX Termination and
Equalization (page 162)
MGTTXN0MGTTXP0MGTTXN1MGTTXP1
Out (Pad)
Differential complements forming a differential transmitter output pair for each transceiver.RX Termination and Equalization (page 162)
Table 1-2:
GTX_DUAL Analog Pin Summary (Cont’d)
Pin
Dir Description
Section (Page)
Table 1-3:
GTX_DUAL Port Summary Port
Dir Domain Description
Section (Page)CLKIN
In
Async
Reference clock input to the shared PMA PLL.Shared PMA PLL (page 87), Clocking (page 98),
Power Control (page 110)DADDR[6:0]In DCLK DRP address bus.Dynamic Reconfiguration Port (page 117)
DCLK In N/A DRP interface clock.Dynamic Reconfiguration Port (page 117)
DEN
In DCLK Enables DRP read or write operations.
Dynamic Reconfiguration Port (page 117)
DFECLKDLYADJ0[5:0]DFECLKDLYADJ1[5:0]
In RXUSRCLK2DFE clock delay adjust control for each transceiver.Decision Feedback Equalization (page 167)DFECLKDLYADJMONITOR0[5:0]DFECLKDLYADJMONITOR1[5:0]
Out RXUSRCLK2DFE clock delay adjust monitor for each transceiver.
Decision Feedback Equalization (page 167)DFEEYEDACMONITOR0[4:0]DFEEYEDACMONITOR1[4:0]Out RXUSRCLK2Vertical Eye Scan for each transceiver (voltage domain).Decision Feedback Equalization (page 167)DFESENSCAL0[2:0]DFESENSCAL1[2:0]Out
RXUSRCLK2
DFE calibration status.Decision Feedback Equalization (page 167)DFETAP10[4:0]DFETAP11[4:0]
In RXUSRCLK2
DFE tap 1 weight value control for each transceiver (5-bit resolution).
Decision Feedback Equalization (page 167)
DFETAP1MONITOR0[4:0]DFETAP1MONITOR1[4:0]
Out RXUSRCLK2
DFE tap 1 weight value monitor
for each transceiver (5-bit
resolution).
Decision Feedback
Equalization (page 167)
Ports and Attributes
CLK25_DIVIDER Integer Sets the divider used to divide CLKIN
down to an internal rate close to
25MHz.
Clocking (page98),
Power Control (page111)
CLKINDC_B Boolean Must be set to TRUE. Oscillators
driving the dedicated reference clock
inputs must be AC coupled.
Clocking (page98), Analog
Design Guidelines
(page254)
CLKRCV_TRST Boolean When set to TRUE, switches on the
differential clock input pair’s internal
termination resistors.
Clocking (page98), Analog
Design Guidelines
(page254)
CM_TRIM_0 CM_TRIM_1
2-bit
Binary
Adjusts the input common mode
values.
RX Termination and
Equalization (page163)
COM_BURST_VAL_0[3:0] COM_BURST_VAL_1[3:0]
4-bit
Binary
Number of bursts transmitted for a
SATA COM sequence.
TX Out-of-Band/Beacon
Signaling (page158)
COMMA_10B_ENABLE_0 COMMA_10B_ENABLE_110-bit
Binary
Sets which bits of
MCOMMA/PCOMMA must be
matched to incoming data and which
bits are don't cares.
Configurable Comma
Alignment and Detection
(page193)
COMMA_DOUBLE_0 COMMA_DOUBLE_1Boolean
When TRUE, a PCOMMA match
followed immediately by an
MCOMMA match is required for
comma detection. Used to detect
A1/A2 framing characters for SONET.
Configurable Comma
Alignment and Detection
(page193)
DEC_MCOMMA_DETECT_0 DEC_MCOMMA_DETECT_1Boolean
Enables detection of negative 8B/10B
commas.
Configurable 8B/10B
Decoder (page201)
DEC_PCOMMA_DETECT_0 DEC_PCOMMA_DETECT_1Boolean
Enables detection of positive 8B/10B
commas.
Configurable 8B/10B
Decoder (page201)
DEC_VALID_COMMA_ONLY_0 DEC_VALID_COMMA_ONLY_1Boolean
Limits the set of commas to which
RXCHARISCOMMA responds.
Configurable 8B/10B
Decoder (page201)
DFE_CAL_TIME
5-bit
Binary
DFE calibration time.
Decision Feedback
Equalization (page168)
DFE_CFG_0[9:0] DFE_CFG_1[9:0]10-bit
Binary
DFE configuration settings.
Decision Feedback
Equalization (page168)
GEARBOX_ENDEC_0 GEARBOX_ENDEC_1
3-bit
Binary
Selects Gearbox mode.
TX Gearbox (page135), RX
Gearbox (page232)
MCOMMA_10B_VALUE_0 MCOMMA_10B_VALUE_110-bit
Binary
Defines comma minus to raise
RXCOMMADET and align the parallel
data.
Configurable Comma
Alignment and Detection
(page194)
MCOMMA_DETECT_0 MCOMMA_DETECT_1Boolean
Set to TRUE to allow minus comma
detection and alignment.
Configurable Comma
Alignment and Detection
(page194)
OOB_CLK_DIVIDER Integer Sets the squelch clock rate based on
CLKIN.
RX OOB/Beacon Signaling
(page175)
Table 1-5:GTX_DUAL Attribute Summary (Cont’d)
Attribute Type Description Section (Page)
Chapter 2:RocketIO GTX Transceiver Wizard
Chapter 3:Simulation
phased out after ISE 11.1 software. The FAST setting is highly recommended for new
customer designs.
This attribute can be used independently of the SIM_GTXRESET_SPEEDUP attribute.
SIM_PLL_PERDIV2
The GTX_DUAL tile contains an analog PLL to generate the transmit and receive clocks
out of a reference clock. Because HDL simulators do not fully model the analog PLL, the
GTX_DUAL Smartmodel includes an equivalent behavioral model to simulate the PLL
output. The SIM_PLL_PERDIV2 attribute is used by the behavioral model to generate the
PLL output as accurately as possible. It must be set to one-half the period of the shared
PMA PLL. See “Examples,” page 58 for how to calculate SIM_PLL_PERDIV2 for a given
rate.
SIM_RECEIVER_DETECT_PASS
The GTX_DUAL includes a TXDETECTRX feature that allows the transmitter to detect
whether its serial ports are currently connected to a receiver by measuring rise time on the
TXP/TXN differential pin pair (see “Receive Detect Support for PCI Express Operation,”
page 153).
The GTX_DUAL SmartModel includes an attribute for simulating TXDETECTRX called
SIM_RECEIVER_DETECT_PASS. This attribute allows TXDETECTRX to be simulated for
each GTX transceiver without modelling the measurement of rise time on the TXP/TXN
differential pin pair.
By default, SIM_RECEIVER_DETECT_PASS is set to TRUE. When TRUE, the attribute
models a connected receiver, and TXDETECTRX operations indicate a receiver is
connected. To model a disconnected receiver, SIM_RECEIVER_DETECT_PASS for the
transceiver is set to FALSE.
Power-Up and Reset
Link Idle Reset
To simulate correctly, the Link Idle Reset circuit, described in“Link Idle Reset Support,”
page 105, must be implemented and connected to each GTX_DUAL instance. This circuit is
included automatically when the Wizard is used to configure the GTX_DUAL instance.
T oggling GSR
The GSR signal is a global routing of nets in the design that provide a means of setting or
resetting applicable components in the device during configuration.
The simulation behavior of this signal is modeled using the glbl module in Verilog and the
ROC/ROCBUF components in VHDL.
Providing Clocks in Simulation
In simulation, the clocks inside the PMA are generated using the SIM_PLL_PERDIV2
parameter (in picoseconds). Any other clocks driven into the user clock must have the
same level of precision, or TX buffer errors (and RX buffer errors in systems without clock
correction) can result. When generating USRCLK, USRCLK2, or reference clock signals in
the test bench, the clock periods must be related to SIM_PLL_PERDIV2 and also be a round
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