FPGA可编程逻辑器件芯片EP3SL70F484I4中文规格书
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Parameter
IP Generated Parameter Value Default Value Description coef_b_5
coef_a_5These parameters are not available in m27×27 operational mode.
coef_b_6
coef_a_6coef_b_7coef_a_7Related Information
•
Maximum Input Data Width for Fixed-point Arithmetic on page 78•
Maximum Output Data Width for Fixed-point Arithmetic on page 80•
Configurations for Input, Pipeline, and Output Registers on page 63•Native Fixed Point DSP Intel Agilex FPGA IP Signals on page 92
5.5.5. Accumulator/Output Chaining
Table 50.Accumulator/Output Chaining Tab
5.Native Fixed Point DSP Intel Agilex FPGA IP Core References
UG-20213 | 2021.02.05
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5.Native Fixed Point DSP Intel Agilex FPGA IP Core References
UG-20213 | 2021.02.05
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Parameter IP Generated Parameter Value Default Value
Description •
m9×9_sumof4•
m18×18_sumof2•
m18×18_plus36•
m18×18_systolic •m27×27
Enable chainout port enable_chainout No
Yes No Select to enable chainout port.Only available for the following operation modes:
•m9×9_sumof4
•m18×18_sumof2
•m18×18_plus36
•m18×18_systolic
•m27×27
Enable disable_chainout disable_chainout No
Yes No Select to enable disable_chainout port.Only available for the following operation modes:
•m9×9_sumof4
•m18×18_sumof2
•m18×18_plus36
•m18×18_systolic
•m27×27
Set the chainin and chainout width chain_inout_width 0
44
640Specify the width of chainin and chainout buses.Only available for the following operation modes:
•m9×9_sumof4
•m18×18_sumof2
•m18×18_plus36
•m18×18_systolic
•
m27×27
Related Information
•
Maximum Input Data Width for Fixed-point Arithmetic on page 78•
Maximum Output Data Width for Fixed-point Arithmetic on page 80•
Configurations for Input, Pipeline, and Output Registers on page 63•Native Fixed Point DSP Intel Agilex FPGA IP Signals on page 92
5.5.
6. Pipelining
Table 51.Pipelining Tab
5.Native Fixed Point DSP Intel Agilex FPGA IP Core References
UG-20213 | 2021.02.05
Send Feedback。