HM5225165BTT-75资料
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ion
Write enable
t uc
Input/output mask Clock input Clock enable Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit No connection 5
54-pin TSOP VCC DQ0 VCCQ DQ1 DQ2 VSSQ DQ3 DQ4 VCCQ DQ5 DQ6 VSSQ DQ7 VCC DQML WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ15 VSSQ DQ14 DQ13 VCCQ DQ12 DQ11 VSSQ DQ10 DQ9 VCCQ DQ8 VSS NC DQMU CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS
54-pin TSOP VCC NC VCCQ NC DQ0 VSSQ NC NC VCCQ NC DQ1 VSSQ NC VCC NC WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS NC VSSQ NC DQ3 VCCQ NC NC VSSQ NC DQ2 VCCQ NC VSS NC DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS
EO
Type No. HM5225165BTT-75* HM5225165BTT-A6 HM5225165BTT-B6* 2
1
Ordering Information
Frequency 133 MHz 100 MHz 100 MHz 133 MHz 100 MHz 100 MHz 133 MHz 100 MHz 100 MHz 133 MHz 100 MHz 100 MHz 133 MHz 100 MHz 100 MHz 133 MHz 100 MHz 100 MHz CAS latency 3 2/3 3 3 2/3 3 3 2/3 3 3 2/3 3 3 2/3 3 3 2/3 3 Package 400-mil 54-pin plastic TSOP II (TTP-54D)
od
Pin name Function DQMU/DQML
Write enable Input/output mask
t uc
Clock input Clock enable Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit No connection 3
HM5225165B/HM5225805B/HM5225405B-75/A6/B6
Pin Arrangement (HM5225405B)
EO
Pin Description
Pin name A0 to A12, BA0, BA1 Function Address input Row address Column address DQ0 to DQ3 CS RAS CAS Data-input/output Chip select
This product became EOL in April, 2004.
Pr
od
t uc
HM5225165B/HM5225805B/HM5225405B-75/A6/B6
• Byte control by DQM : DQM (HM5225805B/HM5225405B) : DQMU/DQML (HM5225165B) • Refresh cycles: 8192 refresh cycles/64 ms • 2 variations of refresh Auto refresh Self refresh
L
Bank select address
Row address strobe command Column address strobe command
Pr
(Top view) WE A0 to A12 A0 to A9, A11 BA0/BA1 (BS) DQM CLK CKE VCC VSS VCCQ VSS Q NC Data Sheet E0082H10
3.3 V power supply Clock frequency: 133 MHz/100 MHz (max) LVTTL interface Single pulsed RAS 4 banks can operate simultaneously and independently Burst read/write operation and burst read/single write operation capability Programmable burst length: 1/2/4/8 2 variations of burst sequence Sequential (BL = 1/2/4/8) Interleave (BL = 1/2/4/8) • Programmable CAS latency: 2/3
Pin Arrangement (HM5225165B)
EO
Pin Description
Pin name A0 to A12, BA0, BA1 Function Address input Row address Column address DQ0 to DQ15 CS RAS CAS Data-input/output Chip select
Notes: 1. 100 MHz operation at CAS latency = 2. 2. 66 MHz operation at CAS latency = 2.
L
Pr
Data Sheet E0082H10
od t uc
2
HM5225165B/HM5225805B/HM5225405B-75/A6/B6
L
Bank select address
Row address strobe command Column address strobe command
Pr
(Top view) WE A0 to A12 A0 to A9 BA0/BA1 (BS) DQM CLK CKE VCC VSS VCCQ VSS Q NC Data Sheet E0082H10
54-pin TSOP VCC DQ0 VCCQ NC DQ1 VSSQ NC DQ2 VCCQ NC DQ3 VSSQ NC VCC NC WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ7 VSSQ NC DQ6 VCCQ NC DQ5 VSSQ NC DQ4 VCCQ NC VSS NC DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS
HM5225165B/HM5225805B/HM5225405B-75/A6/B6
Pin Arrangement (HM5225805B)
EO
Pin Description
Pin name A0 to A12, BA0, BA1 Function Address input Row address Column address DQ0 to DQ7 CS RAS CAS Data-input/output Chip select 4
The HM5225165B is a 256-Mbit SDRAM organized as 4194304-word × 16-bit × 4 bank. The HM5225805B is a 256-Mbit SDRAM organized as 8388608-word × 8-bit × 4 bank. The HM5225405B is a 256-Mbit SDRAM organized as 16777216-word × 4-bit × 4 bank. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.
HM5225165B-75/A6/B6 HM5225805B-75/A6/B6 HM5225405B-75/A6/B6
EO
Description Features
• • • • • • • •
256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword × 16-bit × 4-bank/8-Mword × 8-bit × 4-bank /16-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAM
L
Bank select address
Row address strobe command Column address strobe command
Pr
(Top view) WE A0 to A12 A0 to A8 BA0/BA1 (BS) CLK CKE VCC VSS VCCQ VSS Q NC Data Sheet E0082H10
od
Pin name Function
Write enable
t uc
Input/output mask Clock input Clock enable Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit No connection
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
L
E0082H10 (1st edition) (Previous ADE-203-1073B (Z)) Jan. 31, 2001
HM5225165BLTT-75* 1 HM5225165BLTT-A6 HM5225165BLTT-B6* 2 HM5225805BTT-75* 1 HM5225805BTT-A6 HM5225805BTT-B6* 2 HM5225805BLTT-75* 1 HM5225805BLTT-A6 HM5225805BLTT-B6* 2 HM5225405BTT-75* 1 HM5225405BTT-A6 HM5225405BTT-B6* 2 HM5225405BLTT-75* 1 HM5225405BLTT-A6 HM5225405BLTT-B6* 2
Write enable
t uc
Input/output mask Clock input Clock enable Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit No connection 5
54-pin TSOP VCC DQ0 VCCQ DQ1 DQ2 VSSQ DQ3 DQ4 VCCQ DQ5 DQ6 VSSQ DQ7 VCC DQML WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ15 VSSQ DQ14 DQ13 VCCQ DQ12 DQ11 VSSQ DQ10 DQ9 VCCQ DQ8 VSS NC DQMU CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS
54-pin TSOP VCC NC VCCQ NC DQ0 VSSQ NC NC VCCQ NC DQ1 VSSQ NC VCC NC WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS NC VSSQ NC DQ3 VCCQ NC NC VSSQ NC DQ2 VCCQ NC VSS NC DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS
EO
Type No. HM5225165BTT-75* HM5225165BTT-A6 HM5225165BTT-B6* 2
1
Ordering Information
Frequency 133 MHz 100 MHz 100 MHz 133 MHz 100 MHz 100 MHz 133 MHz 100 MHz 100 MHz 133 MHz 100 MHz 100 MHz 133 MHz 100 MHz 100 MHz 133 MHz 100 MHz 100 MHz CAS latency 3 2/3 3 3 2/3 3 3 2/3 3 3 2/3 3 3 2/3 3 3 2/3 3 Package 400-mil 54-pin plastic TSOP II (TTP-54D)
od
Pin name Function DQMU/DQML
Write enable Input/output mask
t uc
Clock input Clock enable Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit No connection 3
HM5225165B/HM5225805B/HM5225405B-75/A6/B6
Pin Arrangement (HM5225405B)
EO
Pin Description
Pin name A0 to A12, BA0, BA1 Function Address input Row address Column address DQ0 to DQ3 CS RAS CAS Data-input/output Chip select
This product became EOL in April, 2004.
Pr
od
t uc
HM5225165B/HM5225805B/HM5225405B-75/A6/B6
• Byte control by DQM : DQM (HM5225805B/HM5225405B) : DQMU/DQML (HM5225165B) • Refresh cycles: 8192 refresh cycles/64 ms • 2 variations of refresh Auto refresh Self refresh
L
Bank select address
Row address strobe command Column address strobe command
Pr
(Top view) WE A0 to A12 A0 to A9, A11 BA0/BA1 (BS) DQM CLK CKE VCC VSS VCCQ VSS Q NC Data Sheet E0082H10
3.3 V power supply Clock frequency: 133 MHz/100 MHz (max) LVTTL interface Single pulsed RAS 4 banks can operate simultaneously and independently Burst read/write operation and burst read/single write operation capability Programmable burst length: 1/2/4/8 2 variations of burst sequence Sequential (BL = 1/2/4/8) Interleave (BL = 1/2/4/8) • Programmable CAS latency: 2/3
Pin Arrangement (HM5225165B)
EO
Pin Description
Pin name A0 to A12, BA0, BA1 Function Address input Row address Column address DQ0 to DQ15 CS RAS CAS Data-input/output Chip select
Notes: 1. 100 MHz operation at CAS latency = 2. 2. 66 MHz operation at CAS latency = 2.
L
Pr
Data Sheet E0082H10
od t uc
2
HM5225165B/HM5225805B/HM5225405B-75/A6/B6
L
Bank select address
Row address strobe command Column address strobe command
Pr
(Top view) WE A0 to A12 A0 to A9 BA0/BA1 (BS) DQM CLK CKE VCC VSS VCCQ VSS Q NC Data Sheet E0082H10
54-pin TSOP VCC DQ0 VCCQ NC DQ1 VSSQ NC DQ2 VCCQ NC DQ3 VSSQ NC VCC NC WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ7 VSSQ NC DQ6 VCCQ NC DQ5 VSSQ NC DQ4 VCCQ NC VSS NC DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS
HM5225165B/HM5225805B/HM5225405B-75/A6/B6
Pin Arrangement (HM5225805B)
EO
Pin Description
Pin name A0 to A12, BA0, BA1 Function Address input Row address Column address DQ0 to DQ7 CS RAS CAS Data-input/output Chip select 4
The HM5225165B is a 256-Mbit SDRAM organized as 4194304-word × 16-bit × 4 bank. The HM5225805B is a 256-Mbit SDRAM organized as 8388608-word × 8-bit × 4 bank. The HM5225405B is a 256-Mbit SDRAM organized as 16777216-word × 4-bit × 4 bank. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.
HM5225165B-75/A6/B6 HM5225805B-75/A6/B6 HM5225405B-75/A6/B6
EO
Description Features
• • • • • • • •
256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword × 16-bit × 4-bank/8-Mword × 8-bit × 4-bank /16-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAM
L
Bank select address
Row address strobe command Column address strobe command
Pr
(Top view) WE A0 to A12 A0 to A8 BA0/BA1 (BS) CLK CKE VCC VSS VCCQ VSS Q NC Data Sheet E0082H10
od
Pin name Function
Write enable
t uc
Input/output mask Clock input Clock enable Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit No connection
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
L
E0082H10 (1st edition) (Previous ADE-203-1073B (Z)) Jan. 31, 2001
HM5225165BLTT-75* 1 HM5225165BLTT-A6 HM5225165BLTT-B6* 2 HM5225805BTT-75* 1 HM5225805BTT-A6 HM5225805BTT-B6* 2 HM5225805BLTT-75* 1 HM5225805BLTT-A6 HM5225805BLTT-B6* 2 HM5225405BTT-75* 1 HM5225405BTT-A6 HM5225405BTT-B6* 2 HM5225405BLTT-75* 1 HM5225405BLTT-A6 HM5225405BLTT-B6* 2