第8讲 时序逻辑电路设计

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY RPLCOUNT IS PORT(CLK,CLR:IN STD_LOGIC; COUNT:OUT STD_LOGIC_VECTOR(0 TO 7)); END ENTITY RPLCOUNT; ARCHITECTURE ART2 OF RPLCOUNT IS SIGNAL COUNT_IN:STD_LOGIC_VECTOR(0 TO 8); COMPONENT DIFFR IS PORT(CLK,CLR,D:IN STD_LOGIC; Q,QB:OUT STD_LOGIC); END COMPONENT; BEGIN COUNT_IN(0)<=CLK; GEN1:FOR I IN 0 TO 7 GENERATE U:DIFFR PORT MAP(CLK=>COUNT_IN(I), CLR=>CLR,D=>COUNT_IN(I+1), Q=>COUNT(I),QB=>COUNT_IN(I+1)); END GENERATE; END ARCHITECTURE ART2;
EDA技术
讲授：伍宗富
二、计数器设计
1．10进制
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT10 IS PORT (CLK: IN STD_LOGIC; CLR: IN STD_LOGIC; ENA: IN STD_LOGIC; CQ: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CARRY_OUT: OUT STD_LOGIC); END CNT10; ARCHITECTURE ART OF CNT10 IS SIGNAL CQI: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(CLK, CLR, ENA) BEGIN IF CLR='1' THEN CQI<="0000"; ELSIF CLK'EVENT AND CLK='1' THEN IF ENA='1' THEN IF CQI="1001" THEN CQI<="0000";CARRY_OUT<='1'; ELSE CQI<=CQI+'1';CARRY_OUT<='0'; END IF; END IF; END IF; END PROCESS; CQ<=CQI; END ART;
EDA技术
讲授：伍宗富
一、寄存器和移位寄存器设计
2．移位寄存器
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY SHIFTREG8 IS PORT(DATA:IN STD_LOGIC_VECTOR(7 DOWNTO 0); CLK,RESET,SHIFT_LEFT,SHIFT_RIGHT:IN STD_LOGIC; MODE:IN STD_LOGIC_VECTOR(1 DOWNTO 0); QOUT:BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0)); END ENTITY SHIFTREG8; ARCHITECTURE ART OF SHIFTREG8 IS BEGIN PROCESS BEGIN WAIT UNTIL(RISING_EDGE(CLK)); IF(RESET='1')THEN QOUT<="00000000"; ELSE --同步复位功能的实现 CASE MODE IS WHEN "01"=>QOUT<=SHIFT_RIGHT&QOUT(7 DOWNTO 1); --右移一位 WHEN "10"=>QOUT<=QOUT(6 DOWNTO 0)&SHIFT_LEFT; --左移一位 WHEN "11"=>QOUT<=DATA; WHEN OTHERS=>NULL; END CASE; END IF; END PROCESS; END ARCHITECTURE ART;
EDA技术
讲授：伍宗富
三、序列信号发生器设计
2． “01111110”序列信号检测器
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY DETECT IS PORT(DATAIN,CLK:IN STD_LOGIC; Q:OUT STD_LOGIC); END ENTITY DETECT; ARCHITECTURE ART OF DETECT IS TYPE STATETYPE IS(S0,S1,S2,S3,S4,S5,S6,S7,S8); BEGIN PROCESS(CLK) VARIABLE PRESENT_STATE:STATETYPE; BEGIN Q<='0'; CASE PRESENT_STATE IS WHEN S0=> IF DATAIN='0' THEN PRESENT_STATE:=S1; ELSE PRESENT_STATE:=S0;END IF; WHEN S1=> IF DATAIN='1' THEN PRESENT_STATE:=S2; ELSE PRESENT_STATE:=S1;END IF; WHEN S2=> IF DATAIN='1' THEN PRESENT_STATE:=S3; ELSE PRESENT_STATE:=S1;END IF; WHEN S3=> IF DATAIN='1' THEN PRESENT_STATE:=S4; ELSE PRESENT_STATE:=S1;END IF; WHEN S4=> IF DATAIN='1' THEN PRESENT_STATE:=S5; ELSE PRESENT_STATE:=S1;END IF; WHEN S5=> IF DATAIN='1' THEN PRESENT_STATE:=S6; ELSE PRESENT_STATE:=S1;END IF; WHEN S6=> IF DATAIN='1' THEN PRESENT_STATE:=S7; ELSE PRESENT_STATE:=S1;END IF; WHEN S7=> IF DATAIN='0' THEN PRESENT_STATE:=S8;Q<='1'; ELSE PRESENT_STATE:=S0;END IF; WHEN S8=> IF DATAIN='0' THEN PRESENT_STATE:=S1; ELSE PRESENT_STATE:=S2;END IF; END CASE; WAIT UNTIL CLK='1'; END PROCESS; END ARCHITECTURE ART;
EDA技术
讲授：伍宗富
二、计数器设计
2．60进制同步计数器
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNTM60 IS PORT(CI,NRESET,CLK,LOAD:IN STD_LOGIC; D:IN STD_LOGIC_VECTOR(7 DOWNTO 0); CO:OUT STD_LOGIC; QH:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0); QL:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0)); END ENTITY CNTM60; ARCHITECTURE ART OF CNTM60 IS BEGIN CO<='1' WHEN(QH="0101"AND QL="1001"AND CI='1')ELSE'0'; --进位输出的产生 PROCESS(CLK,NRESET) BEGIN IF(NRESET='0')THEN --异步复位 QH<="0000"; QL<="0000"; ELSIF(CLK'EVENT AND CLK='1')THEN --同步置数 IF(LOAD='1')THEN QH<=D(7 DOWNTO 4); QL<=D(3 DOWNTO 0); ELSIF(CI='1')THEN --模60的实现 IF(QL=9)THEN QL<="0000"; IF(QH=5)THEN QH<="0000"; ELSE --计数功能的实现 QH<=QH+1; END IF; ELSE QL<=QL+1; END IF; END IF; END IF; --END IF LOAD END PROCESS; END ARCHITECTURE ART;
EDA技术
讲授：伍宗富
三、序列信号发生器设计
1． “01111110”序列发生器
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY SENQGEN IS PORT(CLK,CLR,CLOCK:IN STD_LOGIC; ZO:OUT STD_LOGIC); END ENTITY SENQGEN; ARCHITECTURE ART OF SENQGEN IS SIGNAL COUNT:STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL Z:STD_LOGIC:='0'; BEGIN PROCESS(CLK,CLR) BEGIN IF(CLR='1')THEN COUNT<="000"; ELSE IF(CLK='1' AND CLK'EVENT)THEN IF(COUNT="111")THEN COUNT<="000"; ELSE COUNT<=COUNT +'1'; END IF; END IF; END IF; END PROCESS; PROCESS(COUNT) BEGIN CASE COUNT IS WHEN "000"=>Z<='0'; WHEN "001"=>Z<='1'; WHEN "010"=>Z<='1'; WHEN "011"=>Z<='1'; WHEN "100"=>Z<='1'; WHEN "101"=>Z<='1'; WHEN "110"=>Z<='1'; WHEN OTHERS=>Z<='0'; END CASE; END PROCESS; PROCESS(CLOCK,Z) BEGIN --消除毛刺的锁存器 IF(CLOCK'EVENT AND CLOCK='1')THEN ZO<=Z; END IF; END PROCESS; END ARCHITECTURE ART;