24c02串行储存器中文官方资料手册
24c02中文资料
24c02中文资料1. 简介24c02是Microchip公司推出的一种串行电子可擦写可编程读写存储器，属于EEPROM（Electrically Erasable Programmable Read-Only Memory）系列。
它采用2-wire串行总线（I2C）接口，具有体积小、功耗低、可靠性高等特点。
本文档将详细介绍24c02的硬件特性、接口规范、存储容量和使用方法。
2. 硬件特性24c02的主要硬件特性如下：•存储容量：24c02有256个字节，每个字节有8位，总计拥有2Kb的存储空间。
•工作电源：24c02需要使用3.3V到5V的供电电压，支持广泛的电源电压范围。
•通信接口：24c02使用I2C串行总线进行通信，具有两根信号线：串行数据线（SDA）和串行时钟线（SCL）。
•封装类型：24c02有多种封装类型可供选择，如DIP（双列直插式封装）、SOP（小型轻负载封装）等。
3. 接口规范24c02采用I2C串行总线接口，其接口规范如下：•数据传输方式：24c02支持字节读写操作和页写操作。
字节读写操作是指每次读写一个字节的数据；页写操作是指每次可以写入8个连续字节的数据。
•起始信号和停止信号：在I2C总线上进行通信时，需要发送起始信号（Start）和停止信号（Stop）以标识数据传输的开始和结束。
•从器件地址：24c02有多个从器件地址可供选择，通过设置硬件地址引脚，可以实现多个24c02器件的级联。
4. 存储容量24c02的存储容量为2Kb，相当于256个字节。
每个字节有8位，可存储0x00到0xFF的数据。
这些存储空间可以被分为多个页，每页包含8个字节。
5. 使用方法以下是24c02的基本使用方法，供参考：•初始化：将24c02与主控芯片（如单片机）连接，并提供正常的供电电源。
同时，设置24c02的硬件地址引脚，确保能正确寻址。
•写入数据：选择要写入数据的存储地址，发送起始信号和器件地址，然后发送数据字节。
at24c02中文资料_数据手册_参数
24c02中文官方手册
CAT24WC01/02/04/08/16 是 一 个 1K/2K/4K/8K/16K 位 串 行 CMOS E2PROM 内 部 含 有 128/256/512/1024/2048 个 8 位字节 CATALYST 公司的先进 CMOS 技术实质上减少了器件的功耗 CAT24WC01 有一个 8 字节页写缓冲器 CAT24WC02/04/08/16 有一个 16 字节页写缓冲器 该器件通过 I2C 总线接口进行操作 有一个专门的写保护功能
1 Vcc 0.7
典型
最大 3 0 10 10
Vcc 0.3 Vcc+0.5
0.4 0.5
单位 mA
A A A V V V V
测试条件 FSCL=100KHz VIN=0 ~Vcc VIN=0 ~Vcc VOUT=0 ~Vcc
IOL=3 mA IOL=1.5 mA
分布电容
TA=25 , f =1.0MHz, Vcc =5V
当使用 24WC08 时最多可连接 2 个器件 且仅使用地址管脚 A2 A0 A1 管脚未用 可以连接到 Vss 或悬空 如果只有一个 24WC08 被总线寻址 A2 管脚可悬空或连接到 Vss
当使用 24WC16 时最多只可连接 1 个器件 所有地址管脚 A0 A1 A2 都未用 管脚可以连接到 Vss 或悬空
WP 写保护 如果 WP 管脚连接到 Vcc 所有的内容都被写保护 只能读 当 WP 管脚连接到 Vss 或悬空 允许 器件进行正常的读/写操作
I2C 总线协议
I2C 总线协议定义如下
5
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24c02中文官方资料手册pdf
ｗ 址输入脚 A0 A1 A2 可悬空或连接到 Vss 如果只有一个 24WC01 被总线寻址 这三个地址输入
脚 A0 A1 A2 必须连接到 Vss
当使用 24WC04 时最多可连接 4 个器件 该器件仅使用 A1 A2 地址管脚 A0 管脚未用 可以连
符号
参数
最小
典型
最大 单位
测试条件
ICC 电源电流
3
mA
FSCL=100KHz
ISB ILI ILO VIL VIH VOL1 VOL2
备用电流(Vcc=5.0V) 输入漏电流 输出漏电流 输入低电压 输入高电压 输出低电压 输出低电压
1 Vcc 0.7
0
A
10
A
10
A
Vcc 0.3 V
Vcc+0.5 V
s
tHD: DAT
数据输入保持时间
0
0
ns
tSUl: DAT
数据输入建立时间
50
50
ns
tR
SDA 及 SCL 上升时间
1
0.3
s
tF
SDA 及 SCL 下降时间
300
300
ns
tSU: STO
停止信号建立时间
4
0.6
s
tDH
数据输出保持时间
100
100
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上电时序
符号
参数
最大
单位
tPUR
上电到读操作
1
EEPROM存储芯片24C02
EEPROM存储芯⽚24C021、24C02简介 24C02是⼀个2Kbit的串⾏EEPROM存储芯⽚，可存储256个字节数据。
⼯作电压范围为1.8V到6.0V，具有低功耗CMOS技术，⾃定时擦写周期，1000000次编程/擦除周期，可保存数据100年。
24C02有⼀个16字节的页写缓冲器和⼀个写保护功能。
通过I2C总线通讯读写芯⽚数据，通讯时钟频率可达400KHz。
可以通过存储IC的型号来计算芯⽚的存储容量是多⼤，⽐如24C02后⾯的02表⽰的是可存储2Kbit的数据，转换为字节的存储量为2*1024/8 = 256byte；有⽐如24C04后⾯的04表⽰的是可存储4Kbit的数据，转换为字节的储存量为2*1024/8 = 512byte;以此来类推其它型号的存储空间。
24C02的管脚图如下： VCC和VSS是芯⽚的电源和地，电压的⼯作范围为：+1.8V~+6.0V。
A0、A1、A2是IC的地址选择脚。
WP是写保护使能脚。
SCL是I2C通讯时钟引脚。
SDA是I2C通讯数据引脚。
2、24C02的设备地址和写保护功能 I2C主机在与24C02通讯时，需要发送⼀个设备地址进⾏寻址，在I2C总线上，每⼀个从机设备的地址都是唯⼀的。
24C02的设备地址包含两部分，第⼀部分是bit7~bit4是固定的“1010”，第⼆部分bit3~bit1位由A2、A1、A0组成。
主机在与24C02进⾏通讯时，除了发送设备地址还需要发送数据的读写⽅向位R/W，24C02的是设备地址与R/W位组成了⼀个字节的数据。
如下图： 上图列出了⼏个存储IC的设备地址与R/W位组成的字节。
由图中可以看到，存储IC地址的bit7~bit4位固定为“1010”；bit3~bit1位由A2、A1、A0引脚的电平状态决定，如果Ax接的是电源（⾼电平），那么Ax=1，如果Ax接的是地，那么Ax=0,即由A2、A1、A0可以组合成8种设备地址，也就是说在同⼀个I2C总线上可以同时挂载8个24C02芯⽚。
FM24C02中文资料
元器件交易网
FM24C04U/05U – 4K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Ordering Information FM 24 C XX U F LZ E XXX
Operating Conditions
Ambient Operating Temperature FM24C04U/05U FM24C04UE/05UE FM24C04UV/05UV Positive Power Supply FM24C04U/05U FM24C04UL/05UL FM24C04ULZ/05ULZ 0°C to +70°C -40°C to +85°C -40°C to +125°C 4.5V to 5.5V 2.7V to 5.5V 2.7V to 5.5V
FM24C04U/05U – 4K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Product Specifications Absolute Maximum Ratings
Ambient Storage Temperature All Input or Output Voltages with Respect to Ground Lead Temperature (Soldering, 10 seconds) ESD Rating –65°C to +150°C –0.3V to 6.5V +300°C 2000V min.
元器件交易网
FM24C04U/05U – 4K-Bit Standard 2-Wire Bus Interface Serial EEPROM
SLA24C02-D中文资料
Standard EEPROM ICs SLx24C01/02/P1/2Kbit(128/256×8bit)Serial CMOS-EEPROM withI2C Synchronous2-Wire Busand Page Protection Mode™Data Sheet1998-07-27I 2C BusPurchase of Siemens I 2C components conveys the license under the Philips I 2C patent to use the components in the I 2C system provided the system conforms to the I 2C specifications defined by Philips.Edition 1998-07-27Published by Siemens AG,Bereich Halbleiter,Marketing-Kommunikation,Balanstraße 73,81541München ©Siemens AG 1998.All Rights Reserved.Attention please!As far as patents or other rights of third parties are concerned,liability is only assumed for components,not for applications,processes and circuits implemented within components or assemblies.The information describes the type of component and shall not be considered as assured characteristics.Terms of delivery and rights to change design reserved.For questions on technology,delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list).Due to technical requirements components may contain dangerous substances.For information on the types in question please contact your nearest Siemens Office,Semiconductor Group.Siemens AG is an approved CECC manufacturer.PackingPlease use the recycling operators known to you.We can also help you –get in touch with your nearest sales office.By agreement we will take packing material back,if it is sorted.You must bear the costs of transport.For packing material that is returned to us unsorted or which we are not obliged to accept,we shall have to invoice you for any costs in-curred.Components used in life-support devices or systems must be expressly authorized for such purpose!Critical components 1of the Semiconductor Group of Siemens AG,may only be used in life-support devices or systems 2with the express written approval of the Semiconductor Group of Siemens AG.1A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system,or to affect its safety or effectiveness of that device or system.2Life support devices or systems are intended (a)to be implanted in the human body,or (b)to support and/or maintain and sustain hu-SLx 24C01/02/P Revision History:Current Version:1998-07-27Previous Version:06.97Page (in previous Version)Page(in current Version)Subjects (major changes since last revision)33Text was changed to “Typical programming time 5ms for up to8bytes”.55WP =V CC protects the upper half entire memory.1515Figure 11:second command byte is a CSR and not CSW.4,54,5CS0,CS1and CS2were replaced by n.c.5–The paragraph “Chip Select (CS0,CS1,CS2)”was removed completely.11,1211,12The erase/write cycle is finished latest after 108ms.2121The write or erase cycle is finished latest after 104ms.1924“Capacitive load …”were added.2525Some timings were changed.2525The line “erase/write cycle”was removed.2525Chapter 8.4“Erase and Write Characteristics”has been added.1/2Kbit (128/256×8bit)Serial CMOS EEPROMs,I 2C Synchronous 2-Wire Bus,Page Protection Mode ™SLx 24C01/02/PFeatures•Data EEPROM internally organized as 128/256bytes and 16/32pages ×8bytes•Page protection mode,flexible page-by-page hardware write protection–Additional protection EEPROM of 16/32bits,1bit per data page–Protection setting for each data page by writing itsprotection bit–Protection management without switching WP pin •Low power CMOS•V CC =2.7to 5.5V operation•Two wire serial interface bus,I 2C-Bus compatible•Filtered inputs for noise suppression with Schmitt trigger•Clock frequency up to 400kHz•High programming flexibility –Internal programming voltage–Self timed programming cycle including erase–Byte-write and page-write programming,between 1and 8bytes –Typical programming time 5ms for up to 8bytes •High reliability–Endurance 106cycles 1)–Data retention 40years 1)–ESD protection 4000V on all pins •8pin DIP/DSO packages•Available for extended temperature ranges –Industrial:−40°C to +85°C –Automotive:−40°C to +125°C1)Values are temperature dependent,for further information please refer to your Siemens Sales office.Ordering Information Other types are available on request–Temperature range (– 55°C … +150°C)–Package (die,wafer delivery)1Pin ConfigurationFigure 1Pin Configuration (top view)TypeOrdering Code Package TemperatureVoltageSLA 24C01-D/P Q67100-H3547P-DIP-8-4–40°C …+85°C 4.5V...5.5V SLA 24C01-S/P Q67100-H3495P-DSO-8-3–40°C …+85°C 4.5V...5.5V SLA 24C01-D-3/P Q67100-H3546P-DIP-8-4–40°C …+85°C 2.7V...5.5V SLA 24C01-S-3/P Q67100-H3494P-DSO-8-3–40°C …+85°C 2.7V...5.5V SLE 24C01-D/P Q67100-H3545P-DIP-8-4–40°C …+125°C 4.5V...5.5V SLE 24C01-S/P Q67100-H3493P-DSO-8-3–40°C …+125°C 4.5V...5.5V SLA 24C02-D/P Q67100-H3542P-DIP-8-4–40°C …+85°C 4.5V...5.5V SLA 24C02-S/P Q67100-H3537P-DSO-8-3–40°C …+85°C 4.5V...5.5V SLA 24C02-D-3/P Q67100-H3541P-DIP-8-4–40°C …+85°C 2.7V...5.5V SLA 24C02-S-3/P Q67100-H3536P-DSO-8-3–40°C …+85°C 2.7V...5.5V SLE 24C02-D/P Q67100-H3540P-DIP-8-4–40°C …+125°C 4.5V...5.5VSLE 24C02-S/PQ67100-H3535P-DSO-8-3–40°C …+125°C 4.5V...5.5VPin Definitions and Functions Pin Description Serial Clock (SCL)The SCL input is used to clock data into the device on the rising edge and to clock data out of the device on the falling edge.Serial Data (SDA)SDA is a bidirectional pin used to transfer addresses,data or control information into the device or to transfer data out of the device.The output is open drain,performing a wired AND function with any number of other open drain or open collector devices.The SDA bus requires a pull-up resistor to V CC .Write Protection (WP)WP switched to V SS allows normal read/write operations.WP switched to V CC protects the entire EEPROM against changes (hardware write protection).Additionally write protection is managed by a protection bit associated to each page.(refer to chapter 7Page Protection Mode TM )Table 1Pin No.Symbol Function 1,2,3N.C.Not connected 4V SSGround5SDA Serial bidirectional data bus 6SCL Serial clock input 7WPWrite protection input 8V CCSupply voltage2DescriptionThe SLx24C01/02/P device is a serial electrically erasable and programmable read only memory(EEPROM),organized as128/256×8bit.The data memory is divided into16/ 32pages.The8bytes of a page can be programmed simultaneously.Each page may be protected individually against changes by its associated protection bit.The device conforms to the specification of the2-wire serial I2C-Bus.Low voltage design permits operation down to2.7V with low active and standby currents.The device operates at5.0V±10%with a maximum clock frequency of400kHz and at 2.7...4.5V with a maximum clock frequency of100kHz.The device is available as5Vtype(VCC =4.5…5.5V)with two temperature ranges for industrial and automotiveapplications and as3V type(VCC =2.7…5.5V)for industrial applications.TheEEPROMs are mounted in eight-pin DIP and DSO packages or are also supplied as chips.Figure2Block Diagram3I2C-Bus CharacteristicsThe SLx24C01/02/P devices support a master/slave bidirectional bus oriented protocol in which the EEPROM always takes the role of a slave. Array Figure3Bus ConfigurationMaster Device that initiates the transfer of data and provides the clock for both transmit and receive operations.Slave Device addressed by the master,capable of receiving and transmitting data.Transmitter The device with the SDA as output is defined as the transmitter.Due to the open drain characteristic of the SDA output the device applying a lowlevel wins.Receiver The device with the SDA as input is defined as the receiver.The conventions for the serial clock line and the bidirectional data line are shown in figure4.I2C-Bus Timing Conventions for START Condition,STOP Condition,Data Valida-tion and Transfer of Acknowledge ACKStandby Mode in which the bus is not busy(no serial transmission,noprogramming):both clock(SCL)and data line(SDA)are in highstate.The device enters the standby mode after a STOP conditionor after a programming cycle.START Condition High to low transition of SDA when SCL is high,preceding allcommands.STOP Condition Low to high transition of SDA when SCL is high,terminating allcommunications.A STOP condition initiates an EEPROMprogramming cycle.A STOP condition after reading a data bytefrom the EEPROM initiates the Standby mode.Acknowledge A successful reception of eight data bits is indicated by thereceiver by pulling down the SDA line during the following clockcycle of SCL(ACK).The transmitter on the other hand has torelease the SDA line after the transmission of eight data bits.The EEPROM as the receiving device responds with anacknowledge,when addressed.The master,on the other side,acknowledges each data byte transmitted by the EEPROM andcan at any time end a read operation by releasing the SDA line(noACK)followed by a STOP condition.Data Transfer Data must change only during low SCL state,data remains validon the SDA bus during high SCL state.Nine clock pulses arerequired to transfer one data byte,the most significant bit(MSB)is transmitted first.4Device Addressing and EEPROM AddressingAfter a START condition,the master always transmits a Command Byte CSW or CSR.After the acknowledge of the EEPROM a Control Byte follows,its content and the transmitter depend on the previous Command Byte.The description of the Command and Control Bytes is shown in table 2.The device has an internal address counter which points to the current EEPROM address.The address counter is incremented–after a data byte to be written has been acknowledged,during entry of further data byte–during a byte read,thus the address counter points to the following address after reading a data byte.Command ByteSelects operation:the least significant bit b0is low for a write operation (Chip Select Write Command Byte CSW)or set high for a read operation (Chip Select Read Command Byte CSR).In both Command Bytes,the bit positions b3to b1are left undefined.Control ByteFollowing CSW (b0=0):contains the seven or eight lower bits of the EEPROM address (EEA)bit A6or A7to A0,or an additional command byte for the handling of the protection bit.Following CSR (b0=1):contains the data read out,transmitted by the EEPROM.The EEPROM data are read as long as the master pulls down SDA after each byte in order to acknowledge the transfer.The read operation is stopped by the master by releasing SDA (no acknowledge is applied)followed by a STOP condition.Table 2Command and Control Byte for I 2C-Bus Addressing of Chip and EEPROMDefinitionFunctionb7b6b5b4b3b2b1b0CSW 1010x x x 0Chip Select for Write CSR 11xxx1Chip Select for Read EEAA7A6A5A4A3A2A1A0EEPROM addressThe timing conventions for read and write operations are described in figures 5and 6.Figure 5Timing of the Command Byte CSWFigure 6Timing of the Command Byte CSR5Write OperationsChanging of the EEPROM data is initiated by the master with the command byte CSW.Depending on the state of the Write Protection pin WP and of the Protection Bits (refer to chapter 7Page Protection Mode TM )either one byte (Byte Write)or up to 8bytes (Page Write)are modified in one programming procedure.5.1Byte WriteFigure 7Byte Write SequenceThe erase/write cycle is finished latest after 8ms.Acknowledge polling may be used for speed enhancement in order to indicate the end of the erase/write cycle (refer to chapter 5.3Acknowledge Polling).Address SettingAfter a START condition the master transmits the Chip Select Write byte CSW.The EEPROM acknowledges the CSW byte during the ninth clock cycle.The following byte with the EEPROM address (A0to A6or A7)is loaded into the address counter of the EEPROM and acknowledged by the EEPROM.Transmission of Data Finally the master transmits the data byte which is also acknowledged by the EEPROM into the internal buffer.Programming CycleThen the master applies a STOP condition which starts the internal programming procedure.The data bytes are written in the memory location addressed in the EEA byte (A0to A6or A7).The programming procedure consists of an internally timed erase/write cycle.In the first step,the selected byte is erased to “1”.With the next internal step,the addressed byte is written according to the contents of the buffer.5.2Page WriteThose bytes of the page that have not been addressed are not included in the programming.Figure 8Page Write SequenceThe erase/write cycle is finished latest after 8ms.Acknowledge polling may be used for speed enhancement in order to indicate the end of the erase/write cycle (refer to chapter 5.3Acknowledge Polling).Address SettingThe page write procedure is the same as the byte write procedure up to the first data byte.In a page write instruction however,entry of the EEPROM address byte EEA is followed by a sequence of one to maximum eight data bytes with the new data to be programmed.These bytes are transferred to the internal page buffer of the EEPROM.Transmission of DataThe first entered data byte will be stored according to the EEPROM address n given by EEA (A0to A6or A7).The internal address counter is incremented automatically after the entered data byte has been acknowledged.The next data byte is then stored at the next higher EEPROM address.EEPROM addresses within the same page have common page address bits A2through A6or A7.Only the respective three least significant address bits A0through A2are incremented,as all data bytes to be programmed simultaneously have to be within the same page.Programming CycleThe master stops data entry by applying a STOP condition,which also starts the internally timed erase/write cycle.In the first step,all selected bytes are erased to “1”.With the next internal step,the addressed bytes are written according to the contents of the page buffer.5.3Acknowledge PollingDuring the erase/write cycle the EEPROM will not respond to a new command byte until the internal write procedure is completed.At the end of active programming the chip returns to the standby mode and the last entered EEPROM byte remains addressed by the address counter.To determine the end of the internal erase/write cycle acknowledge polling can be initiated by the master by sending a START condition followed by a command byte CSR or CSW(read with b0=1or write with b0=0).If the internal erase/ write cycle is not completed,the device will not acknowledge the transmission.If the internal erase/write cycle is completed,the device acknowledges the received command byte and the protocol activities can continue. Array Figure9Flow Chart“Acknowledge Polling”Principle of Acknowledge Polling6Read OperationsReading of the EEPROM data is initiated by the Master with the command byte CSR.6.1Random ReadRandom read operations allow the master to access any memory location.Figure 11Random ReadAddress SettingThe master generates a START condition followed by the command byte CSW.The receipt of the CSW-byte is acknowledged by the EEPROM with a low on the SDA line.Now the master transmits the EEPROM address (EEA)to the EEPROM and the internal address counter is loaded with the desired address.Transmission of CSRAfter the acknowledge for the EEPROM address is received,the master generates a START condition,which terminates the initiated write operation.Then the master transmits the command byte CSR for read,which is acknowledged by the EEPROM.Transmission of EEPROM Data During the next eight clock pulses the EEPROM transmits the data byte and increments the internal address counter.STOP Condition from MasterDuring the following clock cycle the masters releases the bus and then transmits the STOP condition.6.2Current Address ReadThe EEPROM content is read without setting an EEPROM address,in this case the current content of the address counter will be used (e.g.to continue a previous read operation after the Master has served an interrupt).Figure 12Current Address ReadTransmission of CSRFor a current address read the master generates a START condition,which is followed by the command byte CSR (chip select read).The receipt of the CSR-byte is acknowledged by the EEPROM with a low on the SDA line.Transmission of EEPROM Data During the next eight clock pulses the EEPROM transmits the data byte and increments the internal address counter.STOP Condition from MasterDuring the following clock cycle the masters releases the bus and then transmits the STOP condition.6.3Sequential ReadA sequential read is initiated in the same way as a current read or a random read except that the master acknowledges the data byte transmitted by the EEPROM.The EEPROM then continues the data transmission.The internal address counter is incremented by one during each data byte transmission.A sequential read allows the entire memory to be read during one read operation.In the SLx24C02/P,after the highest addressable memory location is reached,the internal address pointer“rolls over”to the address0and the sequential read continues.In the SLx24C01/P,there is no“roll over”.The transmission is terminated by the master by releasing the SDA line(no acknowledge)and generating a STOP condition(see figure13). Array Figure13Sequential Read7Page Protection Mode TMEach page(8bytes)in the Data Memory can be protected against unintended data changes by an associated protection bit.The protection bit memory consists of an additional EEPROM of16/32bits(figure14).Data in the Data Memory can be modified only if the assigned protection bit is erased (logical state“1”).After writing the data bytes to a page,the protection is achieved by writing the associated protection bit(logical state“0”).Further changes in the data in a protected page is possible only after erasing the protection bit. Array Figure14Data Page and Assigned Protection MemoryA special procedure to write or erase a protection bit guarantees proper activation or deactivation respectively of page protection.For protection bit write or erase,all8data bytes of the respective page have to be entered for a second time.The data then are compared internally with the data to be protected,and in case of identity the protectionbit is written or erased respectively.7.1Protection Bit HandlingThe bits of the protection memory can be addressed directly for reading or programming.A protection bit address corresponds to the lowest address within the respective page (A3to A6or A7,A0to A2=zero).The status of each protection bit is sensed internally.A written state(“0”)prevents programming in the associated page.If an already protected memory page is accidentally addressed for programming,the programming procedure is suppressed.The conventional I2C-Bus protocol allows data bytes to be read and programmed only. Therefore an independent instruction sequence for addressing and manipulation of protection bits is implemented.For protection bit instructions,the command byte CSW with its preceding START condition followed by the associated control byte has to be entered twice(figures15through17).The first command byte CSW is followed by the control byte EEA with the bit/page address A0through A2always at zero.The second CSW is required for entering a control byte CTx for protection bit manipulation.The three control bytes for read,write or erase of a protection bit are listed below(table3): Table3Control Byte for Protection Bit ManipulationAddress NameDefinition Function b7b6b5b4b3b2b1b0CTR x x x x x x00Protection bit read CTW x x x x x x01Protection bit write CTE x x x x x x11Protection bit erase7.2Protection Bit Write and EraseFor writing or erasing a protection bit,the data of the respective page have to be known by the master.The data of the page are not affected by the write or erase procedure of the protection bit.The I 2C-Bus protocol is shown in figure 15for protection bit write and figure 16for protection bit erase.Figure 15Sequence for Protection Bit WriteFigure 16Sequence for Protection Bit EraseThe first command byte CSW followed by the control byte EEA addresses the page to be protected.The second command byte CSW (identical content of first CSW)is followed by the control byte CTW =01H for protection bit write or CTE =03H for protection bit erase.Depending on CTx,the addressed protection bit will be either written or erased.The control byte CTx is followed by8parameter bytes identical to the8data bytes of the page to be protected or unprotected.The data of the first entered byte must be identical to the data byte stored at the lowest address of the current page.The other7bytes have to be identical to the bytes stored in ascending address order within the same page.A successful verification of each byte is indicated by the EEPROM by pulling the SDA line to low(acknowledge ACK).After verification of the last byte,the bit programming procedure is initiated by the STOP condition.Programming is started only if all128bits of a page have been verified successfully.If bit programming has taken place,the address counter points to the uppermost address of the respective page.The write or erase cycle is finished latest after4ms.Acknowledge polling may be used for speed enhancement in order to indicate the end of the write or erase cycle(refer to chapter5.3Acknowledge Polling).7.3Protection Bit ReadThe byte sequence for random bit read is shown in figure17.Figure17Byte Sequence for Protection Bit ReadThe first command byte CSW followed by the control byte EEA addresses the protectionbit to be read.The second command byte CSW is followed by the control byte00H forprotection bit read.The first bit(MSB)of the transferred byte is the protection bit of the addressed page.The other7bits are not valid.The page protection status is indicated as followingProtection Bit=1:A normal write operation changes the data in the associated page Protection Bit=0:The data in the associated page are protected against changes.If the master acknowledges a byte with a low state of the SDA line,the protection bit of the next page can be read as the first bit of the following byte.If the master releases the SDA line,a STOP condition has to complete the read procedure.Any number of bytes with a page protection status at the first bit position can be requested by the master.If the bit of the uppermost page has been addressed,the counter has its overflow to the lowest address according to the first page.8Electrical CharacteristicsThe listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread.If nototherwise specified,typical characteristics apply at TA =25°C and the given supplyvoltage.8.1Absolute Maximum RatingsStresses above those listed here may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this data sheet is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. Parameter Limit Values UnitsOperating temperature range1(industrial)range2(automotive)–40to+85–40to+125°C°CStorage temperature–65to+150°C Supply voltage–0.3to+7.0V All inputs and outputs with respect to ground–0.3to VCC+0.5V ESD protection(human body model)4000V 8.2DC CharacteristicsParameter Symbol Limit Values Units Test Conditionmin.typ.max.Supply voltage VCC4.55.5V5V typeVCC2.7 5.5V3V typeSupply current1) (write)ICC13mA VCC=5V;fc=100kHzStandby current2)ISB50µA Inputs at VCCor VSSInput leakage current ILI0.110µA VIN=VCCor VSSOutput leakage current ILO0.110µA VOUT=VCCor VSSInput low voltage VIL–0.30.3×VCCV1)The values for I CC are maximum peak values 2)Valid over the whole temperature range 3)This parameter is characterized onlyInput high voltage V IH 0.7×V CCV CC +0.5VOutput low voltage V OL 0.4V I OL =3mA;V CC =5V I OL =2.1mA;V CC =3V Input/output capacitance (SDA)C I/O83)pFV IN =0V;V CC =5VInputcapacitance (other pins)C IN63)pFV IN =0V;V CC =5VCapacitive load for each bus lineC b 400pF8.2DC Characteristics (cont’d)Parameter SymbolLimit ValuesUnits Test Conditionmin.typ.max.1)The minimum rise and fall times can be calculated as follows:20+(0.1/pF)×Cb [ns]Example:Cb =100pF→tR=20+0.1×100[ns]=30ns8.3AC CharacteristicsParameter Symbol Limit ValuesVCC =2.7-5.5VLimit ValuesVCC=4.5-5.5VUnitsmin.max.min.max.SCL clock frequency fSCL100400kHzClock pulse width low tlow4.7 1.2µsClock pulse width high thigh4.00.6µsSDA and SCL rise time tR10001)300nsSDA and SCL fall time tF3001)300nsStart set-up time tSU.STA4.70.6µsStart hold time tHD.STA4.00.6µsData in set-up time tSU.DAT200100nsData in hold time tHD.DAT00µsSCL low to SDA data out valid tAA0.1 4.50.10.9µsData out hold time tDH10050nsStop set-up time tSU.STO4.00.6µsTime the bus must be free before a new transmission can start tBUF4.7 1.2µsSDA and SCL spike suppression time at constant inputs tl5010050100ns8.4Erase and Write CharacteristicsParameter Symbol Limit ValuesVCC =2.7-5.5VLimit ValuesVCC=4.5-5.5VUnitstyp.max.typ.max. Erase+write cycle(per page)tWR5858ms Erase page protection bit 2.54 2.54ms Write page protection bit 2.54 2.54msBus Timing Data9Package Outlines。
24C02资料 (2)
一、EPROM与EEPROM：EPROM（Erasable Programmable Read Only Memory），中文含意为“可擦除可编程只读存储器”。
它是一种可重写的存储器芯片，并且其内容在掉电的时候也不会丢失；换句话说，它是非易失性的。
它通过EPROM编程器进行编程，EPROM编程器能够提供比正常工作电压更高的电压对EPROM编程。
一旦经过编程，EPROM只有在强紫外线的照射下才能够进行擦除。
为了进行擦除，EPROM的陶瓷封装上具有一个小的石英窗口，这个石英窗口一般情况下使用不透明的粘带覆盖，当擦除时将这个粘带揭掉，然后放置在强紫外线下大约20分钟。
主要IC有27XX系列和27CXX系列。
EEPROM（electrically erasable, programmable, read-only ）是一种电可擦除可编程只读存储器，并且其内容在掉电的时候也不会丢失。
在平常情况下，EEPROM与EPROM一样是只读的，需要写入时，在指定的引脚加上一个高电压即可写入或擦除，而且其擦除的速度极快！通常EEPROM芯片又分为串行EEPROM和并行EEPROM两种，串行EEPROM在读写时数据的输入／输出是通过2线、3线、4线或SPI 总线等接口方式进行的，而并行EEPROM的数据输入／输出则是通过并行总线进行的。
主要IC有28XX系列。
二、24c02芯片硬件介绍：1、引脚说明：A0，A1，A2——地址输入引脚，走位硬件寻址的依据，同种芯片可同时连接8片（2^3）；Vcc，Gnd——电源，接地引脚，1.8-5.5vWp——写保护，当Wp接地时，允许对器件的正常读写操作；当Wp接高电平时，写保护，只能进行读操作。
SDA——串行地址/数据输入/输出端口，双向传输，漏极开路，需外接上拉电阻到Vcc（典型阻值为10k）。
SCL——串行时钟输入，高低电平不同状态与SDA配合，执行不同的命令。
2、存储结构：24c02的容量是2k，256字节。
FM24系列中文资料
直流参数
推荐参数的适用工作条件：TA = -40°C ~ +85°C，VCC = +2.2V ~ +5.5V，（除非另有说明）。
符号 VCC
ICC1
ICC2
ISB1 ISB2 ILI ILO VIL1 VIH1 VOL
参数 电源电压
电源电流
电源电流
等待态电流 等待态电流 输入漏电流 输出漏电流 输入低电平 输入高电平 输出低电平
最小值 2.2
-0.6 VCCx0.7
典型值 0.4 2.0
0.10 0.05
最大值
单位
5.5
V
1.0
mA
3.0
mA
1.0
µA
6.0
µA
3.0
µA
3.0
µA
VCCx0.3
V
VCC+0.5
V
0.4
V
注：1. VIL 最小值和 VIH 最大值未经测试，仅供参考。
FM24C02/04/08(A)/16 两线制串行 EEPROM
Trademarks
Shanghai Fudan Microelectronics Co., Ltd name and logo, the “复旦” logo are trademarks or registered trademarks of Shanghai Fudan Microelectronics Co., Ltd or its subsidiaries in China.
封装类型
产品特点
z 工作电压：2.2V～5.5V z 内部结构：256 x 8 (2K)，512 x 8 (4K)，1024 x 8 (8K)
或 2048 x 8 (16K) z 两线串行接口 z 输入引脚经施密特触发器滤波抑制噪声 z 双向数据传输协议 z 兼容100KHz(2.2V)和400KHz(5V)操作 z 支持硬件写保护 z 支持8字节(02)，16字节(04、08、08A、16) 页写模式 z 支持部分页写 z 写周期内部定时(小于5 ms) z 高可靠性：
AT24c02最全的中文资料
CA T24C 161/162(16K)，CAT24C081 /082(8K) CAT24C041/042(4K)，CAT24C021/022(2K)I2C串行CMOS E2PROM,精确的复位控制器和看门狗定时器控制电路特性•数据线上的看门狗定时器(仅对CA T24Cxxl)籲可编程复位门槛电平籲高数据传送速率为400KHz和I2C总线兼容• 2.7V至6V的工作电压•低功耗CMOS工艺籲16字节页写缓冲区籲片内防误擦除写保护籲高低电平复位信号输出——精确的电源电压监视器——可选择5V、3.3V和3V的复位门槛电平•100万次擦写周期•数据保存可长达100年•8脚DIP或SOIC封装•商业级、工业级和汽车温度范围概述CA T24Cxxx是集E2PROM存储器，复位微控制器和看门狗定时器三种流行功能与一体的芯片。
CAT24C161/162 (16K)，CAT24C081/082 (8K)，CA T24C041/042 (4K)和CAT24C021/022 (2K)以I2C是串行CMOS E2PROM器件。
釆用CMOS工艺大降低了器件的功耗。
CA T24Cxxx 另一特点是16字节的页写缓冲区，提供8脚DIP和SOIC 封装。
CA T24Cxxx的复位功能和看门狗定时器功能保证系统出现故障的时候能给CPU —个复位信号。
CA T24Cxxx 的2脚输出低电平复位信号，7脚输出高电平复位信号。
CAT24Cxxl看狗溢出信号从SDA脚输出。
CAT24Cxx2不具备看门狗功能。
绝对最大参数工作温度：-55°C〜125°C贮存温度：-65°C〜15°C各管脚承受对地电压：-2.0V〜Vcc+2.0V VCC对地电压范围：-2.0V〜7.0V 最大功耗： 1.0W管脚焊接温度(10S): 300 °C输出短路电流：100mA管脚配置]V C C ]RESET方框图表一直流操作特性表二上电时序管脚介绍WP：写保护将该管脚接Vcc，E2PRON就实现写保护（只读)。
24C02中文资料
24C02/24C04/24C08/24C16/24C32/24C641.2.2K4K 8K ，16K ，32K 位和64K 位串行I C 总线EEPROM3.24C02/04/08/16/32/64PROM256/512/1024/2048/4096/8192×8-bit1.8V1μA1mA 24C02/04/08/16/32/648/16/16/16/32/3224C02/04/08/16/32/648-pin PDIP8-pin SOP ●●●●●●●●●●●●SD SCL WP V CC NC A SD A SCL WP V CC 12348765NC NC NC GND SD A SCL WP V CC 12348765 ()SD A SCL WP V CC 12348765A 0A 1A 2GND C02C1621.8V~5.5V- 1mA- 1μA- 24C02, 256 X 8 (2K bits)- 24C04, 512 X 8 (4K bits) - 24C08, 1024 X 8 (8K bits) - 24C16, 2048 X 8 (16K bits)- 24C32, 4096 X 8 (32K bits)- 24C64, 8192 X 8 (64K bits)2I CI C 1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) ( 5 ms)8 (24C02)16(24C04/08/16),32字节页(24C32/64)ESD 2.5kV - 100- 100 8-pin DIP 8-pin SOP RoHS ●●●●●●●22●S D A 123487651A 2GND NC NC C A 2GND C04C082.7V)00n SOP●●SD A SCL WP V CC 12348765A 0A 1A 2GND C32SD ASCL WP V CC 12348765A 0A 1A 2GNDC6424C02/24C04/24C08/24C16/24C32/24C645. Ḛ1 ḚV 6. 乱 ヺ ԡⳈ⌕կ⬉⬉ Ⳉ⌕䕧 ⬉ ⏽V CC Ⳉ⌕䕧 ⬉ V IN V OUT T STG -0.3 ~ V CC +0.3-0.3 ~ V CC +0.3-0.3 ~ +6.5°C -65 ~ +150V °C7. 㤤 ӊヺ ԡⳈ⌕կ⬉⬉ V CC ⏽T A+855.5 1.8-40(䍙 乱 㛑Ӯ 㟈 ӊ )V V ( 㤤 ӊϟ ⦄ 㛑)SDASCL WP V CCNC /NC /NC /A0NC /NC /A1/A1NC /A2/A2/A2C16/C08/C04/C02GNDSTART STOPLOGICSERIAL CONTROLLOGICDEVICE ADDRESS COMPARATORDATA WORD ADDRESS COUNTER LOADCOMPLOADINCY DECODER HIGH VOLTAGE PUMP/TIMING ENDATA RECOVERYEEPROMSERIAL MUXX D E C O D E RDOUT/ACKNOWLEDGEDINESD ⬉ (Ҏԧ )ESD ⬉ ( )V ESD2500200V V乱⬉ 䕧 ⬉ 乱 㛑Ӯ 㟈 ӊ DOUTmA 9. Ⳉ⌕⬉⇨⡍ヺ ԡ ⬉⌕կ⬉⬉⌕I CC V CC =5V⌟䆩 ӊ100kHz 3.0䕧 Ԣ⬉ ⬉μA 3.01.0-0.6V 0.4V IN = V CC GND 0.05( ӊ˖T A = 0°C ̚ +70°C, V CC = +1.8V ̚ +5.5V ˈ䰸䴲 ⊼䞞)䕧 Ԣ⬉ ⬉ μA V IL 0.4V CC0.20.4100kHz V V CC ×0.3I SB V IN = V CC GND V OUT = V CC GND μA 䕧 ⓣ⬉⌕䕧 ⓣ⬉⌕I LI I LO V IH 䕧 催⬉ ⬉ V CC +0.5V V V VV OL3V OL2V = 2.1 mA V 10. Ѹ⌕⬉⇨⡍ ( ӊ˖T A = 0°C ̚ +70°C, V = +1.8V +5.5V, C L = 100 pF ˈ䰸䴲 ⊼䞞)ヺ ԡ䩳催⬉䩳乥⥛, SCL ⌟䆩 ӊ400V CC =1.8V 1000ns 0.050.050.60.90.6 μskHz 1.20.5540V CC =5V 0.4t LOW μs ⍜䰸 䯈 䩳ϟ䰡⊓ 䕧 䯈䱨 䯈t I t AA50t HIGH䩳Ԣ⬉ μsV CC =1.8V V CC =5V V CC =1.8V V CC =5V V CC =1.8V V CC =5V V CC =1.8V V CC =5V8. 㛮⬉( ӊ˖T A = 25°C, f = 1.0 MHz, V CC = +1.8V)pFヺ ԡ䕧 /䕧 ⬉ (SDA)C I/O 䕧 ⬉ (A0, A1, A2, SCL)C IN68 pF⌟䆩 ӊV I/O = 0V V IN = 0V1.2 㒓䞞 䯈t BUF0.5μs V CC =1.8V V CC =5V䇏1.03.0 mA m 042.0C =5.0V, I OL = 3.0 mA CC ×0.7GNDOL1V CC =3.0V, I OL =2.1mA CC =1.8V, I OL = 0.15 mA =C CC = +1.8V ̚+5.5f SCL10. Ѹ⌕⬉⇨⡍ (㓁)䕧 Ϟ 䯈 䕧 䯈0ns500.650.25ns t WRns 100ns ℶ ӊ ゟ 䯈 䕧 䯈t R t DH t F 䕧 ゟ 䯈μs ms䕧 ϟ䰡 䯈t SU.STOV CC =1.8V V CC =5V V CC =1.8V V CC =5Vμs 300100300t HD.DAT t SU.DAT 2 㒓3SCLSDA_INSDA _OUTt F t LOWt SU .STAt HD.STAt AA t DHt BUFt SU.STOt Rt HD.DAT t SU.DAT t HIGH t LOW8th BIT SCLSDAACKSTOPCONDITIONSTART CONDITIONt WR (1)t HD.STAμs 䍋 ӊ 䯈䍋 ӊ ゟ 䯈t SU.STA V CC =1.8V V CC =5V V CC =1.8V V CC =5Vμs 0.60.250.60.25ヺ ԡ ⌟䆩 ӊ ⊼ 䯈W :5 ҢϔϾ ⱘ ℶ ӊ 㟇 䚼 㒧 ⱘ 䯈DŽn 08V μ3001AHIG11.3156247A0A1A2SDA SCL WP GND V CCA2A1A024C02/32/64A2A1A0824C02/32/6424C04A2A1424C04A024C08A2224C08A0A124C1616KA2A1A0/SDA V CC10kΩSCL8WP WPWPV CC12.13. 䆺㒚 䇈24CXX I C 㒓Ӵ䕧 䆂DŽI C ϔ⾡ ǃϸ㒓І㸠䗮䆃 ˈ І㸠 㒓SDA І㸠 䩳㒓SCL DŽϸḍ㒓䛑 乏䗮䖛ϔϾϞ ⬉䰏 ⬉⑤DŽ ⱘ 㒓䜡㕂 4 ⼎4 ϸ㒓 㒓䜡㕂㒓Ϟ 䗕 ⱘ ӊ㹿⿄ 䗕 ˈ ⱘ ӊ㹿⿄ DŽ Ѹ ⱘ ӊ㹿⿄Џ ӊˈ Џ ӊ ⱘ ӊ 㹿⿄Ң ӊDŽЏ ӊѻ⫳І㸠 䩳SCL ˈ㒓ⱘ䆓䯂⢊ ǃѻ⫳START STOP ӊDŽ24CXX I C 㒓ЁЎҢ ӊ DŽ㒓 Ѣぎ䯆⢊ ҹ Ӵ䕧DŽ↣ Ӵ䕧 ѢSTART ӊˈ㒧 ѢSTOP ӊˈѠ㗙П䯈ⱘ 㡖 ≵ 䰤 ⱘˈ⬅ 㒓ϞⱘЏ ӊ DŽ ҹ 㡖˄8ԡ˅Ў ԡӴ䕧ˈ9ԡ ⬅ ѻ⫳ ㄨDŽ䍋 ℶ ӊ䩳㒓䛑Ў催 ⿄ 㒓 ぎ䯆⢊ DŽ SCL Ў催⬉ SDA ⱘϟ䰡⊓˄催 Ԣ 䍋 ӊ˄START ˈㅔ ЎS ˅ˈSDA ⱘϞ ⊓˄Ԣ 催˅ ℶ ӊ˄STOP ˈㅔ ЎP ˅DŽ 㾕 5DŽ5 䍋 ӊ ℶ ӊⱘ НV CCҪ24Cxx MPU SDASCLR PR Pϸ㒓І㸠S Ў催ㅔ ЎⱘϞ ⊓˄Ԣ 㒓І㸠 㒓SS 䍋 ӊ222ԡӴ䕧↣Ͼ 䩳㛝 Ӵ䗕ϔԡ DŽSCL Ў催 SDA 乏 〇 ˈ Ўℸ SDA ⱘ 㹿䅸Ў DŽԡӴ䕧 㾕 6DŽ6 ԡӴ䕧ㄨ㒓Ϟⱘ ↣ ϔϾ 㡖 ѻ⫳ϔϾ ㄨˈЏ ӊ 乏ѻ⫳ϔϾ ⱘ乱 ⱘ 䩳㛝 ˈ㾕 7DŽ7 I C㒓ⱘ ㄨ ԢSDA 㒓㸼⼎ ㄨˈ ㄨ㛝 䯈 〇 ⱘԢ⬉ DŽ Џ ӊ ˈ 乏 Ӵ䕧㒧 ⱘ 㒭 䗕 ˈ ϔϾ 㡖П ⱘ ㄨ㛝 䯈ϡӮѻ⫳ ㄨ ˄ϡ ԢSDA ˅DŽ䖭⾡ ϟˈ 䗕 乏䞞 SDA 㒓Ў催ҹ Џ ӊѻ⫳ ℶ ӊDŽ䗕 䕧 ⱘ䕧 ⱘЏ ӊ ⱘ䍋 ӊ289䴲 ㄨㄨㄨ 䩳㛝㒓〇䆌SDASCL2ѻ⫳ϔϾ ㄨˈЏ ӊ 乏ѻ⫳ϔԢ㒓Ӵӊ ⱘSCL 䍋 ӊS1ӊ䍋 ӊՓ㛑㢃⠛䇏 ˈEEPROM 䛑㽕∖ 8ԡⱘ ӊ ˄㾕 8˅DŽӊ ⬅"1"ǃ"0" 㒘 ˈ 4ԡ Ё ⼎ˈ Ѣ І㸠EEPROM 䛑 ϔḋⱘ Ѣ24C02/32/64ˈ䱣 3ԡA2ǃA1 A0Ў ӊ ԡˈ 乏Ϣ⹀ӊ䕧 㛮 ϔ㟈DŽ Ѣ24C04ˈ䱣 2ԡA2 A1Ў ӊ ԡˈ 1ԡЎ义 ԡDŽA2 A1 乏Ϣ⹀ӊ䕧 㛮 ϔ㟈ˈ㗠A0 ぎ㛮DŽѢ24C08ˈ䱣 1ԡA2Ў ӊ ԡˈ 2ԡЎ义 ԡDŽA2 乏Ϣ⹀ӊ䕧 㛮 ϔ㟈ˈ㗠A1 A0 ぎ㛮DŽѢ24C16ˈ ӊ ԡˈ3ԡ䛑Ў义 ԡˈ㗠A2ǃA1 A0 ぎ㛮DŽ ӊ ⱘLSB Ў䇏/ 䗝 ԡˈ催Ў䇏 ˈԢЎ DŽ㢹↨䕗 ӊ ϔ㟈ˈEEPROM 䕧 ㄨ"0"DŽ ϡϔ㟈ˈ 䖨 ⢊ DŽ8 ӊ 1010A2A1A0R/W MSBLSB1010A2A1P0R/W1010A2P1P0R/W1010P2P1P0R/Wӊ EEPROM Ԣ 㗫 ⱘ⡍⚍ˈ ӊЎ˖˄1˅⬉⑤Ϟ⬉˗˄2˅ ℶ ӊ ӏԩ 䚼 DŽ24C0424C0824C16DŽ ԡ䆂Ёѻ⫳Ё ǃ ⬉ ㋏㒳 ԡ ˈI C 㒓 䗮䖛ҹϟℹ偸 ԡ˖ ˄1˅ѻ⫳9Ͼ 䩳 DŽ˄2˅ SCL Ў催 ˈSDA гЎ催DŽ ˄3˅ѻ⫳ϔϾ䍋 ӊDŽ21. 㡖㽕∖ ӊ ACK ㄨ ˈ 8ԡⱘ DŽ 䖭Ͼ EEPROM ㄨ"0"ˈ✊ ϔϾ8ԡ DŽ 8ԡ ˈEEPROM ㄨ"0"ˈ ⴔ 乏⬅Џ ӊ 䗕 ℶ ӊ 㒜ℶ DŽℸ EEPROM 䖯 䚼 t WR ˈ 䴲 Ёˈ ℸ 䯈 䕧 䛑 Ⳉ ˈEEPROM Ӯ ㄨ˄㾕 9˅DŽ9 㡖SDA 㒓䍋 ӊM S BL S B R /W A C K M S BL S B A C KA C Kӊℶ ӊDŽ24C02/32/6413.2.图10页写24C02器件按8字节/页执行页写，24C04/08/16器件按16字节/页执行页写，24C32/64器件按32字节/页执行页写。
24c02中文资料
24C02中文资料1. 介绍24C02是一种串行电子可擦除可编程只读存储器（EEPROM），由美国Microchip Technology公司生产。
它具有2K位存储容量，可用于存储数据。
24C02具有低功耗、高可靠性和可编程性等特点，因此在许多电子设备中得到广泛应用。
2. 24C02的功能特点•存储容量：24C02具有2K位的存储容量，相当于256个字节，每个字节包含8位二进制数据。
•串行接口：24C02采用串行接口进行数据的读写操作，使得它能够与各种微处理器和其他外围设备进行通信。
•可擦除、可编程：24C02采用电子擦除可编程技术，可以对存储的数据进行擦除和编程的操作。
•低功耗：24C02在工作状态下的功耗非常低，使得它适合应用于移动设备和电池供电的设备。
•高可靠性：24C02采用了自动页写技术，具有高可靠性和稳定性，适用于各种工业和消费类电子产品。
3. 24C02的引脚图和功能说明24C02具有8个引脚，每个引脚的功能如下：•VCC：供电引脚，将其连接到供电电源即可。
•GND：地引脚，连接到系统的地线。
•SDA：串行数据输入/输出引脚，与微处理器或其他设备进行数据传输。
•SCL：串行时钟引脚，用于同步传输数据。
•WC：写控制引脚，用于控制写入和擦除操作。
•A0、A1、A2：地址选择引脚，用于选择设备的地址，使得多个设备可以同时使用。
4. 24C02的工作原理24C02采用了I2C总线协议进行数据通信，它的工作原理如下：•开始信号：主设备发出一个开始信号，通知24C02开始进行工作。
•地址传输：主设备发送一个设备地址和操作位（读或写）到24C02。
•对应设备响应：24C02将自己的设备地址进行识别，并发出一个应答信号。
•数据传输：主设备发送要读取或写入的数据到24C02。
•应答信号：24C02接收到数据后，会发出应答信号。
•停止信号：传输完成后，主设备发送一个停止信号，通知24C02本次操作结束。
24C02资料
概述：
美国微芯科技公司 （Microchip Technology Inc.）生产 的电擦写式只读存储器系列 24CXX、 24LCXX、 24AAXX 和 24FCXX （24XX*）容量范围为 128 位到 512 千位。该系列器件支持 2 线串行接口，以 x8 位存 储器块进行组合。低电压设计允许工作电压最低可至 1.8V（适用 24AAXX 器件） ，待机电流和工作电流分 别为 1 µA 和 1 mA。容量为 1 千位以及超过 1 千位的 器件具有页写入能力。 功能性地址线允许连接到同一条 总线上的器件数目最多可达 8 个。整个 24XX 系列产品 提供标准的 8 引脚 PDIP、表面贴片 SOIC、 TSSOP 和 MSOP 封装。大部分容量为 128 位到 16 千位的器件还 提供 5 引脚 SOT-23 封装。另外还提供 DFN 封装 （2x3mm 或 5x6mm） 。所有封装皆为无铅 （雾锡）封 装。
24AA00/24LC00/24C00 24AA014/24LC014 24AA02/24LC02B 24AA024/24LC024 24AA04/24LC04B 24AA16/24LC16B 24AA64/24LC64 24AA256/24LC256/24FC256
24AA01/24LC01B 24C01C 24C02C 24AA025/24LC025 24AA08/24LC08B 24AA32A/24LC32A 24AA128/24LC128/24FC128 24AA512/24LC512/24FC512
封装类型 （1）
PDIP/SOIC
A0 A1 A2 VSS 1 2 3 4 8 7 6 5 VCC WP(3) SCL SDA A0 A1 A2 VSS
（2） TSSOP/MSOP
BR24C02F-W中文资料
6) Page write function. BR24C01A-W / AF-W / AFJ-W / AFV-W : 8 bytes BR24C02-W / F-W / FJ-W / FV-W : 8 bytes BR24C04-W / F-W / FJ-W / FV-W : 16 bytes
7) DATA security Write protect feature Inhibit to WRITE at low VCC
VIH
0.7VCC
−
−
V
Input low level voltage
VIL
−
−
0.3VCC
V
Output low level coltage来自VOL−−
0.4
V
Input leakage current
ILI
−1
−
1
µA
Output leakage current
ILO
−1
−
1
µA
operatingcurrent dissipation
VCC LEVEL DETECT
8 VCC 7 WP 6 SCL 5 SDA
!Pin descriptions
Pin name
Function
A0, A1, A2 Slave address setting pin
SCL
Serial data clock
SDA
Serial data input / output ∗
tSU : STO 0.6
−
− 4.7 −
−
µs
Bus open time before start of transfer
24C02A中文资料
©1996 Microchip Technology Inc.DS11183D-page 124C01A/02A/04AFEATURES•Low power CMOS technology •Hardware write protect•Two wire serial interface bus, I 2 C ™ compatible • 5.0V only operation•Self-timed write cycle (including auto-erase)•Page-write buffer•1ms write cycle time for single byte•1,000,000 Erase/Write cycles guaranteed •Data retention >200 years •8-pin DIP/SOIC packages•Available for extended temperature ranges DESCRIPTIONThe Microchip Technology Inc. 24C01A/02A/04A is a 1K/2K/4K bit Electrically Erasable PROM. The device is organized as shown, with a standard two wire serial interface. Advanced CMOS technology allows a signif-icant reduction in power over NMOS serial devices. A special feature in the 24C02A and 24C04A provides hardware write protection for the upper half of the block.The 24C01A and 24C02A have a page write capability of two bytes and the 24C04A has a page length of eight bytes. Up to eight 24C01A or 24C02A devices and up to four 24C04A devices may be connected to the same two wire bus.This device offers fast (1ms) byte write and extended (-40 ° C to 125 ° C) temperature operation. It is recommended that all other applications use Microchip’s 24LCXXB.-Commercial (C):0˚C to +70˚C -Industrial (I):-40˚C to +85˚C -Automotive (E):-40˚C to +125˚C24C01A24C02A 24C04A Organization 128 x 8258 x 8 2 x 256 x 8Write Protect None 080-0FF 100-1FF Page Write Buffer2 Bytes2 Bytes8 BytesPACKAGE TYPESBLOCK DIAGRAMNC SS CC A0A1NC A2NCV 1234567141312NC SCL SDA NC981110WP V NC * “TEST” pin in 24C01A24C01A 24C02A 24C04A24C01A 24C02A 24C04A24C01A 24C02A 24C04AA0A1A2V SS12348765V CC WP*SCL SDAA0A1A2V SS12348765V CC WP*SCL SDADIP8-leadSOIC14-lead SOICVcc VssSDASCLData Buffer (FIFO)Data Reg.VppR/W AmpMemory ArrayA d d r e s s P o in te rA0 to A7IncrementA8Slave Addr.Control LogicA0A1A2WP1K/2K/4K 5.0V I 2 C ™Serial EEPROMsI 2 C is a trademark of Philips Corporation.This document was created with FrameMaker 404元器件交易网24C01A/02A/04ADS11183D-page 2 © 1996 Microchip Technology Inc.1.0ELECTRICAL CHARACTERISTICS1.1Maximum Ratings*V CC ...................................................................................7.0V All inputs and outputs w.r.t. V SS ...............-0.6V to V CC +1.0V Storage temperature.....................................-65˚C to +150˚C Ambient temp. with power applied................-65˚C to +125˚C Soldering temperature of leads (10 seconds).............+300˚C ESD protection on all pins................................................4 kV*Notice: Stresses above those listed under “Maximum ratings”may cause permanent damage to the device. This is a stress rat-ing only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.TABLE 1-1:PIN FUNCTION TABLEName FunctionA0No Function for 24C04A only, Must be connected to V CC or V SS A0, A1, A2Chip Address Inputs V SS GroundSDA Serial Address/Data I/O SCL Serial ClockTEST (24C01A only) V CC or V SS WP Write Protect Input VCC+5V Power SupplyTABLE 1-2:DC CHARACTERISTICSFIGURE 1-1:BUS TIMING START/STOPVCC = +5V ( ± 10%)Commercial (C):Tamb =0 ° C to +70 ° C Industrial (I):Tamb =-40 ° C to +85 ° C Automotive (E):Tamb =-40 ° C to +125 ° CParameterSymbolMin.Max.Units ConditionsV CC detector threshold V TH 2.8 4.5V SCL and SDA pins:High level input voltage Low level input voltage Low level output voltage V IH V IL V OL V CC x 0.7-0.3V CC + 1V CC x 0.30.4V V V I OL = 3.2 mA (SDA only)A1 & A2 pins:High level input voltage Low level input voltage V IH V IL V CC - 0.5-0.3V CC + 0.50.5V V Input leakage current ILI—10 µ A V IN = 0V to V CC Output leakage current ILO —10 µ A V OUT = 0V to V CCPin capacitance (all inputs/outputs)C IN , C OUT —7.0pF V IN /V OUT = 0V (Note) Tamb = +25˚C, f = 1 MHzOperating current I CC Write — 3.5mA F CLK = 100 kHz, program cycle time = 1 ms, Vcc = 5V, Tamb = 0˚C to +70˚CI CC Write—4.25mAF CLK = 100 kHz, program cycle time = 1 ms, Vcc = 5V, Tamb = (I) and (E)ICC Read—750 µ AV CC = 5V, Tamb= (C), (I) and (E)Standby current ICCS—100 µ A SDA=SCL=VCC=5V (no PROGRAM active)Note:This parameter is periodically sampled and not 100% testedT SU :STAT HD :STAV HYST SU :STOSTART STOPSCLSDA元器件交易网©1996 Microchip Technology Inc.DS11183D-page 324C01A/02A/04ATABLE 1-3:AC CHARACTERISTICSFIGURE 1-2:BUS TIMING DATAParameterSymbol Min.Typ Max.Units RemarksClock frequency F CLK ——100kHz Clock high time T HIGH 4000——ns Clock low timeT LOW 4700——ns SDA and SCL rise time T R ——1000ns SDA and SCL fall time T F ——300ns START condition hold time T HD :S TA 4000——ns After this period the first clock pulse is generated START condition setup time T SU :S TA 4700——ns Only relevant for repeated START conditionData input hold time T HD :D AT 0——ns Data input setup time T SU :D AT 250——nsData output delay time T AA 300—3500(Note 1)STOP condition setup time T SU :S TO 4700——ns Bus free timeT BUF4700——nsTime the bus must be free before a new transmission can startInput filter time constant (SDA and SCL pins)T I ——100ns Program cycle timeTWC—.41ms Byte mode.4N N ms Page mode, N=# of bytesEndurance —1M ——cycles25 °C, Vcc = 5.0V, BlockMode (Note 2)Note 1:As transmitter the device must provide this internal minimum delay time to bridge the undefined region (min-imum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.2:This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-cation, please consult the Total Endurance Model which can be obtained on our BBS or website.T SU :STAT FT LOWT HIGHT RT HD :DATT SU :DAT T SU :STOT HD :STAT BUFT AAT AAT SPT HD :STASCLSDA INSDA OUT元器件交易网24C01A/02A/04ADS11183D-page 4© 1996 Microchip Technology Inc.2.0FUNCTIONAL DESCRIPTIONThe 24C01A/02A/04A supports a bidirectional two wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access, and gener-ates the START and STOP conditions, while the 24C01A/02A/04A works as slave. Both master and slave can operate as transmitter or receiver but the master device determines which mode is activated.Up to eight 24C01/24c02s can be connected to the bus,selected by the A0, A1 and A2 chip address inputs. Up to four 24C04As can be connected to the bus, selected by A1 and A2 chip address inputs. A0 must be tied to V CC or V SS for the 24C04A. Other devices can be con-nected to the bus but require different device codes than the 24C01A/02A/04A (refer to section Slave Address).3.0BUS CHARACTERISTICSThe following bus protocol has been defined:•Data transfer may be initiated only when the bus is not busy.•During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition.Accordingly, the following bus conditions have been defined (Figure 3-1).3.1Bus not Busy (A)Both data and clock lines remain HIGH.3.2Start Data Transfer (B)A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition.3.3Stop Data Transfer (C)A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.3.4Data Valid (D)The state of the data line represents valid data when,after a START condition, the data line is stable for the duration of the HIGH period of the clock signal.The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data.Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device and is theoretically unlimited.3.5AcknowledgeEach receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit.The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.Note:The 24C01A/02A/04A does not generate any acknowledge bits if an internal pro-gramming cycle is in progress.FIGURE 3-1:DATA TRANSFER SEQUENCE ON THE SERIAL BUS(A)(B)(D)(D)(A)(C)START CONDITIONADDRESS OR ACKNOWLEDGEVALID DATA ALLOWED TO CHANGESTOP CONDITIONSCLSDA元器件交易网© 1996 Microchip Technology Inc.DS11183D-page 524C01A/02A/04A4.0SLAVE ADDRESSThe chip address inputs A0, A1 and A2 of each 24C01A/02A/04A must be externally connected to either V CC or ground (V SS ), assigning to each 24C01A/02A/04A a unique address. A0 is not used on the 24C04A and must be connected to either V CC or V SS . Up to eight 24C01A or 24C02A devices and up to four 24C04A devices may be connected to the bus. Chip selection is then accomplished through software by setting the bits A0, A1 and A2 of the slave address to the corresponding hard-wired logic levels of the selected 24C01A/02A/04A.After generating a START condition, the bus master transmits the slave address consisting of a 4-bit device code (1010) for the 24C01A/02A/04A, followed by the chip address bits A0, A1 and A2. In the 24C04A, the seventh bit of that byte (A0) is used to select the upper block (addresses 100—1FF) or the lower block (addresses 000—0FF) of the array.The eighth bit of slave address determines if the master device wants to read or write to the 24C01A/02A/04A (Figure 4-1).The 24C01A/02A/04A monitors the bus for its corre-sponding slave address all the time. It generates an acknowledge bit if the slave address was true and it is not in a programming mode.FIGURE 4-1:SLAVE ADDRESS ALLOCATION5.0BYTE PROGRAM MODEIn this mode, the master sends addresses and one data byte to the 24C01A/02A/04A.Following the START signal from the master, the device code (4-bits), the slave address (3-bits), and the R/W bit, which is logic LOW, are placed onto the bus by the master. This indicates to the addressed 24C01A/02A/04A that a byte with a word address will follow after it has generated an acknowledge bit. Therefore the next byte transmitted by the master is the word address and will be written into the address pointer of the 24C01A/02A/04A. After receiving the acknowledge of the 24C01A/02A/04A, the master device transmits the data word to be written into the addressed memory location.The 24C01A/02A/04A acknowledges again and the master generates a STOP condition. This initiates the internal programming cycle of the 24C01A/02A/04A (Figure 6-1).SLAVE ADDRESS1010A2A1A0R/W ASTARTREAD/WRITE6.0PAGE PROGRAM MODETo program the 24C01A/02A/04A, the master sends addresses and data to the 24C01A/02A/04A which is the slave (Figure 6-1 and Figure 6-2). This is done by supplying a START condition followed by the 4-bit device code, the 3-bit slave address, and the R/W bit which is defined as a logic LOW for a write. This indi-cates to the addressed slave that a word address will follow so the slave outputs the acknowledge pulse to the master during the ninth clock pulse. When the word address is received by the 24C01A/02A/04A, it places it in the lower 8 bits of the address pointer defining which memory location is to be written. (The A0 bit transmitted with the slave address is the ninth bit of the address pointer for the 24C04A). The 24C01A/02A/04A will generate an acknowledge after every 8-bits received and store them consecutively in a RAM buffer until a STOP condition is detected. This STOP condi-tion initiates the internal programming cycle. The RAM buffer is 2 bytes for the 24C01A/02A and 8 bytes for the 24C04A. If more than 2 bytes are transmitted by the master to the 24C01A/02A, the device will not acknowl-edge the data transfer and the sequence will be aborted. If more than 8 bytes are transmitted by the master to the 24C04A, it will roll over and overwrite the data beginning with the first received byte. This does not affect erase/write cycles of the EEPROM array and is accomplished as a result of only allowing the address registers bottom 3 bits to increment while the upper 5bits remain unchanged.If the master generates a STOP condition after trans-mitting the first data word (Point ‘P’ on Figure 6-1), byte programming mode is entered.The internal, completely self-timed PROGRAM cycle starts after the STOP condition has been generated by the master and all received data bytes in the page buffer will be written in a serial manner.The PROGRAM cycle takes N milliseconds, whereby N is the number of received data bytes (N max = 8 for 24C04A, 2 for 24C01A/02A).元器件交易网24C01A/02A/04ADS11183D-page 6© 1996 Microchip Technology Inc.FIGURE 6-1:BYTE WRITEFIGURE 6-2:PAGE WRITESPBUS ACTIVITY MASTER SDA LINE BUS ACTIVITYS T A R TS T O PCONTROL BYTE WORD ADDRESSDATAA C KA C KA C KSPBUS ACTIVITY MASTERSDA LINE BUS ACTIVITYS T A R TCONTROL BYTE WORD ADDRESS (n)DATA n DATA n + 7S T O PA C KA C KA C KA C KA C KDATA n + 17.0ACKNOWLEDGE POLLINGSince the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write com-mand has been issued from the master, the device ini-tiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master send-ing a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Figure 7-1 for flow diagram.FIGURE 7-1:ACKNOWLEDGE POLLING FLOWSendWrite CommandSend Stop Condition to Initiate Write CycleSend StartSend Control Byte with R/W = 0Did Device Acknowledge (ACK = 0)?Next OperationNOYES元器件交易网© 1996 Microchip Technology Inc.DS11183D-page 724C01A/02A/04A8.0WRITE PROTECTIONProgramming of the upper half of the memory will not take place if the WP pin of the 24C02A or 24C04A is connected to V CC (+5.0V). The device will accept slave and word addresses but if the memory accessed is write protected by the WP pin, the 24C02A/04A will not generate an acknowledge after the first byte of data has been received, and thus the program cycle will not be started when the STOP condition is asserted. Polarity of the WP pin has no effect on the 24C01A.9.0READ MODEThis mode illustrates master device reading data from the 24C01A/02A/04A.As can be seen from Figure 9-2 and Figure 9-3, the master first sets up the slave and word addresses by doing a write. (Note: Although this is a read mode, the address pointer must be written to). During this period the 24C01A/02A/04A generates the necessary acknowledge bits as defined in the appropriate section.The master now generates another START condition and transmits the slave address again, except this time the read/write bit is set into the read mode. After the slave generates the acknowledge bit, it then outputs the data from the addressed location on to the SDA pin,increments the address pointer and, if it receives an acknowledge from the master, will transmit the next consecutive byte. This auto-increment sequence is only aborted when the master sends a STOP condition instead of an acknowledge.Note 1:If the master knows where the addresspointer is, it can begin the read sequence at the current address (Figure 9-1) and save time transmitting the slave and word addresses.Note 2:In all modes, the address pointer will notincrement through a block (256 byte)boundary, but will rotate back to the first location in that block.FIGURE 9-1:CURRENT ADDRESS READFIGURE 9-2:RANDOM READSPBUS ACTIVITY MASTERSDA LINE BUS ACTIVITYS T A R TS T O PCONTROL BYTEDATA nA C KN O A C KSPSBUS ACTIVITY MASTERSDA LINEBUS ACTIVITYS T A R TS T O PCONTROL BYTE A C KWORD ADDRESS (n)CONTROL BYTES T A R TDATA (n)A C KA C KN O A C K元器件交易网24C01A/02A/04ADS11183D-page 8© 1996 Microchip Technology Inc.FIGURE 9-3:SEQUENTIAL READPBUS ACTIVITY MASTER SDA LINE BUS ACTIVITYS T O PCONTROL BYTEA C KN O A C KDATA n DATA n + 1DATA n + 2DATA n + XA C KA C KA C K10.0PIN DESCRIPTION10.1A0, A1, A2 Chip Address InputsThe levels on these inputs are compared with the cor-responding bits in the slave address. The chip is selected if the compare is true. For 24C04 A0 is no function.Up to eight 24C01A/02A's or up to four 24C04A's can be connected to the bus.These inputs must be connected to either V SS or V CC .10.2SDA Serial Address/Data Input/OutputThis is a bidirectional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the SDA bus requires a pull-up resistor to V CC (typical 10K Ω).For normal data transfer, SDA is allowed to change only during SCL LOW. Changes during SCL HIGH are reserved for indicating the START and STOP condi-tions.10.3SCL Serial ClockThis input is used to synchronize the data transfer from and to the device.10.4WP Write ProtectionThis pin must be connected to either V CC or V SS for 24C02A or 24C04A. It has no effect on 24C01A.If tied to V CC , PROGRAM operations onto the upper memory block will not be executed. Read operations are possible.If tied to V SS , normal memory operation is enabled (read/write the entire memory).This feature allows the user to assign the upper half of the memory as ROM which can be protected against accidental programming. When write is disabled, slave address and word address will be acknowledged but data will not be acknowledged.Note 1: A “page” is defined as the maximum num-ber of bytes that can be programmed in a single write cycle. The 24C04A page is 8bytes long; the 24C01A/02A page is 2bytes long.Note 2: A “block” is defined as a continuous areaof memory with distinct boundaries. The address pointer can not cross the bound-ary from one block to another. It will how-ever, wrap around from the end of a block to the first location in the same block. The 24C04A has two blocks, 256 bytes each.The 24C01A and 24C02A each have only one block.元器件交易网元器件交易网24C01A/02A/04A NOTES:© 1996 Microchip Technology Inc.DS11183D-page 924C01A/02A/04ADS11183D-page 10© 1996 Microchip Technology Inc.NOTES:元器件交易网24C01A/02A/04A© 1996 Microchip Technology Inc.DS11183D-page 1124C01A/02A/04A Product Identification SystemTo order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices.Package:P =Plastic DIPSN =Plastic SOIC (150 mil Body), 8-lead SM =Plastic SOIC (207 mil Body), 8-leadSL =Plastic SOIC (150 mil Body), 14-lead, 24C04A onlyTemperature Blank =0°C to +70°CRange:I =-40°C to +85°C E =-40°C to +125°C Device:24C01A 1K I 2C Serial EEPROM24C01AT 1K I 2C Serial EEPROM (Tape and Reel)24C02A 2K I 2C Serial EEPROM24C02AT 2K I 2C Serial EEPROM (Tape and Reel)24C04A 4K I 2C Serial EEPROM24C04AT4K I 2C Serial EEPROM (Tape and Reel)24C01A/02A/04A-/P元器件交易网DS11183D-page 12© 1996 Microchip Technology Inc.Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No repre-sentation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not autho-rized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.W ORLDWIDE S ALES & S ERVICEASIA/PACIFICChinaMicrochip TechnologyUnit 406 of Shanghai Golden Bridge Bldg.2077 Yan’an Road West, Hongiao District Shanghai, Peoples Republic of China Tel: 86 21 6275 5700Fax: 011 86 21 6275 5060 Hong KongMicrochip Technology RM 3801B, Tower Two Metroplaza223 Hing Fong RoadKwai Fong, N.T. Hong KongTel: 852 2 401 1200 Fax: 852 2 401 3431IndiaMicrochip TechnologyNo. 6, Legacy, Convent Road Bangalore 560 025 IndiaTel: 91 80 526 3148 Fax: 91 80 559 9840KoreaMicrochip Technology168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku,Seoul, KoreaTel: 82 2 554 7200 Fax: 82 2 558 5934SingaporeMicrochip Technology 200 Middle Road #10-03 Prime Centre Singapore 188980Tel: 65 334 8870 Fax: 65 334 8850Taiwan, R.O.CMicrochip Technology 10F-1C 207Tung Hua North Road Taipei, Taiwan, ROCTel: 886 2 717 7175 Fax: 886 2 545 0139EUROPEUnited KingdomArizona Microchip Technology Ltd.Unit 6, The CourtyardMeadow Bank, Furlong RoadBourne End, Buckinghamshire SL8 5AJ Tel: 44 1628 850303 Fax: 44 1628 850178FranceArizona Microchip Technology SARL Zone Industrielle de la Bonde 2 Rue du Buisson aux Fraises 91300 Massy - FranceTel: 33 1 69 53 63 20 Fax: 33 1 69 30 90 79GermanyArizona Microchip Technology GmbH Gustav-Heinemann-Ring 125D-81739 Muenchen, GermanyTel: 49 89 627 144 0 Fax: 49 89 627 144 44ItalyArizona Microchip Technology SRLCentro Direzionale Colleone Pas Taurus 1Viale Colleoni 120041 Agrate Brianza Milan ItalyTel: 39 39 6899939 Fax: 39 39 689 9883JAPANMicrochip Technology Intl. Inc.Benex S-1 6F3-18-20, Shin Yokohama Kohoku-Ku, Yokohama Kanagawa 222 JapanTel: 81 45 471 6166 Fax: 81 45 471 61229/3/96AMERICASCorporate OfficeMicrochip Technology Inc.2355 West Chandler Blvd.Chandler, AZ 85224-6199Tel: 602 786-7200 Fax: 602 786-7277Technical Support: 602 786-7627Web: AtlantaMicrochip Technology Inc.500 Sugar Mill Road, Suite 200B Atlanta, GA 30350Tel: 770 640-0034 Fax: 770 640-0307BostonMicrochip Technology Inc.5 Mount Royal Avenue Marlborough, MA 01752Tel: 508 480-9990 Fax: 508 480-8575ChicagoMicrochip Technology Inc.333 Pierce Road, Suite 180Itasca, IL 60143Tel: 708 285-0071 Fax: 708 285-0075DallasMicrochip Technology Inc.14651 Dallas Parkway, Suite 816Dallas, TX 75240-8809Tel: 972 991-7177 Fax: 972 991-8588DaytonMicrochip Technology Inc.Suite 150Two Prestige Place Miamisburg, OH 45342Tel: 513 291-1654 Fax: 513 291-9175Los AngelesMicrochip Technology Inc.18201 Von Karman, Suite 1090Irvine, CA 92612Tel: 714 263-1888 Fax: 714 263-1338New YorkMicrochip Technmgy Inc.150 Motor Parkway, Suite 416Hauppauge, NY 11788Tel: 516 273-5305 Fax: 516 273-5335San JoseMicrochip Technology Inc.2107 North First Street, Suite 590San Jose, CA 95131Tel: 408 436-7950 Fax: 408 436-7955TorontoMicrochip Technology Inc.5925 Airport Road, Suite 200Mississauga, Ontario L4V 1W1, Canada Tel: 905 405-6279Fax: 905 405-6253All rights reserved. © 1996, Microchip Technology Incorporated, USA. 9/96Printed on recycled paper.元器件交易网。
24c02中文官方资料手册pdf
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海纳电子资讯网： ｗｗｗ．ｆｐｇａ－ａｒｍ．ｃｏｍ
上电时序 符号 tPUR tPUW
参数 上电到读操作 上电到写操作
最大 1 1
单位 ms ms
写周期限制
符号
参数
最小
典型
最大
单位
tWR
写周期时间
10
ms
写周期时间是指从一个写时序的有效停止信号到内部编程/擦除周期结束的这一段时间 在写周期期
间 总线接口电路禁能 SDA 保持为高电平 器件不响应外部操作
海纳电子资讯网： ｗｗｗ．ｆｐｇａ－ａｒｍ．ｃｏｍ
目录
1 CSI24WC0 1/02/04/08/16 ……………………………….2-10 2 CSI24WC32/64…………………………………………...11-18 3 CSI24WC128. ……………………………..…………….19-26 4 CSI24WC256. ………………………….….…………….27-34
I2C 总线协议
I2C 总线协议定义如下
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海纳电子资讯网： ｗｗｗ．ｆｐｇａ－ａｒｍ．ｃｏｍ
1 只有在总线空闲时才允许启动数据传送 2 在数据传送过程中 当时钟线为高电平时 数据线必须保持稳定状态 不允许有跳变 时
钟线为高电平时 数据线的任何电平变化将被看作总线的起始或停止信号 起始信号 时钟线保持高电平期间 数据线电平从高到低的跳变作为 I2C 总线的起始信号 停止信号 时钟线保持高电平期间 数据线电平从低到高的跳变作为 I2C 总线的停止信号 图 1 总线时序
时钟频率 SCL,SDA 输入的噪声抑制时间 SCL 变低至 SDA 数据输出及应答信号 新的发送开始前总线空闲时间 起始信号保持时间 时钟低电平周期 时钟高电平周期 起始信号建立时间 数据输入保持时间 数据输入建立时间 SDA 及 SCL 上升时间 SDA 及 SCL 下降时间 停止信号建立时间 数据输出保持时间
24C02
© 1996 Microchip Technology Inc.PreliminaryDS21170A-page 1FEATURES•ISO Standard 7816 pad locations •Low power CMOS technology - 1 mA active current typical-10 µ A standby current typical at 5.5V•Organized as a single block of 128 bytes (128 x 8) or 256 bytes (256 x 8)•Two-wire serial interface bus, I 2 C ™compatible •100 kHz and 400 kHz compatibility•Self-timed write cycle (including auto-erase)•Page-write buffer for up to 8 bytes• 2 ms typical write cycle time for page-write •ESD protection > 4 kV•1,000,000 E/W cycles guaranteed •Data retention > 200 years•Available for extended temperature ranges DESCRIPTIONThe Microchip Technology Inc. 24C01SC and 24C02SC are 1K-bit and 2K-bit Electrically Erasable PROMs with bondpad positions optimized for smart card applications. The devices are organized as a sin-gle block of 128 x 8-bit or 256 x 8-bit memory with a two-wire serial interface. The 24C01SC and 24C02SC also have page-write capability for up to 8 bytes of data.-Commercial (C):0 ° C to +70 ° CDIE LAYOUTBLOCK DIAGRAMSDA DCV CCSCLV SSHV GENERATOREEPROM ARRAY PAGE LATCHESYDECXDECSENSE AMP R/W CONTROLMEMORY CONTROL LOGICI/O CONTROL LOGIC SDA SCLV CC V SS1K/2K 5.0V I 2C Serial EEPROMs for Smart Cards24C01SC/02SCI 2C is a trademark of Philips Corporation.This document was created with FrameMaker 40424C01SC/02SCDS21170A-page 2 ©1996 Microchip Technology Inc.1.0ELECTRICAL CHARACTERISTICSMaximum Ratings*V CC ..............................................................7.0VAll inputs and outputs w.r.t. V SS ......-0.6V to VCC +1.0V Storage temperature..........................-65˚C to +150˚C Ambient temp. with power applied.......-65˚C to +125˚C ESD protection on all pads ....................................≥ 4 kV*Notice: Stresses above those listed under “Maximum ratings”may cause permanent damage to the device. This is a stress rat-ing only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.TABLE 1-1:PAD FUNCTION TABLEName Function V SS SDA SCL V CC DCGroundSerial Address/Data I/O Serial Clock+4.5V to 5.5V Power Supply Don’t connectTABLE 1-2:DC CHARACTERISTICSFIGURE 1-1:BUS TIMING START/STOPV CC = +4.5V to +5.5VCommercial (C):Tamb = 0˚C to +70˚C ParameterSymbol Min.Max.Units ConditionsSCL and SDA pads:High level input voltageV IH .7 V CC ——Low level input voltageV IL —.3 V CC V Hysteresis of Schmidt trigger inputs V HYS .05 V CC—V (Note)Low level output voltage V OL —.40V I OL = 3.0 mA, V CC = 4.5V Input leakage current (SCL)I LI -1010 µ A V IN = .1V to 5.5V Output leakage current (SDA)I LO -1010 µ A V OUT = .1V to 5.5V Pin capacitance (all inputs/outputs)C IN , C OUT —10pF V CC = 5.0V (Note 1)Tamb = 25˚C, F CLK = 1 MHz Operating currentI CC Write —3mA V CC = 5.5VI CC Read—1mA Vcc = 5.5V , SCL = 400 KHz Standby current I CCS—100µ AV CC = 5.5V , SDA = SCL = VCCNote:This parameter is periodically sampled and not 100% tested.SCLSDAT SU :STAT HD :STASTART STOPV HYST SU :STO© 1996 Microchip Technology Inc.Preliminary24C01SC/02SCTABLE 1-3:AC CHARACTERISTICSFIGURE 1-2:BUS TIMING DATAParameterSymbol Min.Max.Units RemarksClock frequency F CLK —400kHz Clock high time T HIGH 600—ns Clock low time T LOW 1300—ns SDA and SCL rise time T R —300ns (Note 1)SDA and SCL fall time T F —300ns (Note 1)START condition hold time T HD : STA 600—ns After this period the first clock pulse is generated START condition setup time T SU : STA 600—ns Only relevant for repeated START condition Data input hold time T HD : DAT 0—ns (Note 2)Data input setup time T SU : DAT 100—ns STOP condition setup time T SU : STO 600—ns Output valid from clock T AA —900ns (Note 2)Bus free timeT BUF1300—nsTime the bus must be free before a new transmission can startOutput fall time from V IH minimum to V IL maximum TOF 20 +0.1 CB 250ns (Note 1), CB ≤ 100 pF Input filter spike suppression (SDA and SCL pins)T SP —50ns (Note 3)Write cycle time T WR —10ms Byte or Page modeEndurance—106—cycles25 ° C, Vcc = 5V , Block Mode (Note 4)Note 1:Not 100% tested. CB = total capacitance of one bus line in pF .2:As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.3:The combined T SP and VHYSspecifications are due to new Schmitt trigger inputs which provide improvednoise spike suppression. This eliminates the need for a TI specification for standard operation.4:This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-cation, please consult the Total Endurance Model which can be obtained on our BBS or website.SCLSDA INSDA OUTT HD :STAT SU :STAT FT HIGHT RT SU :STOT SU :DATT HD :DATT BUFT AA T HD :STAT AAT SPT LOW24C01SC/02SCDS21170A-page 4 ©1996 Microchip Technology Inc.2.0FUNCTIONAL DESCRIPTIONThe 24C01SC/02SC supports a bi-directional two-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access, and gener-ates the START and STOP conditions, while the 24C01SC/02SC works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated.3.0BUS CHARACTERISTICSThe following bus protocol has been defined:•Data transfer may be initiated only when the bus is not busy.•During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition.Accordingly, the following bus conditions have been defined (Figure 3-1).3.1Bus not Busy (A)Both data and clock lines remain HIGH.3.2Start Data Transfer (B)A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition.3.3Stop Data Transfer (C)A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.3.4Data Valid (D)The state of the data line represents valid data when,after a START condition, the data line is stable for the duration of the HIGH period of the clock signal.The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data.Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device and is theoretically unlimited, although only the last 16will be stored when doing a write operation. When an overwrite does occur, it will replace data in a first in first out fashion.3.5AcknowledgeEach receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit.The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case,the slave must leave the data line HIGH to enable the master to generate the STOP condition.Note:The 24C01SC/02SC does not generate any acknowledge bits if an internal pro-gramming cycle is in progress.FIGURE 3-1:DATA TRANSFER SEQUENCE ON THE SERIAL BUSSCLSDA(A )(B)(D)(D)(C)(A )START CONDITIONADDRESS OR ACKNOWLEDGEVALID DATA ALLOWED TO CHANGESTOP CONDITION© 1996 Microchip Technology Inc.PreliminaryDS21170A-page 524C01SC/02SC4.0BUS CHARACTERISTICS4.1Slave AddressAfter generating a START condition, the bus master transmits the slave address consisting of a 4-bit device code (1010) for the 24C01SC/02SC, followed by three don't care bits.The eighth bit of slave address determines if the master device wants to read or write to the 24C01SC/02SC (Figure 4-1).The 24C01SC/02SC monitors the bus for its corre-sponding slave address all the time. It generates an acknowledge bit if the slave address was true, and it is not in a programming mode.FIGURE 4-1:CONTROL BYTE ALLOCATIONOperation Control Code Chip Select R/W Read Write10101010XX XXX10X = Don’t careR/W A1010X X XREAD/WRITESTARTSLAVE ADDRESS 5.0WRITE OPERATION5.1Byte WriteFollowing the start signal from the master, the device code (4 bits), the don't care bits (3 bits), and the R/W bit, which is a logic low, is placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the word address and will be written into the address pointer of the 24C01SC/02SC. After receiving another acknowledge signal from the 24C01SC/02SC, the master device will transmit the data word to be written into the addressed memory location. The 24C01SC/02SC acknowledges again and the master generates a stop condition. This initiates the internal write cycle, and during this time the 24C01SC/02SC will not generate acknowledge signals (Figure 5-1).5.2Page WriteThe write control byte, word address, and the first data byte are transmitted to the 24C01SC/02SC in the same way as in a byte write. But instead of generating a stop condition, the master transmits up to eight data bytes to the 24C01SC/02SC, which are temporarily stored in the on-chip page buffer and will be written into the memory after the master has transmitted a stop condi-tion. After the receipt of each word, the three lower order address pointer bits are internally incremented by one. The higher order five bits of the word address remains constant. If the master should transmit more than eight words prior to generating the stop condition,the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the stop condition is received an inter-nal write cycle will begin (Figure 5-2).FIGURE 5-1:BYTE WRITEFIGURE 5-2:PAGE WRITESPS T A R TS T O PBUS ACTIVITY MASTERSDA LINEBUS ACTIVITYA C KA C KA C KCONTROL BYTEWORD ADDRESSDATASPBUS ACTIVITY MASTERSDA LINEBUS ACTIVITYS T A R TS T O PCONTROL BYTEWORD ADDRESS (n)DATA nDATAn + 7DATAn + 1A C KA C KA C KA C KA C K24C01SC/02SCDS21170A-page 6Preliminary© 1996 Microchip Technology Inc.6.0ACKNOWLEDGE POLLINGSince the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write com-mand has been issued from the master, the device ini-tiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master send-ing a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then NO ACK will be returned. If the cycle is complete, then the device will return the ACK,and the master can then proceed with the next read or write command. See Figure 6-1 for flow diagram.FIGURE 6-1:ACKNOWLEDGE POLLING FLOWSendWrite CommandSend Stop Condition to Initiate Write CycleSend StartSend Control Byte with R/W = 0Did Device Acknowledge (ACK = 0)?Next OperationNOYES7.0READ OPERATIONRead operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read,and sequential read.7.1Current Address ReadThe 24C01SC/02SC contains an address counter that maintains the address of the last word accessed, inter-nally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with R/W bit set to one, the 24C01SC/02SC issues an acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24C01SC/02SC discontinues transmission (Figure 8-2).7.2Random ReadRandom read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24C01SC/02SC as part of a write operation. After the word address is sent, the master generates a start con-dition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then, the master issues the control byte again but with the R/W bit set to a one. The 24C01SC/02SC will then issue an acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer but does generate a stop con-dition and the 24C01SC/02SC discontinues transmis-sion (Figure 8-3).7.3Sequential ReadSequential reads are initiated in the same way as a ran-dom read except that after the 24C01SC/02SC trans-mits the first data byte, the master issues an acknowledge as opposed to a stop condition in a ran-dom read. This directs the 24C01SC/02SC to transmit the next sequentially addressed 8-bit word (Figure 9-1).To provide sequential reads the 24C01SC/02SC con-tains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation.© 1996 Microchip Technology Inc.PreliminaryDS21170A-page 724C01SC/02SC7.4Noise ProtectionThe 24C01SC/02SC employs a V CC threshold detector circuit which disables the internal erase/write logic if the V CC is below 1.5 volts at nominal conditions.The SCL and SDA inputs have Schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus.FIGURE 7-1:CURRENT ADDRESS READFIGURE 7-2:RANDOM READFIGURE 7-3:SEQUENTIAL READSPBUS ACTIVITY MASTERSDA LINEBUS ACTIVITYS T A R TCONTROL BYTEDATA nA C KN OA C KS T O PSPSBUS ACTIVITY MASTER SDA LINEBUS ACTIVITYS TA RT S T O PCONTROL BYTEWORD ADDRESS (n)DATA nA C KA C KN OA C KCONTROL BYTEA C KS T A R TPBUS ACTIVITYS T O PCONTROL BYTEDATA nA C KN OA C KA C KA C KA C KDATA n + 1DATA n + 2DATA n + XBUS ACTIVITY MASTER24C01SC/02SCDS21170A-page 8Preliminary© 1996 Microchip Technology Inc.8.0PAD DESCRIPTIONS8.1SDA Serial Address/Data Input/OutputThis is a bi-directional pad used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the SDA bus requires a pull-up resistor to V CC (typical 10K Ω for 100 kHz, 1K Ω for 400kHz).For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions.8.2SCL Serial ClockThis input is used to synchronize the data transfer from and to the device.8.3DC Don’t ConnectThis pad is used for test purposes and should not be bonded out. It will be pulled to V SS through an internal resistor.9.0DIE CHARACTERISTICSFigure 9-1 shows the die layout of the 24C01SC/02SC,including bondpad positions. Table 9-1 shows the actual coordinates of the bondpad midpoints with respect to the center of the die.FIGURE 9-1:DIE LAYOUTTABLE 9-1:BONDPAD COORDINATESPad NamePad Midpoint,X dir.Pad Midpoint,Y dir.V SS-495.000749.130SDA -605.875-271.875SCL 479.875-746.625V CC 605.875-261.375Note 1:Dimensions are in microns.2:Center of die is at the 0,0 point.DIPSDA DCV CCSCLV SS24C01SC/02SC NOTES:© 1996 Microchip Technology Inc.Preliminary DS21170A-page 924C01SC/02SCNOTES:DS21170A-page 10Preliminary© 1996 Microchip Technology Inc.24C01SC/02SC24C01SC/02SC Product Identification SystemTo order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed sales offices.24C01SC/02SC—/S XXDie Thickness Blank=11 mils08=8 milsOther die thicknesses available, pleaseconsult factory.Package:S=Die in Wafer PakW=WaferWF=Sawed Wafer on FrameTemperature Blank=0°C to +70°CRange:Device:24C01SC1K 12C ISO Smart Card die24C02SC2K 12C ISO Smart Card die© 1996 Microchip Technology Inc.Preliminary DS21170A-page 11DS21170A-page 12Preliminary© 1996 Microchip Technology Inc.WORLDWIDE S ALES & S ERVICEAMERICAS (continued)New YorkMicrochip T echnology Inc.150 Motor Parkway, Suite 416Hauppauge, NY 11788T el: 516 273-5305 Fax: 516 273-5335San JoseMicrochip T echnology Inc.2107 North First Street, Suite 590San Jose, CA 95131T el: 408 436-7950 Fax: 408 436-7955TorontoMicrochip T echnology Inc.5925 Airport Road, Suite 200Mississauga, Ontario L4V 1W1, Canada T el: 905 405-6279Fax: 905 405-6253ASIA/PACIFICHong KongMicrochip T echnology Rm 3801B, T ower T wo Metroplaza,223 Hing Fong Road,Kwai Fong, N.T ., Hong KongT el: 852 2 401 1200 Fax: 852 2 401 3431KoreaMicrochip T echnology168-1, Y oungbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku,Seoul, KoreaT el: 82 2 554 7200 Fax: 82 2 558 5934SingaporeMicrochip T echnology 200 Middle Road #10-03 Prime Centre Singapore 188980T el: 65 334 8870 Fax: 65 334 8850TaiwanMicrochip T echnology 10F-1C 207T ung Hua North Road T aipei, T aiwan, ROCT el: 886 2 717 7175 Fax: 886 2 545 0139EUROPEUnited KingdomArizona Microchip T echnology Ltd.Unit 6, The CourtyardMeadow Bank, Furlong RoadBourne End, Buckinghamshire SL8 5AJT el: 44 1 628 850303 Fax: 44 1 628 850178FranceArizona Microchip T echnology SARL Zone Industrielle de la Bonde 2 Rue du Buisson aux Fraises 91300 Massy - FranceT el: 33 1 69 53 63 20 Fax: 33 1 69 30 90 79GermanyArizona Microchip T echnology GmbH Gustav-Heinemann-Ring 125D-81739 Muenchen, GermanyT el: 49 89 627 144 0 Fax: 49 89 627 144 44ItalyArizona Microchip T echnology SRL Centro Direzionale ColleoniPalazzo T aurus 1 V . Le Colleoni 120041, Agrate Brianza, Milan ItalyT el: 39 39 689 9939 Fax: 39 39 689 9883JAPANMicrochip T echnology Intl. Inc.Benex S-1 6F3-18-20, Shin Y okohama Kohoku-Ku, Y okohama Kanagawa 222 JapanT el: 81 45 471 6166 Fax: 81 45 471 61225/10/96AMERICASCorporate OfficeMicrochip T echnology Inc.2355 West Chandler Blvd.Chandler, AZ 85224-6199T el: 602 786-7200 Fax: 602 786-7277Technical Support: 602 786-7627Web: /AtlantaMicrochip T echnology Inc.500 Sugar Mill Road, Suite 200B Atlanta, GA 30350T el: 770 640-0034Fax: 770 640-0307BostonMicrochip T echnology Inc.5 Mount Royal Avenue Marlborough, MA 01752T el: 508 480-9990Fax: 508 480-8575ChicagoMicrochip T echnology Inc.333 Pierce Road, Suite 180Itasca, IL 60143T el: 708 285-0071 Fax: 708 285-0075DallasMicrochip T echnology Inc.14651 Dallas Parkway, Suite 816Dallas, TX 75240-8809T el: 214 991-7177 Fax: 214 991-8588DaytonMicrochip T echnology Inc.Suite 150T wo Prestige PlaceMiamisburg, OH 45342T el: 513 291-1654 Fax: 513 291-9175Los AngelesMicrochip T echnology Inc.18201 Von Karman, Suite 1090Irvine, CA 92715T el: 714 263-1888 Fax: 714 263-1338Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No repre-sentation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not autho-rized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.All rights reserved. © 1996, Microchip Technology Incorporated, USA. 5/96。
CW24C02最新资料（信隆特供）
CW24C02最新资料（信隆特供）2K位串行I2C总线EEPROM1.描述引脚排列CW24C02/02B/02C是电可擦除PROM，电压可允许低至1.8V，待机电流和工作电流分别为1μA和1mA。
CW24C02/02B/02C 具有页写能力，每页为8字节。
2.特点●宽工作电压：1.8V~5.5V●低电压技术-1mA典型工作电流-1μA典型待机电流●存储器组织结构-CW24C02，256 X 8（2K bits）●2线串行接口，完全兼容I2C总线●I2C时钟频率为1 MHz（5V），400 kHz（1.8V，2.5V，2.7V）●施密特触发输入噪声抑制●硬件数据写保护●内部写周期（最大5 ms）●可按字节写●页写：8字节页（CW24C02）●可按字节，随机和序列读●自动递增地址●ESD保护大于2.5kV（顶视）●高可靠性- 擦写寿命：100万次- 数据保持时间：100年●封装：SOP8L、TSSOP8、SOT23-5-●无铅工艺，符合RoHS标准3.应用领域●智能化仪器仪表●工业控制●家用电器汽车电子CW24C02计算机笔记本电脑通信设备中国风CW指定代理商订购信息XX = 02/02B02C注：后缀A或B是新版本号“A”版减小了待机电流“B”版减小了待机电流和写周期“C”版同“B”版引脚说明推荐工作条件最大额定参数引脚电容直流电气特性（推荐工作条件：T交流电气特性图2. 总线时序图3. 写周期时序存储结构详细操作说明13.1I 2C 数据总线和传输协议I 2C 总线接口CW24CXX 支持I 2C 总线传输协议。
I 2C 是一种双向、两线通讯接口，分别是串行数据线SDA 和串行时钟线SCL 。
两根线都必须通过一个上拉电阻接到电源。
典型的总线配置如图4所示。
图4. 典型两线总线配置总线上发送数据的器件被称作发送器，接收数据的器件被称作接收器。
控制信息交换的器件被称作主器件，受主器件控制的器件则被称作从器件。
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广州周立功单片机发展有限公司 Tel
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上电时序 符号 tPUR tPUW
参数 上电到读操作 上电到写操作
最大 1 1
单位 ms ms
写周期限制
符号
参数
最小
典型
最大
单位
tWR
写周期时间
10
应答信号 I2C 总线数据传送时 每成功地传送一个字节数据后 接收器都必须产生一个应答信号 应答的器 件在第 9 个时钟周期时将 SDA 线拉低 表示其已收到一个 8 位数据 CAT24WC01/02/04/08/16 在接收到起始信号和从器件地址之后响应一个应答信号 如果器件已选择 了写操作 则在每接收一个 8 位字节之后响应一个应答信号 当 CAT24WC01/02/04/08/16 工作于读模式时 在发送一个 8 位数据后释放 SDA 线并监视一个应答 信号 一旦接收到应答信号 CAT24WC01/02/04/08/16 继续发送数据 如主器件没有发送应答信号 器 件停止传送数据且等待一个停止信号
ms
写周期时间是指从一个写时序的有效停止信号到内部编程/擦除周期结束的这一段时间 在写周期期
间 总线接口电路禁能 SDA 保持为高电平 器件不响应外部操作
功能描述
CAT24WC01/02/04/08/16 支持 I2C 总线数据传送协议 I2C 总线协议规定 任何将数据传送到总线的 器件作为发送器 任何从总线接收数据的器件为接收器 数据传送是由产生串行时钟和所有起始停止信 号的主器件控制的 主器件和从器件都可以作为发送器或接收器 但由主器件控制传送数据 发送或接 收 的模式 通过器件地址输入端 A0 A1 和 A2 可以实现将最多 8 个 24WC01 和 24WC02 器件 4 个 242C04 器件,2 个 24WC08 器件和 1 个 24WC16 器件连接到总线上
符号
测试项
CI/O
I/O 电容 SDA 脚
CIN
输出电容 A0 A1 A2 SCL WP
最大 8 6
单位 PF PF
条件 VI/O=0V VIN=0V
交流特性 Vcc=+1.8V +6.0V 除非特别说明 输出负载能力为 1 个 TTL 门和 100pF
读写周期范围
符号
参数
FSCL TI tAA tBUF tHD: STA tLOW tHIGH tSU: STA tHD: DAT tSUl: DAT tR tF tSU: STO tDH
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目录
1 CSI24WC0 1/02/04/08/16 ……………………………….2-10 2 CSI24WC32/64…………………………………………...11-18 3 CSI24WC128. ……………………………..…………….19-26 4 CSI24WC256. ………………………….….…………….27-34
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直流操作特性
Vcc=+1.8V +6.0V 除非特别说明
符号
参数
最小
ICC ISB ILI ILO VIL VIH VOL1 VOL2
电源电流 备用电流(Vcc=5.0V) 输入漏电流 输出漏电流 输入低电压 输入高电压 输出低电压 输出低电压
管脚配置
管脚描述
管脚名称
A0 A1 A2 SDA SCL WP Vcc Vss
功能 器件地址选择 串行数据/地址 串行时钟 写保护 +1.8V 6.0V 工作电压 l
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概述
CAT24WC01/02/04/08/16 是 一 个 1K/2K/4K/8K/16K 位 串 行 CMOS E2PROM 内 部 含 有 128/256/512/1024/2048 个 8 位字节 CATALYST 公司的先进 CMOS 技术实质上减少了器件的功耗 CAT24WC01 有一个 8 字节页写缓冲器 CAT24WC02/04/08/16 有一个 16 字节页写缓冲器 该器件通过 I2C 总线接口进行操作 有一个专门的写保护功能
管脚描述
SCL 串行时钟 CAT24WC01/02/04/08/16 串行时钟输入管脚用于产生器件所有数据发送或接收的时钟 这是一个输 入管脚 SDA 串行数据/地址 CAT24WC01/02/04/08/16 双向串行数据/地址管脚用于器件所有数据的发送或接收 SDA 是一个开漏 输出管脚 可与其它开漏输出或集电极开路输出进行线或 wire-OR A0 A1 A2 器件地址输入端 这些输入脚用于多个器件级联时设置器件地址 当这些脚悬空时默认值为 0 24WC01 除外 当使用 24WC01 或 24WC02 时最大可级联 8 个器件 如果只有一个 24WC02 被总线寻址 这三个地 址输入脚 A0 A1 A2 可悬空或连接到 Vss 如果只有一个 24WC01 被总线寻址 这三个地址输入 脚 A0 A1 A2 必须连接到 Vss 当使用 24WC04 时最多可连接 4 个器件 该器件仅使用 A1 A2 地址管脚 A0 管脚未用 可以连 接到 Vss 或悬空 如果只有一个 24WC04 被总线寻址 A1 和 A2 地址管脚可悬空或连接到 Vss 当使用 24WC08 时最多可连接 2 个器件 且仅使用地址管脚 A2 A0 A1 管脚未用 可以连接到 Vss 或悬空 如果只有一个 24WC08 被总线寻址 A2 管脚可悬空或连接到 Vss 当使用 24WC16 时最多只可连接 1 个器件 所有地址管脚 A0 A1 A2 都未用 管脚可以连接到 Vss 或悬空 WP 写保护 如果 WP 管脚连接到 Vcc 所有的内容都被写保护 只能读 当 WP 管脚连接到 Vss 或悬空 允许 器件进行正常的读/写操作
图 4 应答时序
图 5 从器件地址位
1. A0 A1 和 A2 对应器件的管脚 1 2 和 3 2. a8 a9 和 a10 对应存储阵列地址字地址
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广州周立功单片机发展有限公司 Tel
020 38730976 38730977 Fax 38730925
页写 用页写 CAT24WC01 可一次写入 8 个字节数据 CAT24WC02/04/08/16 可以一次写入 16 个字节的 数据 页写操作的启动和字节写一样 不同在于传送了一字节数据后并不产生停止信号 主器件被允许 发送 P CAT24WC01 P=7 CAT24WC02/04/08/16 P=15 个额外的字节 每发送一个字节数据后 CAT24WC01/02/04/08/16 产生一个应答位并将字节地址低位加 1 高位保持不变 如果在发送停止信号之前主器件发送超过P+1个字节 地址计数器将自动翻转 先前写入的数据被 覆盖 接收到P+1字节数据和主器件发送的停止信号后 CAT24CXXX启动内部写周期将数据写到数据区 所 有接收的数据在一个写周期内写入CAT24WC01/02/04/08/16
钟线为高电平时 数据线的任何电平变化将被看作总线的起始或停止信号
起始信号 时钟线保持高电平期间 数据线电平从高到低的跳变作为 I2C 总线的起始信号 停止信号 时钟线保持高电平期间 数据线电平从低到高的跳变作为 I2C 总线的停止信号
图 1 总线时序
图 2 写周期时序
图 3 起始/停止时序
器件寻址
主器件通过发送一个起始信号启动发送过程 然后发送它所要寻址的从器件的地址 8 位从器件地 址的高 4 位固定为 1010 见图 5 接下来的 3 位 A2 A1 A0 为器件的地址位 用来定义哪个器件 以及器件的哪个部分被主器件访问 上述 8 个 CAT24WC01/02 4 个 CAT24WC04 2 个 CAT24WC08
方框图
极限参数
工作温度 工业级 -55 +125
商业级 0 +75 贮存温度 -65 +150
各管脚承受电压 -2.0 Vcc+2.0V
Vcc 管脚承受电压 -2.0 +7.0V
封装功率损耗 Ta=25 焊接温度(10 秒) 300
1.0W
输出短路电流 100mA
可靠性参数
符号
参数
NEND TDR VZAP ILTH
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广州周立功单片机发展有限公司 Tel
020 38730976 38730977 Fax 38730925
1 个 CAT24WC16 可单独被系统寻址 从器件 8 位地址的最低位 作为读写控制位 1 表示对从器件 进行读操作 0 表示对从器件进行写操作 在主器件发送起始信号和从器件地址字节后 CAT24WC01/02/04/08/16 监视总线并当其地址与发送的从地址相符时响应一个应答信号 通过 SDA 线 CAT24WC01/02/04/08/16 再根据读写控制位 R/W 的状态进行读或写操作
写操作
字节写 在字节写模式下 主器件发送起始命令和从器件地址信息 R/W 位置零 给从器件 在从器件产生 应答信号后 主器件发送 CAT24WC01/02/04/08/16 的字节地址 主器件在收到从器件的另一个应答信号 后 再发送数据到被寻址的存储单元 CAT24WC01/02/04/08/16 再次应答 并在主器件产生停止信号后 开始内部数据的擦写 在内部擦写过程中 CAT24WC01/02/04/08/16 不再应答主器件的任何请求 图 6 字节写时序
时钟频率 SCL,SDA 输入的噪声抑制时间 SCL 变低至 SDA 数据输出及应答信号 新的发送开始前总线空闲时间 起始信号保持时间 时钟低电平周期 时钟高电平周期 起始信号建立时间 数据输入保持时间 数据输入建立时间 SDA 及 SCL 上升时间 SDA 及 SCL 下降时间 停止信号建立时间 数据输出保持时间