FPGA可编程逻辑器件芯片XXC95144-10PQ100I中文规格书

Chapter1 Configuration OverviewConfiguration Modes and PinsVirtex®-5 devices are configured by loading application-specific configuration data—thebitstream—into internal memory. Because Xilinx FPGA configuration memory is volatile,it must be configured each time it is powered-up. The bitstream is loaded into the devicethrough special configuration pins. These configuration pins serve as the interface for anumber of different configuration modes:∙Master-serial configuration mode∙Slave-serial configuration mode∙Master SelectMAP (parallel) configuration mode (x8 and x16 only)∙Slave SelectMAP (parallel) configuration mode (x8, x16, and x32)∙JTAG/Boundary-Scan configuration mode∙Master Serial Peripheral Interface (SPI) Flash configuration mode∙Master Byte Peripheral Interface Up (BPI-Up) Flash configuration mode(x8 and x16 only)∙Master Byte Peripheral Interface Down (BPI-Down) Flash configuration mode(x8 and x16 only)The configuration modes are explained in detail in Chapter2, “Configuration Interfaces.”The specific configuration mode is selected by setting the appropriate level on thededicated Mode input pins M[2:0]. The M2, M1, and M0 mode pins should be set at aconstant DC voltage level, either through pull-up or pull-down resistors, or tied directly toground or V CC_CONFIG. The mode pins should not be toggled during and afterconfiguration. See Table2-1, page37 for the mode pin setting options.The terms Master and Slave refer to the direction of the configuration clock (CCLK):∙In Master configuration modes, the Virtex-5 device drives CCLK from an internaloscillator. To get the desired frequency, BitGen -g ConfigRate is used. The“BitGen” section of the Development System Reference Guide provides moreinformation. After configuration, the CCLK is turned off unless the persist optionis selected or SEU detection is used. The CCLK pin is 3-stated with a weak pull-up.∙In Slave configuration modes, CCLK is an input.The JTAG/Boundary-Scan configuration interface is always available, regardless of theMode pin settings. The JTAG/Boundary-Scan configuration mode disables all otherconfiguration modes to prevent conflicts between configuration interfaces.Certain pins are dedicated to configuration (Table1-1), while others are dual-purpose(Table1-2). Dual-purpose pins serve both as configuration pins and as user I/O afterconfiguration. Dedicated configuration pins retain their function after configuration.Configuration SequenceConfiguration SequenceWhile each of the configuration interfaces is different, the basic steps for configuring a Virtex-5 device are the same for all modes. Figure 1-2 shows the Virtex-5 configuration process. The following subsections describe each step in detail, where the current step is highlighted in gray at the beginning of each subsection.The Virtex-5 device is initialized and the configuration mode is determined by sampling the mode pins in three setup steps.Setup (Steps 1-3)The setup process is similar for all configuration modes (see Figure 1-3).The setup steps are critical for proper device configuration. The steps include Device Power-Up, Clear Configuration Memory, and Sample Mode Pins.Table 1-7:Sync Word Bit Swap ExampleSync Word[31:24](1)[23:16][15:8][7:0]Bitstream Format 0xAA 0x990x550x66Bit Swapped0x550x990xAA0x66Notes:1.[31:24] changes from 0xAA to 0x55 after bit swapping.Table 1-8:Sync Word Data Sequence Example for x8, x16, and x32 ModesCCLK Cycle 1234D[7:0] pins for x8 0x550x990xAA0x66D[15:0] pins for x160x55990xAA66D[31:0] pins for x320x5599AA66Figure 1-2:Virtex-5 Device Configuration ProcessUG191_c1_01_050406StepsBoundary-Scan for Virtex-5 Devices Using IEEE Standard 1149.1TAP ControllerFigure3-2 diagrams a 16-state finite state machine. The four TAP pins control how data isscanned into the various registers. The state of the TMS pin at the rising edge of TCKdetermines the sequence of state transitions. There are two main sequences, one forshifting data into the data register and the other for shifting an instruction into theinstruction register.A transition between the states only occurs on the rising edge of TCK, and each state has adifferent name. The two vertical columns with seven states each represent the InstructionPath and the Datapath. The data registers operate in the states whose names end with"DR," and the instruction register operates in the states whose names end in "IR." The statesare otherwise identical.The operation of each state is described below.Test-Logic-Reset:All test logic is disabled in this controller state, enabling the normal operation of the IC.The TAP controller state machine is designed so that regardless of the initial state of thecontroller, the Test-Logic-Reset state can be entered by holding TMS High and pulsingTCK five times. Consequently, the Test Reset (TRST) pin is optional.Run-Test-Idle:In this controller state, the test logic in the IC is active only if certain instructions arepresent. For example, if an instruction activates the self test, then it is executed when thecontroller enters this state. The test logic in the IC is idle otherwise.Select-DR-Scan:This controller state controls whether to enter the Datapath or the Select-IR-Scan state.Select-IR-Scan:This controller state controls whether or not to enter the Instruction Path. The controllercan return to the Test-Logic-Reset state otherwise.Capture-IR:In this controller state, the shift register bank in the Instruction Register parallel loads apattern of fixed values on the rising edge of TCK. The last two significant bits must alwaysbe 01.Shift-IR:In this controller state, the instruction register gets connected between TDI and TDO, andthe captured pattern gets shifted on each rising edge of TCK. The instruction available onthe TDI pin is also shifted in to the instruction register.Exit1-IR:This controller state controls whether to enter the Pause-IR state or Update-IR state.Pause-IR:This state allows the shifting of the instruction register to be temporarily halted.Exit2-DR:This controller state controls whether to enter either the Shift-IR state or Update-IR state.Update-IR:In this controller state, the instruction in the instruction register is latched to the latch bankof the Instruction Register on every falling edge of TCK. This instruction becomes thecurrent instruction after it is latched.。