LOW POWER ENERGY RECOVERY COMPLEMENTARY

Journal of Circuits,Systems,and ComputersVol.15,No.4(2006)491–504c World Scientific Publishing CompanyLOW POWER ENERGY RECOVERY COMPLEMENTARYPASS-TRANSISTOR LOGICROBERT C.CHANG∗Department of Electrical Engineering,National Chung Hsing University,Taiwanchchang@.twPO-CHUNG HUNG†Cheertek Co.,Ltd.,TaiwanJohnHung@HSIN-LEI LIN∗Department of Electrical Engineering,National Chung Hsing University,Taiwand9164302@.twRevised18November2005A proposed adiabatic logic called Energy Recovery Complementary Pass-transistor Logic(ERCPL)is presented in this paper.It operates with a two-phase nonoverlapping power-clock supply.It uses bootstrapping to achieve efficient power saving and eliminates anynonadiabatic losses on the charge-steering devices.A scheme is used to recover partof the energy trapped in the bootstrapping nodes.We compare the energy dissipationbetween ERCPL and other logic circuits by simulation.Simulation results show that apipelined ERCPL carry look-ahead adder can achieve a power reduction of80%overthe conventional CMOS case.Operation of an8-bit ERCPL CLA fabricated using theTSMC0.35µm1P4M CMOS technology has been experimentally verified.Keywords:Low power;ERCPL;CLA.1.IntroductionDue to the increasing demand for portable electronic equipment with state-of-the-art computational power and reliability,reducing power consumption has become an important issue in integrated circuit design.Adiabatic logic(or so-called energy recovery logic)is a design style to reduce power consumption.Adiabatic switch-ing can circumvent the CV2dissipated energy barrier,generated by operating ∗No.250,KuoKuang Rd.,South District,Taichung City402,Taiwan(R.O.C.).†No.2,Dusing1st Rd.,Hsinchu City300,Taiwan(R.O.C.).491492R.C.Chang,P.-C.Hung&H.-L.LinCMOS circuits conventionally.1The energy dissipated in adiabatic circuits can be divided into two kinds:adiabatic loss and nonadiabatic loss.2An adiabatic circuit cannot avoid adiabatic loss.Adiabatic logics can usually reduce only part of the nonadiabatic loss.Various adiabatic logic architectures have been proposed for low power VLSI design.2−5Most use diodes or diode-like devices for precharge,which causes unavoidable energy loss due to the voltage drop across the diodes.4ECRL,4 ADCPL,5PAL,6PAL-2N,7and CAL8were proposed to eliminate the precharge diodes,but they suffer from a close recovery path.The key component in adiabatic circuits is an energy-efficient charge-steering device.9–13For full energy recovery,the path between the power-clock supply and an output node may not be closed during charging or discharging.To assure this condition,a retractile cascade timing scheme is required.13The bootstrapping technique is an approach to form retractile cascade timing scheme without generating complex clock phases.This technique precharges the charge-steering transistor gate high and makes the transistor turn on as the power-clock supply begins to ramp high.Effective bootstrapping makes the switch transistor gate voltage rise high enough above the highest applied clock voltage to keep the channel conductance high.14NMOS Energy Recovery Logic(NERL) was proposed in the bibliography.15NERL exhibits low energy consumption due to efficient energy transfer and recovery using bootstrapping.Figure1shows an NERL inverter.Its energy dissipation can be written as in the bibliography.15E NEAR=C boot V dd V th,(1) where C boot is the capacitance of the bootstrapping node,V dd is the peak value of the power supply,and V th is the threshold voltage of the isolation transistors M5and M6.This paper describes a proposed adiabatic logic family called Energy Recovery Complementary Pass-transistor Logic(ERCPL).It uses a complemen-tary pass-transistor logic tree(CPL)as the logic-evaluating tree and bootstrapping technique.ERCPL is diode free and is a dual-rail logic family operated with a two-phase nonoverlapping supply clock.Energy is recovered in the recovery phase of the power clock.A pipeline structure can be directly implemented without any specific latch.In Sec.2,the basic ERCPL design and operation will be presented.Circuit design is given in Sec.3.Experimental results are presented in Sec.4.Section5is the conclusion.2.Energy Recovery Complementary Pass-Transistor Logic2.1.ERCPL gatesAn ERCPL gate constitutes a differential structure and uses only NMOS transistors. It operates with a two-phase nonoverlapping power-clock supply.The basic ERCPL inverter circuit is illustrated in Fig.2.An ERCPL gate can be divided into two parts, logic function and charge-discharge circuit.The logic function part(M9–M12)uses complementary pass-transistor for generating a proper logic value.Different logic can be acquired by changing this part with different logic tree.The logic trees ofLow Power Energy Recovery Complementary Pass-Transistor Logic493Fig.1.Schematic of the NERL inverter.Fig.2.Schematic of an ERCPL inverter.basic gates such as AND,XOR,and AND–OR are shown in Fig.3.The charge-discharge part(M1–M8)uses bootstrapping for full energy recovery.M1and M2act as bootstrapping NMOS transistors.M7and M8are isolation switches.Transistors M3–M6are used to discharge bootstrapping nodes for correct operation.494R.C.Chang,P.-C.Hung&H.-L.LinFig.3.Logic trees of complementary pass-transistor using in ERCPL gates.(a)AND,(b)XOR, and(c)AND–OR.Two nonoverlap power-clock supplies(φ1andφ2)are used with180◦phase difference.Figure4shows the ERCPL inverter chain.The phase arrangement and timing diagram of ERCPL inverter chain is shown in Fig.5.The waveform of the power clock can be trapezoid or triangular.Here we used a triangular waveform for convenience.φ1is used to control the isolation transistor to precharge the boot-strapping node(BN1or BN2).Whenφ1rises,we assume that IN whose phase is no different withφ1also rises,and INbar remains low.The transistors M7,M8,M9, and M11turn on.BN1is precharged to V dd–V th,and BN2is still at low voltage.Low Power Energy Recovery Complementary Pass-Transistor Logic495Fig.4.ERCPL inverter chain.Fig.5.Simulated timing waveforms of ERCPL inverter chain.496R.C.Chang,P.-C.Hung&H.-L.LinWhenφ1and IN ramps down,M7,M8,M9,and M11turn off,the bootstrapping nodes are isolated from the input and BN1stores a high voltage information.φ2, which is used to transfer charge from power-clock supply through turned-on tran-sistor M1,then ramps from0to V dd.At the same time,BN1is bootstrapped to a voltage higher than V dd due to the gate-to-channel capacitance of transistor M1 and turns on M1.Power-clock supplyφ2charges the output node OUT in an adia-batic manner to V dd,and drives the next stage in the phase ofφ2.Whenφ2ramps down,OUT also ramps down,and the charge stored on it is recovered to supply through the entire discharge process.The energy on the output node is fully recov-ered but not on the bootstrapping node.The NERL connects the bootstrapping node to the ground and releases the energy as heat.Instead,our ERCPL wastes part of this energy and distributes the other part for storage in the capacitance of the input nodes and inner nodes.ERCPL dissipates less energy as heat.The bootstrapping node discharge process that saves the trapped charge is described as follows.2.2.Charge recycle in ERCPLConsider the ERCPL cascaded inverter chain given in Fig.4.Figure4also shows the phase arrangement of the cascaded ERCPL inverter chain.The bootstrapping node discharge process consists of two successive stages.This process is illustrated in Fig.6.We only show half of the circuit for simplicity.The waveforms of the node voltages in Fig.6are shown in Fig.7.During period t1,we assume thatFig.6.Bootstrapping node discharge process.Low Power Energy Recovery Complementary Pass-Transistor Logic497Fig.7.Timing waveforms of node voltages during the discharge process.node A is charged high followingφ2,and BN2is charged to V dd–V th.Thenφ2 ramps down,and isolation switch M7of stageφ2turns off.Charge is trapped in node q and BN2.During period t3,φ2rises again.If A is low and A is high,M7 and M10of stage2will turn on.The transistor M3of stage1turns on.Current willflow through M7of stageφ2,M10of stageφ2,and M3of stage1due to voltage drop.This charge-sharing process will stop when the nodes reach a bal-anced voltage.The diode-connected transistor M5of stage1adjusts the voltage in the following way:if the balanced voltage is higher than V th,M5of stage1 will turn on until the balanced voltage is lower than V th.If the balanced voltage is lower than V th,its voltage level remains.Therefore,there is charge saved at most asQ saved=V th C share,(2) where C share is the total node capacitance participated in the charge-sharing pro-cess.We can see that the current Iflows through M7of stage2due to charge498R.C.Chang,P.-C.Hung&H.-L.Linsharing.This bootstrapping node discharge process is nonadiabatic.However,a part of energy is saved from the energy dissipation in Eq.(2).3.Circuit DesignIn order to compare power dissipation of ERCPL and NERL,a carry look-ahead adder of NERL is designed.The only difference of CLA between NERL and ERCPL is the clocking arrangement.Because ERCPL computes only one logic evaluation per phase,a complex logic with a long chain of stages will cause a long latency and inefficient performance.For example,a32-bit ripple carry adder needs32-phases to execute one addition,and the latency is16cycles.There are some pipelined CLA structures adopted in different adiabatic logic style designs that can reduce the latency proposed by those two references.4,5In this paper,we constructed an8-bit CLA using ERCPL,for examining and evaluating the performance and power dissipation.This design is similar to the one in the bibliography,4except that our ERCPL CLA uses a2-phase power-clock supply rather than4-phase.The schematic of the ERCPL CLA is shown in Fig.8.Four kinds of ERCPL gates—AND,XOR,AND–OR,and buffer—are needed in this adder design.The basic cell,depicted as a rectangle,consists of one AND gate and one AND–OR gate. Because the charge-discharge part of the ERCPL gate acts like a clock-powered latch,the circuit constructed with it has an inherent functionality of pipeline. For this reason,buffers are needed for signal synchronization.This8-bit CLA calculates thefirst result of addition throughfive stages,and the latency is2.5 cycles.4.Experimental Result4.1.Simulation resultsIn order to compare the power dissipation with conventional CMOS,4NERL and our proposed logic,we simulated those circuits with HSPICE.We used device models available for the TSMC0.35µm1P4M CMOS technology for simulation. The peak voltage of the power-clock supply is3.3V.Except that the bootstrap-ping NMOS transistor sizes are chosen large enough for correct bootstrapping function,the other transistors are chosen with the smallest size.The W/L ratio of transistors M5and M6in Fig.2can be larger for higher operation fre-quency.Ideal power-clock generator is used in our simulation.Figure9shows the power consumption versus frequency of the10-stage inverter chain offive different kinds of logic.The output load is0.1pF.In thefigure,we can see that the NERL dissipated67%of energy dissipated in conventional CMOS at 125MHz.The ERCPL takes a further step in reducing the power dissipation to52%.Table1lists the percentage of power dissipation of adiabatic inverter chains to conventional paring with the performances of the logic schemes,the transistor number of our proposed ERCPL technique is more thanLow Power Energy Recovery Complementary Pass-Transistor Logic499Fig.8.Schematic of an8-bit carry look-ahead adder.that of CMOS,but its power dissipation is half than that of CMOS.Although our proposed ERCPL technique is only more than the NERL by two transis-tors,our scheme is efficient to save about one-fourth of power dissipation.The area penalty decreases with the increase of the logic tree and the progress of the process.500R.C.Chang,P.-C.Hung&H.-L.LinFig.9.Power consumption versus frequency for the inverter chains.Table1.Percentage of power dissipation from adiabatic inverterchains to conventional CMOS.10-stage inverter chain@125MHz CMOS NERL ERCPLPower dissipation(µW)185.6124.796.0Percentage to CMOS100%67.2%51.7%Transistor counts31012Fig.10.Power consumption versus frequency for the8-bit CLAs.Low Power Energy Recovery Complementary Pass-Transistor Logic501Fig.11.Photomicrograph of an8-bit ERCPL carry look-ahead adder.Fig.12.Generated2-phase nonoverlapping signal.Above:φ1.Below:φ2.502R.C.Chang,P.-C.Hung&H.-L.LinFig.13.Output waveforms.Above:φ1.Below:C out=logic“1”.A comparison of the power dissipation versus operation frequency of the8-bit CLA is shown in Fig.10.The result shows that ERCPL can be more energy efficient than the NERL and conventional CMOS.At125MHz,conventional CMOS CLA,NERL CLA,and ERCPL CLA consume0.868mW,0.256mW,and0.177mW, respectively.Thus,NERL CLA can save71%and80%energy of CMOS CLA and ERCPL CLA,respectively.4.2.Measurement resultsAn8-bit ERCPL carry look-ahead adder was designed and fabricated using the TSMC0.35µm1P4M CMOS technology.A photomicrograph of the8-bit ERCPL CLA is shown in Fig.11.To test this chip,we must generate two nonoverlap-ping power-clock signals to serve as the supply for the adiabatic circuit.Figure12 shows the two-phase nonoverlapping power-clock signals that are obtained from the function generator and a simple rectifying circuit.If the inputs of the adders are A8...A1=11111111and B8...B1=00000001,then the results are C out=1and S8...S1=00000000.Figures13and14show logic“1”of Cout and logic“0”of S8, respectively.Because we placed the ERCPL buffers at the outputs of this adder, there are six pipeline stages in this chip,and the output signals are in the same phase with1.Therefore,the measurement results verified that the add operation of ERCPL CLA is correct.Low Power Energy Recovery Complementary Pass-Transistor Logic503Fig.14.Output waveforms.Above:φ1.Below:S8=logic“0”.5.ConclusionIn this paper,we proposed ERCPL for energy recovery logics.ERCPL facilitates efficient energy recovery and low power consumption using the bootstrapping tech-nique to obtain efficient energy utilization and reduce the nonadiabatic energy loss dissipated in NERL.In the inverter-chain case,simulation results show that logic families we proposed have higher energy efficiency than NERL.NERL dissipates 67.2%of the conventional CMOS power,and ERCPL dissipates only51.7%.In the CLA case,NERL saves71%of the conventional CMOS power,and ERCPL saves up to80%.We also designed an8-bit carry look-ahead adder with ERCPL using TSMC0.35µm1P4M CMOS technology.The operation of this CLA was experimentally verified.AcknowledgmentsThis work was supported by National Science Council(NSC)of Taiwan,R.O.C. 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