MM54HC191中文资料

TL F 5322MM54HC190 MM74HC190 MM54HC191 MM74HC191January1988 MM54HC190 MM74HC190SynchronousDecade Up Down Counters with ModeControl MM54HC191 MM74HC191Synchronous Binary Up Down Counterswith Mode ControlGeneral DescriptionThese high speed synchronous counters utilize advancedsilicon-gate CMOS technology They possess the high noiseimmunity and low power consumption of CMOS technologyalong with the speeds of low power Schottky TTLThese circuits are synchronous reversible up down count-ers The MM54HC191 MM74HC191are4-bit binary count-ers and the MM54HC190 MM74HC190are BCD countersSynchronous operation is provided by having all flip-flopsclocked simultaneously so that the outputs change simulta-neously when so instructed by the steering logic This modeof operation eliminates the output counting spikes normallyassociated with asynchronous(ripple clock)countersThe outputs of the four master-slave flip-flops are triggeredon a low-to-high level transition of the clock input if theenable input is low A high at the enable input inhibits count-ing The direction of the count is determined by the level ofthe down up input When low the counter counts up andwhen high it counts downThese counters are fully programmable that is the outputsmay be preset to either level by placing a low on the loadinput and entering the desired data at the data inputs Theoutput will change independent of the level of the clock in-put This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with thepreset inputsTwo outputs have been made available to perform the cas-cading function ripple clock and maximum minimum countThe latter output produces a high-level output pulse with aduration approximately equal to one complete cycle of theclock when the counter overflows or underflows The rippleclock output produces a low-level output pulse equal inwidth to the low-level portion of the clock input when anoverflow or underflow condition exists The counters can beeasily cascaded by feeding the ripple clock output to theenable input of the succeeding counter if parallel clocking isused or to the clock input if parallel enabling is used Themaximum minimum count output can be used to accom-plish look-ahead for high-speed operationFeaturesY Level changes on Enable or Down Up can be made re-gardless of the level of the clock inputY Wide power supply range 2–6VY Low quiescent supply current 80m A maximum(74HC Series)Y Low input current 1m A maximumConnection DiagramDual-In-Line PackageTL F 5322–1Top ViewLoadEnable DownClock FunctionG UpH L L u Count UpH L H u Count DownL X X X LoadH H X X No ChangeAsynchronous inputs Low input to load sets Q A e AQ B e B Q C e C and Q D e DOrder Number MM54HC190 191or MM74HC190 191C1995National Semiconductor Corporation RRD-B30M105 Printed in U S AAbsolute Maximum Ratings(Notes1 2) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage(V CC)b0 5to a7 0V DC Input Voltage(V IN)b1 5to V CC a1 5V DC Output Voltage(V OUT)b0 5to V CC a0 5V Clamp Diode Current(I IK I OK)g20mA DC Output Current per pin(I OUT)g25mA DC V CC or GND Current per pin(I CC)g50mA Storage Temperature Range(T STG)b65 C to a150 C Power Dissipation(P D)(Note3)600mW S O Package only500mW Lead Temp (T L)(Soldering10seconds)260 C Operating ConditionsMin Max Units Supply Voltage(V CC)26V DC Input or Output Voltage0V CC V (V IN V OUT)Operating Temp Range(T A)MM74HC b40a85 C MM54HC b55a125 C Input Rise or Fall TimesV CC e2 0V(t r t f)1000ns V CC e4 5V500nsV CC e6 0V400nsDC Electrical Characteristics(Note4)T A e25 C 74HC54HCSymbol Parameter Conditions V CC T A eb40to85 C T A eb55to125 C UnitsTyp Guaranteed LimitsV IH Minimum High Level V V Input Voltage V VV VV IL Maximum Low Level V V Input Voltage V VV VV OH Minimum High Level V IN e V IH or V ILOutput Voltage l I OUT l s m A V VV VV VV IN e V IH or V ILl I OUT l s mA V Vl I OUT l s mA V V V OL Maximum Low Level V IN e V IH or V ILOutput Voltage l I OUT l s m A V VV VV VV IN e V IH or V ILl I OUT l s mA V Vl I OUT l s mA V V I IN Maximum Input V IN e V CC or GND V g g g m ACurrentI CC Maximum Quiescent V IN e V CC or GND V m ASupply Current I OUT e m ANote1 Absolute Maximum Ratings are those values beyond which damage to the device may occurNote2 Unless otherwise specified all voltages are referenced to groundNote3 Power Dissipation temperature derating plastic‘‘N’’package b12mW C from65 C to85 C ceramic‘‘J’’package b12mW C from100 C to125 C Note4 For a power supply of5V g10%the worst case output voltages(V OH and V OL)occur for HC at4 5V Thus the4 5V values should be used when designing with this supply Worst case V IH and V IL occur at V CC e5 5V and4 5V respectively (The V IH value at5 5V is3 85V )The worst case leakage current(I IN I CC and I OZ)occur for CMOS at the higher voltage and so the6 0V values should be usedV IL limits are currently tested at20%of V CC The above V IL specification(30%of V CC)will be implemented no later than Q1 CY’892AC Electrical Characteristics T A e25 C V CC e5 0V t r e t f e6ns C L e15pF(unless otherwise specified)Symbol ParameterFrom ToTyp Units (Input)(Output)f MAX Maximum Clock MHzFrequencyt PLH t PHL Maximum Propagation Delay Time Load Q A Q B nsQ C Q Dt PLH t PHL Maximum Propagation Delay Time Data A Q A Q B nsB C D Q C Q Dt PLH t PHL Maximum Propagation Delay Time Clock Ripple nsClockt PLH t PHL Maximum Propagation Delay Time Clock Q A Q B nsQ C Q Dt PLH t PHL Maximum Propagation Delay Time Clock Max Min nst PLH t PHL Maximum Propagation Delay Time Down Up Ripple nsClockt PLH t PHL Maximum Propagation Delay Time Down Up Max Min ns t PHL t PLH Maximum Propagation Delay Time Enable Ripple Clock nst W Minimum Clock Clear or Load ns Input Pulse WidthAC Electrical Characteristics V CC e2 0V to6 0V C L e50pF t r e t f e6ns(unless otherwise specified)From To T A e25 C 74HC54HCSymbol Parameter(Input)(Output)V CC T A e b40to85 C T A eb55to125 C UnitsTyp Guaranteed Limitsf MAX Maximum Clock V MHzFrequency V MHzV MHz t PLH t PHL Maximum Propagation Load Q A Q B V ns Delay Time Q C Q D V nsV ns t PLH t PHL Maximum Propagation Data A Q A Q B V ns Delay Time B C D Q C Q D V nsV ns t PLH t PHL Maximum Propagation Clock Ripple V ns Delay Time Clock V nsV ns t PLH t PHL Maximum Propagation Clock Q A Q B V ns Delay Time Q C Q D V nsV ns3AC Electrical Characteristics(Continued)Symbol ParameterFrom ToConditions V CCT A e25 C74HC54HCUnits (Input)(Output)T A eb40to85 C T A eb55to125 CTyp Guaranteed Limitst PLH t PHL Maximum Propagation Clock Max Min V ns Delay Time V nsV nst PLH t PHL Maximum Propagation Down Up Ripple V ns Delay Time Clock V nsV nst PLH t PHL Maximum Propagation Down Up Max Min V ns Delay Time V nsV nst PHL t PLH Maximum Propagation Enable Ripple V ns Delay Time Clock V nsV nst W Minimum Clock Load or V ns Clear Input Pulse Width V nsV nst S Minimum Setup Time Data Load V nsV nsV nst H Data Hold Time Load Data V b nsV b nsV b nst S Minimum Setup Time Down Up Clock V nsV nsV nst H Minimum Hold Time Clock Down Up V b nsV b nsV b nst S Minimum Setup Time Enable Clock V nsV nsV nst H Minimum Hold Time Clock Enable V b nsV b nsV b nst rem Minimum Removal Time Load Clock V nsV nsV nst THL t TLH Maximum Output V s Rise and Fall Time V nsV nst W Minimum Load V ns Pulse Width V nsV nsC IN Input Capacitance pFC PD Power Dissipation pFCapacitance NoteNote5 C PD determines the no load dynamic power consumption P D e C PD V CC2f a I CC V CC and the no load dynamic current consumption I S e C PD V CC f aI CC4Logic Diagrams’HC190Decade CountersTL F 5322–2 Pin(16)e V CC Pin(8)e GND5Logic Diagrams(Continued)’HC191Binary CountersTL F 5322–3Pin(16)e V CC Pin(8)e GND6Timing Diagrams’HC190Synchronous Decade CountersTypical Load Count and Inhibit SequencesTL F 5322–4Sequence(1)Load(preset)to BCD seven(2)Count up to eight nine zero one and two(3)Inhibit(4)Count down to one zero nine eight and seven’HC191Synchronous Binary CountersTypical Load Count and Inhibit SequenceTL F 5322–5Sequence(1)Load(preset)to binary thirteen(2)Count up to fourteen fifteen zero one and two(3)Inhibit(4)Count down to one zero fifteen fourteen and thirteen7M M 54H C 190 M M 74H C 190 M M 54H C 191 M M 74H C 191Physical Dimensions inches (millimeters)Order Number MM54HC190J MM54HC191J MM74HC190J or MM74HC191JNS Package J16AOrder Number MM74HC190N or MM74HC191NNS Package N16ELIFE SUPPORT POLICYNATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which (a)are intended for surgical implant support device or system whose failure to perform can into the body or (b)support or sustain life and whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system or to affect its safety or with instructions for use provided in the labeling can effectivenessbe reasonably expected to result in a significant injury to the userNational Semiconductor National Semiconductor National Semiconductor National Semiconductor CorporationEuropeHong Kong LtdJapan Ltd1111West Bardin RoadFax (a 49)0-180-530858613th Floor Straight Block Tel 81-043-299-2309。