MC2856中文资料
MC33064中文资料
(ICC) Supply Current - ( A)
ACTIVE REGION
MONITOR REGION
-8
-6
-4
-2
0
2
4
6
8
10
Input Voltage less Threshold Voltage - (mV)
PA C K A G E O R D E R I N F O R M A T I O N TA (°C) 0 to 70 -40 to 85 -55 to 125
NOTE: For current data & package dimensions, visit our web site: .
PRODUCT HIGHLIGHT
S U P P LY C U R R E N T
400 385 370 355 340 325 310 295 280 265 250 -10
N.C. N.C. N.C. N.C.
DM PACKAGE (Top View)
3. GROUND 2. VIN 1. RESET
THERMAL DATA
DM PACKAGE: THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA LP PACKAGE: THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA 156°C/W 165°C/W LP PACKAGE (Top View)
MC1496技术参数中文版(2021年整理精品文档)
MC1496技术参数中文版编辑整理：尊敬的读者朋友们：这里是精品文档编辑中心，本文档内容是由我和我的同事精心编辑整理后发布的，发布之前我们对文中内容进行仔细校对，但是难免会有疏漏的地方，但是任然希望（MC1496技术参数中文版）的内容能够给您的工作和学习带来便利。
同时也真诚的希望收到您的建议和反馈，这将是我们进步的源泉，前进的动力。
本文可编辑可修改，如果觉得对您有帮助请收藏以便随时查阅，最后祝您生活愉快业绩进步，以下为MC1496技术参数中文版的全部内容。
MC1496/MC1496B平衡式调制解调器这类器件用于输出电压是输入电压（信号）和转换电压（载波)乘积场合。
典型应用包括抑制载波调幅，同步检波，FM检波，鉴相器。
更多的应用信息请参照ON半导体公司AN531的应用手册。
特性：1.极佳的载波抑制性能− 65 dB typ @ 0。
5 MHz−50 dB typ @ 10 MHz2.增益和信号处理可调3。
平衡输入和输出4.高共模抑制比典型值为—85dB5.器件内部含有8个三极管6.多种封装形式极限参数(如无特别说明，测试温度为25。
C)评价符号值单位外加电压（v6-v8，v10—v1,v12—v8,v8-v4,v8—v1,v10—v4,v6-v10,v2-v5，v3—v5）V30V不同的输出信号V8-v10V4—V1+5。
0 ±（5+I5Re）V最大偏压I510mA 热敏电阻双列直插式封装R100°C/W工作环境温度范围MC1496MC1496B T A0 to +70 −40to +125°C存储温度范围T stg−65 to +150°C超过极限参数可能会造成器件永久性的损坏。
电气特性（测试条件：(VCC = 12 Vdc， VEE = −8.0 Vdc， I5 = 1.0 mAdc， RL = 3.9 k ，Re = 1。
0 k , TA = Tlow to Thigh），如无特别说明，所有的输入输出均为单极性。
ET80960JA3V252中文资料
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit MicroprocessorDatasheetProduct Featuress Code Compatible with all 80960Jx ProcessorssHigh-Performance Embedded Architecture —One Instruction/Clock Execution —Core Clock Rate is:1x the Bus Clock for 80960JA/JF/JS 2x the Bus Clock for 80960JD/JC 3x the Bus Clock for 80960JT —Load/Store Programming Model —Sixteen 32-Bit Global Registers—Sixteen 32-Bit Local Registers (8 sets)—Nine Addressing Modes—User/Supervisor Protection Model sTwo-Way Set Associative Instruction Cache—80960JA - 2Kbyte —80960JF/JD - 4Kbyte —80960JS/JC/JT - 16Kbyte —Programmable Cache-Locking MechanismsDirect Mapped Data Cache —80960JA - 1Kbyte —80960JF/JD - 2Kbyte —80960JS/JC/JT - 4Kbyte —Write Through Operation sOn-Chip Stack Frame Cache—Seven Register Sets May Be Saved —Automatic Allocation on Call/Return —0-7 Frames Reserved for High-Priority InterruptssOn-Chip Data RAM—1Kbyte Critical Variable Storage —Single-Cycle Access s3.3V Supply Voltage —5V Tolerant Inputs—TTL Compatible Outputs sHigh Bandwidth Burst Bus—32-Bit Multiplexed Address/Data—Programmable Memory Configuration —Selectable 8-, 16-, 32-Bit Bus Widths —Supports Unaligned Accesses—Big or Little Endian Byte Ordering sHigh-Speed Interrupt Controller —31 Programmable Priorities —Eight Maskable Pins plus NMI#—Up to 240 Vectors in Expanded Mode sTwo On-Chip Timers—Independent 32-Bit Counting —Clock Prescaling by 1, 2, 4 or 8—Internal Interrupt Sources s Halt Mode for Low Powers IEEE 1149.1 (JTAG) Boundary Scan Compatibility sPackages—132-Lead Pin Grid Array (PGA)—132-Lead Plastic Quad Flat Pack (PQFP)—196-Ball Mini Plastic Ball Grid Array (MPBGA)Order Number: 273159-006August 2004INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.Intel may make changes to specifications and product descriptions at any time, without notice.Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.The 80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling1-800-548-4725 or by visiting Intel’s website at .AlertVIEW, AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, CT Connect, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile, i386, i486, i960, iCOMP, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel Create & Share, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetMerge, Intel NetStructure, Intel Play, Intel Play logo, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel Xeon, Intel XScale, IPLink, Itanium, LANDesk, LanRover, MCS, MMX, MMX logo, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, PDCharm, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, RemoteExpress, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside., The Journey Inside, TokenExpress, Trillium, VoiceBrick, Vtune, and Xircom are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.*Other names and brands may be claimed as the property of others.Copyright © Intel Corporation, 2002, 2004Contents Contents1.0Introduction (7)2.080960Jx Overview (9)2.180960 Processor Core (10)2.2Burst Bus (11)2.3Timer Unit (11)2.4Priority Interrupt Controller (11)2.5Instruction Set Summary (12)2.6Faults and Debugging (12)2.7Low Power Operation (12)2.8Test Features (12)2.9Memory-Mapped Control Registers (13)2.10Data Types and Memory Addressing Modes (13)3.0Packaging Information (15)3.1Available Processors and Packages (15)3.2Pin Descriptions (16)3.2.1Functional Pin Definitions (16)3.2.280960Jx 132-Lead PGA Pinout (23)3.2.380960Jx 132-Lead PQFP Pinout (27)3.2.480960Jx 196-Ball MPBGA Pinout (30)4.0Electrical Specifications (35)4.1Absolute Maximum Ratings (35)4.2Operating Conditions (35)4.3Connection Recommendations (36)4.4VCC5 Pin Requirements (VDIFF) (36)4.5VCCPLL Pin Requirements (37)4.6 D.C. Specifications (38)4.7 A.C. Specifications (42)4.7.1 A.C. Test Conditions and Derating Curves (45)4.7.1.1Output Delay or Hold vs. Load Capacitance (46)4.7.1.2T LX vs. AD Bus Load Capacitance (47)4.7.1.3ICC Active vs. Frequency (49)4.7.2 A.C. Timing Waveforms (53)5.0Device Identification (59)5.180960JS/JC/JT Device Identification Register (60)5.280960JD Device Identification Register (61)5.380960JA/JF Device Identification Register (62)6.0Thermal Specifications (63)6.1Thermal Management Accessories (68)6.1.1Heatsinks (68)7.0Bus Functional Waveforms (69)7.1Basic Bus States (79)7.2Boundary-Scan Register (80)ContentsFigures180960Jx Microprocessor Package Options (7)280960Jx Block Diagram (10)3132-Lead Pin Grid Array Top View-Pins Facing Down (23)4132-Lead Pin Grid Array Bottom View-Pins Facing Up (24)5132-Lead PQFP - Top View (27)6196-Ball Mini Plastic Ball Grid Array Top View-Balls Facing Down (30)7196-Ball Mini Plastic Ball Grid Array Bottom View-Balls Facing Up (31)8VCC5 Current-Limiting Resistor (36)9VCCPLL Lowpass Filter (37)10 A.C. Test Load (45)11Output Delay or Hold vs. Load Capacitance–80960JS/JC/JT (3.3 V Signals) (46)12Output Delay or Hold vs. Load Capacitance–80960JS/JC/JT (5V Signals) (46)13Output Delay or Hold vs. Load Capacitance–80960JA/JF/JD (47)14T LX vs. AD Bus Load Capacitance–80960JS/JC/JT (3.3V Signals) (47)15T LX vs. AD Bus Load Capacitance–80960JS/JC/JT (5V Signals) (48)16T LX vs. AD Bus Load Capacitance–80960JA/JF/JD (48)17I CC Active (Power Supply) vs. Frequency–80960JA/JF (49)1880960JA/JF I CC Active (Thermal) vs. Frequency (49)1980960JD I CC Active (Power Supply) vs. Frequency (50)2080960JD I CC Active (Thermal) vs. Frequency (50)2180960JC I CC Active (Power Supply) vs. Frequency (51)2280960JC I CC Active (Thermal) vs. Frequency (51)2380960JS I CC Active (Power Supply) vs. Frequency (52)2480960JS I CC Active (Thermal) vs. Frequency (52)25CLKIN Waveform (53)26T OV1 Output Delay Waveform (53)27T OF Output Float Waveform (54)28T IS1 and T IH1 Input Setup and Hold Waveform (54)29T IS2 and T IH2 Input Setup and Hold Waveform (54)30T IS3 and T IH3 Input Setup and Hold Waveform (55)31T IS4 and T IH4 Input Setup and Hold Waveform (55)32T LX, T LXL and T LXA Relative Timings Waveform (56)33DT/R# and DEN# Timings Waveform (56)34TCK Waveform (57)35T BSIS1 and T BSIH1 Input Setup and Hold Waveforms (57)36T BSOV1 and T BSOF1 Output Delay and Output Float Waveform (57)37T BSOV2 and T BSOF2 Output Delay and Output Float Waveform (58)38T BSIS2 and T BSIH2 Input Setup and Hold Waveform (58)3980960JS/JC/JT Device Identification Register Fields (60)4080960JD Device Identification Register Fields (61)4180960JA/JF Device Identification Register Fields (62)42Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus (69)43Burst Read and Write Transactions Without Wait States, 32-Bit Bus (70)44Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus (71)45Burst Read and Write Transactions Without Wait States, 8-Bit Bus (72)46Burst Read and Write Transactions With 1, 0 Wait Statesand Extra Tr State on Read, 16-Bit Bus (73)47Double Word Read Bus Request, Misaligned One Byte FromQuad Word Boundary, 32-Bit Bus, Little Endian (74)Contents 48HOLD/HOLDA Waveform For Bus Arbitration (75)49Cold Reset Waveform (76)50Warm Reset Waveform (77)51Entering the ONCE State (78)52Bus States with Arbitration (80)53Summary of Aligned and Unaligned Accesses (32-Bit Bus) (84)54Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued) (85)Tables180960Jx 3.3-V Microprocessor Family (7)280960Jx Instruction Set (14)380960Jx Processors Available in 132-Pin PGA Package (15)480960Jx Processors Available in 132-Pin PQFP Package (15)580960Jx Processors Available in Extended Temperature (16)680960Jx Processors Available in 196-Ball MPBGA Package (16)7Pin Description Nomenclature (17)8Pin Description—External Bus Signals (18)9Pin Description—Processor Control Signals, Test Signals, and Power (21)10Pin Description—Interrupt Unit Signals (22)11132-Lead PGA Pinout—In Signal Order (25)12132-Lead PGA Pinout—In Pin Order (26)13132-Lead PQFP Pinout—In Signal Order (28)14132-Lead PQFP Pinout—In Pin Order (29)15196-Ball MPBGA Pinout—In Signal Order (32)16196-Ball MPBGA Pinout—In Pin Order (33)17Absolute Maximum Ratings (35)1880960Jx Operating Conditions (35)19VDIFF Parameters (37)2080960Jx D.C. Characteristics (38)2180960Jx I CC Characteristics (39)2280960Jx A.C. Characteristics (42)23Note Definitions for Table 22, 80960Jx AC Characteristics (45)2480960Jx Device Type and Stepping Reference (59)2580960JS/JC/JT Device ID Register Field Definitions (60)2680960JS/JC/JT Device ID Model Types (60)2780960JD Device ID Field Definitions (61)2880960JD Device ID Model Types (61)2980960JA/JF Device ID Field Definitions (62)3080960JA/JF Device ID Model Types (62)31Thermal Resistance for q CA and q JC Reference Table (63)32Maximum Ambient Temperature Reference Table (63)33132-Lead PGA Package Thermal Characteristics (64)3480960JA/JF/JD 196-Ball MPBGA Package Thermal Characteristics (64)3580960JS/JC/JT 196-Ball MPBGA Package Thermal Characteristics (65)36132-Lead PQFP Package Thermal Characteristics (65)37Maximum T A at Various Airflows in °C (80960JT) (66)38Maximum T A at Various Airflows in °C (80960JC) (66)39Maximum T A at Various Airflows in °C (80960JD) (67)40Maximum T A at Various Airflows in °C (80960JS) (67)41Maximum T A at Various Airflows in °C (80960JA/JF) (68)Contents42Boundary-Scan Register—Bit Order (81)43Natural Boundaries for Load and Store Accesses (81)44Summary of Byte Load and Store Accesses (82)45Summary of Short Word Load and Store Accesses (82)46Summary of n-Word Load and Store Accesses (n = 1, 2, 3, 4) (83)Revision HistoryDate Revision DescriptionSeptember 2002005Removed reference to A80960JF-16 from Table 3 on page15. Removed reference to NG80960JC-40, NG80960JC-33, NG80960JS-16,and NG80960JF-16 from Table 4 on page15.Removed reference to GD80960JC-40, GD80960JC-33, and 80960JS-16 in Table 6 on page16.Removed reference to 80960JC-40, 80960JC-33, 80960JS-16, and 80960JF-16 in Table 18 on page35.Removed reference to 80960JC-40, 80960JC-33, 80960JS-16, and 80960JF-16 from Table 21 on page39.Removed reference to 80960JC-40, 80960JC-33, 80960JS-16 and 80960JF-16 from Table 22 on page42.September 1999004Added new extended temp device offerings. See Table 5 on page16. Removed PGA package availability from JS/JC/JT processors. Changed AC timing parameter T OV1 (min) for extended temp devices only.See Table 22 on page42.June 1999003Merged the 80960JS/JC datasheet information into this datasheet (previously named 80960JA/JF/JD/JT 3.3V Embedded 32-Bit Microprocessor datasheet).Updated I CC values for the 80960JS/JC/JT processors. Increased TIH1 specification for the 80960JS/JC/JT processors. Updated MPBGA thermal specifications.December 1998002Corrected orientation of MPBGA package diagrams (Figure 6 on page30 and Figure 7 on page31).Added Figure 11 on page46,Figure 12 on page46,Figure 14 on page47, and Figure 15 on page48 to distinguish 80960JT 3.3-V and 5-V signal derating curves from the 80960JA/JF/JD derating curves.March 1998001This datasheet supersedes revisions to the following 80960Jx datasheets: #273109 (JT), #272971-002 (JD), and #276146-001 (JA/JF). In addition to combining the documents into one, the following content was changed: Figure 1 on page7: Added MPBGA package to diagram.Section 3.2.4, “80960Jx 196-Ball MPBGA Pinout” on page30: Added new Figures 6 and 7, Tables 10, 11 and 13.Figure 16 on page48: Added with the note that follows the figure.August 2004006To address the fact that many of the package prefix variables have changed, all package prefix variables in this document are now indicated with an "x".80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor1.0IntroductionThis document contains information for the 80960Jx microprocessors, including electrical characteristics and package pinout information. Detailed functional descriptions, other than parametric performance, are published in the i960® Jx Microprocessor Developer’s Manual(272483) and may be viewed online at /design/i960/Techinfo/80960JX/.Throughout this datasheet, references to ‘80960Jx’ indicate features that apply to the 3.3-V Jx processors only:Figure 1. 80960Jx Microprocessor Package Optionsi960®iM©19xxx80960JXXXXXXXXX SS132-Pin PQFPTable 1. 80960Jx 3.3-V Microprocessor FamilyProcessor Voltage Instruction Cache Data Cache Core Clock80960JA 3.3 V (5 V Tolerant) 2 Kbyte 1 Kbyte 1x 80960JF 3.3 V (5 V Tolerant) 4 Kbyte 2 Kbyte 1x 80960JD 3.3 V (5 V Tolerant) 4 Kbyte 2 Kbyte 2x 80960JS 3.3 V (5 V Tolerant)16 Kbyte 4 Kbyte 1x 80960JC 3.3 V (5 V Tolerant)16 Kbyte 4 Kbyte 2x 80960JT3.3 V (5 V Tolerant)16 Kbyte4 Kbyte3xNOTE: To address the fact that many of the package prefix variables have changed, all package prefix variables in this document are now indicated with an "x".This page intentionally left blank.80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor 2.080960Jx OverviewThe 80960Jx processor offers high performance to cost-sensitive 32-bit embedded applications.The 80960Jx is object code compatible with the 80960 core architecture and is capable of sustainedexecution at the rate of one instruction per clock. This processor’s features include generousinstruction cache, data cache, and data RAM. It also boasts a fast interrupt mechanism anddual-programmable timer units.The 80960Jx processor’s clock multiplication operates the processor core at two or three times thebus clock rate to improve execution performance without increasing the complexity of boarddesigns.Memory subsystems for cost-sensitive embedded applications often impose substantial wait statepenalties. The 80960Jx integrates considerable storage resources on-chip to decouple CPUexecution from the external bus.The 80960Jx rapidly allocates and de-allocates local register sets during context switches. Theprocessor must flush a register set to the stack only when it saves more than seven sets to its localregister cache.A 32-bit multiplexed burst bus provides a high-speed interface to system memory and I/O. A fullcomplement of control signals simplifies the connection of the 80960Jx to external components.The user programs physical and logical memory attributes through memory-mapped controlregisters (MMRs), an extension not found on the i960® Kx, Sx or Cx processors. Physical andlogical configuration registers enable the processor to operate with all combinations of bus widthand data object alignment. The processor supports a homogeneous byte ordering model.This processor integrates two important peripherals: a timer unit and an interrupt controller. Theseand other hardware resources are programmed through memory-mapped control registers, anextension to the familiar i960 processor architecture.The timer unit (TU) offers two independent 32-bit timers for use as real-time system clocks andgeneral-purpose system timing. These operate in either single-shot or auto-reload mode and maygenerate interrupts.The interrupt controller unit (ICU) provides a flexible, low-latency means for requesting interrupts.The ICU provides full programmability of up to 240 interrupt sources into 31 priority levels. TheICU takes advantage of a cached priority table and optional routine caching to minimize interruptlatency. Clock doubling on the 80960JD/JC processors reduces interrupt latency by 40% comparedto the 80960JA/JF, and clock tripling on the 80960JT reduces interrupt latency by 20% comparedto the 80960JD/JC. Local registers may be dedicated to high-priority interrupts to further reducelatency. Acting independently from the core, the ICU compares the priorities of posted interruptswith the current process priority, off-loading this task from the core. The ICU also supports theintegrated timer interrupts.The 80960Jx features a Halt mode designed to support applications where low power consumptionis critical. The halt instruction shuts down instruction execution, resulting in a power savings of upto 90 percent.The 80960Jx’s testability features, including ONCE (On-Circuit Emulation) mode and BoundaryScan (JTAG), provide a powerful environment for design debug and fault diagnosis.80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit MicroprocessorThe Solutions960® program features a wide variety of development tools which support the i960 processor family. Many of these tools are developed by partner companies; some are developed by Intel, such as profile-driven optimizing compilers. For more information on these products, contact your local Intel representative.2.180960 Processor CoreThe 80960Jx family is a scalar implementation of the 80960 core architecture. Intel designed this processor core as a very high performance device that is also cost-effective. Factors that contribute to the core ’s performance include:•Core operates at the bus speed with the 80960JA/JF/JS•Core operates at two or three times the bus speed with the 80960JD/JC and 80960JT,respectively•Single-clock execution of most instructions •Independent Multiply/Divide Unit•Efficient instruction pipeline minimizes pipeline break latency•Register and resource scoreboarding allow overlapped instruction execution •128-bit register bus speeds local register caching •Two-way set associative, integrated instruction cache •Direct-mapped, integrated data cache•1-Kbyte integrated data RAM delivers zero wait state program dataFigure 2. 80960Jx Block DiagramProgrammable Interrupt Controller Control Address/Instruction SequencerPhysical Region Configuration Interrupt Port1K Data RAMMemory Interface Execution Multiply UnitDivide UnitMemory-Mapped Register InterfaceData BusGlobal / Local Register FileSRC2DESTSRC1addressControleffective ConstantsGenerationUnitAddress 32-bit Address 32-bit DataBus Request Queuesand Two 32-BitTimers8-SetLocal Register CacheS R C 1S R C 2D E S TPLL, Clocks,Power MgmtBoundary Scan ControllerTAP 5CLKINS R C 1S R C 2D E S TS R C 1D E S T93232-bit buses address / data21Instruction Cache 80960JA - 2K 80960JF/JD - 4K80960JS/JC/JT - 16KDirect Mapped Data Cache 80960JA - 1K 80960JF/JD - 2K 80960JS/JC/JT -1283 Independent 32-Bit SRC1, SRC2, and DEST BusesBus Control Unit80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor2.2Burst BusA 32-bit high-performance Bus Controller Unit (BCU) interfaces the 80960Jx to external memoryand peripherals. The BCU fetches instructions and transfers data at the rate of up to four 32-bitwords per six clock cycles. The external address/data bus is multiplexed.Users may configure the 80960Jx’s bus controller to match an application’s fundamental memoryorganization. Physical bus width is register-programmed for up to eight regions. Byte ordering anddata caching are programmed through a group of logical memory templates and a defaults register.The BCU’s features include:•Multiplexed external bus to minimize pin count•32-, 16-, and 8-bit bus widths to simplify I/O interfaces•External ready control for address-to-data, data-to-data and data-to-next-address wait state types•Support for big or little endian byte ordering to facilitate the porting of existing program code•Unaligned bus accesses performed transparently•Three-deep load/store queue to decouple the bus from the coreUpon reset, the 80960Jx conducts an internal self-test. Then, before executing its first instruction, itperforms an external bus confidence test by performing a checksum on the first words of theinitialization boot record (IBR).2.3Timer UnitThe timer unit (TU) contains two independent 32-bit timers that are capable of counting at severalclock rates and generating interrupts. Each is programmed by use of the TU registers. Thesememory-mapped registers are addressable on 32-bit boundaries. The timers have a single-shotmode and auto-reload capabilities for continuous operation. Each timer has an independentinterrupt request to the 80960Jx’s interrupt controller. The TU may generate a fault whenunauthorized writes from user mode are detected. Clock prescaling is supported.2.4Priority Interrupt ControllerA programmable interrupt controller manages up to 240 external sources through an 8-bit externalinterrupt port. Alternatively, the interrupt inputs may be configured for individual edge- or level-triggered inputs. The interrupt unit (IU) also accepts interrupts from the two on-chip timer channelsand a single Non-Maskable Interrupt (NMI#) pin. Interrupts are serviced according to their prioritylevels relative to the current process priority.Low interrupt latency is critical to many embedded applications. As part of its highly flexibleinterrupt mechanism, the 80960Jx exploits several techniques to minimize latency:•Interrupt vectors and interrupt handler routines may be reserved on-chip.•Register frames for high-priority interrupt handlers may be cached on-chip.•The interrupt stack may be placed in cacheable memory space.•Interrupt microcode executes at two or three times the bus frequency for the 80960JD/JC and 80960JT, respectively.80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor2.5Instruction Set SummaryThe 80960Jx adds several new instructions to the i960 processor core architecture. The newinstructions are:•Conditional Move•Conditional Add•Conditional Subtract•Byte Swap•Halt•Cache Control•Interrupt ControlTable 2 identifies the instructions that the 80960Jx supports. Refer to the i960® Jx MicroprocessorDeveloper’s Manual (272483) for a detailed description of each instruction.2.6Faults and DebuggingThe 80960Jx employs a comprehensive fault model. The processor responds to faults by makingimplicit calls to a fault handling routine. Specific information collected for each fault allows thefault handler to diagnose exceptions and recover appropriately.The processor also has built-in debug capabilities. In software, the 80960Jx may be configured todetect as many as seven different trace event types. Alternatively, mark and fmark instructionsmay generate trace events explicitly in the instruction stream. Hardware breakpoint registers arealso available to trap on execution and data addresses.2.7Low Power OperationIntel fabricates the 80960Jx using an advanced sub-micron manufacturing process. The processor’ssub-micron topology provides the circuit density for optimal cache size and high operating speedswhile dissipating modest power. The processor also uses dynamic power management to turn offclocks to unused circuits.Users may program the 80960Jx to enter Halt mode for maximum power savings. In Halt mode,the processor core stops completely while the integrated peripherals continue to function, reducingoverall power requirements up to 90 percent. Processor execution resumes from internally orexternally generated interrupts.2.8Test FeaturesThe 80960Jx incorporates numerous features that enhance the user’s ability to test both theprocessor and the system to which it is attached. These features include ONCE (On-CircuitEmulation) mode and Boundary Scan (JTAG).80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor The 80960Jx provides testability features compatible with IEEE Standard Test Access Port andBoundary Scan Architecture (IEEE Std. 1149.1).One of the boundary scan instructions, HIGHZ, forces the processor to float all its output pins(ONCE mode). ONCE mode may also be initiated at reset without using the boundary scanmechanism.ONCE mode is useful for board-level testing. This feature allows a mounted 80960Jx toelectrically “remove” itself from a circuit board. This allows for system-level testing in which aremote tester, such as an in-circuit emulator, may exercise the processor system.The provided test logic does not interfere with component or circuit board behavior and ensuresthat components function correctly, connections between various components are correct, andvarious components interact correctly on the printed circuit board.The JTAG Boundary Scan feature is an attractive alternative to conventional “bed-of-nails” testing.It may examine connections that might otherwise be inaccessible to a test system.2.9Memory-Mapped Control RegistersThe 80960Jx, although compliant with the i960 processor core, has the added advantage ofmemory-mapped, internal control registers not found on the i960 Kx, Sx or Cx processors. Theseregisters give software the interface to easily read and modify internal control registers.Each of these registers is accessed as a memory-mapped, 32-bit register. Access is accomplishedthrough regular memory-format instructions. The processor ensures that these accesses do notgenerate external bus cycles.2.10Data Types and Memory Addressing ModesAs with all i960 processors, the 80960Jx instruction set supports several data types and formats:•Bit•Bit fields•Integer (8-, 16-, 32-, 64-bit)•Ordinal (8-, 16-, 32-, 64-bit unsigned integers)•Triple word (96 bits)•Quad word (128 bits)The 80960Jx provides a full set of addressing modes for C and assembly programming:•Two Absolute modes•Five Register Indirect modes•Index with displacement•IP with displacement。
MFW28515T资料
B4-3MFW SERIES 70 WATTSDC/DC C ONVERTERS 28 V OLT I NPUTSize (max.): 3.20 x 2.46 x 0.595 inches (81.3 x 62.5 x 15.11 mm)See Section B8, case L, for dimensions.Weight:140 grams typicalScreening: Standard or ES.See Section C2 for screeningoptions, see Section A5 for ordering information.DESCRIPTIONThe MFW Series™of DC/DC converters offers up to 70 watts of power from single, dual, or triple outputs in one package. Using hybrid thick film technology a power density of over 20 watts per cubic inch is achieved. These devices are packaged in hermetically sealed cold rolled steel enclosures with a tin plate finish making them ideal for use in military, aerospace, or other high reliability applications. Unscreened models are guaranteed to pass a gross leak test (maximum leak rate of 0.001 atm-cc/sec). Environmentally screened units (designated by the /ES suffix) are hermetically solder sealed. See Section C2 for screening specifications.D ESIGN M ETHODOLOGYThe MFW Series converters utilize a quasi-square wave forward converter design with a nominal switching frequency of 245 kHz.Isolation between input and output is provided with a transformer in the forward power loop and a wideband, temperature insensitive optical link in the feedback control loop. Output regulation is accom-plished with constant frequency pulse width modulation. In addition,the load regulation of the single output models is further enhanced through the use of remote output voltage sense pins to overcome the adverse effects of line resistance voltage drops. Short circuit protection is provided by detecting peak primary switching current on a cycle by cycle basis and limiting it to approximately 130% of the full load input current. This method results in quick and positive current limiting under short circuit conditions.L OW N OISEThe MFW Series converters offer low noise on both the input and output lines. A two section, four pole LC input filter is included to provide very low reflected line ripple current. Adherence to MIL-STD-461C (CE03) is possible with the addition of the FMB-461 filter.Output ripple is maintained at less than 50 mV p-p for single and dual output models and 85 mV for triple output models.W IDE V OLTAGE R ANGEAll models of the MFW Series are designed to provide full power operation over an input voltage range of 19 to 40 VDC. Operation below an input of 19 volts, including operation in MIL-STD-704E emergency power conditions, is possible with derated output power.Please refer to the derating information and the low voltage drop-out graphs (Figures 10 and 11) on the following pages.W IDE T EMPERATURE R ANGEFull load operation of any of the MFW Series converters is available at case temperatures of –55°C to + 85°C. Operation up to +125°C is possible with derated output power. The MFW Series converters are provided in a flange mount case designed to facilitate the removal of internally generated heat. Because of this, heat sinking requirements are minimal. Sustained full power operation does however require that an efficient heat sink be attached to the base-plate. Please refer to the heat sink requirements section for more information.I NHIBIT /S YNC F EATUREStandard on all models of the MFW Series is a dual mode inhibit/sync pin. This pin serves as both an output inhibit and as a synchronization input. In the inhibit mode an open collector TTL compatible low (<0.8 V) will disable internal switching thereby inhibiting the unit's output. Inhibiting in this manner results in an extremely low quiescent current. Since a pull-up resistor is included internally, this pin may be left open should the inhibit function not be desired.In a digital system it is often desirable to synchronize the input or output ripple with the system clock. For this reason each model of the MFW Series was designed to synchronize with a system clock applied to the inhibit/sync pin. Please refer to the technical data section for timing details for the external sync feature.F EATURES•–55°C to + 85°C operation •19 to 40 VDC input •Fully Isolated•Optocoupler feedback•Fixed frequency, 245 kHz typical •Topology – Push-Pull Forward•50 V for up to 50 ms transient protection •Inhibit/sync function•Indefinite short circuit protection •Remote sense on single models •Up to 84% efficiencyRECOMMENDED OPERATING CONDITIONSABSOLUTE MAXIMUM RATINGSTYPICAL CHARACTERISTICSB4-4MFW SERIES 70 WATTDC/DC CONVERTERSSINGLE OUTPUTS MFW2805S MFW2812S MFW2815S PARAMETER CONDITION MIN TYP MAX MINTYP MAXMIN.TYPMAXUNITS OUTPUT FULL LOAD 4.95 5.00 5.0511.8812.0012.1214.8515.0015.15VDC VOLTAGE OUTPUT V IN = 19 TO 40——12.00—— 5.83—— 4.67A CURRENT OUTPUT Tc = –55°C TO +85°C ——60——70——70W POWER OUTPUT FULL LOAD BW ≤2 MHz —3050—3050—3050mV p-p RIPPLE LINEV IN = 19 TO 40—1020—1020—1020mV REGULATION LOADNO LOAD TO FULL—1020—1025—1025mV REGULATION INPUT VOLTAGE 192840192840192840VDC INPUT NO LOAD —7590—7090—7090mA CURRENT INHIBITED —3035—3035—3035INPUT REFL.FULL LOAD —1025—1025—1025mA p-p RIPPLEBW ≤10 MHz EFFICIENCY 7880—8183—8183—%STARTUP WITH LOW—510—810—810msDELAYIMPEDANCE SOURCEOutput Power•60 to 70 watts depending on modelLead Soldering Temperature (10 sec per lead)•300°CStorage Temperature Range (Case)•–55°C to +125°COutput Voltage Temperature Coefficient •150 ppm/°C, typicalInput to Output Capacitance •160 pF, typical Isolation•100 megohm minimum at 500 V Conversion Frequency•Free run mode 245 kHz, typical Inhibit Pin Voltage (unit enabled)• 4.5 to 5.5 VElectrical Characteristics:25°C Tc,28 VDC Vin,100% load,free run,unless otherwise specified.Input Voltage Range•19 to 40 VDC continuous (see Derating)Case Operating Temperature (Tc)•–55°C to +85°C full powerSYNC AND INHIBITDERATING OUTPUT POWER/CURRENT AND INPUT VOLTAGESync In (245 to 370 kHz.)•Duty cycle 70% min, 98% max •Logic low 0.8 V max •Logic high 4.5 V min•Referenced to input common•If sync is not used, leave unconnected Inhibit TTL Open Collector •Logic low (output disabled)Inhibit pin current 1 mA max •Referenced to input common •Logic high (output enabled)V = ≥4.5 VTemperatures are referenced to the temperature at the converter’s baseplate •Linearly derate output power/current from 100% at 85°C to 0% at 125°C.•Above 105°C linearly derate steady state input voltage to 33 volts at 125°C.•Indefinite short circuit protection is not guaranteed above 85°C case.•Operation below an input voltage of 19 volts, including operation in MIL-STD-704E emergency power conditions, is possible with derated output power. See Figures 10 and 11.B4-5MFW SERIES70 WATTDC/DC CONVERTERSDUAL AND TRIPLE OUTPUTS MFW2812DMFW2815D MFW28512TMFW28515T PARAMETER CONDITION MINTYPMAXMINTYPMAXMINTYPMAXMINTYPMAXUNITS OUTPUT FULL MAIN —————— 4.95 5.05 5.10 4.90 4.95 5.05VOLTAGELOADDUAL ±11.88±12.00±12.12±14.85±15.00±15.15±11.65±11.80±12.05±15.05±15.30±15.55VDCOUTPUT V IN =MAIN ——————— 4.010.0— 4.010.0A CURRENT 1, 219 TO 40DUAL— 2.92 5.5— 2.33 4.4— 1.67 4.2— 1.33 3.33OUTPUT MAIN ———————2050—2050POWER 1, 2±DUAL —3566.5—3566.5—2050—2050W TOTAL ——70——70——60——60OUTPUT FULL LOAD MAIN ———————5085—5085mV p-p RIPPLEBW ≤2 MHzDUAL —3050—3050—5085—5085LINE V IN =MAIN ———————220—220mV REGULATION 19 TO 40DUAL —1025—1025—100200—100200LOAD 3NO LOAD MAIN ———————520—520mVREGULATION TO FULLDUAL—2550—2550—480600—300450CROSS 4DUAL REGULATION +PO = 3 W TO 35 W–PO = 35 W— 1.5 3.0— 1.5 3.0——————+PO = 20 W TO 50 W %–PO = 50 W TO 20 W—2.04.0—2.03.5——————CROSS 5MAIN +PO = 33 W REGULATION DUAL+PO = 3 W TO 27 W ——————— 2.3 6.0— 2.3 5.0–PO = 27 W TO 3 WMAIN%+PO = 3 W TO 30 W DUAL ±PO = 15 W——————— 5.49.0— 5.07.0INPUT VOLTAGE 192840192840192840192840VDC INPUT NO LOAD —7590—7590—60110—60110mA CURRENT INHIBITED —3035—3035—3035—3035INPUT REFL.FULL LOAD —1540—1540—1540—1540mA p-p RIPPLE BW ≤10 MHzEFFICIENCY 8083—8083—8084—8084—%STARTUP —1525—1525—610—610msDELAYElectrical Characteristics:25°C Tc,28 VDC Vin,100% load,free run,unless otherwise specified.Notes1.On dual output models the maximum combined output power is 70 watts.A maximum of 95% (66.5 W) is available from any single output.2.On triple output models the maximum combined output power is 60 watts.A maximum of 50 watts is available from a single output.3.Balanced loads.4.Regulation effect on the negative dual output during the defined conditions.5.Regulation effect on both dual outputs during the defined conditions.B4-6MFW SERIES 70 WATTDC/DC CONVERTERSC ALCULATING M AXIMUM A MBIENT T EMPERATUREThe MFW Series of DC/DC converters has an upper operating temperature of + 85°C at the baseplate of the case. The degree of heat sinking required to remain within this limit may be determined from Figure 1 which shows the maximum allowed internal power dissipation (P DISS vs. ambient temperature for various heat sink thermal resistances. P DISS may be calculated as: P DISS = P OUT / efficiency – P OUTThe efficiency for all combinations of P OUT and V IN for the various models may be obtained from the graphs on the preceding pages. Example:Converter = MFW2815D, T AMB = 70°C,V IN = 28 VDC, P OUT = 45 watts Efficiency = 85% (From Figure 7)P DISS = (45 / 85) – 45 = 7.95 wattsFrom Figure 1 we can see that this situation will require thermal resistance of approximately 4.5°C / watt.Conversely we may also find the maximum ambient temperature which can be tolerated if we know the heat sink thermal resistance. Example:Converter = MFW2805S, V IN = 28 VDC, P OUT = 45 W.Thermal Resistance = 3°C / watt.Efficiency = 83.5% (From Figure 3)P DISS = (45 / 0.835) – 45 = 8.89 watts.From Figure 1 we can see that the maximum allowed ambient temperature is approximately 75°C.H EAT S INK R ECOMMENDATIONSAn MFW Series converter in still air (other than convective currents)and with no conductive cooling paths other than through electrical connections at the pins will exhibit a thermal resistance of approxi-mately 4°C / watt. In cases where this value proves to be too high it is recommended that additional heat sinking be supplied. The simplest method of accomplishing this is to firmly attach the converter to a PCB thereby providing a conductive thermal path.Secondly it is recommended that airflow be provided over the converter. Although each situation requires a thorough thermal analysis these two measures can reduce the thermal resistance to as low as 2°C / watt. If calculations indicate further heat sinking is required it is recommended that additional thermal mass be provided either under the base plate or on top of the converter's mounting flanges or both.THERMAL MANAGEMENTB4-7MFW SERIES70 WATTDC/DC C ONVERTERSB4-8MFW SERIES 70 WATTDC/DC CONVERTERSTypical Performance Curves:25°C Tc ,28 VDC Vin,100% load,free run,unless otherwise specified.IGUREF IGURE 9IGURE IGURE 20621-001-DTS Rev A DQ# 1016All technical information is believed to be accurate, but no responsibility is assumed for errors or omissions. Interpoint reserves the right to make changes in products or specifications without notice. MFW Series is a trademark of Interpoint.Copyright ©1991- 1999 Interpoint. All rights reserved.C ASESCASE LB8-31CASE L C ASESB8-32C2-12QA SCREENING 85°C PRODUCTSTEST (85°C Products excluding HR products)STANDARD/ESPRE-CAP INSPECTION Method 2017yesyesTEMPERATURE CYCLE (10 times)Method 1010, Cond. B, -55°C to 125°C noyesCONSTANT ACCELERATION Method 2001, 500 g noyesBURN-IN96 hours at 70°C ambient (typical)noyesFINAL ELECTRICAL TEST MIL-PRF-38534, Group A Subgroups 1 and 4: +25°C case yesyesHERMETICITY TESTINGFine Leak, Method 1014, Cond. A no yes Gross Leak, Method 1014, Cond. C no yes Gross Leak, Dip (1 x 10-3)yesnoFINAL VISUAL INSPECTION Method 2009yesyesTest methods are referenced to MIL-STD-883 as determined by MIL-PRF-38534.MFW Series MTW SeriesMHE/MLP Series MHL Series MRH Series MTO Series MSR Series DCH SeriesFM/FMA/FMB EMI Filters MSF EMI Filter85°C P RODUCTSApplies to the following products:。
MC-7856中文资料
ELECTRICAL CHARACTERISTICS (T CASE = 30 °C, V DD = 24 V, Z S = Z I = 75 Ω)PART NUMBER MC-7856G SYMBOLSPARAMETERSUNITS MIN TYP MAX CONDITIONSBW Frequency RangeMHz 50860G A Gain dB 21.523.0 f = 860 MHz S Gain Slope dB 02.050 to 860 MHzGf Gain Flatness dB 1.050 to 860 MHz; Peak to Valley S 11Input Return LossdB 18.050 to 160 MHzdB 17.0160 to 320 MHz dB 16.0320 to 640 MHz dB 14.5640 to 860 MHz S 22Output Return LossdB 18.050 to 160 MHz dB 17.0160 to 320 MHz dB 16.0320 to 640 MHz dB 14.5640 to 860 MHz S 12Reverse IsolationdB 3050 to 860 MHz CTB Composite Triple Beat,110 Channels dB -60-55V OUT = +44 dBmV/ch CSO Composite Second Order, 110 Channels dB -63-55V OUT = +44 dBmV/ch XMod Cross Modulation, 110 Channels dB -63-55V OUT = +44 dBmV/chI DD DC Current mA 220240NFNoise FiguredB 5.3 6.250 MHz dB5.76.5860 MHzCalifornia Eastern LaboratoriesOUTLINE DIMENSIONS (Units in mm)PACKAGE OUTLINEFEATURES•GALLIUM ARSENIDE ACTIVE DEVICES •LOW DISTORTION •LOW NOISE FIGURE (5.7 dB TYP at 860 MHz)•HIGH RELIABILITY(FIT = 125 at heat sink temperature of 100°C,Report available)•INDUSTRY COMPATIBLE PACKAGEDESCRIPTIONThe MC-7856 is a GaAs hybrid integrated circuit designed to be used as the input device in CATV applications up to 860MH z . This unit has a minimum gain of 21.5 dB at 860 MHz,and because it is a GaAs device, it has lower distortion and lower noise figure. Reliability is assured by NEC's stringent quality and process control procedures. Devices are as-sembled and tested using fully automated equipment to maxi-mize the consistency in part to part performance. The MC-7856G features round connection pins and slightly different body dimensions for customers desiring these packaging di-mensions.元器件交易网MC-7856GABSOLUTE MAXIMUM RATINGS 1 (T CASE = 30 °C)SYMBOLSPARAMETERS UNITS RATINGSV DD Supply VoltageV 30V I Input Voltage (Single Tone)dBmV 65T OP Operating Temperature °C -30 to +100T STGStorage Temperature°C-40 to +100Note:1. Operation in excess of any one of these parameters may result in permanent damage.TYPICAL SCATTERING PARAMETERSV DD = 24 VFREQUENCY S 11S 21S 12S 22(MHz)MAG ANG MAGANGMAGANGMAG ANG500.062-165.5011.74-3.982 0.014 -0.058 0.02617.301000.045172.5011.89 -31.570 0.014-23.830 0.049 -31.511500.021 157.4011.94 -54.3000.013-43.140 0.078 -52.402000.00418.3611.97-75.8400.013 -62.090 0.098-65.992500.029-34.0312.06-96.8200.013-80.690 0.119-78.343000.058-41.2612.08-117.7000.012-99.3600.134-87.613500.074-50.8212.10-139.100 0.012-118.6000.137-100.704000.090-60.9812.15-159.4000.012-138.0000.137 -111.904500.085-68.9212.23179.300 0.012 -157.700 0.116-127.805000.076-74.9612.34158.2000.013-177.1000.092-147.005500.059-68.8512.45136.6000.013163.600 0.057 -174.806000.046 -37.7512.55114.6000.013145.8000.036115.306500.066 -19.0412.6092.6600.014128.900 0.04742.647000.100-13.2812.6370.410 0.014 112.7000.08610.897500.132-23.5212.7648.2500.014 96.990 0.109-18.208000.166-34.35 13.03 25.370 0.01382.490 0.130-42.31850 0.191-47.1913.43 1.254 0.013 67.470 0.138-70.149000.205 -66.62 13.78 -25.040 0.01249.570 0.136-97.729500.196-76.9113.63-51.9600.01028.7700.146-111.3010000.220-89.6213.48 -78.8800.00813.2400.184-134.8010500.230-102.3013.34 -108.2000.006-6.1160.210-154.40S 21 MAG:3.0/DIV., 15.00 FS S 12 MAG:0.01/DIV., 0.05 FSEXCLUSIVE NORTH AMERICAN AGENT FOR RF, MICROWAVE & OPTOELECTRONIC SEMICONDUCTORS• Headquarters • 4590 Patrick Henry Drive • Santa Clara, CA 95054-1817 • (408) 988-3500 • Telex 34-6393 • FAX (408) 988-027924-Hour Fax-On-Demand: 800-390-3232 (U.S. and Canada only) • Internet: 05/17/2000DATA SUBJECT TO CHANGE WITHOUT NOTICE元器件交易网。
PC 2856德国拜耳
IEC 60695-11-10
氧指数
27.0 %27.0％
ISO 4589-1/-2
光学性质
公
评论
传输，可见
89.0 %89.0％
ISO 13468-1，-2
加工性能
公
评论
熔体温度
280-320°C280-320°C
300°C300°C
注塑成型; ISO 294
模具温度
80.0°C80.0°C
ISO 1133
力学性能
公
评论
抗拉强度，屈服
66.0MPa66.0兆帕
ISO 527-1/-2
断裂伸长率
>= 50.0 %> = 50.0％
标称ISO 527-1/-2
屈服伸长率
6.10 %6.10％
ISO 527-1/-2
拉伸模量
2.40GPa2.40GPA
ISO 527-1/-2
简支梁冲击缺口
NBNB
热性能
公
评论
线性热膨胀系数，
65.0µm/m-°C65.0μm/m-°C
平行ISO 11359-1/-2
热膨胀系数，线性，横向流动
65.0µm/m-°C65.0μm/m-°C
ISO 11359-1/-2
比热容
1.70J/g-°C1.70J/g-°C
融化
热传导率
0.173W/mK0.173W / mK的
IEC 60093
表面电阻
>=1.00e+15ohm> =1.00E +15欧姆。
IEC 60093
介电常数
3.003.00
IEC 60250
CS5366-CQZ;CS5366-DQZ;CS5366-CQZR;CS5366-DQZR;中文规格书,Datasheet资料
114 dB, 192 kHz, 6-Channel A/D ConverterFeatures♦Advanced Multi-bit Delta-Sigma Architecture ♦24-Bit Conversion ♦114 dB Dynamic Range ♦-105 dB THD+N♦Supports Audio Sample Rates up to 216 kHz ♦Selectable Audio Interface Formats–Left-Justified, I²S, TDM–6-Channel TDM Interface Formats♦Low Latency Digital Filter♦Less than 535 mW Power Consumption ♦On-Chip Oscillator Driver♦Operation as System Clock Master or Slave ♦Auto-Detect Speed in Slave Mode ♦Differential Analog Architecture♦Separate 1.8 V to 5 V Logic Supplies forControl and Serial Ports♦High-Pass Filter for DC Offset Calibration ♦Overflow Detection♦Footprint Compatible with the 8-ChannelCS5368Additional Control Port Features♦Supports Standard I²C™ or SPI™ ControlInterface♦Individual Channel HPF Disable♦Overflow Detection for Individual Channels ♦Mute Control for Individual Channels♦Independent Power-Down Control per ChannelPairCS5366DescriptionThe CS5366 is a complete 6-channel analog-to-digital converter for digital audio systems. It performs sampling, an-alog-to-digital conversion, and anti-alias filtering, generating 24-bit values for all 6-channel inputs in serial form at sample rates up to 216 kHz per channel.The CS5366 uses a 5th-order, multi-bit delta sigma modulator followed by low latency digital filtering and decima-tion, which removes the need for an external anti-aliasing filter. The ADC uses a differential input architecture which provides excellent noise rejection.Dedicated level translators for the Serial Port and Control Port allow seamless interfacing between the CS5366 and other devices operating over a wide range of logic levels. In addition, an on-chip oscillator driver provides clocking flexibility and simplifies design.The CS5366 is the industry’s first audio A/D to support a high-speed TDM interface which provides a serial output of 6 channels of audio data with sample rates up to 216 kHz within a single data stream. It further reduces layout complexity and relieves input/output constraints in digital signal processors.The CS5366 is available in a 48-pin LQFP package in both Commercial (-40°C to 85°C) and Automotive grades (-40°C to +105°C). The CDB5366 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please see “Ordering Information” on page 41 for complete ordering information.The CS5366 is ideal for high-end and pro-audio systems requiring unrivaled sound quality, transparent conversion, wide dynamic range and negligible distortion, such as A/V receivers, digital mixing consoles, multi-channel record-ers, outboard converters, digital effect processors, and automotive audio systems.TABLE OF CONTENTS1. PIN DESCRIPTION (6)2. TYPICAL CONNECTION DIAGRAM (9)3. CHARACTERISTICS AND SPECIFICATIONS (10)RECOMMENDED OPERATING CONDITIONS (10)ABSOLUTE RATINGS (10)SYSTEM CLOCKING (10)DC POWER (11)LOGIC LEVELS (11)PSRR, VQ AND FILT+ CHARACTERISTICS (11)ANALOG CHARACTERISTICS (COMMERCIAL) (12)ANALOG CHARACTERISTICS (AUTOMOTIVE) (13)DIGITAL FILTER CHARACTERISTICS (14)OVERFLOW TIMEOUT (14)SERIAL AUDIO INTERFACE - I²S/LJ TIMING (15)SERIAL AUDIO INTERFACE - TDM TIMING (16)SWITCHING SPECIFICATIONS - CONTROL PORT - I²C TIMING (17)SWITCHING SPECIFICATIONS - CONTROL PORT - SPI TIMING (18)4. APPLICATIONS (19)4.1 Power (19)4.2 Control Port Mode and Stand-Alone Operation (19)4.2.1 Stand-Alone Mode (19)4.2.2 Control Port Mode (19)4.3 Master Clock Source (20)4.3.1 On-Chip Crystal Oscillator Driver (20)4.3.2 Externally Generated Master Clock (20)4.4 Master and Slave Operation (21)4.4.1 Synchronization of Multiple Devices (21)4.5 Serial Audio Interface (SAI) Format (22)4.5.1 I²S and LJ Format (22)4.5.2 TDM Format (23)4.5.3 Configuring Serial Audio Interface Format (23)4.6 Speed Modes (23)4.6.1 Sample Rate Ranges (23)4.6.2 Using M1 and M0 to Set Sampling Parameters (23)4.6.3 Master Mode Clock Dividers (24)4.6.4 Slave Mode Audio Clocking With Auto-Detect (24)4.7 Master and Slave Clock Frequencies (25)4.8 Reset (27)4.8.1 Power-Down Mode (27)4.9 Overflow Detection (27)4.9.1 Overflow in Stand-Alone Mode (27)4.9.2 Overflow in Control Port Mode (27)4.10 Analog Connections (28)4.11 Optimizing Performance in TDM Mode (29)4.12 DC Offset Control (29)4.13 Control Port Operation (30)4.13.1 SPI Mode (30)4.13.2 I²C Mode (31)5. REGISTER MAP (32)5.1 Register Quick Reference (32)5.2 00h (REVI) Chip ID Code & Revision Register (32)5.3 01h (GCTL) Global Mode Control Register (32)5.4 02h (OVFL) Overflow Status Register (33)5.5 03h (OVFM) Overflow Mask Register (33)5.6 04h (HPF) High-Pass Filter Register (34)5.7 05h Reserved (34)5.8 06h (PDN) Power Down Register (34)5.9 07h Reserved (34)5.10 08h (MUTE) Mute Control Register (34)5.11 09h Reserved (35)5.12 0Ah (SDEN) SDOUT Enable Control Register (35)6. FILTER PLOTS (36)7. PARAMETER DEFINITIONS (39)8. PACKAGE DIMENSIONS (40)THERMAL CHARACTERISTICS (40)9. ORDERING INFORMATION (41)10. REVISION HISTORY (41)LIST OF FIGURESFigure 1. CS5368 Pinout (6)Figure 2. Typical Connection Diagram (9)Figure 3. I²S/LJ Timing (15)Figure 4. TDM Timing (16)Figure 5. I²C Timing (17)Figure 6. SPI Timing (18)Figure 7. Crystal Oscillator Topology (20)Figure 8. Master/Slave Clock Flow (21)Figure 9. Master and Slave Clocking for a Multi-Channel Application (21)Figure 10. I²S Format (22)Figure 11. LJ Format (22)Figure 12. TDM Format (23)Figure 13. Master Mode Clock Dividers (24)Figure 14. Slave Mode Auto-Detect Speed (24)Figure 15. Recommended Analog Input Buffer (28)Figure 16. SPI Format (30)Figure 17. I²C Write Format (31)Figure 18. I²C Read Format (31)Figure 19. SSM Passband (36)Figure 20. DSM Passband (36)Figure 21. QSM Passband (36)Figure 22. SSM Stopband (37)Figure 23. DSM Stopband (37)Figure 24. QSM Stopband (37)Figure 25. SSM -1 dB Cutoff (38)Figure 26. DSM -1 dB Cutoff (38)Figure 27. QSM -1 dB Cutoff (38)LIST OF TABLESTable 1. Power Supply Pin Definitions (19)Table 2. DIF1 and DIF0 Pin Settings (23)Table 3. M1 and M0 Settings (23)Table 4. Frequencies for 48 kHz Sample Rate using LJ/I²S (25)Table 5. Frequencies for 96 kHz Sample Rate using LJ/I²S (25)Table 6. Frequencies for 192 kHz Sample Rate using LJ/I²S (25)Table 7. Frequencies for 48 kHz Sample Rate using TDM (25)Table 8. Frequencies for 48 kHz Sample Rate using TDM (25)Table 9. Frequencies for 96 kHz Sample Rate using TDM (26)Table 10. Frequencies for 96 kHz Sample Rate using TDM (26)Table 11. Frequencies for 192 kHz Sample Rate using TDM (26)Table 12. Frequencies for 192 kHz Sample Rate using TDM (26)1.PIN DESCRIPTION ArrayFigure 1. CS5366 PinoutPin Name Pin #Pin DescriptionAIN2+, AIN2-AIN4+, AIN4-AIN3+, AIN3-AIN6+, AIN6-AIN5+, AIN5-AIN1+, AIN1-1,211,1213,1443,4445,4647,48Differential Analog (Inputs) - Audio signals are presented differently to the delta sigma modula-tors via the AIN+/- pins.GND3,810,1516,1718,1929,32Ground (Input) - Ground reference. Must be connected to analog ground.VA4,9Analog Power (Input)- Positive power supply for the analog sectionREF_GND5Reference Ground (Input) - For the internal sampling circuits. Must be connected to analog ground.FILT+6Positive Voltage Reference (Output) - Reference voltage for internal sampling circuits. VQ7Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage.VX20Crystal Oscillator Power (Input) - Also powers control logic to enable or disable oscillator cir-cuits.XTI XTO 2122Crystal Oscillator Connections (Input/Output) - I/O pins for an external crystal which may be used to generate MCLK.MCLK23System Master Clock (Input/Output) - When a crystal is used, this pin acts as a buffered MCLK Source (Output). When the oscillator function is not used, this pin acts as an input for the system master clock. In this case, the XTI and XTO pins must be tied low.LRCK/FS24Serial Audio Channel Clock (Input/Output)In I²S mode Serial Audio Channel Select. When low, the odd channels are selected.In LJ mode Serial Audio Channel Select. When high, the odd channels are selected.In TDM Mode a frame sync signal. When high, it marks the beginning of a new frame of serial audio samples. In Slave Mode, this pin acts as an input pin.SCLK25Main timing clock for the Serial Audio Interface (Input/Output) - During Master Mode, this pin acts as an output, and during Slave Mode it acts as an input pin.TSTO26Test Out (Output) - Must be left unconnected.SDOUT227Serial Audio Data (Output) - Channels 3,4VLS28Serial Audio Interface Power - Positive power for the serial audio interface.SDOUT1/TDM30Serial Audio Data (Output) - Channels 1,2, TDM.SDOUT3/TDM31Serial Audio Data (Output) - Channels 5,6, TDM is complementary TDM data.VD33Digital Power (Input) - Positive power supply for the digital section.VLC35Control Port Interface Power - Positive power for the control port interface.OVFL36Overflow (Output, open drain) - Detects an overflow condition on both left and right channels.RST41Reset (Input) - The device enters a low power mode when low.Stand-Alone ModeCLKMODE34CLKMODE(Input) - Setting this pin HIGH places a divide-by-1.5 circuit in the MCLK path to the core device circuitry.DIF1 DIF03738DIF1, DIF0 (Input) - Sets the serial audio interface format.M1 M03940Mode Selection (Input) - Determines the operational mode of the device.MDIV42MCLK Divider (Input) - Setting this pin HIGH places a divide-by-2 circuit in the MCLK path to the core device circuitry.Control Port ModeCLKMODE34CLKMODE (Input) - This pin is ignored in Control Port Mode and the same functionality is obtained from the corresponding bit in the Global Control Register. Note: Should be connected to GND when using the part in Control Port Mode.AD1/CDIN37I²C Format, AD1 (Input) - Forms the device address input AD[1]. SPI Format, CDIN (Input) - Becomes the input data pin.AD0/CS38I²C Format, AD0 (Input) - Forms the device address input AD[0]. SPI Format, CS (Input) - Acts as the active low chip select input.SCL/CCLK39I²C Format, SCL (Input) - Serial clock for the serial control port. An external pull-up resistor is required for I²C control port operation.SPI Format, CCLK (Input) - Serial clock for the serial control port.SDA/CDOUT40I²C Format SDA (Input/Output) - Acts as an input/output data pin. An external pull-up resistor is required for I²C control port operation.SPI Format CDOUT (Output) - Acts as an output only data pin.MDIV42MCLK Divider (Input) - This pin is ignored in Control Port Mode and the same function-ality is obtained from the corresponding bit in the Global Control Register.Note: Should be connected to GND when using the part in Control Port Mode.2.TYPICAL CONNECTION DIAGRAM Array Figure 2. Typical Connection DiagramFor analog buffer configurations, refer to Cirrus Application Note AN241. Also, a low-cost single-ended-to-differen-tial solution is provided on the Customer Evaluation Board.3.CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONSGND = 0 V, all voltages with respect to 0 V.1.TDM Quad-Speed Mode specified to operate correctly at VLS ≥ 3.14 V.ABSOLUTE RATINGSOperation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Transient currents up to ±100 mA on the analog input pins will not cause SCR latch-up.SYSTEM CLOCKINGParameterSymbol MinTypMax UnitDC Power Supplies:Positive Analog Positive Crystal Positive Digital Positive Serial Logic Positive Control LogicVA VX VD VLS VLC 4.754.753.141.7111.71 5.05.03.33.33.3 5.25VAmbient Operating Temperature(-CQZ) (-DQZ)T AC T AA-40-40--85105°CParameterSymbolMin Typ Max UnitsDC Power Supplies:Positive Analog Positive Crystal Positive Digital Positive Serial Logic Positive Control LogicVA VX VD VLS VLC -0.3-+6.0VInput Current I in -10-+10mA Analog Input Voltage V IN -0.3VA+0.3V Digital Input VoltageV IND VL+0.3Ambient Operating Temperature (Power Applied)T A -50+125°CStorage TemperatureT stg-65+150ParameterSymbolMinTyp MaxUnitInput Master Clock Frequency MCLK 0.51255.05MHz Input Master Clock Duty Cyclet clkhl4060%分销商库存信息:CIRRUS-LOGICCS5366-CQZ CS5366-DQZ CS5366-CQZR CS5366-DQZR。
MC88916中文资料
MC88916OUTLINE DIMENSIONSMotorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.How to reach us:USA/EUROPE: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; T atsumi–SPD–JLDC, T oshikatsu Otsuki,P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 6F Seibu–Butsuryu–Center, 3–14–2 T atsumi Koto–Ku, T okyo 135, Japan. 03–3521–8315 MFAX: RMFAX0@ –TOUCHTONE (602) 244–6609HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B T ai Ping Industrial Park, INTERNET: http://Design–51 Ting Kok Road, T ai Po, N.T., Hong Kong. 852–26629298。
2855中文资料
Zoom® ComStar TM 56KSpeakerPhone/FaxModemA Complete CommunicationsCenter For Your Computer!The Zoom ComStar 56K Model 2818 for PC-compatible computers combines a full-featured V.34modem capable of 56,000 Kbps Internet and centralsite downloads with a powerful voice mail system,digital answering machine, 14,400 bps fax, convenientspeed dialer, and a synchronous interface supportingthe ITU H.324 videophone technology standard. It isPlug and Play compatible for easy installation underMicrosoft® Windows® 95 and is also softwareconfigurable.The Zoom ComStar 56K comes complete with a high-quality external microphone and speaker. It comeswith Cheyenne® BitWare® Fax/Voice/Data forWindows; ZOOM/LINK® CD-ROM with modem-enabled games, conferencing software, supportinformation, and more.About the Zoom ComStar 56KZoom ComStar 56K Speakerphone/FaxModem transforms your ordinary computer into anextraordinary telecommunications tool. ComStar 56K (internal) Model 2818 for PC-compatible computers is a high-speed V.34 faxmodem that can download data from compatible sites atspeeds up to 56,000 bps and at higher speeds with compression for fast Internet and LAN access.It combines a full-featured K56flex TM faxmodem, 14,400 bps fax, and full-duplex speakerphone over conventional telephone lines and features flash memory and reprogrammable DSP fordownloading feature enhancements and upgrades to future standards with simple softwarecommands. Other advanced features include a synchronous interface supporting the ITU H.324 videophone technology standard,* digital answering machine, voice mail, convenient speeddialer, and Plug-and-Play compatibility for easy installation. The Zoom ComStar 56K comescomplete with a high-quality external microphone and speaker, and all necessary software. ComStar 56K is built in the U.S.A. by Zoom Telephonics, Inc., a leading supplier of telecommunications equipment since 1977 and is backed by Zoom's outstanding 7-year warranty. Featuresr K56flex technology for 56,000 bps data downloads from compatible sitesr33,600 bps V.34 data transmission speedr14,400 bps Group 3, Class 1 and 2 faxr V.42bis and MNP 5 compression for data speeds up to 230,400 bpsr Reprogrammable Digital Signal Processor (DSP) enables easy software upgradeability to assure superior interoperability and overall performance and easy upgrades to futurestandards.r Flash memory for easy firmware upgradesr56K Faxmodem: Connect to the Internet, World Wide Web and on-line services, anddownload files fast and error-free at up to 56,000 bps with K56flex, the joint development of Rockwell and Lucent Technologies. Send "printer-quality" faxes direct from your PC, plus faxback and fax-on-demand.r Speakerphone: For "hands-free" communications and conference calls. True full-duplex speakerphone lets callers on both ends talk at the same time for natural conversation.r Videophone-Ready: Supports the ITU H.324 video technology standard and H.324compliant software from Intel, PictureTel, VDONet, Smith Micro, and others.*r Digital Answering Machine: An easy-to-use personal answering machine with high-quality recording and playback, pager notification, and other advanced features.r Voice Mail: A full-featured, configurable voice mail system for home or office withmultiple mailboxes, fax-on-demand, and remote retrieval of messages.r Other Features: Plug-and-Play with Windows 95 computers (software configurable also), VoiceView® compatibility, Directory Dialing, Distinctive Ring,** Caller ID,** andZoomGuard lightning protection.Technical SpecificationsData Speeds:r300 to 33,600 bps full-duplex with international standardsr Up to 56,000 bps receive/33,600 bps send with K56flexFax Speeds:r 300 to 14,400 bpsr Group 3, Class 1 and Class 2Standards Supported:r Data: K56flex, V34, V.32bis, V.32, V.22bis, V.22 A/B, V.22, V.23, V.21, Bell 103/212Ar Fax: V.33, V.29, V.17, V.27ter, V.21 channel 2Compression: V.42bis, MNP 5r Error Control: V.42, MNP 2 - 4, MNP 10 and MNP 10ECr Plug and Playr AT and extended AT command set compatibleCommand Set:Hayes AT-Command compatible, with extended MNP 5, MNP 10, and V.42bis commandsVoice Encoding:Enhanced ADPCM, programmable at 2 or 4 bits per sampleSpeakerphone:Full-duplex with microphone and speaker included; headset capability; software volume controlInterface:Plug and Play; COM1 - COM8, IRQ, 3, 4, 5, 7, 9, 10, 12, 15 supports TAPIVideoconferencing enabled:Synchronous interface supports ITU H.324 standard for videoconferencing applications.*Hardware Features:r Dual RJ-11 telephone jacks one for phone line, one for optional phoner Output jack for external 8 ohm audio speaker (8 ohm external speaker included)r Input jack for external microphone (microphone included)r Jumper-selectable electret microphone biasr Telephone cable with RJ-11 connectorsr Buffered 16550 UART to reduce PC interrupts and boost performancer Handset record and playbackDimensions and Power Requirements:r Dimensions: standard IBM PC board 2.7 in. W by 5.4 in. L by 0.75 in. H (fits 16-bit PC-compatible slot)r Power consumption: 1.5W typicalSystem Requirements:r486 or faster PC compatible computer with 1 available 16-bit ISA slotr8 MB RAMr 3.5 in. floppy driver Hard drive with a minimum of 5 MB available r Microsoft Windows 3.1 or higherr Mouse recommendedRegulatory Approvals:rFCC Parts 15B and 68 r UL, C-ULr Industry CanadaWarranty:Warranted against defects in material andworkmanship for a period of seven years from the date of original retail purchase* Requires video camera and video capture support, sound card with microphone input, ITU H.324-compliant videoconferencing application, and appropriate computer and operating system to run the application.** Requires Distinctive Ring or Caller ID support from local telephone company.Zoom Telephonics, Inc.207 South Street Boston, MA 02111617 423-1072800 631-3116Fax: 617 423-3923Web Site: BBS: 617 423-3733Nasdaq: ZOOMZoom is a registered trademark and ComStar, Zoom/FaxModem, ZoomGuard are trademarks of Zoom Telephonics, Inc. K56flex is a trademark of Rockwell International Corporation and Lucent Technologies, Inc. Windows is a registered trademark of Microsoft. MNP is a registered trademark and MNP 10EC is a trademark of Microcom Inc. All other registered trademarks and trademarks are the property of their respective owners.Made in the U.S.A.©2000 Zoom Telephonics, Inc.1777。
MC7806A中文资料
Rev. 1.0.1Features•Output Current up to 1A •Output V oltages of 5, 6, 8, 9, 10, 12, 15, 18, 24V•Thermal Overload Protection •Short Circuit Protection•Output Transistor Safe Operating Area ProtectionDescriptionThe MC78XX/LM78XX/MC78XXA series of three terminal positive regulators are available in theTO-220/D-PAK package and with several fixed output voltages, making them useful in a wide range ofapplications. Each type employs internal current limiting,thermal shut down and safe operating area protection,making it essentially indestructible. If adequate heat sinking is provided, they can deliver over 1A output current.Although designed primarily as fixed voltage regulators,these devices can be used with external components toobtain adjustable voltages and currents.TO-220D-PAK1. Input2. GND3. Output11Internal Block DigramMC78XX/LM78XX/MC78XXA3-Terminal 1A Positive Voltage RegulatorMC78XX/LM78XX/MC78XXAAbsolute Maximum RatingsElectrical Characteristics (MC7805/LM7805)(Refer to test circuit ,0°C < T J < 125°C, I O = 500mA, V I = 10V, C I = 0.33µF, C O = 0.1µF, unless otherwise specified)Note:1. Load and line regulation are specified at constant junction temperature. Changes in V o due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbol Value Unit Input Voltage (for V O = 5V to 18V)(for V O = 24V)V I V I 3540V V Thermal Resistance Junction-Cases (TO-220)R θJC 5oC/WThermal Resistance Junction-Air (TO-220)R θJA 65o C/WOperating Temperature Range T OPR 0 ~ +125o C Storage Temperature RangeT STG-65 ~ +150o CParameterSymbolConditionsMC7805/LM7805UnitMin.Typ.Max.Output VoltageV OT J =+25 o C4.85.0 5.25.0mA ≤Io ≤1.0A, P O ≤15W V I = 7V to 20V 4.75 5.0 5.25 V Line Regulation (Note1)ReglineT J =+25 o C V O = 7V to 25V - 4.0100mV V I = 8V to 12V - 1.650Load Regulation (Note1)Regload T J =+25 o C I O = 5.0mA to1.5A-9100mV I O =250mA to 750mA -450Quiescent Current I Q T J =+25 o C - 5.08.0mA Quiescent Current Change ∆I Q I O = 5mA to 1.0A -0.030.5mA V I = 7V to 25V -0.3 1.3Output Voltage Drift ∆V O /∆T I O = 5mA--0.8-mV/ o C Output Noise Voltage V N f = 10Hz to 100KHz, T A =+25 o C -42-µV/Vo Ripple Rejection RR f = 120HzV O = 8V to 18V 6273-dB Dropout Voltage V Drop I O = 1A, T J =+25 o C -2-V Output Resistance r O f = 1KHz-15-m ΩShort Circuit Current I SC V I = 35V, T A =+25 o C -230-mA Peak CurrentI PKT J =+25 o C- 2.2-AMC78XX/LM78XX/MC78XXAElectrical Characteristics (MC7806)(Refer to test circuit ,0°C < T J < 125°C, I O = 500mA, V I =11V, C I = 0.33µF, C O = 0.1µF, unless otherwise specified)Note:1. Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbolConditionsMC7806UnitMin.Typ.Max.Output VoltageV OT J =+25 o C5.756.0 6.255.0mA ≤I O ≤1.0A, P O ≤15W V I = 8.0V to 21V 5.7 6.0 6.3 V Line Regulation (Note1)Regline T J =+25 o C V I = 8V to 25V -5120mV V I = 9V to 13V - 1.560Load Regulation (Note1)Regload T J =+25 o C I O =5mA to 1.5A -9120mV I O =250mA to750A -360Quiescent Current I Q T J =+25 o C - 5.08.0mA Quiescent Current Change ∆I Q I O = 5mA to 1A --0.5mA V I = 8V to 25V -- 1.3Output Voltage Drift ∆V O /∆T I O = 5mA--0.8-mV/ o C Output Noise Voltage V N f = 10Hz to 100KHz, T A =+25 o C -45-µV/Vo Ripple Rejection RR f = 120HzV I = 9V to 19V 5975-dB Dropout Voltage V Drop I O = 1A, T J =+25 o C -2-V Output Resistance r O f = 1KHz-19-m ΩShort Circuit Current I SC V I = 35V, T A =+25 o C -250-mA Peak CurrentI PKT J =+25 o C- 2.2-AMC78XX/LM78XX/MC78XXAElectrical Characteristics (MC7808)(Refer to test circuit ,0°C < T J < 125°C, I O = 500mA, V I =14V, C I = 0.33µF, C O = 0.1µF, unless otherwise specified)Note:1. Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbolConditionsMC7808UnitMin.Typ.Max.Output VoltageV OT J =+25 o C7.78.08.35.0mA ≤ I O ≤1.0A, P O ≤15W V I = 10.5V to 23V 7.68.08.4 V Line Regulation (Note1)Regline T J =+25 o C V I = 10.5V to 25V - 5.0160mV V I = 11.5V to 17V - 2.080Load Regulation (Note1)Regload T J =+25 o C I O = 5.0mA to 1.5A -10160mV I O = 250mA to 750mA - 5.080Quiescent Current I Q T J =+25 o C - 5.08.0mA Quiescent Current Change ∆I Q I O = 5mA to 1.0A -0.050.5mA V I = 10.5A to 25V -0.5 1.0Output Voltage Drift ∆V O /∆T I O = 5mA--0.8-mV/ o C Output Noise Voltage V N f = 10Hz to 100KHz, T A =+25 o C -52-µV/Vo Ripple Rejection RR f = 120Hz, V I = 11.5V to 21.5V 5673-dB Dropout Voltage V Drop I O = 1A, T J =+25 o C -2-V Output Resistance r O f = 1KHz-17-m ΩShort Circuit Current I SC V I = 35V, T A =+25 o C -230-mA Peak CurrentI PKT J =+25 o C- 2.2-AMC78XX/LM78XX/MC78XXAElectrical Characteristics (MC7809)(Refer to test circuit ,0°C < T J < 125°C, I O = 500mA, V I =15V, C I = 0.33µF, C O = 0.1µF, unless otherwise specified)Note:1. Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbolConditionsMC7809UnitMin.Typ.Max.Output VoltageV OT J =+25°C8.6599.355.0mA ≤ I O ≤1.0A, P O ≤15W V I = 11.5V to 24V 8.699.4 V Line Regulation (Note1)Regline T J =+25°C V I = 11.5V to 25V -6180mV V I = 12V to 17V -290Load Regulation (Note1)Regload T J =+25°C I O = 5mA to 1.5A -12180mV I O = 250mA to 750mA -490Quiescent Current I Q T J =+25°C - 5.08.0mA Quiescent Current Change ∆I Q I O = 5mA to 1.0A --0.5mA V I = 11.5V to 26V -- 1.3Output Voltage Drift ∆V O /∆T I O = 5mA--1-mV/ °C Output Noise Voltage V N f = 10Hz to 100KHz, T A =+25 °C -58-µV/Vo Ripple Rejection RR f = 120HzV I = 13V to 23V 5671-dB Dropout Voltage V Drop I O = 1A, T J =+25°C -2-V Output Resistance r O f = 1KHz-17-m ΩShort Circuit Current I SC V I = 35V, T A =+25°C -250-mA Peak CurrentI PKT J = +25°C- 2.2-A(Refer to test circuit ,0°C< T J < 125°C, I O = 500mA, V I =16V, C I = 0.33µF, C O =0.1µF, unless otherwise specified)Note:1. Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbolConditionsMC7810UnitMin.Typ.Max.Output VoltageV OT J =+25 °C9.61010.45.0mA ≤ I O ≤1.0A, P O ≤15W V I = 12.5V to 25V 9.51010.5 V Line Regulation (Note1)Regline T J =+25°C V I = 12.5V to 25V -10200mV V I = 13V to 25V -3100Load Regulation (Note1)Regload T J =+25°C I O = 5mA to 1.5A -12200mV I O = 250mA to 750mA -4400Quiescent Current I Q T J =+25°C - 5.18.0mA Quiescent Current Change ∆I Q I O = 5mA to 1.0A --0.5mA V I = 12.5V to 29V -- 1.0Output Voltage Drift ∆V O /∆T I O = 5mA--1-mV/°C Output Noise Voltage V N f = 10Hz to 100KHz, T A =+25 °C -58-µV/Vo Ripple Rejection RR f = 120HzV I = 13V to 23V 5671-dB Dropout Voltage V Drop I O = 1A, T J =+25 °C -2-V Output Resistance r O f = 1KHz-17-m ΩShort Circuit Current I SC V I = 35V, T A =+25 °C -250-mA Peak CurrentI PKT J =+25 °C- 2.2-A(Refer to test circuit ,0°C < T J < 125°C, I O = 500mA, V I =19V, C I = 0.33µF, C O =0.1µF, unless otherwise specified)Note:1. Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbolConditionsMC7812UnitMin.Typ.Max.Output VoltageV OT J =+25 o C11.51212.55.0mA ≤ I O ≤1.0A, P O ≤15W V I = 14.5V to 27V 11.41212.6 V Line Regulation (Note1)ReglineT J =+25 o CV I = 14.5V to 30V -10240mV V I = 16V to 22V - 3.0120Load Regulation (Note1)Regload T J =+25 o C I O = 5mA to 1.5A -11240mV I O = 250mA to 750mA - 5.0120Quiescent Current I Q T J =+25 o C - 5.18.0mA Quiescent Current Change ∆I Q I O = 5mA to 1.0A -0.10.5mA V I = 14.5V to 30V -0.5 1.0Output Voltage Drift ∆V O /∆T I O = 5mA--1-mV/ o C Output Noise Voltage V N f = 10Hz to 100KHz, T A =+25 o C -76-µV/Vo Ripple Rejection RR f = 120HzV I = 15V to 25V 5571-dB Dropout Voltage V Drop I O = 1A, T J =+25 o C -2-V Output Resistance r O f = 1KHz-18-m ΩShort Circuit Current I SC V I = 35V, T A =+25 o C -230-mA Peak CurrentI PKT J = +25 o C- 2.2-AMC78XX/LM78XX/MC78XXAElectrical Characteristics (MC7815)(Refer to test circuit ,0°C < T J < 125°C, I O = 500mA, V I =23V, C I = 0.33µF, C O =0.1µF, unless otherwise specified)Note:1. Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbolConditionsMC7815UnitMin.Typ.Max.Output VoltageV OT J =+25 o C14.41515.65.0mA ≤ I O ≤ 1.0A, P O ≤ 15W V I = 17.5V to 30V 14.251515.75 V Line Regulation (Note1)ReglineT J =+25 o C V I = 17.5V to 30V -11300mV V I = 20V to 26V -3150Load Regulation (Note1)Regload T J =+25 o C I O = 5mA to 1.5A-12300mV I O = 250mA to 750mA -4150Quiescent Current I Q T J =+25 o C - 5.28.0mA Quiescent Current Change ∆I Q I O = 5mA to 1.0A --0.5mA V I = 17.5V to 30V -- 1.0Output Voltage Drift ∆V O /∆T I O = 5mA--1-mV/ o C Output Noise Voltage V N f = 10Hz to 100KHz, T A =+25 o C -90-µV/Vo Ripple Rejection RR f = 120HzV I = 18.5V to 28.5V 5470-dB Dropout Voltage V Drop I O = 1A, T J =+25 o C -2-V Output Resistance r O f = 1KHz-19-m ΩShort Circuit Current I SC V I = 35V, T A =+25 o C -250-mA Peak CurrentI PKT J =+25 o C- 2.2-A(Refer to test circuit ,0°C < T J < 125°C, I O = 500mA, V I =27V, C I = 0.33µF, C O =0.1µF, unless otherwise specified)Note:1. Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbolConditionsMC7818UnitMin.Typ.Max.Output VoltageV OT J =+25 o C17.31818.75.0mA ≤ I O ≤1.0A, P O ≤15W V I = 21V to 33V 17.11818.9 V Line Regulation (Note1)ReglineT J =+25 o CV I = 21V to 33V -15360mV V I = 24V to 30V -5180Load Regulation (Note1)Regload T J =+25 o C I O = 5mA to 1.5A -15360mV I O = 250mA to 750mA - 5.0180Quiescent Current I Q T J =+25 o C - 5.28.0mA Quiescent Current Change ∆I Q I O = 5mA to 1.0A --0.5mA V I = 21V to 33V --1Output Voltage Drift ∆V O /∆T I O = 5mA--1-mV/ o C Output Noise Voltage V N f = 10Hz to 100KHz, T A =+25 o C -110-µV/Vo Ripple Rejection RR f = 120HzV I = 22V to 32V 5369-dB Dropout Voltage V Drop I O = 1A, T J =+25 o C -2-V Output Resistance r O f = 1KHz-22-m ΩShort Circuit Current I SC V I = 35V, T A =+25 o C -250-mA Peak CurrentI PKT J =+25 o C-2.2-A(Refer to test circuit ,0°C < T J < 125°C, I O = 500mA, V I =33V, C I = 0.33µF, C O =0.1µF, unless otherwise specified)Note:1. Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbolConditionsMC7824UnitMin.Typ.Max.Output VoltageV OT J =+25 o C2324255.0mA ≤ I O ≤ 1.0A, P O ≤ 15W V I = 27V to 38V 22.82425.25 V Line Regulation (Note1)Regline T J =+25 o C V I = 27V to 38V -17480mV V I = 30V to 36V -6240Load Regulation (Note1)Regload T J =+25 o C I O = 5mA to 1.5A -15480mV I O = 250mA to 750mA - 5.0240Quiescent Current I Q T J =+25 o C - 5.28.0mA Quiescent Current Change ∆I Q I O = 5mA to 1.0A -0.10.5mA V I = 27V to 38V -0.51Output Voltage Drift ∆V O /∆T I O = 5mA--1.5-mV/ o C Output Noise Voltage V N f = 10Hz to 100KHz, T A =+25 o C -60-µV/Vo Ripple Rejection RR f = 120HzV I = 28V to 38V 5067-dB Dropout Voltage V Drop I O = 1A, T J =+25 o C -2-V Output Resistance r O f = 1KHz-28-m ΩShort Circuit Current I SC V I = 35V, T A =+25 o C -230-mA Peak CurrentI PKT J =+25 o C- 2.2-AMC78XX/LM78XX/MC78XXAElectrical Characteristics (MC7805A)(Refer to the test circuits. 0°C < T J < 125°C, I o =1A, V I = 10V, C I =0.33µF, C O =0.1µF, unless otherwise specified)Note:1. Load and line regulation are specified at constant junction temperature. Change in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbol ConditionsMin.Typ.Max.UnitOutput VoltageV OT J =+25 o C4.955.1V I O = 5mA to 1A, P O ≤ 15W V I = 7.5V to 20V 4.85 5.2Line Regulation (Note1)ReglineV I = 7.5V to 25V I O = 500mA-550mV V I = 8V to 12V -350T J =+25 o CV I = 7.3V to 20V -550V I = 8V to 12V- 1.525Load Regulation (Note1)RegloadT J =+25 o CI O = 5mA to 1.5A -9100mV I O = 5mA to 1A -9100I O = 250mA to 750mA -450Quiescent Current I Q T J =+25 o C - 5.06mA Quiescent Current Change∆I Q I O = 5mA to 1A--0.5mA V I = 8 V to 25V, I O = 500mA --0.8V I = 7.5V to 20V, T J =+25 o C --0.8Output Voltage Drift ∆V/∆T Io = 5mA--0.8-mV/ o C Output Noise Voltage V N f = 10Hz to 100KHz T A =+25 o C-10-µV/Vo Ripple Rejection RR f = 120Hz, I O = 500mA V I = 8V to 18V -68-dB Dropout Voltage V Drop I O = 1A, T J =+25 o C -2-V Output Resistance r O f = 1KHz-17-m ΩShort Circuit Current I SC V I = 35V, T A =+25 o C -250-mA Peak CurrentI PKT J = +25 o C- 2.2-AMC78XX/LM78XX/MC78XXAElectrical Characteristics (MC7806A)(Refer to the test circuits. 0°C < T J < 125°C, I o =1A, V I =11V, C I =0.33µF, C O =0.1µF, unless otherwise specified)Note:1. Load and line regulation are specified at constant junction temperature. Change in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbol ConditionsMin.Typ.Max.UnitOutput VoltageV OT J =+25 o C5.5866.12V I O = 5mA to 1A, P O ≤ 15W V I = 8.6V to 21V 5.766 6.24Line Regulation (Note1)ReglineV I = 8.6V to 25V I O = 500mA-560mV V I = 9V to 13V -360T J =+25 o CV I = 8.3V to 21V -560V I = 9V to 13V- 1.530Load Regulation (Note1)RegloadT J =+25 o CI O = 5mA to 1.5A -9100mV I O = 5mA to 1A -4100I O = 250mA to 750mA - 5.050Quiescent Current I Q T J =+25 o C - 4.36mA Quiescent Current Change ∆I Q I O = 5mA to 1A--0.5mA V I = 9V to 25V, I O = 500mA --0.8V I = 8.5V to 21V, T J =+25 o C --0.8Output Voltage Drift ∆V/∆T I O = 5mA--0.8-mV/ o C Output Noise Voltage V N f = 10Hz to 100KHz T A =+25 o C-10-µV/Vo Ripple Rejection RR f = 120Hz, I O = 500mA V I = 9V to 19V -65-dB Dropout Voltage V Drop I O = 1A, T J =+25 o C -2-V Output Resistance r O f = 1KHz-17-m ΩShort Circuit Current I SC V I = 35V, T A =+25 o C -250-mA Peak CurrentI PKT J =+25 o C- 2.2-AMC78XX/LM78XX/MC78XXAElectrical Characteristics (MC7808A)(Refer to the test circuits. 0°C < T J < 125°C, I o =1A, V I = 14V, C I =0.33µF, C O =0.1µF, unless otherwise specified)Note:1. Load and line regulation are specified at constant junction temperature. Change in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbol ConditionsMin.Typ.Max.UnitOutput VoltageV OT J =+25 o C7.8488.16V I O = 5mA to 1A, P O ≤15W V I = 10.6V to 23V 7.788.3Line Regulation (Note1)ReglineV I = 10.6V to 25V I O = 500mA-680mV V I = 11V to 17V -380T J =+25 o CV I = 10.4V to 23V -680V I = 11V to 17V-240Load Regulation (Note1)RegloadT J =+25 o CI O = 5mA to 1.5A -12100mV I O = 5mA to 1A -12100I O = 250mA to 750mA -550Quiescent Current I Q T J =+25 o C - 5.06mA Quiescent Current Change ∆I Q I O = 5mA to 1A--0.5mA V I = 11V to 25V, I O = 500mA --0.8V I = 10.6V to 23V, T J =+25 o C --0.8Output Voltage Drift ∆V/∆T I O = 5mA--0.8-mV/ o C Output Noise Voltage V N f = 10Hz to 100KHz T A =+25 o C-10-µV/Vo Ripple Rejection RR f = 120Hz, I O = 500mA V I = 11.5V to 21.5V -62-dB Dropout Voltage V Drop I O = 1A, T J =+25 o C -2-V Output Resistance r O f = 1KHz-18-m ΩShort Circuit Current I SC V I = 35V, T A =+25 o C -250-mA Peak CurrentI PKT J =+25 o C- 2.2-AMC78XX/LM78XX/MC78XXAElectrical Characteristics (MC7809A)(Refer to the test circuits. 0°C < T J < 125°C, I o =1A, V I = 15V, C I =0.33µF, C O =0.1µF, unless otherwise specified)Note:1. Load and line regulation are specified at constant, junction temperature. Change in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbolConditionsMin.Typ.Max.UnitOutput VoltageV OT J =+25°C8.829.09.18V I O = 5mA to 1A, P O ≤15W V I = 11.2V to 24V 8.659.09.35Line Regulation (Note1)ReglineV I = 11.7V to 25V I O = 500mA-690mV V I = 12.5V to 19V -445T J =+25°CV I = 11.5V to 24V -690 V I = 12.5V to 19V -245Load Regulation (Note1)RegloadT J =+25°CI O = 5mA to 1.0A -12100mV I O = 5mA to 1.0A -12100I O = 250mA to 750mA -550Quiescent Current I Q T J =+25 °C- 5.0 6.0mA Quiescent Current Change ∆I Q V I = 11.7V to 25V, T J =+25 °C --0.8mA V I = 12V to 25V, I O = 500mA --0.8I O = 5mA to 1.0A --0.5Output Voltage Drift ∆V/∆T I O = 5mA--1.0-mV/ °C Output Noise Voltage V N f = 10Hz to 100KHz T A =+25 °C-10-µV/Vo Ripple Rejection RR f = 120Hz, I O = 500mA V I = 12V to 22V -62-dB Dropout Voltage V Drop I O = 1A, T J =+25 °C - 2.0-V Output Resistance r O f = 1KHz-17-m ΩShort Circuit Current I SC V I = 35V, T A =+25 °C -250-mA Peak CurrentI PKT J =+25°C- 2.2-A(Refer to the test circuits. 0°C < T J < 125°C, I o =1A, V I = 16V, C I =0.33µF, C O =0.1µF, unless otherwise specified)Note:1. Load and line regulation are specified at constant junction temperature. Change in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbolConditionsMin.Typ.Max.UnitOutput VoltageV OT J =+25°C9.81010.2V I O = 5mA to 1A, P O ≤ 15W V I =12.8V to 25V 9.61010.4Line Regulation (Note1)ReglineV I = 12.8V to 26V I O = 500mA-8100mV V I = 13V to 20V -450 T J =+25 °CV I = 12.5V to 25V -8100 V I = 13V to 20V -350Load Regulation (Note1)RegloadT J =+25 °CI O = 5mA to 1.5A -12100mV I O = 5mA to 1.0A -12100 I O = 250mA to 750mA -550Quiescent Current I Q T J =+25 °C- 5.0 6.0mA Quiescent Current Change ∆I QV I = 13V to 26V, T J =+25 °C --0.5mA V I = 12.8V to 25V, I O = 500mA --0.8 I O = 5mA to 1.0A--0.5Output Voltage Drift ∆V/∆T I O = 5mA --1.0-mV/ °C Output Noise Voltage V N f = 10Hz to 100KHz T A =+25 °C-10-µV/Vo Ripple Rejection RR f = 120Hz, I O = 500mA V I = 14V to 24V -62-dB Dropout Voltage V Drop I O = 1A, T J =+25°C - 2.0-V Output Resistance r O f = 1KHz-17-m ΩShort Circuit Current I SC V I = 35V, T A =+25 °C -250-mA Peak CurrentI PKT J =+25 °C- 2.2-A(Refer to the test circuits. 0°C < T J < 125°C, I o =1A, V I = 19V, C I =0.33µF, C O =0.1µF, unless otherwise specified)Note:1. Load and line regulation are specified at constant junction temperature. Change in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbol ConditionsMin.Typ.Max.UnitOutput VoltageV OT J =+25 °C11.751212.25V I O = 5mA to 1A, P O ≤15W V I = 14.8V to 27V 11.51212.5Line Regulation (Note1)ReglineV I = 14.8V to 30V I O = 500mA-10120mV V I = 16V to 22V -4120 T J =+25 °CV I = 14.5V to 27V -10120 V I = 16V to 22V-360Load Regulation (Note1)RegloadT J =+25 °CI O = 5mA to 1.5A -12100mV I O = 5mA to 1.0A -12100 I O = 250mA to 750mA -550Quiescent Current I Q T J =+25°C- 5.16.0mA Quiescent Current Change ∆I QV I = 15V to 30V, T J =+25 °C -0.8mA V I = 14V to 27V, I O = 500mA -0.8 I O = 5mA to 1.0A-0.5Output Voltage Drift ∆V/∆T I O = 5mA --1.0-mV/°C Output Noise Voltage V N f = 10Hz to 100KHz T A =+25°C-10-µV/Vo Ripple Rejection RR f = 120Hz, I O = 500mA V I = 14V to 24V -60-dB Dropout Voltage V Drop I O = 1A, T J =+25°C - 2.0-V Output Resistance r O f = 1KHz-18-m ΩShort Circuit Current I SC V I = 35V, T A =+25 °C -250-mA Peak CurrentI PKT J =+25 °C- 2.2-AMC78XX/LM78XX/MC78XXAElectrical Characteristics (MC7815A)(Refer to the test circuits. 0°C < T J < 125°C, I o =1A, V I =23V, C I =0.33µF, C O =0.1µF, unless otherwise specified)Note:1. Load and line regulation are specified at constant junction temperature. Change in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbol ConditionsMin.Typ.Max.UnitOutput VoltageV OT J =+25 °C14.71515.3V I O = 5mA to 1A, P O ≤15W V I = 17.7V to 30V 14.41515.6Line Regulation (Note1)ReglineV I = 17.9V to 30V I O = 500mA-10150mV V I = 20V to 26V -5150 T J =+25°CV I = 17.5V to 30V -11150 V I = 20V to 26V-375Load Regulation (Note1)RegloadT J =+25 °CI O = 5mA to 1.5A -12100mV I O = 5mA to 1.0A -12100 I O = 250mA to 750mA -550Quiescent Current I Q T J =+25 °C- 5.2 6.0mA Quiescent Current Change ∆I QV I = 17.5V to 30V, T J =+25 °C --0.8mA V I = 17.5V to 30V, I O = 500mA --0.8 I O = 5mA to 1.0A--0.5Output Voltage Drift ∆V/∆T I O = 5mA --1.0-mV/°C Output Noise Voltage V N f = 10Hz to 100KHz T A =+25 °C-10-µV/Vo Ripple Rejection RR f = 120Hz, I O = 500mA V I = 18.5V to 28.5V -58-dB Dropout Voltage V Drop I O = 1A, T J =+25 °C - 2.0-V Output Resistance r O f = 1KHz-19-m ΩShort Circuit Current I SC V I = 35V, T A =+25 °C -250-mA Peak CurrentI PKT J =+25°C- 2.2-AMC78XX/LM78XX/MC78XXAElectrical Characteristics (MC7818A)(Refer to the test circuits. 0°C < T J < 125°C, I o =1A, V I = 27V, C I =0.33µF, C O =0.1µF, unless otherwise specified)Note:1. Load and line regulation are specified at constant junction temperature. Change in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbol ConditionsMin.Typ.Max.UnitOutput VoltageV OT J =+25 °C17.641818.36V I O = 5mA to 1A, P O ≤15W V I = 21V to 33V 17.31818.7Line Regulation (Note1)ReglineV I = 21V to 33V I O = 500mA-15180mV V I = 21V to 33V -5180 T J =+25 °CV I = 20.6V to 33V -15180 V I = 24V to 30V-590Load Regulation (Note1)RegloadT J =+25°CI O = 5mA to 1.5A -15100mV I O = 5mA to 1.0A -15100 I O = 250mA to 750mA -750Quiescent Current I Q T J =+25 °C- 5.2 6.0mA Quiescent Current Change ∆I QV I = 21V to 33V, T J =+25 °C --0.8mA V I = 21V to 33V, I O = 500mA --0.8 I O = 5mA to 1.0A--0.5Output Voltage Drift ∆V/∆T I O = 5mA --1.0-mV/ °C Output Noise Voltage V N f = 10Hz to 100KHz T A =+25°C-10-µV/Vo Ripple Rejection RR f = 120Hz, I O = 500mA V I = 22V to 32V -57-dB Dropout Voltage V Drop I O = 1A, T J =+25°C - 2.0-V Output Resistance r O f = 1KHz-19-m ΩShort Circuit Current I SC V I = 35V, T A =+25°C -250-mA Peak CurrentI PKT J =+25 °C- 2.2-AMC78XX/LM78XX/MC78XXAElectrical Characteristics (MC7824A)(Refer to the test circuits. 0°C < T J < 125°C, I o =1A, V I = 33V, C I =0.33µF, C O =0.1µF, unless otherwise specified)Note:1. Load and line regulation are specified at constant junction temperature. Change in VO due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbol ConditionsMin.Typ.Max.UnitOutput VoltageV OT J =+25 °C23.52424.5V I O = 5mA to 1A, P O ≤15W V I = 27.3V to 38V 232425Line Regulation (Note1)ReglineV I = 27V to 38V I O = 500mA-18240mV V I = 21V to 33V -6240 T J =+25 °CV I = 26.7V to 38V -18240 V I = 30V to 36V-6120Load Regulation (Note1)RegloadT J =+25 °CI O = 5mA to 1.5A -15100mV I O = 5mA to 1.0A -15100 I O = 250mA to 750mA -750Quiescent Current I Q T J =+25 °C- 5.2 6.0mA Quiescent Current Change ∆I QV I = 27.3V to 38V, T J =+25 °C --0.8mA V I = 27.3V to 38V, I O = 500mA --0.8 I O = 5mA to 1.0A--0.5Output Voltage Drift ∆V/∆T I O = 5mA --1.5-mV/ °C Output Noise Voltage V N f = 10Hz to 100KHz T A = 25 °C-10-µV/Vo Ripple Rejection RR f = 120Hz, I O = 500mA V I = 28V to 38V -54-dB Dropout Voltage V Drop I O = 1A, T J =+25 °C - 2.0-V Output Resistance r O f = 1KHz-20-m ΩShort Circuit Current I SC V I = 35V, T A =+25 °C -250-mA Peak CurrentI PKT J =+25 °C- 2.2-AMC78XX/LM78XX/MC78XXATypical Perfomance CharacteristicsFigure 1.Quiescent Current Figure 3.Output Voltage Figure 2.Peak Output Current Figure 4.Quiescent CurrentI21Typical ApplicationsFigure 5.DC ParametersFigure 6.Load RegulationFigure 7.Ripple RejectionFigure 8.Fixed Output RegulatorInputOutputMC78XX/LM78XXInputOutputMC78XX/LM78XXInputOutputMC78XX/LM78XXInputOutputMC78XX/LM78XX22Figure 9.Constant Current RegulatorNotes :(1)To specify an output voltage. substitute voltage value for "XX." A common ground is required between the input and theOutput voltage. The input voltage must remain typically 2.0V above the output voltage even during the low point on the input ripple voltage.(2)C I is required if regulator is located an appreciable distance from power Supply filter.(3)C O improves stability and transient response.V O = V XX (1+R 2/R 1)+I Q R 2Figure 10.Circuit for Increasing Output VoltageI RI ≥5 I QV O = V XX (1+R 2/R 1)+I Q R 2Figure 11.Adjustable Output Regulator (7 to 30V)InputOutputMC78XX/LM78XX CICoInput OutputMC78XX/LM78XXCICoI RI 5IQ≥InputOutputMC7805LM7805LM741CoCI23Figure 12.High Current Voltage RegulatorFigure 13.High Output Current with Short Circuit ProtectionFigure 14.Tracking Voltage RegulatorInputOutputMC78XX/LM78XXInputOutputMC78XX/LM78XXMC78XX/LM78XXLM741MC7815MC7915Figure 15.Split Power Supply ( ±15V-1A)OutputInputMC78XX/LM78XXFigure 16.Negative Output Voltage CircuitInput OutputMC78XX/LM78XXFigure 17.Switching Regulator24Mechanical DimensionsPackageTO-22025Mechancal Dimensions (Continued)PackageD-PAK26。
MC145026中文资料
R1, C1Resistor 1, Capacitor 1 (Pins 6, 7)As shown in Figures 2 and 3, these pins accept a resistor and capacitor that are used to determine whether a narrow pulse or wide pulse has been received. The time constant R1 x C1 should be set to 1.72 encoder clock periods:R1 C1 = 3.95 R TC C TCR2/C2Resistor 2/Capacitor 2 (Pin 10)As shown in Figures 2 and 3, this pin accepts a resistor and capacitor that are used to detect both the end of a received word and the end of a transmission. The time constant R2 x C2 should be 33.5 encoder clock periods (four data periods per Figure 11): R2 C2 = 77 R TC C TC. This time constant is used to determine whether the D in pin has remained low for four data periods (end of transmission). A separate on–chip comparator looks at the voltage–equivalent two data periods (0.4 R2 C2) to detect the dead time between received words within a transmission.VTValid Transmission Output (Pin 11)This valid transmission output goes high after the second word of an encoding sequence when the following conditions are satisfied:1.the received addresses of both words match the local de-coder address, and2.the received data bits of both words match.VT remains high until either a mismatch is received or no input signal is received for four data periods.V SSNegative Power Supply (Pin 8)The most–negative supply potential. This pin is usually ground.V DDPositive Power Supply (Pin 16)The most–positive power supply pin.MC145026•MC145027•MC145028•SC41343•SC41344MOTOROLAMC145026•MC145027•MC145028•SC41343•SC41344MOTOROLA16APPLICATIONS INFORMATIONINFRARED TRANSMITTERIn Figure 18, the MC145026 encoder is set to run at an os-cillator frequency of about 4 to 9 kHz. Thus, the time required for a complete two–word encoding sequence is about 20 to 40 ms. The data output from the encoder gates an RC oscilla-tor running at 50 kHz; the oscillator shown starts rapidly enough to be used in this application. When the “send” button is not depressed, both the MC145026 and oscillator are in a low–power standby state. The RC oscillator has to be trimmed for 50 kHz and has some drawbacks for frequency stability. A superior system uses a ceramic resonator oscilla-tor running at 400 kHz. This oscillator feeds a divider as shown in Figure 19. The unused inputs of the MC14011UB must be grounded.The MLED81 IRED is driven with the 50 kHz square wave at about 200 to 300 mA to generate the carrier. If desired, two IREDs wired in series can be used (see Application Note AN1016 for more information). The bipolar IRED switch,shown in Figure 18, offers two advantages over a FET. First,a logic FET has too much gate capacitance for the MC14011UB to drive without waveform distortion. Second,the bipolar drive permits lower supply voltages, which are an advantage in portable battery–powered applications.The configuration shown in Figure 18 operates over a supply range of 4.5 to 18 V. A low–voltage system which operates down to 2.5 V could be realized if the oscillator sec-tion of a MC74HC4060 is used in place of the MC14011UB.The data output of the MC145026 is inverted and fed to the RESET pin of the MC74HC4060. Alternately, the MC74HCU04 could be used for the oscillator.Information on the MC14011UB is in book number DL131/D. The MC74HCU04 and MC74HC4060 are found in book number DL129/D.INFRARED RECEIVERThe receiver in Figure 20 couples an IR–sensitive diode to input preamp A1, followed by band–pass amplifier A2 with a gain of about 10. Limiting stage A3 follows, with an output of about 800 mV p–p. The limited 50 kHz burst is detected by comparator A4 that passes only positive pulses, and peak–detected and filtered by a diode/RC network to extract the data envelope from the burst. Comparator A5 boosts the sig-nal to logic levels compatible with the MC145027/28 data input. The D in pin of these decoders is a standard CMOS high–impedance input which must not be allowed to float.Therefore, direct coupling from A5 to the decoder input is utilized.Shielding should be used on at least A1 and A2, with good ground and high–sensitivity circuit layout techniques applied.For operation with supplies higher than + 5 V, limiter A4’s positive output swing needs to be limited to 3 to 5 V. This is accomplished via adding a zener diode in the negative feed-back path, thus avoiding excessive system noise. The bias-ing resistor stack should be adjusted such that V3 is 1.25 to 1.5 V.This system works up to a range of about 10 meters. The gains of the system may be adjusted to suit the individual design needs. The 100 Ω resistor in the emitter of the first 2N5088 and the 1 k Ω resistor feeding A2 may be altered if different gain is required. In general, more gain does not nec-essarily result in increased range. This is due to noise floor limitations. The designer should increase transmitter power and/or increase receiver aperature with Fresnal lensing to greatly improve range. See Application Note AN1016 for additional information.Information on the MC34074 is in data book DL128/D.TRINARY SWITCH MANUFACTURERS Midland Ross–Electronic Connector Div.GreyhillAugat/Alcoswitch Aries ElectronicsThe above companies may not have the switches in a DIP .For more information, call them or consult eem Electronic En-gineers Master Catalog or the Gold Book . Ask for SPDT with center OFF .Alternative: An SPST can be placed in series between a SPDT and the Encoder or Decoder to achieve trinary action.Motorola cannot recommend one supplier over another and in no way suggests that this is a complete listing of trinary switch manufacturers.。
MC14106B中文资料
MC14106B 中文资料目录元件的最大额定值 (1)MC14106B功能介绍 (1)电气特性 (3)芯片转换特性 (4)芯片应用举例 (4)应用1 按键防抖 (4)应用2 积分电路 (5)MC14106B封装信息 (6)PDIP-14封装 (6)SOIC-14封装 (7)TSSOP-14封装 (8)元件的最大额定值条件之上进行功能操作。
长期暴露在高于推荐工作条件的环境下可能会影响器件的可靠性。
表中的电压值均为对地电压。
MC14106B功能介绍MC14106B共14个引脚，其中14号引脚为VDD（+），7号引脚为VSS （-），其余引脚为输入输出引脚，1,3,5,9,11,13号引脚为输入引脚，2,4,6,8,10,12号引脚为输出引脚。
内部逻辑如图1如所示，从图1中我们可以看出，MC14106B内部共有6组相同功能施密特触发器，每组施密特触发器的逻辑如图2所示。
图1图2下面通过图3所示施密特触发器讲解其工作过程。
其工作时序如图4所示。
当输入端输入低电平（VSS）时，输出端输出高电平（V OH）。
当输入端电平变为高电平（VDD）时，输出端电平经过一小段时间后也会发生变化，变为低电平（V OL）。
当输入端电平由VDD变为VSS后，一小段时间后，输出端电平变为高电平（V OH）。
施密特触发器最重要的是以下几个参数：从输入端电平由低到高变化到50%时，至输出端电平由高到低变化变化至50%时的时间记做t PHL；从输入端电平由高到低变化到50%时，至输出端电平由低到高变化变化至50%时的时间记做t PLH。
当输出端产生下调沿时，电平从90%变化至10%所用的时间t f；当输出端产生上跳沿时，电平从10%变化至90%所用的时间t r。
这些参数主要与VDD有关，可以通过下面提供的电气特性表格查出典型值。
图3图4通过图5进一步讲解施密特触发器的工作流程。
当输入端的电平达到V T+之后，输出端电平才会发生负跳变，当输入端平超过V T+之后，即使略低于该值，输出端不会发生负跳变，直到当输入端电平低于V T-，输出端才会发生正跳变。
MC14526BCPG,MC14526BDWR2G,MC14526BDWG,MC14526BDW,MC14526BDWR2,MC14526BFG, 规格书,Datasheet 资料
high, causes the “0” output to go high. “0” (Pin 12) — The “0” (Zero) output issues a pulse one
VSS (Pin 8) — The most negative power supply potential. This pin is usually ground.
MC14526BCP AWLYYWWG
1
PDIP−16 1
P SUFFIX
CASE 648
14526B AWLYWWG
1 SOIC−16 WB DW SUFFIX 1 CASE 751G
MC14526B ALYWG
1 SOEIAJ−16 F SUFFIX 1 CASE 966
A
= Assembly Location
X
L
X
H
X
L Asynchronous preset
L
H
L
X
L Decrement inhibited
L
L
L
X
L Decrement inhibited
L
L
L
L
L No change** (inactive edge)
H
L
L
L
L No change** (inactive edge)
L
L
L
L
L Decrement**
input.
output depends on the Preset Enable input level. See the
Clock (Pin 6) — The counter decrements by one for each Function Table.
MC2716 技术规格书
CDMA2000 1xEVDO Rev. A 网络下 800MHz: 824~849MHz 1900MHz: 1850 ~ 1910 MHz 800MHz: ±300Hz 1900MHz: ±150Hz 800MHz: 23dBm~30dBm@-105.5dBm 1900MHz: 18dBm~27dBm@-105.5dBm <-50dBm@-25dBm <-61dBm ±1.0µs >0.944 ( Test 1: -25dBm/1.23MHz) -48.3dBm/1.23MHz±9.5dB (Test 2: -65dBm/1.23MHz) -8.3dBm/1.23MHz±9.5dB (Test 3: -93.5dBm/1.23MHz) 20.3dBm /1.23MHz±9.5dB -42dBc/30KHz or -54dBm/1.23MHz(|Δf|: 885KHz~1.98MHz)
42 44 38 36 22 20 14 12 10 8 49 15 18 21 26 27 29 34 35 37 40 43 50 1 3 5 6 7 11 13 17 19 16 23 25 28 30 31 32 33 45 46 47 48 49 51
信号名称 +3.3V
LED_WWAN_N LED_WLAN_N
接收灵敏度 接收信号范围 单音抗干扰度 双音互调杂散
-105.5dBm@FER=0.5% -25dBm~ -105.5dBm@FER≤0.5% FER≤1.0%(-102.4dBm/BW,-30dBm@±900KHz) FER≤1.0%(Test1: -102.4dBm/BW, +900/+1700KHz, -43dBm)
3 外观和结构
项目
MC-4516CC726资料
©1997DATA SHEETThe mark • shows major revised points.Document No. M13048EJ5V0DS00 (5th edition)Date Published September 1998 NS CP(K)Printed in JapanThe information in this document is subject to change without notice.DescriptionThe MC-4516CC726 is a 16,777,216 words by 72 bits synchronous dynamic RAM module on which 18 pieces of 64M SDRAM : µPD4564841 (Rev. E) are assembled.This module provides high density and large quantities of memory in a small space without utilizing the surface-mounting technology on the printed circuit board.Decoupling capacitors are mounted on power supply line for noise reduction.Features• 16,777,216 words by 72 bits organization (ECC type)• Clock frequency and clock access timeFamily/CAS latencyClock frequencyClock access timePower consumption (MAX.)(MAX.)(MAX.)Active Standby MC-4516CC726-A80CL = 3125 MHz 6 ns 5,184 mW 32.4 mW CL = 2100 MHz 6 ns 5,022 mW (CMOS level input )MC-4516CC726-A10CL = 3100 MHz 6 ns 5,184 mW CL = 277 MHz7 ns5,022 mW• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge • Pulsed interface• Possible to assert random column address in every cycle • Quad internal banks controlled by BA0 and BA1 (Bank Select)• Programmable burst-length : 1, 2, 4, 8 and full page • Programmable wrap sequence (sequential / interleave)• Programmable /CAS latency (2, 3)• Automatic precharge and controlled precharge • CBR (Auto) refresh and self refresh • All DQs have 10 Ω ±10 % of series resistor • Single 3.3 V ± 0.3 V power supply • LVTTL compatible • 4,096 refresh cycles/64 ms• Burst termination by Burst Stop command and Precharge command • 168-pin dual in-line memory module (Pin pitch = 1.27 mm)• Unbuffered type • Serial PD2Ordering InformationPart numberClock frequency MHz (MAX.)PackageMounted devicesMC-4516CC726F-A80125 MHz168-pin Dual In-line Memory Module (Socket Type)18 pieces of µ PD4564841G5 (Rev. E)(400 mil TSOP (II))MC-4516CC726F-A10100 MHzEdge connector : Gold plated 34.93 mm (1.375 inch) height3Pin Configuration168-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)[MC-4516CC726F]SS SS SS SS (A13)SS SS SS SS SS V V V V BA1 V V V V V A0 - A11:Address Inputs[Row : A0 - A11, Column : A0 - A8]BA0 (A13), BA1 (A12):SDRAM Bank SelectDQ0 - DQ63, CB0 - CB7:Data Inputs/OutputsCLK0 - CLK3:Clock Input CKE0, CKE1:Clock Enable Input /CS0 - /CS3:Chip Select Input /RAS :Row Address Strobe /CAS :Column Address Strobe /WE :Write EnableDQMB0 - DQMB7:DQ Mask EnableSA0 - SA2:Address Input for EEPROM SDA :Serial Data I/O for PD SCL :Clock Input for PD V CC :Power Supply V SS :Ground WP :Write ProtectNoteNC:No ConnectionNote WP is not used yet. It is connected to ground./XXX indicates active low signal.4Block DiagramCB 0CB 1CB 2CB 3CB 4CB 5CB 6CB 7SCLSDAA12: D0 - D17/CAS: D0 - D17V CC D0 - D17D0 - D17V SSA13: D0 - D17DQ 1DQ 2DQ 3DQ 4DQ 5DQ 6DQ 7DQ 0DQ 9DQ 10DQ 11DQ 12DQ 13DQ 14DQ 15DQ 8DQ 33DQ 34DQ 35DQ 36DQ 37DQ 38DQ 39DQ 32CLK0CLK2CLK1CLK3C LK : D0, D1, D2, D5, D6C LK : D9, D10, D11, D14, D15C LK : D3, D4, D7, D8C LK : D12, D13, D16, D1710 kRemarks 1.The value of all resistors is 10 Ω except CKE1 and WP.2.WP is not used yet. It is connected to ground.3.D0 - D17 : µ PD4564841 (Rev. E)(2M words × 8 bits × 4 banks)5Electrical Specifications• All voltages are referenced to V SS (GND).• After power up, wait more than 100 µs and then, execute power on sequence and auto refresh before proper device operation is achieved.Absolute Maximum RatingsParameterSymbol ConditionRating Unit Voltage on power supply pin relative to GND V CC –0.5 to +4.6V Voltage on input pin relative to GND V T –0.5 to +4.6V Short circuit output current I O 50mA Power dissipationP D 18W Operating ambient temperature T A 0 to +70°C Storage temperatureT stg–55 to +125°CCaution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.Recommended Operating ConditionsParameterSymbol ConditionMIN.TYP.MAX.Unit Supply voltage V CC 3.0 3.33.6V High level input voltage V IH 2.0V CC + 0.3V Low level input voltage V IL −0.3+0.8V Operating ambient temperatureT A70°CCapacitance (T A = 25 °C, f = 1 MHz)ParameterSymbol Test conditionMIN.TYP.MAX.Unit Input capacitanceC I1A0 - A11, BA0 (A13), BA1 (A12), /RAS,/CAS, /WE 63102pFC I2CLK0 - CLK32440C I3CKE0, CKE13456C I4/CS0 - /CS31733C I5DQMB0 - DQMB71021Data input/output capacitanceC I/ODQ0 - DQ63, CB0 - CB71119pFParameter Symbol Test condition Grade MIN.MAX.Unit Notes Operating current I CC1Burst length=1/CAS latency = 2-A80945mA1t RC ≥t RC(MIN.), I O = 0mA-A10855/CAS latency = 3-A80990-A10900Precharge standby current in I CC2P CKE ≤ V IL(MAX.), t CK =15ns18mApower down mode I CC2PS CKE ≤ V IL(MAX.), t CK =∞9Precharge standby current in non power down modeI CC2N CKE≥V IH(MIN.), t CK =15ns, /CS≥V IH(MIN.),Input signals are changed one time during 30ns.360mAI CC2NS CKE ≥ V IH(MIN.), t CK =∞Input signals are stable.108Active standby current in I CC3P CKE ≤ V IL(MAX.), t CK =15ns90mApower down mode I CC3PS CKE ≤ V IL(MAX.), t CK =∞72Active standby current in I CC3N CKE≥V IH(MIN.), t CK =15ns, /CS≥V IH(MIN.),450mAnon power down mode Input signals are changed one time during 30ns.I CC3NS CKE ≥ V IH(MIN.), t CK =∞Input signals are stable.180 Operating current I CC4t CK ≥t CK(MIN.)/CAS latency = 2-A801,170mA2 (Burst mode)I O = 0mA-A10945/CAS latency = 3-A801,350-A101,170 Refresh current I CC5t RC ≥t RC(MIN.)/CAS latency = 2-A801,395mA3-A101,395/CAS latency = 3-A801,440-A101,440 Self refresh current I CC6CKE ≤ 0.2V18mAInput leakage current I I(L)V I=0 to 3.6V,All other pins not under test =0 V–18+18µAInput leakage current (CKE1)−500+500µAOutput leakage current I O(L)D OUT is disabled, V O =0 to 3.6V–3+3µAHigh level output voltage V OH I O =–4.0mA 2.4VLow level output voltage V OL I O =+4.0mA0.4VNotes 1.I CC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, I CC1 is measured on condition that addresses are changed only one time during t CK (MIN.).2.I CC4 depends on output loading and cycle rates. Specified values are obtained with the output open. Inaddition to this, I CC4 is measured on condition that addresses are changed only one time during t CK (MIN.).3.I CC5 is measured on condition that addresses are changed only one time during t CK (MIN.).•6AC Characteristics Test Conditions•AC measurements assume t T =1ns.•Reference level for measuring timing of input signals is 1.4V. Transition times are measured between V IH and V IL.•If t T is longer than 1ns, reference level for measuring timing of input signals is V IH (MIN.) and V IL (MAX.).•An access time is measured at 1.4V.2.0 VCLK1.4 V0.8 V2.0 VInput1.4 V0.8 VOutput7Parameter Symbol-A80-A10UnitNoteMIN.MAX.MIN.MAX.Clock cycle time/CAS latency = 3t CK38(125 MHz)10(100 MHz)ns/CAS latency = 2t CK210(100 MHz)13(77 MHz)ns Access time from CLK/CAS latency = 3t AC366ns1/CAS latency = 2t AC267ns1 CLK high level width t CH33nsCLK low level width t CL33nsData-out hold time t OH33ns1 Data-out low-impedance time t LZ00nsData-out high-impedance time/CAS latency = 3t HZ33636ns/CAS latency = 2t HZ23637nsData-in setup time t DS22nsData-in hold time t DH11ns Address setup time t AS22ns Address hold time t AH11nsCKE setup time t CKS22nsCKE hold time t CKH11nsCKE setup time (Power down exit)t CKSP22ns Command (/CS0 - /CS3, /RAS, /CAS, /WE,DQMB0 - DQMB7) setup timet CMS22nsCommand (/CS0 - /CS3, /RAS, /CAS, /WE,DQMB0 - DQMB7) hold timet CMH11nsNote 1. Output loadOutput50 pF50ΩRemark These specifications are applied to the monolithic device.8Parameter Symbol-A80-A10Unit NoteMIN.MAX.MIN.MAX.REF to REF/ACT command period t RC7070nsACT to PRE command period t RAS48120,00050120,000nsPRE to ACT command period t RP2020nsDelay time ACT to READ/WRITE command t RCD2020nsACT(0) to ACT(1) command period t RRD1620nsData-in to PRE command period t DPL810nsData-in to ACT(REF) command period/CAS latency = 3t DAL31CLK+201CLK+20ns(Auto precharge)/CAS latency = 2t DAL21CLK+201CLK+20nsMode register set cycle time t RSC22CLK Transition time t T0.530130nsRefresh time (4,096 refresh cycles)t REF6464ms910Serial PD(1/2)Byte No.Function DescribedHex Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Notes 0Defines the number of bytes written into serial PD memory80H 10000000128 bytes 1Total number of bytes of serial PD memory 08H 00001000256 bytes 2Fundamental memory type 04H 00000100SDRAM 3Number of rows 0CH 0000110012 rows 4Number of columns 09H 000010019 columns 5Number of banks 02H 00000010 2 banks 6Data width48H 010******* bits 7Data width (continued)00H 0000000008Voltage interface 01H 00000001LVTTL 9CL = 3 Cycle time(-A80)80H 100000008 ns (-A10)A0H 1010000010 ns 10CL =3 Access time(-A80)60H 01100000 6 ns (-A10)60H 01100000 6 ns 11DIMM configuration type 02H 00000010ECC 12Refresh rate/type 80H 10000000Normal 13SDRAMwidth08H 00001000×814Error checking SDRAM width 08H 00001000×815Minimum clock delay 01H 00000001 1 clock 16Burst length supported8FH 100011111, 2, 4, 8, F 17Number of banks on each SDRAM 04H 00000100 4 banks 18/CAS latency supported 06H 000001102, 319/CS latency supported 01H 00000001020/WE latency supported 01H 00000001021SDRAM module attributes 00H 0000000022SDRAM device attributes : General 0EH 0000111023CL = 2 Cycle time(-A80)A0H 1010000010 ns (-A10)D0H 1101000013 ns 24CL = 2 Access time(-A80)60H 01100000 6 ns (-A10)70H 011100007 ns25-2600H 00000000(-A80)14H 0001010020 ns 27t RP(MIN.)(-A10)14H 0001010020 ns 28t RRD(MIN.)(-A80)10H 0001000016 ns (-A10)14H 0001010020 ns (-A80)14H 0001010020 ns 29t RCD(MIN.)(-A10)14H 0001010020 ns 30t RAS(MIN.)(-A80)30H 0011000048 ns (-A10)32H 0011001050 ns 31Module bank density10H164M bytes11(2/2)Byte No.Function DescribedHex Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Notes32Command and address signal input setup time20H 001000002ns 33Command and address signal input hold time10H11 ns34Data signal input setup time 20H 00100000 2 ns 35Data signal input hold time10H 00010000 1 ns36-6100H 0000000062SPD revision12H 00010010 1.263Checksum for bytes 0 - 62(-A80)F2H 11110010(-A10)58H11164-71Manufacture’s JEDEC ID code 72Manufacturing location 73-90Manufacture’s P/N 91-92Revision code 93-94Manufacturing date 95-98Assembly serial number 99-125Mfg specific126Intel specification frequency 64H 01100100100 MHz127Intel specification /CAS (-A80)FFH 11111111latency support(-A10)FDH1111111Timing ChartRefer to the SYNCHORONOUS DRAM MODULE TIMING CHART Information (M13348X).•Package Drawing168 PIN DUAL IN-LINE MODULE (SOCKET TYPE)12131415CAUTION FOR HANDLING MEMORY MODULESWhen handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them.When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document.NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others.While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features.NEC devices are classified into the following three quality grades:"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application.Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronicequipment and industrial robotsSpecial: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designedfor life support)Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc.The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.Anti-radioactive design is not implemented in this product.M4 96. 5。
MC7805中文资料
3.BOARD OPERATION3.1ACF–II Operating ModeAFC–II has four operating modes. Any one of these modes can be selected using the digital code input to MODE 0 and MODE 1 using ROTARY SW. The function of each mode is as follows.(1)Normal fsc ModeThis is the mode for usual Y/C separation. It separates Y/C from the video signal that is input to the A/D converter.The coring parameter of the vertical enhancer can be set up by the digital code that is input to C0 – C3 (block level parameter), C4 – C7 (white level parameter), and D4 – D7 (noise slice level parameter). The clock is a 3.579545 MHz subcarrier input to the CLK connector; the built–in 4x PLL generates 4xfsc clock.(2)Normal 4xfsc ModeThis mode is used for Y/C separation. It separates Y/C from the video signal that is input to the A/D con-verter.The coring parameter of the vertical enhancer can be set up by the digital code that is input to C0 – C3 (block level parameter), C4 – C7 (white level parameter), and D4 – D7 (noise slice level parameter). The clock is 14.31818 MHz which is a 4x subcarrier input to the CLK connector.(3)Digital Input Comb Filter ModeThis mode uses the A/D converter, filter, and D/A converter as two independent blocks. The digital data converted by the A/D converter is output on C0 – C7. Data input on D0 – D7 is processed by the ACF–II. Filtering is performed by the algorithm of ACF–II and the Y/C video is output as analog signals from Y out and C out. These two blocks can operate with input clock signals that have different frequencies or phases and can be operated independently by using the CLK(AD) for the A/D converter, and the CLK input for the D/A converter.The clock is 14.31818 MHz which is a 4x subcarrier input to the CLK connector and the CLK(AD) con-nector.(4)Digital Output Comb Filter ModeIn addition to the normal Y/C analog outputs, the MC141622EVK can provide the Y/C signals as digital luminance and chrominance signals. The digital luminance data is output on C0 – C7 and the digital chrominance data is output on D0 – D7. This digital data can be modified by other digital processing. MC141622EVK MOTOROLA 24.2Clock Generator CompoundingThe clock generator (MC1378P) provides the necessary reference oscillator and phase locks the clock to the color subcarrier by inputting the composite video signal.VC1 adjusts the horizontal VCO to synchronize the output of the burst gate (pin 5 on the MC1378P) with the input video signal. VC2 adjusts the chroma VCO for maximum amplitude output from the clock buffer (pin 1 on the MC14576).VR3 adjusts pull–in of the chroma PLL filter. This is usually fixed to the center position. VR4 selects the dc bias for the clock buffer output and is usually 2.25 V.4.3Video Amplifier AdjustmentOn the video amplifier (MC14577), the gain is adjusted by VR1. This sets the input range (3.0 Vp–p) of the A/D converter in MC141622FU.VR2 is the clamp level adjustment. This adjusts the sync tip clamping of the input video signal to the video amplifier.4.4Outside InterfaceThe outside interface should provide a composite video input signal to BNC1. The MC141622EVK pro-vides Y/C separation and outputs the luminance from BNC2 and the color signal from BNC3. There is an S output connector on this board for easy connection to instruments having an S input connector.BNC4 and BNC5 are for the external input of each CLK and CLK(AD). However, when using these, it is necessary to modify the board pattern; i.e., cut (J5, J6).There is no filter for bandwidth limitations on this board beyond that imposed by the bandwidth limitations of the MC14577 buffer amplifier. To minimize noise resulting from excessive bandwidth, the bandwidth of input video signal should be limited to no more than one half of the clock frequency.MC141622EVK MOTOROLA 4MC141622EVK MOTOROLA66.MC141622EVK PARTS LISTReference Designation Description IC1MC141622FU IC2MC14576CP IC3MC14577CP IC4MC7805CT IC5MC14576CP IC6MC1378P TR12SC2002TR22SC2002TR32SA953R19.1 k ΩR262 k ΩR3, R475 ΩR5 3.6 k ΩR6750 k ΩR7, R8 2.0 k ΩR9510 ΩR10150 ΩR11510 k ΩR12, R13 2.2 k ΩR1447 k Ω x 4R1547 k Ω x 8R1610 k Ω x 8R1747 k Ω x 8R1810 k Ω x 8R19, R2010 k Ω x 4R21200 ΩR22 1.8 k ΩR23680 ΩR24750 k ΩR25 2.2 k ΩR267.5 m ΩR27 1.0 m ΩR28150 ΩR29470 k ΩL1 – L933 µH L10 4.7 µH L1133 µH VR1 1 k ΩVR2 2.2 k ΩVR3 1 k ΩVR4 1 m ΩVC1, VC230 pF SW1, SW2Toggle Switch DIP SW1, DIP SW28 Channel Dip Switch ROTARY SW16 Channel Switch 4 MHz Cer. Res 14.32 MHz CrystalReference Designation Description C10.1 µF C2, C347 µF C4, C5, C60.1 µF C747 µF C80.1 µF C910 µF C100.1 µF C1110 µF C120.33 µF C131.0 µF C14, C150.1 µF C1647 µF C170.1 µF C18 1.0 µF C1947 µF C20, C210.1 µF C2247 µF C230.1 µF C2447 µF C250.1 µF C2647 µF C2710 µF C280.1 µF C29, C3047 µF C310.1 µF C320.022 µF C33, C34 1.0 µF C350.1 µF C360.001 µF C3747 µF C38 – C450.1 µF C461.0 µF C47, C480.1 µF C49 – C51 1.0 µF C520.1 µF C5347 µF C540.047 µF C55 – C570.1 µF。
调制解调芯片汇总
宽带FM中频系统
MC13256
GMSK/FM/FSK等调制
混频—滤波—中频放大—滤波—限幅放大—鉴频—放大
COMS低功耗锁相环（1.2M）
CD4046有两个相ຫໍສະໝຸດ 比较器，可用于FM/FSK调制解调
带锁定检测的锁相环(19M)
CD74HC7046
有三个相位比较器，可用于FM/FSK调制解调
通用高频（50M）锁相环
NE564
FM和FSK的调制和解调
低功耗音频解码器
LMC567
ASK解调（含PLL）
SONY低压FM中频放大器
CXA1184
传呼机系统中频放大，FM接收
传呼机FM中频侦测芯片
TA31142
FM二次变频接收
芯片类型
芯片型号
功能电路
乘法器
MC1496/MC1596
AM、DSB、SSB调制，同步检波，混频、倍频电路
XCC
同上
AD835
压控放大器，AM、DSB调制，倍频，混频
低功耗窄带FM中频接收芯片
MC3361
FM中频接收：(混频—滤波—中频限幅放大—鉴频—音频放大)
FM通信接收器
MC13135
窄带FM接收：（一级混频—滤波—二级混频—滤波—限幅—鉴频—放大）
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FM O
Parameter Peak reverse voltage DC reverse voltage Peak forward current Average rectification current Surge current(10msec)
Total allowance dissipation(Ta=25℃)
Ratings 75 50 300 100 4 125 ＋150 -55～＋150
Hale Waihona Puke Unit V V mA mA A mW ℃ ℃ ① ② ① ② D1 ③ D2 内 部 接 続 図 マ ー キ ③ ン グ 図
FSM
PT Tj Tstg
Junction temperature Storage temperature
OUTLINE DRAWING
Unit：ｍｍ
FEATURE
● Small pin capacitance ● Quick switching time 0.5 0.1 ●High voltage ●Series connected two elements ●Good two element characteristics ● Double and super mini package for mounting 0～0.1 0.7
ELECTRICAL CHARACTERISTICS（Ta=25℃）
Parameter Symbol VF1 Forward voltage VF2 VF3 Reverse current Pin capacitance Reverse recovery time IR1 CT trr I F=10mA I F=50mA I F=100mA VR=50V VR=0V，f=1MHz Test conditions Limits Min Typ 0.77 0.90 0.95 2.8 ― Max 0.9 1.0 1.2 0.1 4.0 4.0 μA pF ns V Unit
Ａ 4
ISAHAYA ELECTRONICS CORPORATION
元器件交易网
〈SMALL-SIGNAL DIODE〉
MC2856
FOR HIGH SPEED SWITCHING APPLICATION SILICON EPITAXIAL TYPE(SERIES TYPE)
0.5
APPLICATION
For general high speed switching of audio machine,VCR.
JEITA：SC-90 TERMINAL CONNECTER ①：CATHODE1 ②：CATHODE2 ③： ANODE(COMMON)
Note) The dimension without tolerance represent central value. MAXIMUM RATINGS（Ta=25℃）
元器件交易网
〈SMALL-SIGNAL DIODE〉
MC2856
FOR HIGH SPEED SWITCHING APPLICATION SILICON EPITAXIAL TYPE(COMMON ANODE) DESCRIPTION
MC2856 is a super mini package plastic seal type silicon epitaxial type double diode,especially designed for high speed switching application. Due to the small pin capacitance,short switching time(reverse recovery 0.5 ① ② ③ 0.3 time),It is most suitable for high speed switching application and 1.6 1.0 limitter,clipper application. 0.4 1.6 0.8 0.4
Jan.2003
ISAHAYA ELECTRONICS CORPORATION
元器件交易网
Marketing division, Marketing planning department
6-41 Tsukuba, Isahaya, Nagasaki, 854-0065 Japan
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