Cadence+SILICON+DESIGN+CHAIN+EXTENDS+LOW+POWER+DESIGN+COLLABORATION

WHITE PAPERSILICON DESIGN CHAIN EXTENDS LOW POWER DESIGN COLLABORATIONTABLE OF CONTENTSIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Tackling the low power problem: phase I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Exploring additional power management options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5TABLE OF FIGURESFigure 1Supply voltage versus delay for a buffer in 90nm technology . . . . . . . . . . . . . . . . . . . . . . . . . .3 Figure 2Low power design impact on timing slack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51INTRODUCTIONThe global electronics industry was once characterized by neatly stacked vertical companies. For example, ASIC vendors historically created their own process-specific libraries, developed their own design tools and sign-off methodologies, and operated their own foundries. That all changed over the last decade, a period in which many of these companies spun out large parts of their businesses and divested themselves of ever more expensive manufacturing capacity. The result is the current industry landscape—a horizontal network of design chain suppliers spread around the globe. For a time, this disaggregation brought desired business efficiencies, but with the advent of nanometer process nodes, cracks inevitably beganto appear in IC design supply chain. Whereas above 130-nanometer companies could afford to ignore many second- and third-order effects such as noise and crosstalk, today’s designs require deeper collaboration among the various industry players in order to overcome the effects of physics—especially on signal integrity, dynamic and leakage power consumption, and manufacturability.Recognizing this need to cooperate more closely on nanometer design issues, industry leaders Applied Materials, ARM, Cadence and TSMC formed the Silicon Design Chain (SDC) Initiative. Combining their expertise, these companies have established a charter to drive programs designed to address the top issues facing their customers as they adopt advanced process technologies.In 2004, members of the SDC identified power management as the most critical design consideration for high-performance wired devices due to leakage issues and potentially expensive cooling and packaging costs, as well as lower reliability associated with high levels of on-chip power dissipation. During the following year and one half, the SDC member companies executed the first phase of an ongoing collaborative project to address the problem of power management. In this first phase, understanding that the introduction of new design techniques must be managed step by step to ensure success, the team chose to focus on using four power-lowering techniques: automatic multi-threshold leakage-performance optimization, static voltage scaling, clock gating and a new accurate delay prediction methodology that works across multiple voltage domains. The result was a design approach that dramatically reduced both dynamic and leakage power. The SDC team validated this low power solution in silicon with the successful implementation of a chip based on the ARM1136JF-S™processor module. The device, aimed at mobileand wireless applications, yielded a greater than 40% savings in power consumption.Phase I of the low power initiative, focused on several of the most obvious methods for power management. In Phase II, ARM and Cadence are working on a additional methods to attack leakage more aggressively. For example, to lower leakage or dynamic power in circuits, the best approach involves shutting down circuitry when it is not being used. This technique is called power gating. Another approach to lowering dynamic power consumption involves intelligently lowering the operating frequency of the circuit when high clock speeds are not required by the function the circuit needs to perform. This approach is termed dynamic voltage scaling because the device will have multiple operating frequencies. Both of these techniques will be fully explored in phase II along with the need to address test and formal verification for low power circuits.2TACKLING THE LOW POWER PROBLEM: PHASE IIn implementing the first proof point project, the team used a number of innovative techniques to achieve a successful low power design. For dynamic power reduction, they employed two new methodologies—voltage scaling and clock gating—both key technologies supported in the TSMC Reference Flow 6.0.Voltage scaling means partitioning the IC as a multi-supply voltage (MSV) design, which isolates parts of the chip into islands that are designed to operate at different supply voltages based on their respective timing characteristics. By aggregating the less critical operations into islands that had the voltage scaled down to 0.8V, the team was able to save 36% of the dynamic power for that portion of the design.The team achieved additional dynamic power reduction via clock gating, which involves using a gating circuit to shut off the clock for registers where the data is loaded only infrequently (but where the clock signal would continue to switch at every clock cycle and thereby drive capacitance load). Clock gating can achieve a 10 to 29% dynamic power savings. Cadence Encounter RTL Compiler can automate clock gating by automatically optimizing the integration of clock-gating cells from the ARM standard cell library (partof its family of Artisan®physical IP). Using this approach, the team was able to gate 85% of the registers in the low power chip. This combination of voltage scaling and clock gating resulted in a 38% decrease in dynamic power consumption.Since the chip’s 90-nanometer process meant static power dissipation could account for as much as 50% of the overall power consumed, the team next attacked leakage power. They used the ARM standard cell libraries that contain a matched set of logic cells, each having different threshold voltages (Vt) and the same physical footprint. The cells with the higher threshold voltage leak less, but run slower, than their counterpart cells with lower threshold voltages. These cells utilize TSMC transistors that are designed specifically to allow designers to make performance versus. leakage trade-offs to meet their design goals. As recommended in the TSMC Reference Flow 6.0, RTL Compiler achieved an optimal mix of high- andlow-Vt cells during synthesis, which resulted in a netlist implementation that met performance goals at the lowest possible level of leakage current. After place-and-route, the design was then tuned to provide the final optimization that accounted for the actual wires. Using this improved static power reduction methodology, the Silicon Design Chain design team achieved a 46.7% savings in leakage power.Once power was optimized, the team needed to perform analysis and verification of the low power design. Using multiple power supplies within the chip complicated the timing analysis step because the tools needed to achieve have accurate delay models for each operating voltage when computing the timing. Proper modeling for level-shifter and clamp cells was also needed to compute the delays correctly. Using the effective current source model (ECSM) helped the team solve these issues at 90 nanometers. Accuracy was also a primary concern during sign-off, because IR drop effects on timing are accentuatedat the lower supply voltages that were used in the MSV design. Leveraging the TSMC Reference Flow 6.0, the SDC team relied on Cadence VoltageStorm and Cadence CeltIC NDC to analyze the IR drop across the 1.0V and 0.8V power grids, and the resultant voltages were input into the ECSM-based delay calculator in CeltIC NDC (SignalStorm) to provide near-SPICE accurate timing across the two supply voltage regions.3EXPLORING ADDITIONAL POWER MANAGEMENT OPTIONSWhile phase I was an excellent start to addressing power management, there are additional opportunities to attack leakage current more aggressively through careful planning of operational and sleep modes. As transistor counts continue to rise and 90- and 65-nanometer processes proliferate, power management is becoming one of the most critical concerns for design teams. Because at 90nm and below, the physics of silicon—which for decades allowed chips to be scaled with a corresponding increase in speed and reduction in power consumption—begin to work against conventional engineering, especially in the area of leakage power. For example, Intel recently announced that to achieve the performance increase needed for its next-generation processor, it would switch to a dual-core architecture, rather than trying to drive up frequency on a single core architecture. The leakage problem was too hard to solve. Similarly, within a week of Intel’s announcement, Texas Instruments announced its SmartReflex™technology that analyzes and manages power consumption in the processor domain, while adaptively controlling the power supply through software to optimize the use of battery power.The techniques for managing power dissipation will vary with the type of device. In products where performance is the paramount concern, such as gaming or graphics processors, managing leakage power becomes a significant challenge. Also, multi-function electronics products create new issues. The latest handheld organizer might, for example, let you check your calendar and email and allow you to watcha video. These massively complex devices require radically different operating frequencies, dependingon the function the device is performing. In designs such as these, engineers would want to employ one power management technique to handle varying performance requirements as well as another technique to shut some circuitry off completely when you don't need it.In addition, while essential for creating successful products, implementing power management techniques introduces new challenges for design, test and verification tools. This added complexity—coupled with issues such as narrower margins associated with lower swing voltages in individual gates—creates new complexities in test and verification.3.1NEW TECHNIQUES FOR POWER MANAGEMENT AND LOW POWER TEST AND VERIFICATIONSDC members ARM and Cadence are continuing their work on reducing power consumption. The teamis expanding its successful low power methodology by exploring the next set of integrated power management capabilities. The first new area of investigation involves crafting an optimized approach for implementing reliable and robust power shut-down and start-up sequences, which is augmented with a state retention capability for the powered down circuitry. The second area of focus is to create dynamic voltage and frequency scaling procedures that can be used to intelligently lower power consumption based upon need. Meanwhile, new cells to support variable operating voltages and power shifting circuitry all pose new challenges for formal verification as well as for accepted design-for-test (DFT) approaches. Both formal verification and DFT must be upgraded to deal with low power design techniques and will be addressed as part of a comprehensive power management methodology.Figure 1. Supply voltage versus delay for a buffer in 90nm technology3.2POWER GATINGThe best way to reduce power is to shut it off. Power gating is a technique that can dramaticallyreduce leakage power, which involves shutting down an entire region or whole sub-block of an IC. This enables design teams to save power by turning off circuitry for functions of a device that are not active, such as when someone is using a cell phone’s built-in camera function but not making a phone call at the same time.While the concept is simple, the challenge lies in the implementation—i.e., knowing where to insert power gates and how to connect the switches, and creating the myriad of electrical connections required to actually perform the shut down. Powering up and ramping down these areas also requires carefully planned transition cycle circuitry to prevent current spikes that could damage the device. Designers must anticipate and simulate numerous scenarios to understand power savings achieved during power down versus the switching power required during ramp up. Without this careful analysis, the design might waste as much power in the transition as it saves by shutting the power down.It is also important to consider minimum states of the logic block that need to be preserved for faster wake up. Preserving the logic state, involves saving critical information into a memory function that is maintained during the power-down cycle.To speed the turnaround time of analysis and implementation, the Low power Initiative uses the Cadence Encounter digital IC design platform to provide a domain-aware infrastructure. This infrastructure employs a system-level understanding of where to add power gates and how and when to control gates for an optimal reduction of leakage power. To take advantage of this automated feature, logic designers opportunistically partition their chips so that voltage can be varied or shut down on different subdivisions of the chip based upon knowledge of which operations are running on that portion of the circuit. RTLCompiler synthesis technology recognizes different power domains and inserts isolation cells and retention registers where needed. Using intelligent architectural partitioning and Encounter’s automated power techniques, designers are able to minimize leakage and dynamic power consumption across their design. The Cadence Encounter platform is further utilized to automatically insert power switches, and place and route power domain blocks. It also enables optimization of switch size based on electrical characteristics. Finally, timing and signal integrity analysis is performed to account for additional IR drop in switches and delays occurring through isolation cells and to control signal-to-noise characteristics.The SDC’s focus is to validate interdependent technology from each member company. For power gating, key components of the ARM Power Management Kit facilitate an automated power management flow:• Power gates that control voltage islands via switchable voltage rails using header or footer cells• Level shifters and isolation cells that enable up and down voltage shift with an optional enable signal • Always-on-buffers—buffer signals in powered-down regionsThe ARM technology-based solutions work in concert with the Encounter platform’s synthesis, placement and analysis capabilities. This combination ensures optimal power, frequency and signal integrity throughout the design process.Cadence technology leverages detailed cell characterization data that is contained in the ARM physical IP models. This data is used to perform timing and signal integrity analysis to account for additional IR drop in switches and delays occurring through isolation cells and to control signal-to-noise characteristics.3.3DYNAMIC VOLTAGE AND FREQUENCY SCALINGOperating at higher frequencies consumes more dynamic power. Dynamic voltage and frequency scaling (DVFS) is a power saving technique that allows design teams to make fine-granularity trade-offs between power consumption and performance by dynamically lowering the voltage in individual frequency domains.In practice, this technique requires using slower clocks that consume less power and using embedded software to dynamically scale the voltage in these blocks depending on the function the device is performing—e.g., whether a music player is in standby mode or playing an MP3 file. One of the key challenges of this approach is considering all the scenarios in advance and optimizing the design to achieve the best balance of power and performance for each operating condition. ARM and Cadence teams are working to simplify this task by developing design IP and Encounter platform technology and methodologies to automate the optimization process. Specifically, ARM and Cadence are collaborating to prove the system-level implementation of the new ARM technology for DVFS and power shutdown, which uses algorithms to intelligently achieve the lowest voltage on a frequency pair necessary to meet the minimum performance required for a specific operation. The new ARM Artisan advanced specialized cells for low power designs are a key enabling technology for this robust power-lowering approach.3.4LOW POWER TESTThere is no silver bullet for conquering power issues in nanometer designs. Depending on product requirements, each design team will need to a use a mix of the techniques proved in both phases of the low power project. Adding advanced power management to the design, however, adds operating modes and thereby increases test complexity. This creates a problem regarding how to manage coverage of all the different modes in the least number of patterns.In addition, low power design techniques dramatically increase timing criticality, because a properly optimized design would have traded all the available timing slack for power reduction. As shown in Figure 2, the timing criticality profile of the test chip shifts toward the left of the graph as morelow power techniques are used in the design. As a result, the majority of paths in a low power designwill become timing critical. Thus, identifying delay defects becomes a very important part of thetest strategy.Figure 2. low power design impact on timing slackThe SDC team is working with the Cadence Encounter platform technology to enhance and automate front-end DFT and test diagnostics, which includes design planning and implementation as well as development of very accurate delay path tests. Among the most significant results of this approach is coverage for virtually all of the real timing paths.3.5LOW POWER VERIFICATIONlow power designs require equivalence checking and other advanced verification techniques. SDC team addresses these issues by applying newly added Encounter platform technologies. Encounter Conformal provides a low power equivalence-checking capability with functional checks for advanced low power design. This capability ensures that low power optimizations do not introduce logical errors in the design. Encounter Conformal also performs state-retention register-mapping checks, verifies level-shifter insertion between different voltage islands, and verifies power connectivity and power switching in power-gated designs. In addition, Encounter formally validates power control, logic isolation, and state-retention functions in power-gated designs.4CONCLUSIONThe need to save power while maintaining performance goals at 90 and 65 nanometers creates challenges in design and test that necessitate deep collaboration among key members of the design chain—foundries, EDA companies, and IP suppliers. In the second phase of the power management methodology, ARM and Cadence are working together to validate interdependent technology for low power design. Meanwhile, a shared knowledge of design requirements, up and down the design chain, helps to ensure that the design can be reliably manufactured. This type of close collaboration enables the SDC team to validate, through proof point projects, important new techniques in power management, DFT, and low power formal verification.Cadence Design Systems, Inc.Corporate Headquarters2655 Seely AvenueSan Jose, CA 95134800.746.6223408.943.1234© 2006 Cadence Design Systems, Inc. All rights reserved. Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. All others are propertiesof their respective holders.6657 01/06。