CXA2089中文资料

DescriptionThe CXA2089Q/S is a 5-input, 2-output audio/video switch featuring I 2C bus compatibility for TVs. This IC has input pins that are compatible with S2 protocol.Features•3 inputs that are compatible with S2 protocol •Serial control with I 2C bus •5 inputs, 2 outputs•The desired inputs can be selected independently for each of the 2 outputs•Wide band video amplifier (20MHz, –3dB)•Y/C MIX circuit•Slave address can be changed (90H/92H)•Audio muting from external pin•High impedance maintained by I 2C bus lines (SDA,SCL) even when power is OFF•Wide audio dynamic range (3Vrms typ.)ApplicationsAudio/video switch featuring I 2C bus compatibility for TVsStructureBipolar silicon monolithic ICAbsolute Maximum Ratings •Supply voltage V CC 12V •Operating temperature Topr –20 to +75°C •Storage temperature Tstg –65 to +150°C •Allowable power dissipationP D 1500mWOperating Conditions Supply voltage9 ±0.5VCXA2089Q/SS2-Compatible 5-Input 2-Output Audio/Video SwitchSony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.CXA2089Q 48 pin QFP (Plastic)CXA2089S48 pin SDIP (Plastic)Block Diagram CXA2089QVOUT1YOUT1TV V4V3V2V1Y3Y2Y1C3C2C1YIN1TRAP1GNDCOUT1CIN1VOUT2YOUT2COUT2BIAS V CC ADR SDA SCL DC OUTMUTES-3S2-1LTV LV4S-2S-1S2-3S2-2LV3LV2LV1LOUT1ROUT1LOUT2ROUT2RTV RV4RV3RV2RV1Audio system is attenuated by 6dB for 6k Ωresistor input, and a total gain is 0dB (LOUT1 and ROUT1 can be changed to –6dB).CXA2089SVOUT1YOUT1TV V4V3V2V1Y3Y2Y1C3C2C1YIN1TRAP1GNDCOUT1CIN1VOUT2YOUT2COUT2BIAS V CCADR SDA SCL DC OUT MUTES-3S2-1LTV LV4S-2S-1S2-3S2-2LV3LV2LV1LOUT1ROUT1LOUT2ROUT2RTV RV4RV3RV2RV1Audio system is attenuated by 6dB for 6k Ωresistor input, and a total gain is 0dB (LOUT1 and ROUT1 can be changed to –6dB).BIAS CIN1LOUT1VOUT1ROUT1TRAP1YOUT1GND COUT1LTV TV RTV RV4V4LV4S-3S2-3C3RV3Y3LV3V3S-2S2-2Y I N 1M U T EV C CV O U T 2R O U T 2Y O U T 2L O U T 2C O U T 2D C O U TS D AS C L A D RV 1L V 1Y 1R V 1C 1S 2-1S -1V 2L V 2Y 2R V 2C 2Pin ConfigurationCXA2089QB I A SC I N 1L O U T 1V O U T 1R O U T 1T R A P 1Y O U T 1G N DC O U T 1L T VT VR T VR V 4V 4L V 4S -3S 2-3C 3R V 3Y 3L V 3V 3S -2S 2-2Y I N 1M U T EV C CV O U T 2R O U T 2Y O U T 2L O U T 2C O U T 2D C O U TS D AS C LA D RV 1L V 1Y 1R V 1C 1S 2-1S -1V 2L V 2Y 2R V 2C 2CXA2089SPin Description Pin numbers in brackets are for the CXA2089S.Electrical Characteristics(Ta = 25°C, V CC= 9V) ItemCurrent consumption I CC No signal, no load304562mASymbol Conditions Min.Typ.Max.Unit Video system(Measurement circuit; Fig. 1)GainFrequency response characteristics Frequency response characteristics(Y/C mix)Input dynamic range Cross talk GVvFBWv1FBWv2DdvVctvf = 100kHz, 0.3Vp-p inputf = 100kHz, input frequency whereoutput amplitude is –3dB with 0.3Vp-poutput serving as 0dBf = 100kHz,maximum with distortion < 1.0%f = 4.43MHz, 1Vp-p input5.915101.4—6.42015——6.9———–50dBMHzMHzVp-pdBAudio system(Measurement circuits; Fig. 2 to Fig. 5)GainFrequency response characteristicsTotal harmonic distortionInput dynamic range Cross talkRipple rejection ratio Output DC offset Residual noiseS/N ratio GV AFBW ATHDDd AVct AVct AVoffVN AS/Nf = 1kHz, 1Vp-p input,5.7kΩresistor inserted to inputf = 1kHz, input frequency whereoutput amplitude is –3dB with 1Vp-poutput serving as 0dBf=1kHz, 2.2Vp-p input, where 400HzHPF + 80kHz LPF are insertedf=1kHz, maximum with distortion < 0.3%f=1kHz, 1Vp-p inputf=100Hz, 0.3Vp-p applied to VccOffset voltage between input andoutputWhen 400Hz HPF+ 30kHz LPF areinsertedf=1kHz, 1Vrms inputWhen 400Hz HPF + 30kHz LPF areinserted–150—2.8——–30—0.033.0–90–55—20–1001—0.05—–80–403030–90dBkHz%VrmsdBdBmVµVrmsdBHigh level input voltageLow level input voltageLow level output voltageHigh level input currentLow level input currentMaximum clock frequencyMinimum waiting time for data changeMinimum waiting time for data transfer startLow level clock pulse widthHigh level clock pulse widthMinimum waiting time for start preparation Minimum data hold time Minimum data preparation timeRise timeFall timeMinimum waiting time for stop preparation V IHV ILV OLI IHI ILf SCLt BUFt HD;STAt LOWt HIGHt SU;STAt HD;DATt SU;DATt Rt Ft SU;STOWith SDA 3mA current suppliedV IH= 4.5VV IL= 0.4V3.04.74.04.74.04.7150——4.7————————————————5.01.50.41010100———————1300—VVVµAµAkHzµsµsµsµsµsnsnsµsnsµsLogic systemItem Symbol Conditions Min.Typ.Max.UnitF i g . 1-a . V i d e o s y s t e m (g a i n , f r e q u e n c y r e s p o n s e c h a r a c t e r i s t i c s , i n p u t d y n a m i c r a n g e , c r o s s t a l k ) m e a s u r e m e n t c i r c u i t (C X A 2089Q )O u t p u t s i g n a l i s m e a s u r e d f r o m o n e o f t h e f o l l o w i n g p i n s : 29, 31, 33, 40, 43 a n d 45.E l e c t r i c a l C h a r a c t e r i s t i c s M e a s u r e m e n t C i r c u i ts i g n a lM e a s u r F i g . 1-b . V i d e o s y s t e m (g a i n , f r e q u e n c y r e s p o n s e c h a r a c t e r i s t i c s , i n p u t d y n a m i c r a n g e , c r o s s t a l k ) m e a s u r e m e n t c i r c u i t (C X A 2089S )M e a s u r e m e n t p o i n tF i g . 2-a . A u d i o s y s t e m (g a i n , f r e q u e n c y r e s p o n s e c h a r a c t e r i s t i c s , t o t a l h a r m o n i c d i s t o r t i o n , i n p u t d y n a m i c r a n g e , c r o s s t a l k ) m e a s u r e m e n t c i r c u i t (C X A 2089Q )O u t p u t s i g n a l i s m e a s u r e d f r o m o n e o f t h e f o l l o w i n g p i n s : 30, 32, 39 a n d 41.s i g n a lM e a s u F i g . 2-b . A u d i o s y s t e m (g a i n , f r e q u e n c y r e s p o n s e c h a r a c t e r i s t i c s , t o t a l h a r m o n i c d i s t o r t i o n , i n p u t d y n a m i c r a n g e , c r o s s t a l k ) m e a s u r e m e n t c i r c u i t (C X A 2089S )F i g . 3-a . A u d i o s y s t e m (r i p p l e r e j e c t i o n r a t i o ) m e a s u r e m e n t c i r c u i t (C X A 2089Q )A f =100H z , 0.3V p -p s i g n a l i s a p p l i e d t o V c c a n d t h e o u t p u t s i g n a l s f r o m P i n s 30, 32, 39 a n d 41 a r e m e a s u r e d .A f =100H z , 0.3V p -p s i g n a l i s a p p l i e d t o V c c a n d t h e o u t p u t s i g n a l s f r o m P i n s 36, 38, 45 a n d 47 a r e m e a s u r e d .M e a s u r F i g . 3-b . A u d i o s y s t e m (r i p p l e r e j e c t i o n r a t i o ) m e a s u r e m e n t c i r c u i t (C X A 2089S )M e a s u r e m e n t F i g . 4-a . A u d i o s y s t e m (o u t p u t D C o f f s e t v o l t a g e ) m e a s u r e m e n t c i r c u i t (C X A 2089Q )M e a s u r r e m e n t p o i n tF i g . 4-b . A u d i o s y s t e m (o u t p u t D C o f f s e t v o l t a g e ) m e a s u r e m e n t c i r c u i t (C X A 2089S )F i g . 5-a . A u d i o s y s t e m (r e s i d u a l n o i s e ) m e a s u r e m e n t c i r c u i t (C X A 2089Q )M e a s u r F i g . 5-B . A u d i o s y s t e m (r e s i d u a l n o i s e ) m e a s u r e m e n t c i r c u i t (C X A 2089S )I 2C BUS Control SignalSCLSDAFig. 6. I 2C BUS Control Signal Timing ChartDescription of OperationThe CXA2089Q/S is a TV I 2C bus-compatible AV switch IC. The video system and the stereo audio system both have 5 inputs and 2 outputs each. 3 of the 5 video system inputs support S2 and S protocols.The desired inputs can be independently assigned to each output (in the audio system, the left and right channels are processed as one unit) by I 2C bus control. However, the same input is assigned to both the video and audio system output 2.I 2C BUS Registers 1) I 2C BUSThe I 2C bus (inter-IC bus) is an inter-IC bus system developed by Philips. Two lines (SDA – serial data, SCL –serial clock) provide control over start, stop, data transfer, synchronization, and collision avoidance. The IC outputs are either open collector or open drain, forming a bus line in the wired OR format.SCLSDAS: Start condition; SDA is set "Low" when SCL is "High"P: Stop condition; SDA is set "High" when SCL is "High"A: Acknowledge; signal sent from the slaveData is transmitted by MSB-first. One data unit consists of 8 bits, to which the acknowledge signal, which indicates that the data has been accepted by the slave, is attached at the end. Normally, the slave ∗1IC receives data at the rising edge of SCL and the master ∗2IC changes data at the falling edge of SCL.∗1Slave:An IC that is placed under the control of the master. In a normal system, all devices excluding thecentral microcomputer are slaves.∗2Master: A central microcomputer or other controlling IC.2) Control RegistersThe CXA2089Q/S control is exercised by writing 2-byte data into the two 8-bit control registers which control the output selector circuits for the 2 outputs.S Slave address A DATA1A DATA2A PS: Start conditionA: AcknowledgeP: Stop conditionControl register structure (DATA1 and DATA2)•All registers are set to "0" during IC power on.•"∗" indicates undefined.Slave add. DATA1 DATA21A-GAIN∗S/COMP1S/COMP2V-IN1AV-IN2100DC OUTADRA-IN1R/W b7b6b5b4b3b2b1b0∗R/W (1): Read/write mode0: Control data write1: Status register readADR (1): This bit sets the slave address set by the address pin.0: 90H1: 92HA-GAIN (1): LOUT1/ROUT1 output gain selector0: 0dB output1: –6dB outputS/COMP1 and S/COMP2 (1 each): S terminal input/composite signal input selectorsBy setting S/COMP1 to "0", when composite signal input is selected, YOUT1/COUT1 output theinputs from YIN1/CIN1.0: Composite signal inputs (TV, V1 to V4 inputs)1: S terminal inputs (Y1/C1 to Y3/C3 inputs)V-IN1 (3 each): This bit selects the input signals output to each video output.0: Mute1: Selects the TV input2: Selects the V1 and Y1/C1 inputs3: Selects the V2 and Y2/C2 inputs4: Selects the V3 and Y3/C3 inputs5: Selects the V4 inputs6: Mute7: MuteA-IN1 (3 each): This bit selects the input signals output to each audio output.0: Mute1: Selects the LTV/RTV inputs2: Selects the LV1/RV1 inputs3: Selects the LV2/RV2 inputs4: Selects the LV3/RV3 inputs5: Selects the LV4/RV4 inputs6: Mute7: MuteAV-IN2 (3): This bit selects the input signals output to output 2 (VOUT2, YOUT2/COUT2, LOUT2/ROUT2).Note)Both the video output and the audio output are selected at the same time only for AV-IN2.0: Mute1: Selects the TV and LTV/RTV inputs2: Selects the V1, Y1/C1 and LV1/RV1 inputs3: Selects the V2, Y2/C2 and LV2/RV2 inputs4: Selects the V3, Y3/C3 and LV3/RV3 inputs5: Selects the V4 and LV4/RV4 inputs6: Mute7: MuteDC OUT (2): This bit sets the DC voltage output from DC OUT.0: 4.5V1: 0V2: 1.9V3: 4.5V3) Status Registers•When reading two bytesS Slave address A DATA1A DATA2NA P•When reading one byteS Slave address A DATA1NA PS: Start conditionA: AcknowledgeNA: No acknowledgeP: Stop conditionWhen communication is to be terminated in the status register reading mode, the no-acknowledge signal is needed to assure that the master does not issue the acknowledge signal to the slave.It is possible to read only DATA1 of the status register by sending the no-acknowledge signal after DATA1.S-C1, S-C2, S-C3 (2 each): S2-1, S2-2 and S2-3 pin status0: 4:3 video signal1: 4:3 letter-box signal2: 16:9 video squeezed signal3: No signalS-C1 to S-C3 are actually determined by comparing the S2-1 to S2-3 pin DC voltages with twothreshold. However, when the S-1 to S-3 pins are open, the outputs are fixed to "3".S2-1 to S2-3 pin DC voltage S-C1 to S-C31.3V or less1.3V or more to2.5V or less2.5V or moreS-1 to S-3 OPEN 0 1 2 3Status register structure (DATA1 and DATA2) "∗" indicates undefined.Slave add. DATA1 DATA21S1SELS1SELS2SELS2SELS3SELS3SEL∗∗0100S-C1S-C3ADRS-C2∗1 b7b6b5b4b3b2b1b0S1SEL to S3SEL (1 each): S-1 to S-3 pin status0: S-1 to S-3 pins are not grounded.1: S-1 to S-3 pins are grounded.S1SEL to S3SEL are actually determined by comparing the S-1 to S-3 pin DC voltages with 3.5V.S-1 to S-3 pin DC voltage S1SEL to S3SEL3.5V or more 3.5V or less 0 14) Power-on ResetThe CXA2089Q/S has an internal power-on reset function that sets each control register to "0" during IC power ON.The power-on reset V TH has hysteresis.Power-on resetreleasedPower-on reset4.5V5.6VV CCCXA2089Q/SV I D E O 3 i n p u tV I D E O 2 o u t p u tV I D E O 1 o u t p u T V i n p u tV I D E O 4 i n p u tA p p l i c a t i o n C i r c u i t (C X A 2089Q )•D e p e n d i n g o n t h e o u t p u t b i a s o f t h e c o m b f i l t e r s , p a y a t t e n t i o n t o t h e p o l a r i t i e s o f t h e c a p a c i t o r s s i n c e t h e b i a s a t P i n s 36 a n d 38 i s a p p r o x i m a t e l y 3.1V a n d 4.5V , r e s p e c t i v e l y .c t P i n 25 t o V c c w h e n s e t t i n g t h e s l a v e a d d r e s s I C t o 92H .u d i o o u t p u t c a n b e m u t e d b y s e t t i n g P i n 35 t o r m o r e .R A P (P i n 42) a r e o f 3.58M H z s u b c a r r i e r .t t e n t i o n t o t h e p o l a r i t i e s o f t h e c a p a c i t o r s s i n c e o u t p u t o f v i d e o s y s t e m a n d a u d i o s y s t e m h a s a l b i a s , r e s p e c t i v e l y .A p p l i c a t i o n c i r c u i t s s h o w n a r e t y p i c a l e x a m p l e s i l l u s t r a t i n g t h e o p e r a t i o n o f t h e d e v i c e s . S o n y c a n n o t a s s u m e r e s p o n s i b i l i t y f o ra n y p r ob l e m s a r i s i n g o u t o f t h e u s e o f t h e s ec i r c u i t s o r f o r a n y i n f r i n g e m e n t o f t h i rd p a r t y p a te n t a n d o t h e r r i g h t d u e t o s a m e .A p p l i c a t i o n C i r c u i t (C X A 2089S )•D e p e n d i n g o n t h e o u t p u t b i a s o f t h e c o m b f i l t e r s , p a y a t t e n t i o n t o t h e p o l a r i t i e s o f t h e c a p a c i t o r s s i n c e t h e b i a s a t P i n s 42 a n d 44 i s a p p r o x i m a t e l y 3.1V a n d 4.5V , r e s p e c t i v e l y .•C o n n e c t P i n 31 t o V c c w h e n s e t t i n g t h e s l a v e a d d r e s s o f t h e I C t o 92H .•T h e a u d i o o u t p u t c a n b e m u t e d b y s e t t i n g P i n 41 t o 3.5V o r m o r e .•T h e T R A P (P i n 48) a r e o f 3.58M H z s u b c a r r i e r .•P a y a t t e n t i o n t o t h e p o l a r i t i e s o f t h e c a p a c i t o r s s i n c e e a c h o u t p u t o f v i d e o s y s t e m a n d a u d i o s y s t e m h a s o p t i o n a l b i a s , r e s p e c t i v e l y .A p p l i c a t i o n c i r c u i t s s h o w n a r e t y p i c a l e x a m p l e s i l l u s t r a t i n g t h e o p e r a t i o n o f t h e d e v i c e s . S o n y c a n n o t a s s u m e r e s p o n s i b i l i t y f o r a n y p r o b l e m s a r i s i n g o u t o f t h e u s e o f t h e s e c i r c u i t s o r f o r a n y i n f r i n g e m e n t o f t h i r d p a r t y p a t e n t a n d o t h e r r i g h t d u e t o s a m e .Example of Representative CharacteristicsVideo system frequency response characteristics100k–2Frequency [Hz]1M 10M 100M2468V i d e o s y s t e m i n p u t /o u t p u t g a i n [d B ]1kAudio system frequency response characteristics–8Frequency [Hz]10k100k1M–6–4–22A u d i o s y s t e m i n p u t /o u t p u t g a i n [dB ]Audio system distortion vs. Input amplitude0.002Input amplitude [Vrms]1240.010.1110T o t a l h a r m o n i c d i s t o r t i o n [%]3Package OutlineUnit: mmCXA2089QSONY CODE EIAJ CODEJEDEC CODEPACKAGE STRUCTUREPACKAGE MATERIALLEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHTEPOXY RESINSOLDER / PALLADIUM PLATING COPPER / 42 ALLOY 48PIN QFP (PLASTIC)37+ 0.1QFP-48P-L04∗QFP048-P-1212-B0.7gNOTE : PALLADIUM PLATINGThis product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).CXA2089S48PIN SDIP (PLASTIC)SONY CODE EIAJ CODE JEDEC CODEPACKAGE STRUCTUREPACKAGE MATERIALLEAD TREATMENT LEAD MATERIAL PACKAGE MASSEPOXY RESINPLATING 42/COPPER ALLOY 5.1gSDIP-48P-02SDIP048-P-0600+ 0.4SOLDER/PALLADIUM1.All mat surface type.Two kinds of package surface:2.Center part is mirror surface.。