MEMORY存储芯片MT41J64M16JT-125G中文规格书
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Active Standby IPP3N Current (AL = 0) Same conditions as IDD3N above
Active Power-Down Current (AL = 0) CKE: LOW; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank group address, bank address inputs: stable at 1; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks open; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0
Precharge Standby ODT Current CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank gropup address, bank address inputs: partially toggling according to the IDD2NT Measurement-Loop Pattern table; Data I/O: VSSQ; DM_n: stable at 1; Bank activity: all banks closed; Output buffer and RTT: enabled in mode registers;2 ODT signal: toggling according to the IDD2NT Measurement-Loop Pattern table; Pattern details: see the IDD2NT Measurement-Loop Pattern table
Precharge Standby Current (AL = 0) CKE: HIGH; External clock: On; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank group address, bank address Inputs: partially toggling according to the IDD2N and IDD3N Measurement-Loop Pattern table; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks closed; Output buffer and RTT: enabled in mode registers;2 ODT signal: stable at 0; Pattern details: see the IDD2N and IDD3N MeasurementLoop Pattern table
ቤተ መጻሕፍቲ ባይዱ
Td3 DES Add2
Td4 DES Valid
Td5 DES Valid
CKE
DQS_t, DQS_c
DQ
PL3 + AL + CL
UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7
Time Break
Don’t Care
Notes:
1. Multipurpose registers read/write enable (MR3 A2 = 1).
Active Standby Current (AL = 0) CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank group address, bank address inputs: partially toggling according to the IDD2N and IDD3N Measurement-Loop Pattern table; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks open; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0; Pattern details: see the IDD2N and IDD3N MeasurementLoop Pattern table
8Gb: x4, x8, x16 DDR4 SDRAM Current Specifications – Measurement Conditions
Table 137: Basic IDD, IPP, and IDDQ Measurement Conditions (Continued)
Symbol IPP0 IDD1
Precharge Power-Down Current CKE: LOW; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank group address, bank address inputs: stable at 0; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks closed; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0
8Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register
c. Remaining address inputs, including A10, and BG1 and BG0 are "Don’t Care."
7. tWR_MPR must be satisfied to complete MPR WRITE. 8. Steps 5 through 7 may be repeated to write additional MPRx locations. 9. After the last MPRx WRITE, tMPRR must be satisfied prior to exiting. 10. Issue MRS command to exit MPR mode; MR3[2] = 0. 11. When the tMOD sequence is completed, the DRAM is ready for normal operation
Precharge Quiet Standby Current CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank group address, bank address inputs: stable at 0; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks closed; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0
2. Address setting: BA1 and BA0 indicate the MPR location A10 and other address pins are "Don’t Care"
3. Parity latency (PL) is added to data output delay when CA parity latency mode is enabled.
IDD2N
IDD2NT
IDD2P IDD2Q IDD3N
IPP3N IDD3P
Description
Operating One Bank Active-Precharge IPP Current (AL = 0) Same conditions as IDD0 above
Operating One Bank Active-Read-Precharge Current (AL = 0) CKE: HIGH; External clock: on; tCK, nRC, nRAS, nRCD, CL: see the previous table; BL: 8;1, 5 AL: 0; CS_n: HIGH between ACT, RD, and PRE; Command, address, bank group address, bank address inputs, Data I/O: partially toggling according to the IDD1 Measurement-Loop Pattern table; DM_n: stable at 0; Bank activity: cycling with one bank active at a time: 0, 0, 1, 1, 2, 2, ... (see the following table); Output buffer and RTT: enabled in mode registers;2 ODT Signal: stable at 0; Pattern details: see the IDD1 Measurement-Loop Pattern table
Address
T0
Ta0
Ta1
MPR Enable
PREA
MRS1
DES
tRP
tMOD
Valid
Valid
Valid
Tb0
Tc0
Tc1
WRITE Add2
DES
DES
tWR_MPR
Valid
Valid
Tc2 READ Add
Td0 DES Valid
Td1 DES Valid
Td2 DES Valid
from the core (such as ACT).
MPR WRITE Waveforms
The following waveforms show MPR write accesses.
Figure 39: MPR WRITE and WRITE-to-READ Timing
CK_c CK_t Command
Active Power-Down Current (AL = 0) CKE: LOW; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank group address, bank address inputs: stable at 1; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks open; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0
Precharge Standby ODT Current CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank gropup address, bank address inputs: partially toggling according to the IDD2NT Measurement-Loop Pattern table; Data I/O: VSSQ; DM_n: stable at 1; Bank activity: all banks closed; Output buffer and RTT: enabled in mode registers;2 ODT signal: toggling according to the IDD2NT Measurement-Loop Pattern table; Pattern details: see the IDD2NT Measurement-Loop Pattern table
Precharge Standby Current (AL = 0) CKE: HIGH; External clock: On; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank group address, bank address Inputs: partially toggling according to the IDD2N and IDD3N Measurement-Loop Pattern table; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks closed; Output buffer and RTT: enabled in mode registers;2 ODT signal: stable at 0; Pattern details: see the IDD2N and IDD3N MeasurementLoop Pattern table
ቤተ መጻሕፍቲ ባይዱ
Td3 DES Add2
Td4 DES Valid
Td5 DES Valid
CKE
DQS_t, DQS_c
DQ
PL3 + AL + CL
UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7
Time Break
Don’t Care
Notes:
1. Multipurpose registers read/write enable (MR3 A2 = 1).
Active Standby Current (AL = 0) CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank group address, bank address inputs: partially toggling according to the IDD2N and IDD3N Measurement-Loop Pattern table; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks open; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0; Pattern details: see the IDD2N and IDD3N MeasurementLoop Pattern table
8Gb: x4, x8, x16 DDR4 SDRAM Current Specifications – Measurement Conditions
Table 137: Basic IDD, IPP, and IDDQ Measurement Conditions (Continued)
Symbol IPP0 IDD1
Precharge Power-Down Current CKE: LOW; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank group address, bank address inputs: stable at 0; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks closed; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0
8Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register
c. Remaining address inputs, including A10, and BG1 and BG0 are "Don’t Care."
7. tWR_MPR must be satisfied to complete MPR WRITE. 8. Steps 5 through 7 may be repeated to write additional MPRx locations. 9. After the last MPRx WRITE, tMPRR must be satisfied prior to exiting. 10. Issue MRS command to exit MPR mode; MR3[2] = 0. 11. When the tMOD sequence is completed, the DRAM is ready for normal operation
Precharge Quiet Standby Current CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank group address, bank address inputs: stable at 0; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks closed; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0
2. Address setting: BA1 and BA0 indicate the MPR location A10 and other address pins are "Don’t Care"
3. Parity latency (PL) is added to data output delay when CA parity latency mode is enabled.
IDD2N
IDD2NT
IDD2P IDD2Q IDD3N
IPP3N IDD3P
Description
Operating One Bank Active-Precharge IPP Current (AL = 0) Same conditions as IDD0 above
Operating One Bank Active-Read-Precharge Current (AL = 0) CKE: HIGH; External clock: on; tCK, nRC, nRAS, nRCD, CL: see the previous table; BL: 8;1, 5 AL: 0; CS_n: HIGH between ACT, RD, and PRE; Command, address, bank group address, bank address inputs, Data I/O: partially toggling according to the IDD1 Measurement-Loop Pattern table; DM_n: stable at 0; Bank activity: cycling with one bank active at a time: 0, 0, 1, 1, 2, 2, ... (see the following table); Output buffer and RTT: enabled in mode registers;2 ODT Signal: stable at 0; Pattern details: see the IDD1 Measurement-Loop Pattern table
Address
T0
Ta0
Ta1
MPR Enable
PREA
MRS1
DES
tRP
tMOD
Valid
Valid
Valid
Tb0
Tc0
Tc1
WRITE Add2
DES
DES
tWR_MPR
Valid
Valid
Tc2 READ Add
Td0 DES Valid
Td1 DES Valid
Td2 DES Valid
from the core (such as ACT).
MPR WRITE Waveforms
The following waveforms show MPR write accesses.
Figure 39: MPR WRITE and WRITE-to-READ Timing
CK_c CK_t Command