AM28F010资料
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s 10,000 write/erase cycles minimum
s Write and erase voltage 12.0 V ±5% s Latch-up protected to 100 mA
from –1 V to VCC +1 V
s Flasherase™ Electrical Bulk Chip-Erase — One second typical chip-erase
AMD’s Flash technology combines years of EPROM and EEPROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The Am28F010 electrically erases all bits simultaneously using Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection.
AMD’s Flash technology reliably stores memory contents even after 10,000 erase and program cycles. The AMD cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The Am28F010 uses a 12.0 V ± 5% VPP high voltage input to perform the Flasherase and Flashrite algorithms.
ing edge of WE# or CE# whichever occurs first. To simplify the following discussion, the WE# pin is used as the write cycle control pin throughout the rest of this text. All setup and hold times are with respect to the WE# signal.
BLOCK DIAGRAM
VCC VSS VPP
WE#
CE# OE#
State Control
Command Register
Erase Voltage Switch
To Array
Program Voltage Switch
Chip Enable Output Enable
Logic
DQ0–DQ7 Input/Output
Family Part Number Speed Options (VCC = 5.0 V ± 10%) Max Access Time (ns) CE# (E#) Access (ns) OE# (G#) Access (ns)
11559H-1
Am28F010
-70
-90
-120
-150
-200
70
AMD’s Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The Am28F010 uses a command register to manage this functionality, while maintaining a JEDEC Flash Standard 32-pin pinout. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility.
32 VCC 31 WE# (W#) 30 NC 29 A14 28 A13 27 A8 26 A9 25 A11 24 OE# (G#) 23 A10 22 CE# (E#) 21 DQ7 20 DQ6 19 DQ5 18 DQ4 17 DQ3
s CMOS Low power consumption — 30 mA maximum active current — 100 µA maximum standby current — No data retention power consumption
s Compatible with JEDEC-standard byte-wide 32-Pin EPROM pinouts — 32-pin PDIP — 32-pin PLCC — 32-pin TSOP
s On-chip address and data latches
s Advanced CMOS flash memory technology — Low cost single transistor memory cell
s Automatic write/erase pulse stop timer
The standard Am28F010 offers access times as fast as 70 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the Am28F010 has separate chip enable (CE#) and output enable (OE#) controls.
The Am28F010 is byte programmable using 10 ms programming pulses in accordance with AMD’s Flashrite programming algorithm. The typical room temperature programming time of the Am28F010 is two seconds. The entire chip is bulk erased using 10 ms erase pulses according to AMD’s Flasherase alrogithm. Typical erasure at room temperature is accomplished in less than one second. The windowed package and the 15–20
Publication# 11559 Rev: H Amendment/+2 Issue Date: January 1998
元器件交易网
minutes required for EPROM erasure using ultra-violet light are eliminated.
Buffers
Data Latch
Low VCC Detector A0–A16
Program/Erase Pulse Timer
Y-Decoder X-Decoder
Y-Gating
1,048,576 Bit Cell Matrix
Address Latch
PRODUCT SELECTOR GUIDE元器件交易网Fra bibliotekFINAL
Am28F010
1 Megabit (128 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory
DISTINCTIVE CHARACTERISTICS
s High performance — 70 ns maximum access time
The highest degree of latch-up protection is achieved with AMD’s proprietary non-epi process. Latch-up protection is provided for stresses up to 100 milliamps on address and data pins from –1 V to VCC +1 V.
Commands are written to the command register using standard microprocessor write timings. Register contents serve as inputs to an internal state-machine which controls the erase and programming circuitry. During write cycles, the command register internally latches address and data needed for the programming and erase operations. For system design simplification, the Am28F010 is designed to support either WE# or CE# controlled writes. During a system write cycle, addresses are latched on the falling edge of WE# or CE# whichever occurs last. Data is latched on the ris-
GENERAL DESCRIPTION
The Am28F010 is a 1 Megabit Flash memory organized as 128 Kbytes of 8 bits each. AMD’s Flash memories offer the most cost-effective and reliable read/ write non-volatile random access memor y. The Am28F010 is packaged in 32-pin PDIP, PLCC, and TSOP versions. It is designed to be reprogrammed and erased in-system or in standard EPROM programmers. The Am28F010 is erased when shipped from the factory.
90
120
150
200
70
90
120
150
200
35
35
50
55
55
2
Am28F010
元器件交易网
CONNECTION DIAGRAMS
PDIP
VPP 1 A16 2 A15 3 A12 4
A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 DQ0 13 DQ1 14 DQ2 15 VSS 16
s Flashrite™ Programming — 10 µs typical byte-program — Two seconds typical chip program
s Command register architecture for microprocessor/microcontroller compatible write interface
s Write and erase voltage 12.0 V ±5% s Latch-up protected to 100 mA
from –1 V to VCC +1 V
s Flasherase™ Electrical Bulk Chip-Erase — One second typical chip-erase
AMD’s Flash technology combines years of EPROM and EEPROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The Am28F010 electrically erases all bits simultaneously using Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection.
AMD’s Flash technology reliably stores memory contents even after 10,000 erase and program cycles. The AMD cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The Am28F010 uses a 12.0 V ± 5% VPP high voltage input to perform the Flasherase and Flashrite algorithms.
ing edge of WE# or CE# whichever occurs first. To simplify the following discussion, the WE# pin is used as the write cycle control pin throughout the rest of this text. All setup and hold times are with respect to the WE# signal.
BLOCK DIAGRAM
VCC VSS VPP
WE#
CE# OE#
State Control
Command Register
Erase Voltage Switch
To Array
Program Voltage Switch
Chip Enable Output Enable
Logic
DQ0–DQ7 Input/Output
Family Part Number Speed Options (VCC = 5.0 V ± 10%) Max Access Time (ns) CE# (E#) Access (ns) OE# (G#) Access (ns)
11559H-1
Am28F010
-70
-90
-120
-150
-200
70
AMD’s Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The Am28F010 uses a command register to manage this functionality, while maintaining a JEDEC Flash Standard 32-pin pinout. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility.
32 VCC 31 WE# (W#) 30 NC 29 A14 28 A13 27 A8 26 A9 25 A11 24 OE# (G#) 23 A10 22 CE# (E#) 21 DQ7 20 DQ6 19 DQ5 18 DQ4 17 DQ3
s CMOS Low power consumption — 30 mA maximum active current — 100 µA maximum standby current — No data retention power consumption
s Compatible with JEDEC-standard byte-wide 32-Pin EPROM pinouts — 32-pin PDIP — 32-pin PLCC — 32-pin TSOP
s On-chip address and data latches
s Advanced CMOS flash memory technology — Low cost single transistor memory cell
s Automatic write/erase pulse stop timer
The standard Am28F010 offers access times as fast as 70 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the Am28F010 has separate chip enable (CE#) and output enable (OE#) controls.
The Am28F010 is byte programmable using 10 ms programming pulses in accordance with AMD’s Flashrite programming algorithm. The typical room temperature programming time of the Am28F010 is two seconds. The entire chip is bulk erased using 10 ms erase pulses according to AMD’s Flasherase alrogithm. Typical erasure at room temperature is accomplished in less than one second. The windowed package and the 15–20
Publication# 11559 Rev: H Amendment/+2 Issue Date: January 1998
元器件交易网
minutes required for EPROM erasure using ultra-violet light are eliminated.
Buffers
Data Latch
Low VCC Detector A0–A16
Program/Erase Pulse Timer
Y-Decoder X-Decoder
Y-Gating
1,048,576 Bit Cell Matrix
Address Latch
PRODUCT SELECTOR GUIDE元器件交易网Fra bibliotekFINAL
Am28F010
1 Megabit (128 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory
DISTINCTIVE CHARACTERISTICS
s High performance — 70 ns maximum access time
The highest degree of latch-up protection is achieved with AMD’s proprietary non-epi process. Latch-up protection is provided for stresses up to 100 milliamps on address and data pins from –1 V to VCC +1 V.
Commands are written to the command register using standard microprocessor write timings. Register contents serve as inputs to an internal state-machine which controls the erase and programming circuitry. During write cycles, the command register internally latches address and data needed for the programming and erase operations. For system design simplification, the Am28F010 is designed to support either WE# or CE# controlled writes. During a system write cycle, addresses are latched on the falling edge of WE# or CE# whichever occurs last. Data is latched on the ris-
GENERAL DESCRIPTION
The Am28F010 is a 1 Megabit Flash memory organized as 128 Kbytes of 8 bits each. AMD’s Flash memories offer the most cost-effective and reliable read/ write non-volatile random access memor y. The Am28F010 is packaged in 32-pin PDIP, PLCC, and TSOP versions. It is designed to be reprogrammed and erased in-system or in standard EPROM programmers. The Am28F010 is erased when shipped from the factory.
90
120
150
200
70
90
120
150
200
35
35
50
55
55
2
Am28F010
元器件交易网
CONNECTION DIAGRAMS
PDIP
VPP 1 A16 2 A15 3 A12 4
A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 DQ0 13 DQ1 14 DQ2 15 VSS 16
s Flashrite™ Programming — 10 µs typical byte-program — Two seconds typical chip program
s Command register architecture for microprocessor/microcontroller compatible write interface