STB12NM50T4中文资料

STB12NM50T4中⽂资料
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March 2005
STP12NM50 - STP12NM50FP STB12NM50 - STB12NM50-1
************************?-12ATO-220/FP/D2/I2PAK
Zener-Protected SuperMESH?MOSFET
Table 1: General Features
s TYPICAL R DS (on) = 0.30 ?
s HIGH dv/dt AND AVALANCHE CAPABILITIES s
LOW INPUT CAPACITANCE AND GATE CHARGE
s 100% AVALANCHE TESTED
s LOW GATE INPUT RESISTANCE
s
TIGHT PROCESS CONTROL AND HIGH MANUFACTURING YIELDS
DESCRIPTION
The MDmesh? is a new revolutionary MOSFET technology that associates the Multiple Drain pro-cess with the Company’s PowerMESH? horizon-tal layout. The resulting product has an outstanding low on-resistance, impressively high dv/dt and excellent avalanche characteristics. The adoption of the Company’s proprietary strip tech-nique yields overall dynamic performance that is significantly better than that of similar competi-tion’s products.
APPLICATIONS
The MDmesh? family is very suitable for increas-ing power density of high voltage converters allow-ing system miniaturization and higher efficiencies.
Table 2: Order Codes
TYPE
V DSS (@Tj max )R DS(on)I D STB12NM50STB12NM50-1STP12NM50STP12NM50FP
550 V 550 V 550 V 550 V
< 0.35 ?< 0.35 ?< 0.35 ?< 0.35 ?
12 A 12 A 12 A 12 A
SALES TYPE MARKING PACKAGE PACKAGING STB12NM50T4B12NM50D 2PAK TAPE & REEL
STB12NM50-1B12NM50I 2PAK TUBE STP12NM50P12NM50TO-220TUBE STP12NM50FP
P12NM50FP
TO-220FP
TUBE
Rev. 2
STP12NM50 - STP12NM50FP - STB12NM50 - STB12NM50-1
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Table 3: Absolute Maximum ratings
( ) Pulse width limited by safe operating area
(1) I SD ≤12A, di/dt ≤400A/µs, V DD ≤ V (BR)DSS , T j ≤ T JMAX.(*) Limited only by maximum temperature allowed Table 4: Thermal Data
Table 5: Avalanche Characteristics
ELECTRICAL CHARACTERISTICS (T CASE =25°C UNLESS OTHERWISE SPECIFIED)Table 6: On /Off
Symbol
Parameter
Value
Unit
STB12NM50STB12NM50STP12NM50
STP12NM50FP
V GS Gate- source Voltage
± 30
V I D Drain Current (continuous) at T C = 25°C 1212 (*)A I D Drain Current (continuous) at T C = 100°C 7.57.5 (*)A I DM ( )Drain Current (pulsed)4848 (*)A P TOT Total Dissipation at T C = 25°C 16035W Derating Factor
1.280.28W/°C V ISO Insulation Winthstand Voltage (DC)--
2500
V dv/dt (1)Peak Diode Recovery voltage slope 15V/ns T j T stg
Operating Junction Temperature Storage Temperature
-65 to 150-65 to 150
°C °C
TO-220/ D2PAK /
I2PAK
TO-220FP Rthj-case Thermal Resistance Junction-case Max 0.78
3.57
°C/W Rthj-amb
Thermal Resistance Junction-ambient Max
62.5°C/W T l
Maximum Lead Temperature For Soldering Purpose
300
°C
Symbol Parameter
Max Value
Unit I AR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by T j max)
6A E AS
Single Pulse Avalanche Energy
(starting T j = 25 °C, I D = I AR , V DD = 50 V)
400
mJ
Symbol Parameter
Test Conditions
Min.Typ.
Max.
Unit V (BR)DSS Drain-source Breakdown Voltage
I D = 250 µA, V GS = 0
500
V I DSS Zero Gate Voltage
Drain Current (V GS = 0)V DS = Max Rating
V DS = Max Rating, T C = 125°C 110µA µA I GSS Gate-body Leakage Current (V DS = 0)V GS = ± 30 V
± 100nA V GS(th)Gate Threshold Voltage V DS = V GS , I D = 50 µA 3
45V R DS(on
Static Drain-source On Resistance
V GS = 10 V, I D = 6 A
0.30
0.35
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STP12NM50 - STP12NM50FP - STB12NM50 - STB12NM50-1
ELECTRICAL CHARACTERISTICS (CONTINUED)Table 7: Dynamic
Table 8: Source Drain Diode
(1) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.(2) Pulse width limited by safe operating area.
(3) C oss eq. is defined as a constant equivalent capacitance giving the same charging time as C oss when V DS increases from 0 to 80% V DSS .
Symbol Parameter
Test Conditions
Min.
Typ.Max.
Unit g fs (1)Forward Transconductance V DS = 15 V , I D = 6 A
5.5S C iss C oss C rss Input Capacitance Output Capacitance Reverse Transfer Capacitance V DS = 25 V, f = 1 MHz, V GS
= 0
100018025pF pF pF C OSS eq (3).
Equivalent Output Capacitance V GS = 0 V, V DS = 0 to 400 V 90pF t d(on)t r Turn-on Delay Time Rise Time
V DD = 250 V, I D = 6 A, R G = 4.7 ?, V GS = 10 V (see Figure 17)2010ns ns Q g Q gs Q gd Total Gate Charge Gate-Source Charge Gate-Drain Charge V DD = 400 V, I D = 12 A,V GS = 10 V (see Figure 20)
2881839nC nC nC Rg
Gate Input Resistance
f = 1MHz Gate DC Bias = 0 Test Signal Level = 20mV Open Drain
1.6
Symbol Parameter
Test Conditions
Min.
Typ.
Max.Unit I SD I SDM (2)Source-drain Current
Source-drain Current (pulsed)1248A A V SD (1)Forward On Voltage I SD = 12 A, V GS = 0 1.5
V t rr Q rr I RRM Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 12 A, di/dt = 100 A/µs V DD = 100V (see Figure 18)
2702.2316.5ns µC A t rr Q rr I RRM
Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current
I SD = 12 A, di/dt = 100 A/µs V DD = 100V, T j = 150°C (see Figure 18)
340318
ns µC A
STP12NM50 - STP12NM50FP - STB12NM50 - STB12NM50-1
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Figure 3: Safe Operating Area For TO-220/
Figure 6: Thermal Impedance TO-220/D2PAK/
STP12NM50 - STP12NM50FP - STB12NM50 - STB12NM50-1
Figure 9: Transconductance
Figure 12: Static Drain-Source On Resistance
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STP12NM50 - STP12NM50FP - STB12NM50 - STB12NM50-1 Figure 15: Source-Drain Forward Characteris-
tics
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STP12NM50 - STP12NM50FP - STB12NM50 - STB12NM50-1
Figure 16: Unclamped Inductive Load Test Cir-cuit
Figure 17: Switching Times Test Circuit For Resistive Load Figure 18: Test Circuit For Inductive Load Switching and Diode Recovery Times
Figure 19: Unclamped Inductive Wafeform
Figure 20: Gate Charge Test Circuit
STP12NM50 - STP12NM50FP - STB12NM50 - STB12NM50-1
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STP12NM50 - STP12NM50FP - STB12NM50 - STB12NM50-1
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STP12NM50 - STP12NM50FP - STB12NM50 - STB12NM50-1
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TAPE AND REEL SHIPMENT (suffix ”T4”)*
TUBE SHIPMENT (no suffix)*
D 2PAK FOOTPRINT
* on sales type
DIM.mm inch MIN.
MAX.MIN.
MAX.A 330
12.992
B 1.50.059
C 12.813.20.5040.520
D 20.20795G 24.426.40.960 1.039N 100
3.937
T
30.4 1.197
BASE QTY BULK QTY 1000
1000REEL MECHANICAL DATA
DIM.mm inch MIN.MAX.MIN.
MAX.
A010.510.70.4130.421B015.715.90.6180.626D 1.5 1.60.0590.063D1 1.59 1.610.0620.063E 1.65 1.850.0650.073F
11.411.60.4490.456K0 4.8 5.00.1890.197P0 3.9 4.10.1530.161P111.912.10.4680.476P2 1.9 2.1
0.0750.082R 50 1.574
T 0.250.350.00980.0137
W
23.7
24.30.9330.956
TAPE MECHANICAL DATA
STP12NM50 - STP12NM50FP - STB12NM50 - STB12NM50-1 Table 9: Revision History
Date Revision Description of Changes 27-Sep-20041Complete version
09-Mar-20052New Stylesheet
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STP12NM50 - STP12NM50FP - STB12NM50 - STB12NM50-1
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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