EDA练习

Exercise ManualforQuartus® II Software Design Series:FoundationSoftware Requirements to complete all exercisesQuartus II software version 11.0Link to the Quartus II Handbook:/literature/hb/qts/quartusii_handbook.pdfUse the link below to download the design files for the exercises: /customertraining/ILT/Quartus_II_Design_Series_Foundation_11_0_v1.zip2Copyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v1Copyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v13Exercise 14Copyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v1Copyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v15Exercise 1Objectives:∙ Create a project using the New Project Wizard ∙ Name the project ∙ Pick a deviceNote : In these exercises, you’ll crea te a brand new project and complete an existingdesign. You’ll have the choice of creating the design using three different types of design entry: Verilog, VHDL, or as a Quartus II schematic. Where noted, be sure to only follow the instructions appropriate for your choice of design entry method. By the end of the class, you’ll have a final, optimized design, ready for programming into a Cyclone ® IV E FPGA device.Be sure to completely read the instructions for each step and sub-step in this lab manual. Each step first summarizes what you’ll be doing in that step before providing complete instructions. Use the lines next to each step (____) to keep track of your progress or to check off completed steps in the exercises.If you have any questions or problems, please ask the instructor for assistance.Copyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v16Step 1: Create new project for use in the lab exercises____ 1. Unzip the lab project files. In an Explorer window, go toC:\altera_trn\Quartus_II_Software_Design_Series_Foundation . The name of the directory may be shortened to Quartus_II_Foundation or similar on some machines. This will be your lab installation directory. Delete any old lab file folders that may already exist there labeled QIIF*. Double-click the executable file found in that location or the file you downloaded from the link in your class registration email. If you still cannot find this file, ask your instructor for assistance. In the WinZip dialog box, simply click Unzip to automatically extract the files in place to a new folder named QIIF11_0 in the directory mentioned above. Close WinZip. ____ 2. Start the Quartus II software. In the Windows Start menu from the All Programslist, go to the Altera folder and then the Quartus II 11.0 folder. Depending on your operating system, click Quartus II 11.0 (64-bit) or Quartus II 11.0 (32-bit) to start the program. Check with your instructor if unsure. There may also be a shortcut on the desktop. ____ 3. Start the New Project Wizard. You can open it from the Getting Started WithQuartus II Software welcome dialo g that appears. If you’ve closed this window, in the Tasks window on the left side of the Quartus II interface, expand the Start Project folder and double-click Open New Project Wizard . You can also select New Project Wizard… from the File menu. The New Project Wizard appears. If the Introduction screen appears, click Next . ____ 4. Complete the New Project Wizard to create the project. Select one of the workingdirectories shown in Table 1 depending on the type of design entry you want to use. Name the project pipemult and leave the top level entity name pipemult.Table 1. Settings for page 1 of New Project Wizard____ 5. Click Next to advance to page 2.Copyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v17____ 6.On page 2, click the browse button . Navigate to the project directory as theSelect File dialog box may not automatically be pointing there. Select the top-level file pipemult (.v, .vhd, or .bdf, depending on the design entry method you chose in #4). After clicking Open , click Add to add the file to the project. Click Next .Note that this step isn’t really necessary since the design file is already l ocated in the project working directory. The new project would automatically include the design file as part of the project. Files or file directories (libraries) only need to be added on page 2 of the New Project Wizard if they are not located in the project directory. Adding the file to the project removes the warning that the file has not been added.____ 7. On page 3, select Cyclone IV E as the Family . In the Show in ‘Available device’list section, set Package to FBGA , Pin count to 256, and Speed grade to Fastest . This filters the list of available devices. Select the EP4CE6F17C6 device from the Available devices:window.____ 8. Click Next ./////////////////////////////////////////////////////////////////////////////////////////////////////////////8Copyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v1Copyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v1910Copyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v1Copyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v111Copyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v112____ 9. On page 4 (shown below), you can specify third-party EDA tools you may be using.Since these exercises will be done entirely within the Quartus II software without any other tools, click Nextto skip this step.____ 10. The summary screen appears.Copyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v113____ 11. Click Finish .The project is now created.Keep the project open as you continue through the exercises. There is no need to close the project. If you do close the project for some reason, be sure to select Open Project instead of just Open from the File menu (or Open Existing Project from the Tasks window). The Open command is used to simply open a single file instead of a project, preventing the ability to perform many project-based operations, such as compilation.Exercise SummaryCreated a project using the New Project Wizard– Named the project – Picked a deviceEND OF EXERCISE 1Exercise 214Copyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v115Copyright © 2011 Altera Corporation A-MNL-QII-F-EX-11-0-v1Copyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v116Exercise 2Objectives:∙ Create a multiplier and RAM block using the MegaWizard Plug-in Manager tocomplete the design ∙ Create a HEX file to initialize the RAM block using the Memory Editor ∙ Analyze and elaborate the design to check for errorsPipelined Multiplier DesignFigure 1 shows a schematic representation of the top-level design file you will be using today. It consists of a multiplier and a RAM block. Data is fed to the multiplier from an external source and stored in the RAM block, which is also controlled externally. The data is then read out of the RAM block by a separate address control.Figure 1Copyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v117IMPORTANT NOTE: For exercises 2-6, you should either continue working in the Ex1 directory (preferred), or you can open a project (File menu or Tasks window ⇒ Open [Existing] Project ⇒ Select pipemult.qpf and click Open ) found in one of the Ex#directories. The Ex# directories each contain projects in the three versions (schematic, Verilog, VHDL) completed up to the beginning of that exercise in the exercise manual. The Solutions directory contains a Word document with the answers to questions asked in the exercises as well as the final project as it would be set up at the end of exercise 5.Step 1: Build an 8x8 multiplier using the MegaWizard ® Plug-in Manager____ 1. Choose Tools ⇒ MegaWizard Plug-In Manager or double-click MegaWizardPlug-In Manager in the Create Design folder of the Tasks window. In the window that appears, select Create a new custom megafunction variation . Click Next . ____ 2. Select the megafunction to create. On page 2a (shown above), do the following:a. Expand the Arithmetic folder and select LPM_MULT .b. In the drop-down menu, make sure the Cyclone IV E device family is selected.The selection of a device family here lets the MegaWizard Plug-In Manager know what device resources are available as the megafunction is created. You could change the device family if you wanted to create the same megafunction but for a different project that uses a different device.c. Choose VHDL or Verilog HDL output depending on your choice of HDL andexercise directory. If you are using the Schematic exercise, choose either VHDL or Verilog. d. For the name of the output file, type mult . You can add this to the end of thedirectory path or erase the entire path to automatically place the generated megafunction files in the project directory.Copyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v118____ 3. Click Next .///////////////////////////////////////////////////////////////////////////////////////////// \Copyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v11920Copyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v1Copyright © 2011 Altera Corporation22____ 4.On page 3 (General), set the width of the dataa and datab buses to 8 bits if they are not already set. For the remaining settings in this window, use the defaults thatappear.Copyright © 2011 Altera Corporation24____ 5. Click Next .____ 6. On page 4 (General 2), use all the default settings (i.e. datab input does NOT have aconstant value, use unsigned multiplication, and select the default multiplier implementation).____ 7. Click Next.____ 8. On page 5 (Pipelining), choose Yes, I want an output latency of 2 clock cycles .____ 9.Click Next.____ 10.You should now be on page 6 (section 2 of the MegaWizard called EDA). This tab indicates the simulation model file needed to simulate LPM_MULT in an EDAsimulation tool (e.g. ModelSim or some other 3rd-party simulation tool). The lpmsimulation model file should be indicated as shown above. You also have the optionof generating a timing and resource estimation netlist for use by a 3rd-party synthesistools. We are not using any third-party tools, so just click Next.Copyright © 2011 Altera Corporation26____ 11. On page 7, using Table 2 below check the appropriate boxes depending on theDesign Entry Method selected.Table 2. MegaWizard files to generate____ 12. Click Finish to create the megafunction. If a dialog box appears asking if you wantto add the QIP file to the Quartus II project, click Yes .The multiplier is built.If for some reason your megafunction is incorrect or you forgot or missed a checkbox for generating all the required output files, open the MegaWizard Plug-In Manager again from the Tools menu or Tasks window. Select to edit an existing megafunction. Then select the main variation file for the megafunction (mult.v or mult.vhd), and go through the pages of the MegaWizard again (skip around with the tabs at the top) to fix your mistakes or generate the missing file(s). Click Finish to update the megafunction files.Step 2: Create a 32x16 RAM using the MegaWizard Plug-In Manager____ 1.Open the MegaWizard Plug-In Manager again (Tools or Tasks window MegaWizard Plug-In Manager). Select to Create a new custom megafunctionvariation, and click Next.____ 2.Select the megafunction to create. On page 2a (shown above), do the following:a.Expand the Memory Compiler folder and select RAM: 2-PORT.b.As before, choose the Cyclone IV E device family and VHDL or Verilog HDL.c.For the name of the output file,enter ram.____ 3.Click Next.///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ///28Copyright © 2011 Altera Corporation30Copyright © 2011 Altera CorporationCopyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v13132Copyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v1Copyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v133____ 4. On page 3, select O ne read port and one write port for the Dual –port RAM mode.Select memory size by words .____ 5. Click Next .____ 6. On page 4 (Widths/Blk Type ), set the width of the data_a bus to 16 and the numberof 16-bit words to 32. Select the Memory block type to Auto and Max depth to Auto .____ 7.Click Next twice.34Copyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v1Copyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v135____ 8. On page 7 (Regs/Clkens/Aclrs ), disable the option to register the Read outputport(s) ‘q’. Accept the remaining default settings.____ 9. Click Next 2 times.____ 10. On page 10 (Mem Init ), click Yes, use this file for the memory content data.Once enabled, type in the file name ram.hex . You’ll be creating this file next, but you can enter it now so you don’t have to go back into the MegaWiza rd later.____ 11. Click Next .Copyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v136____ 12. On page 11, the altera_mf simulation model file is displayed as being needed tosimulate this function in a 3rd -party EDA simulation tool. Click Next . ____ 13. Choose the same files to generate for ram as you selected for mult earlier (Step 1,#11). Click Finish to close the wizard and then Yes to add the Quartus II IP file to the project.You have now created the two components needed for this design. Now you will create the HEX file needed to initialize the contents of the RAM.Step 3: Create HEX file using the Memory Editor____ 1. From the Tasks window, in the Create Design folder, double-click Create NewDesign File . (You may have to change the Tasks Flow to Full Design.) You couldalso go to the File menu and select Newor clickin the toolbar.____ 2. In the New dialog box, expand the Memory Files category and select Hexadecimal(Intel-Format) File.____ 3. Click OK .Copyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v137____ 4. In the memory size dialog box, choose 32 as the number of words and 16 as theword size.____ 5. Click OK.The Memory Editor now displays your memory space. If your memory space is not displayed exactly as above, you can change the number of cells per row (View menu) to 16, the memory radix (View menu) to Hexadecimal , and the address radix to Decimal .____ 6. Highlight all of the memory locations in your memory space. Right-click and selectCustom Fill Cells . ____ 7. Use the Custom Fill Cells dialog box to enter your own values to initialize yourmemory. You can enter any values you want. Do one of the following:a. Repeating Sequence: Enter a series of numbers separated by commas orspaces to be repeated in memory. b. Incrementing/Decrementing: Enter a start value and another value bywhich to increment or decrement the start value.____ 8. Save the file as ram.hex in the project directory (you may have to navigate to theproject directory again before you save). Close ram.hex.Copyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v138Step 4: Instantiate and connect design blocks according to design entry method Choose ONE of the following procedures based on your design entry method (VHDL, Verilog, or Schematic). Follow only the directions for your selected design entry method and then proceed to Step 5. VHDLPerform these instructions only if you are using VHDL.____ 1. Open pipemult.vhd . You can use the Open command from the File menu, click thetoolbar button, or double-click the top-level entity in the Project Navigator. You can also double-click Open Existing Design File in the Create Design folder of the Tasks window.This is the top-level file for the design. Normally, you would have to instantiate both ram and mult and connect them together. In the interest of time, the file has been almost completed for you, but it is missing the instantiation of the multiplier.____ 2. Open the file mult.cmp . Copy the component declaration from mult.cmp and pasteit into the architecture declaration section of pipemult.vhd where indicated. ____ 3. Close mult.cmp .____ 4. Open the file mult_inst.vhd . Copy the contents of mult_inst.vhd (the componentinstantiation) and paste into the architecture body of pipemult.vhd where indicated. Change the following signal names in the instantiation:clock_sig to clk1 dataa_sig to dataa datab_sig to datab result_sigtomult_to_ram____ 5. Save pipemult.vhd . ____ 6. Close mult_inst.vhd .____ 7. Continue to Step 5: Check the design .VerilogPerform these instructions only if you are using Verilog entry.____ 1. Open pipemult.v . You can use the Open command from the File menu, click thetoolbar button, or double-click the entity in the Project Navigator. You can also double-click Open Existing Design File in the Create Design folder of the Tasks window.Copyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v139This is the top-level file for the design. Normally, you would have to instantiate both ram and mult and connect them together. In the interest of time, the file has been almost completed for you, but it is missing the instantiation of the multiplier.____ 2. Open the file mult_inst.v . Copy the contents of mult_inst.v (the componentinstantiation) and paste into the body of pipemult.v where indicated. Change the following signal names in the instantiation:clock_sig to clk1 dataa_sig to dataa datab_sig to datab result_sigtomult_to_ram____ 3. Close mult_inst.v . ____ 4. Save pipemult.v .____ 5. Continue to Step 5: Check the design .SchematicPerform these instructions only if you are using schematic entry.____ 1. Open pipemult.bdf . You can use the Open command from the File menu, click thetoolbar button, or double-click the entity in the Project Navigator. You can also double-click Open Existing Design File in the Create Design folder of the Tasks window.This is the top-level schematic file for the design. Normally, you would have to instantiate both ram and mult sub-designs and connect them together manually. In the interest of time, the schematic file has been almost completed for you, but it is missing the ram and mult blocks and the output pins q[15..0].____ 2. In the schematic file, double-click any empty space in the schematic so that theSymbol window appears. In the Symbol window, click to expand the symbols defined in the Project folder. Double-click the mult symbol. Click the left mouse button to place the symbol inside the schematic file where indicated.Note: The three ports on the left side of the multiplier should line up exactly with the wires coming from the input pins (no X’s). If not, you may not have specified the multiplier parameters correctly when configuring the megafunction. If this is the case, hit the Esc key to cancel the symbol placement, reopen the MegaWizard Plug-In Manager, and select Edit an existing megafunction variation to open and edit the mult megafunction to fix the problem and regenerate the symbol.____ 3. Right-click on the mult symbol and choose Properties . In the Symbol Propertiesdialog box, change the Instance name: from inst to mult_inst . Click OK .Copyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v140____ 4. Double-click an open area again to reopen the Symbol window. This time, select theram symbol and place it in the schematic file where indicated.Note: With ram , the lower 4 ports on the left side of the symbol should line up with the wires coming from the input pins. The data port should be unconnected.____ 5. As you did with mult, use the Symbol Properties dialog box to change the name ofthe ram instantiation from inst to ram_inst . ____ 6. Open the Symbol window again and this time, as a shortcut, type output in the Name:field.The Symbol window found the output symbol automatically by name.____ 7. Click OK and place the output pin near the output port of the inst2 register symbol.Double-click the pin_name and change it to q[15..0]. ____ 8.Click on the bus drawing tool , found in the schematic editor toolbar, and draw thebus connections between mult (result ) and ram (data ).Your resulting schematic should look like the above figure.____ 9. Save pipemult.bdf .Copyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v141Step 5: Check the design____ 1. From the Processing menu, select Start ⇒ Start Analysis & Elaboration .Analysis and elaboration checks that all the design files are present and connections have been made correctly. It also establishes the project hierarchy.____ 2. Click OK when analysis and elaboration is completed. If there are any errors detailedin the Messages window, check your connections or return to the MegaWizard Plug-In Manager for either megafunction to fix the problem (select to edit an existing megafunction instead of creating a new one). You can safely ignore any blue warnings that appear.Feel free to explore the Project Navigator that now contains the complete project hierarchy.／／／／／／Exercise Summary∙ Generated a multiplier and RAM using the MegaWizard Plug-In Manager andincorporated into a design ∙ Created a HEX file for RAM initialization using the Memory Editor ∙ Checked the design files using Analysis and ElaborationEND OF EXERCISE 2Exercise 342Copyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v143Copyright © 2011 Altera Corporation A-MNL-QII-F-EX-11-0-v1Copyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v144Exercise 3Objectives:∙ Perform full compilation∙ Locate information in the Compilation Report∙ Explore cross-probing capabilities by viewing logic in various windowsTable 3 – Compilation ReportCopyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v145Step 1: Compile the design____ 1. Select Start Compilation from the Processing menu or clicklocated in thetoolbar to perform a full compilation of the design. You can also double-clickCompile Design in the Tasks window. A dialog box will appear to indicate when the compilation is complete. ____ 2. Click OK .／／／／Step 2: Gather information from the Compilation Report)The Compilation Report provides all information on design processing. You use it to understand how the compiler interpreted your design and to verify results. It is organized by compiler executables, with each one generating its own folder. By default, the Compilation Report opens when any processing begins and displays the Flow Summary Section when that process finishes.____ 1. From the Flow Summary section of the Compilation Report , record the Total logicelements , Total memory bits , number of Embedded multiplier 9-bit elements and Total pins in the table at the beginning of this exercise (Table 3).From these results, you can see that this design is currently using only dedicated device resources (i.e. embedded memory, embedded multipliers) and no logic other than the registers included within these resources. ／／／Copyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v146／／／／／／／／／／／／／／／／／／／／／／／／／／／／／／／／／／____ 2. Expand the Fitter folder in the Compilation Report . Locate the Resource Sectionfolder. From the Resource Utilization by Entity table, record again in Table 3, the resource counts for the mult and ram sub-designs.／／／／／／／／／／／／／／／／／／／／／／／／／／／／／／／／／／／Copyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v147____ 3. From the Control Signals table, also in the Resource Section , record the controlsignals found and their fan-out.／／／／／／／／／／／／／／／／／／／／／／／／／／／／／／／／／／／In the next few steps, you will take a look at some additional ways to analyze the results of your compilation and determine the location of the output registers.Copyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v148Step 3: Explore the design logically using the RTL ViewerThe RTL Viewer allows you to view a logical representation of an analyzed design graphically. It is a very helpful tool for debugging HDL synthesis results.____ 1. From the Tools menu, open the RTL Viewer (under Netlist Viewers ). You can alsoaccess the RTL Viewer from the Compile Design section of the Tasks window.You should see the diagram shown above. The output register block is namedinst2[15..0] in the schematic version of the project, but the rest of the diagram is the same for all three versions. This is a graphical view displaying the logicalrepresentation of the design. Currently it shows the I/O, the instantiation of the mult and ram sub-designs, and an additional set of output registers. Notice the registers are external to the memory block per the original design.／／／／／／／／／／／／／／／／／／／／／／／／／／／／／／／／／／____ 2. Select the ram sub-design to highlight it. The outline of the block turns bright redwhen the block is selected. Right-click and select Ungroup Selected Nodes .Copyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v149The ram block is now displayed with all of the input and output buses expanded. This operation is helpful when you want to see how individual bits are connected. This operation can be performed on internal blocks and I/O.／／／／／／／／／／／／／／／／／／／／／／／／／／／／／／／／／Copyright © 2011 Altera CorporationA-MNL-QII-F-EX-11-0-v150Select the ram sub-design again if it was deselected. Right-click and select Group Related Nodes .This returns the RTL Viewer to the previous view.____ 3. Double-click on the ramsub-design block.You have now descended the hierarchy into the ram sub-design. As a result, the view changes to the above (or similar) image. This shows that the ram sub-design is made up of a single megafunction block called altsyncram . You can continue double-clicking blocks to descend the hierarchy to its lowest level: single-bit RAM functions. Let’s view this lowest level of the hierarchy in a different way.／／／／／／／／／／／／／／／／／／／／／／／／／／／／／／／____ 4. Double-click in any empty space.This returns the viewer to the top-level view of the design. If you’ve descended further into the hierarchy, you may need to do this a few times to return to the top.。