WM8805数据手册 中英文对照

* WM8805是一种高性能的用户模式S / PDIF收发器,支持8个接收通道和1传输通道。

*用晶振或由外部提供高质量的主时钟用来恢复低抖动地由S / PDIF提供的主时钟。

*用高性能的内部锁相环产生所有典型的音频
时钟。

一个专用的CLKOU
脚提供了一个高驱动时钟输出。

*通过提供一个选项,允许设备仅仅是用来清理(de抖动)接收到的数字音频
信号。

*该设备可用于在软件的控制模式或独立的硬件控制模式。

在软件控制方式,支持2-wire和3-wire接口模式。

*状态和错误监测是内置的,结果可以通过控制接口读出,在“标志”模式下
通过音频数据接口GPO脚(音频数据和状态标志附加)。

*音频数据接口支持I2S,向左对齐,右对齐和DSP音频格式的字长16位,
与采样率从32到192KHz/秒。

*设备提供一个28脚无铅SSOP封装。

1.数字输入插脚有施密特触发器的输入缓冲区。

2.参考表6设备配置在上电或硬件复位。

1.锁相环和数字供电必须始终在供电电压范围0.3 v以内内。

2.锁相环和数字地必须始终在地电压的0.3 v以内。

1. 锁相环和数字供电必须始终在供电电压范围0.3 v以内内。

2. 锁相环和数字地必须始终在地电压的0.3 v以内。

DEVICE DESCRIPTION
设备描述
INTRODUCTION FEATURES
介绍功能
•IEC-60958-3 compatible with 32 to 192k frames/s support.
IEC - 60958 - 3兼容32到192 k帧/ s的支持
•Supports AES-3 data frames.
支持aes 3数据帧
•Support for reception and transmission of S/PDIF data.
支持S / PDIF数据的接收和传输。

•Clock synthesis PLL with reference clock input and low jitter output.时钟合成锁相环根据参考时钟输入并输出低抖晃的信号。

•Supports input reference clock frequencies from 10MHz to 27MHz.支持输入参考时钟的频率从10 mhz到27 mhz。

•Dedicated high drive clock output pin.
专用高驱动时钟输出引线。

•Register controlled channel status bit configuration.
寄存器控制通道状态位配置。

•Register read-back of recovered channel status bits and error flags.
寄存器复诵的通道状态比特和错误恢复的标志。

•Detection of non-audio data, sample rate and de-emphasis.
检测非音频数据,采样率和去加重。

•Programmable GPOs for error flags and frame status flags.
可编程GPOs错误标志和帧状态标志。

The WM8805 is an IEC-60958 compatible S/PDIF transceiver with support for up to eight received
S/PDIF data streams and one transmitted S/PDIF data stream.
这个WM8805是iec - 60958兼容的S / PDIF收发器,支持多达8个接收S / PDIF数据流和
一个S / PDIF传输数据流。

The receiver performs data and clock recovery, and transmits recovered data from the chip either
through the digital audio interface or, alternatively, the device can loop the received S/PDIF data
back out through the S/PDIF transmitter producing a de-jittered S/PDIF transmit data stream. The
recovered clock may be routed to a high drive output pin for external use. If there is no S/PDIF input
data stream the PLL can be configured to output all standard MCLK frequencies or it can be
configured to maintain the frequency of the last received S/PDIF data stream.
接收器处理数据和时钟恢复,并且通过芯片任何一个数字音频接口传输恢复的数据或者
设备可以循环确认S / PDIF数据，回收由S / PDIF发射机产生一个S / PDIF低抖动传输数据流。

这个恢复的时钟可能被路由发送到一个高驱动外部引线输出。

如果没有S/PDIF输入数据流，这
个锁相环可以被配置为输出所有标准MCLK频率或去维持最后一次收到的S / PDIF数据流的频率。

The transmitter generates S/PDIF frames where audio data may be sourced from the S/PDIF
receiver or the digital audio interface. Timing for the S/PDIF transmitter interface can be sourced
from the internally derived MCLK ine loop through mod or it can be taken from an external source.
S/PDIF FORMAT S/PDIF is a serial, bi-phase-mark encoded data stream. An S/PDIF frame consists of
two subframes. Each sub-frame is made up of:
发射器生成的S/PDIF音频数据帧,它可能来自S / PDIF接收机和数字音频接口。

在所相环
模式下定时来源于内部驱动的MCLK主时钟或来自外部源。

串行双相编码数据流。

一个S / PDIF帧包含了两个子帧，每个子帧由下面的部分组成：
S/PDIF FORMAT S/PDIF 格式
S/PDIF is a serial, bi-phase-mark encoded data stream. An S/PDIF frame consists of two subframes.
Each sub-frame is made up of:
*S / PDIF是串行,双相标记编码数据流。

一个S / PDIF帧包括两个子帧。

每个子帧是由下列各项构成:
•Preamble – a synchronization pattern used to identify the start of a 192-frame block or subframe
•序文——一个同步模式用来识别192 -帧块或付帧的标志
•4-bit Auxiliary Data (AUX) – ordered LSB to MSB
•4位辅助数据(辅助)——顺序为MSB到LSB
•20-bit Audio Data (24-bit when combined with AUX) – ordered LSB to MSB
*20位音频数据(24位当加上4位附加位（AUX）时)——顺序为MSB到LSB
•Validity Bit – a 1 indicates invalid data in the associated sub-frame
•有效位- 1显示无效的数据在相关的付帧
•User Bit – over 192-frames, this forms a User Data Block
*用户位——192 -帧位,这形成一个用户数据块
•Channel Bit – over 192-frames, this forms a Channel Status Block
*通道位——超过192——帧,这形成一个通道状态块
•Parity Bit – used to maintain even parity over the sub-frame (not including the preamble)
*校验位——用于维持甚至奇偶校验在付帧内(不包括序言)
An S/PDIF Block consists of 192 frames. Channel and user blocks are incorporated within the 192-
frame S/PDIF Block. For Consumer mode only the first 40-frames are used to make up the Channel
and User blocks. Figure 6 illustrates the S/PDIF format. The WM8805 does not support transmission
of user channel data. Received user channel data may be accessed via GPO pins.
一个S / PDIF块由192帧组成。

通道和用户块合并在一起在S / PDIF块192帧之内。

对于
用户模式仅仅第一个40帧用来携带通道和用户块。

图6演示了S / PDIF格式。

这个WM8805
不支持用户数据传输通道。

被承认用户通道数据可以通过GPO脚访问。

POWER UP CONFIGURATION 上电配置
The operating mode of the WM8805 is dependent upon the state of SDIN, SCLK, SDOUT, CSB and
GPO0 when the device is powered up or a hardware reset occurs. Table 6 summarises the
configuration options.
当设备启动或一个硬件复位发生时，WM8805的操作模式取决于SDIN,SDOUT SCLK,SDOUT,
CSB and GPO0的状态。

表6总结了配置选项
注意:当设备运行在硬件模式AIF_CONF[1:0]配置音频接口。

参考表16描述模式。

表6设备配置在上电或硬件复位
注意:当设备运行在硬件模式AIF_CONF[1:0]配置音频接口。

参考表16描述模式。

表6设备配置在上电或硬件复位
When the device powers up, all power up configuration pins are configured as inputs for a minimum
of 9.4us and a maximum of 25.6us following the release of the external reset. The times are based
on 27MHz and 10MHz crystal clock frequencies respectively. This enables the pins to be sampled
and the device to be configured before the pins are released to their selected operating conditions.
Figure 7 illustrates how SDIN is sampled.
当设备上电时,所有的上电配置脚被配置为输入在最低9.4us和最高25.6us时跟随外部复位。

时间
基准是分别建立在27 mhz和10 mhz晶体时钟频率上。

这使得这些脚被取样和设备被配置之前释
放它们选定的操作条件。

图7说明了SDIN如何取样。

If the device is powered up in Software control mode, all functions of the device are powered down by
default and must be powered up individually by writing to the relevant bits of the PWRDN register
(Table 7). In Hardware Control Mode, all functions of the device are powered up by default.
如果设备在软件控制模式中上电,用缺省方式上电设备的所有功能，必须在上电后分别地编写
PWRDN寄存器有关的位(表7)。

在硬件控制模式下,设备的所有功能是默认启动。

CONTROL INTERFACE OPERATION 控制界面操作
Control of the WM8805 is implemented in either hardware control mode or software control mode.
The method of control is determined by sampling the state of the SDIN/HWMODE pin at power up or
at a hardware reset. If SDIN/HWMODE is low during power up the device is configured in hardware
control mode, otherwise the device is configured in software control mode.
无论是用硬件控制模式或软件控制模式都能实现WM8805的控制。

该控制方法是在电源上电或硬件
复位时由HWMODE/SDIN 脚采样状态所决定。

如果在上电期间SDIN / HWMODE脚是低电平设备将
被配置在硬件控制模式,否则设备配置在软件控制方式。

Software control is achieved using a 3-wire (3-wire write, 4-wire read) or a 2-wire serial interface.
软件控制是通过使用一个3线(3线写四读)或一个2线串行接口来完成。

The serial interface format is configured by sampling the state of the GPO0/SWIFMODE pin on power up or at a hardware reset. If the GPO0/SWIFMODE pin is low the interface is configured in 2-
wire mode, otherwise the interface is configured in 3-wire SPI compatible mode.
在上电或硬件复位时由GPO0 / SWIFMODE脚的采样状态配置串行接口格式。

如果GPO0 / SWIFMODE
脚是低电平接口配置在2线模式,否则接口配置在3线SPI兼容模式。

3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE – REGISTER WRITE
3线(SPI兼容)串行控制模式——寄存器写
SDIN is used for the program data, SCLK is used to clock in the program data and CSB is used to
latch in the program data. SDIN is sampled on the rising edge of SCLK. The 3-wire interface write
protocol is shown in Figure 8.
SDIN为编程数据,SCLK是编程数据中的时钟而CSB 是用来锁定编程数据的。

SDIN
在SCLK的上升沿采样。

3线接口的编写协议如图8所示。

•W is a control bit indicating a read or write operation. 0 =write operation, 1 = read operation •REGA[6:0] is the register Address.
•DIN[7:0] is the data to be written to the register being addressed.
•CSB is edge sensitive – the data is latched on the rising edge of CSB.
•W是一个控制位表明一个读或写操作。

0 =写操作,1 =读操作
•REGA[6:0]是寄存器地址。

•DIN[7:0]是数据它被写入到指定的寄存器地址。

•CSB是边缘敏感——数据被锁定在CSB的上升沿。

3-WIRE SERIAL CONTROL MODE REGISTER READ-BACK 3线串行控制模式寄存器读出
Not all registers can be read. Only the device ID (registers R0, R1 and R2) and the status registers
can be read. These status registers are labelled as “read only” in the Register Map section.
The read-only status registers can be read back via the SDOUT pin. The registers can be read by
one of two methods, selected by the CONT register bit and the ‘W’ control bit. The oscillator must be
powered up before 3-wire control interface read-back is possible.
When CONT =1 and ‘W’=0, a single read-only register can be read back by writing to any other
register or to a dummy register. The register to be read is determined by the READMUX[2:0] bits.
When a write to the device is performed, the device will respond by returning the status byte of the
register selected by the READMUX register bits. The data is returned on the SDOUT pin. This 3-wire
interface read-back method using a write access is shown in Figure 9.
并不是所有的寄存器可以被阅读。

仅有设备ID(寄存器R0、R1和R2)和状态寄存器可以
被读取。

在寄存器映射部分的这些状态寄存器都如同贴上“只读”的标签。

这些只读状态寄存器可以通过SDOUT脚读取。

这些寄存器可以通过两种方法之一读取，
选择CONT寄存器位和‘W’控制位。

这个振荡器必须在3在线控制接口读回之前上电才是可能的。

当CONT= 1,和' W‘= 0,一个只读寄存器用写给其它任何寄存器或虚拟寄存器来读取。

寄存器读取取决于READMUX[2:0)位。

当一个写入到设备被执行时,这设备将用挑选出的寄存器字节进行回应，这个状态字节就是
READMUX寄存器位。

这些数据在SDOUT脚返回。

这3线接口读取使用写访问方法见图9所示。

The SDOUT pin is tri-state unless CSB is held low; therefore CSB must be held low for the duration
of the read.
SDOUT脚是三态的除非CSB是低电平;为了持续地读因此CSB必须是低电平
The second method of reading the read only status registers is If CONT=0 and ‘W’=1. Using this method the user can read back directly from a register by reading the register address. The device
will respond with the contents of the register. The protocol for this read-back method is shown in
Figure 10.
第二种方法是读只读状态寄存器是如果CONT= 0,' W ' = 1。

使用这个方法用户可以通过读取寄存器地址
直接从寄存器读回。

该设备将回复寄存器内容。

这个协议对于读取方法显示在图10。

2-WIRE SERIAL CONTROL WITH READ-BACK MODE 2线串行控制读取模式
The WM8805 supports software control via a 2-wire serial bus. Many devices can be controlled by
the same bus and each device has a unique 7-bit address (see Table 11).
WM8805通过一个2线串行总线支持软件控制。

许多设备可以被相同的总线控制并且每个
设备都有一个独立的7位地址(见表11)。

The controller indicates the start of data transfer with a high to low transition on SDIN while SCLK
remains high. This indicates that a device address, DEVA(7:1), and data, REG(6:0), will follow. All
devices on the 2-wire bus will shift in the next eight bits on SDIN (7-bit address DEVA(7:1), + read/write ‘W’ bit, MSB first). If the device address received matches the address of the WM8805,
the WM8805 responds by driving SDIN low on the next clock pulse (ACK). This is a device acknowledgement of an address match. If the address does not match that of the WM8805, the
device returns to the idle condition and waits for a new start cond ition and valid address.
数据传送开始时，控制器显示在SDIN上的电平从高到低过渡，然而SCLK仍然维持高电平。

这表明一个设备地址DEVA (7:1)和数据REG(6:0)将紧随。

所有设备在CI2总线上将
在SDIN上移入下一个8位数据（7位地址DEVA(7:1),+读/写' W '位,MSB打头)。

如果收到设备地址
与WM8805地址相匹配,这个WM8805在下一个时钟脉冲(ACK)期间驱动SDIN为低电平作为响
应。

这是设备的一个地址匹配确认。

如果这个WM8805的地址不匹配,设备返回到空闲状态,
并等待一个新的开始条件和有效地址。

Once the WM8805 has acknowledged a matching address, the controller sends the first byte of
control data, which is the WM8805 register address (REGA[6:0]). The WM8805 then acknowledges
reception of the control data byte by pulling SDIN low for one clock pulse (another ACK). The controller then sends the second byte of control data (DIN[7:0], i.e. the eight bits of register data to
be written), and the WM8805 acknowledges again by pulling SDIN low (another ACK).
The transfer of data is complete when there is a low to high transition on SDIN while SCLK is high.
After receiving a complete address and data sequence the WM8805 returns to the idle state and
waits for another start condition. If a start or stop condition is detected out of sequence at any point
during data transfer (i.e. SDIN changes while SCLK is high), the device returns to the idle condition.
一旦WM8805确认一个匹配的地址,控制器发送控制数据的第一个字节,这是WM8805寄存
器地址(REGA[6:0])。

然后这个WM8805在一个时钟脉冲（另一个ACK)拉低SDIN电平来确认接
收的控制数据字节。

这个控制器然后发送第二个字节的控制数据(DIN[7:0],即写入寄存器的8位数据),
并且WM8805用拉低SDIN(另一个ACK)再次确认。

当在SDIN上电平有一个从低到高转换然而SCLK仍是高电平，数据传送的是完整。

在收到
一个完整的地址和数据序列后WM8805返回到空闲状态和等待另一个开始状态。

如果一个启动
或停止条件被检测出在数据传输任何时刻SDIN变化而SCLK高电平),设备返回到空闲状态。

Multiple consecutive register writes can be performed in 2-wire control mode by setting the CONT bit
high. This method allows the entire register map to be defined in a one continuous write operation.
多个连续的寄存器写入可以在I2C控制模式通过设置CONT位为高电平执行。

这种方法允许整
个寄存器映射定义在一个连续的写操作。

The WM8805 has two possible device addresses, which can be selected using the CSB pin during
hardware reset.
有两个可能的WM8805设备地址,在硬件复位期间可以使用CSB脚选择WM8805设备地址。

2-WIRE SERIAL CONTROL MODE -REGISTER READ-BACK I2C线串行控制模式寄存器读出
The WM8805 allows read-back of certain registers in 2-wire mode. The protocol is similar to that
used to write to the device. The controller will issue the device address followed by a write bit, the
register index will then be passed to the WM8805. At this point the controller will issue a repeated
start condition and resend the device address along with a read bit. The WM8805 will acknowledge
this and the WM8805 will become a slave transmitter. The WM8805 will transmit the data from the
indexed register on SDIN MSB first. When the controller receives the data it will not
acknowledge
receipt of the data indicating that it will resume master transmitter control of SDIN. The controller will
then issue a stop command completing the read cycle. Figure 13 illustrates the read protocol.
这个WM8805允许某些寄存器在I2C模式下读出。

协议类似于设备的写入。

控制器将
发布一个设备地址随后紧跟着一个写入位,寄存器索引将被传递到WM8805。

此时此刻控制
器将发出一个重复启动条件和发送设备地址连同一位R（读操作位）。

这个WM8805将进行
应答并且WM8805将变为从发射机。

这个WM8805将在SDIN上第一MSB索引寄存器传输数据，
当控制器接收数据不回应表明它将恢复主发射机SDIN的控制。

然后控制器将发出停止命令完成
读周期。

图13展示了阅读协议。

2-WIRE SERIAL CONTROL MODE – CONTINUOUS READ-BACK 2线串行控制模式——连续读取
As in 3-wire mode, there are two methods of reading back data: continuous and non-continuous
read-back. Continuous read-back is selected by setting CONT to 1. In continuous read-back mode,
the device will return the indexed register first followed by consecutive registers in increasing index
order until the controller does not acknowledge the data then issues a stop sequence. This is shown
in Figure 14
在3线模式,有两种方法:连续的回读数据和非连续读取。

连续选择回读通过设置CONT到1。

在连续回读模式,该设备将首先返回索引寄存器其次是用增加连续索引寄存器的指针直到控制器
不承认连续索引寄存器数据。

这是显示在图14
SOFTWARE REGISTER RESET 软件寄存器复位
Writing to register 0000000 will reset the WM8805. This will reset all register bits to their default
values. Note that the WM8805 is powered down by default so writing to this register will power down
the device.
DEVICE ID AND REVISION IDENTIFICATION 设备ID和版本识别
Registers 0,1 and 2 can be read to identify the device ID and IC revision number. Refer to Table 12
for details.
写寄存器0000000，WM8805将重置。

这将重置所有寄存器为其默认值。

注意, WM8805在掉电时用缺省值写进这些寄存器,写这个寄存器将断电该设备。

寄存器0、1和2可以读取识别设备ID和IC修订编号。

参见表12详情。

HARDWARE CONTROL MODE 硬件控制模式
The WM8805 can be operated in either software or hardware control modes. The method of control
is determined by sampling the state of the SDIN pin during power up or hard reset. If SDIN is LOW
during power up or hardware reset, the WM8805 will be switched into hardware control mode.
无论在软件或硬件控制模式WM8805都能操作。

该控制的方法是由硬件复位SDIN脚采样的
状态所决定。

如果SDIN是低电平期间上电或硬件复位,WM8805将切换到硬件控制模式。

In hardware control mode the user has limited control over the configuration of the device. Most of
the features will assume default values but some can be configured using external pins. When the
device is configured in hardware control mode, all functions of the device are powered up.
The clock and data recovery module with the WM8805 will require a 12 MHz crystal derived
master clock as the default values for this module cannot be altered in Hardware Control mode.
在硬件控制模式下，用户享有有限的控制设备的配置。

大多数这些特性会由假设缺省值确定,
但一些配置可以使用外部管脚。

当装置被配置在硬件控制模式下,设备的所有功能由上电确定。

在硬件控制模式下，WM8805的时钟和数据恢复模块需要12 MHz晶振驱动，主时钟作为这个模
块的默认值不能修改。

MASTER / SLAVE MODE SELECTION主/从模式选择
The WM8805 can be configured in either master or slave mode In software control mode this is set
by writing to AIF_MS in the AIFRX register. In hardware control mode this is controlled by sampling
the SCLK pin on power up or hardware reset.
在软件控制模式下，WM8805可以配置为主或从模式这通过写AIFRX 寄存器里的AIF_MS
决定。

在硬件控制模式，这是由上电和硬件复位时对SCLK脚采样所控制。

DIGITAL ROUTING CONTROL 数字路由控制
See page 20 for a full description of the signal routing options available in the WM8805. In Software
control mode the values set in registers TXSRC and RXINSEL determine the S/PDIF Rx data source
and destination. In hardware control mode the device can receive data only from RX0 but can set the
value of TXSRC directly using the CSB pin. This determines the S/PDIF transmitter data source
在WM8805里所有信号路由描述选择见第20页。

在软件控制方式下，设定寄存器TXSRC
和RXINSEL的值决定了S / PDIFEL Rx数据源和目的地。

在硬件控制模式下,设备只能从RX0接收
数据，但可以直接使用CSB脚设置TXSRC的值。

这就决定了S / PDIF发射机数据源。

AUDIO INTERFACE CONTROL音频接口控制
In software control mode the audio data word length and audio data format can be set independently
for the receiver and transmitter sides of the interface. However, in hardware control mode both sides
of the interface are combined and the configuration is set using SDOUT and GPO0 pins as described
in Table 6 and Table 16. Note that AIF_CONF[1:0] configures the audio interface when the device
operates in hardware mode.
在软件控制模式下，音频数据字长和音频数据格式是能为接收机和发射机的界面接口独立地设置。

然而在硬件控制模式这两个接口的组合和配置使用SDOUT和GPO0脚设置，其描述在表6和表16。

注
意, 当设备在硬件模式运作AIF_CONF[1:0]配置音频接口。

STATUS INFORMATION 状态信息
In hardware control mode the WM8805 outputs a selection of status flags for the user. Table 17
describes the flags which are available and the output pins on which they are available.
在硬件控制模式下WM8805为用户输出一个选择的状态标志。

表17描述了可用的标志和输出端口,它们是可用的。

A full description of the status flags is given in Table 45.
给出一个完整的状态标志描述在表45。

Digital signal routing within the WM8805 is controlled by two registers, RXINSEL and TXSRC.
RXINSEL selects the S/PDIF input which is passed through the clock and data recovery circuit to the
S/PDIF receiver and TXSRC selects the data source that is passed to the S/PDIF transmitter.
In order to ensure proper operation when changing TXSRC, the S/PDIF transmitter module should be
powered down prior to changing the TXSRC control register and powered up again once the routing
path has been changed.
在WM8805内数字信号通路由两个寄存器,RXINSEL和TXSRC控制。

RXINSEL选择S / PDIF
的输入,输入信号通过时钟和数据恢复电路去S / PDIF接收机而TXSRC选择数据源,传递到S / PDIF
发射机。

为了确保正确操作，当改变TXSRC时,S / PDIF发射机模块应该断电前改变TXSRC控制寄存
器，在再一次上电时，路由路径已经被更改。

MASTER CLOCK AND PHASE LOCKED LOOP主时钟和锁相环路
SOFTWARE MODE INTERNAL CLOCKING 软件模式内部时钟
The WM8805 is equipped with a comprehensive clocking scheme that provides maximum flexibility
and function and many configurable routing possibilities for the user in software mode. An overview
of the software mode clocking scheme is shown in Figure 16.
这个WM8805为用户在软件模式下配备了一个全面的方案提供了最大的灵活性和功能和
许多可配置路由。

软件模式时钟方案的概述如图16
The clocking scheme can be divided into four sections. These are detailed as follows:
这个计时方案被分为四部份，详细说明如下：
OSCILLATOR 震荡器
primary function of the oscillator is to generate the oscillator clock (OSCCLK) for the PLL input.
Whenever the PLL or the S/PDIF receiver is enabled, the oscillator must be used to generate the
OSCCLK signal for the PLL.
The secondary function of the oscillator is to generate the OSCCLK so that it can be selected
internally as the clock source for:
•The MCLK output pin, when the pin is configured as an output.
•The CLKOUT output pin, when enabled.
The oscillator has one control bit as shown in Table 19. The oscillator must be powered up to
generate the OSCCLK signal.
震荡器主要的功能是为PLL输入产生时钟震荡，每当PLL或S/pdif接收器被使能，震荡器就必须
为PLL产生oscclk信号。

震荡器次要的功能是产生oscclk以便它被选择为内部的时钟源，为了：
*当MCLK被设定为输出脚时，MCLK脚作为主时钟输出。

以及
*当CLKOUT脚被使能时，此脚作CLKOUT输出脚。

震荡器有一个控制位如表19所示。

震荡器必须在上电后才能产生震荡信号。

The oscillator uses a Pierce type oscillator drive circuit. This circuit requires an external crystal and
appropriate external loading capacitors. The oscillator circuit contains a bias generator within the
WM8805 and hence an external bias resistor is not required. Crystal frequencies between 10 and
14.4MHz or 16.28 and 27MHz can be used in software mode. The recommended circuit is shown in
the recommended components diagram, please refer to Figure 29.
震荡器采用Pierce类型的震荡电路，这个电路需要一个外部晶振和适当的外部电容。

这
个在wm8805内的震荡电路包含了斜率发生器因而不再需要外部的偏压电阻。

在软件模式下
晶体频率为10-14.4MHz或16.28-27MHz之间。

被推荐的电路图请参考图29。

Alternatively, an external CMOS compatible clock signal can be applied to the XIN pin in the absence
of a crystal, although this is not recommended when using the PLL as the PLL requires a jitter-free
OSCCLK signal for optimum performance.
另外在没有晶振的情况下，外部的与COMS兼用的时钟信号加在XIN脚上，虽然这是不被
推荐的但因使用了PLL以及PLL需要的低抖晃率的ossclk信号可以获得最佳的操作特性。

PHASE-LOCKED LOOP (PLL)
The WM8805 has an on-chip phase-locked loop (PLL) circuit that can be used to synthesise clock
signals from the external oscillator clock. The PLL can be used to:
WM8805有一个片上锁相环（PLL)电路，它能被用于综合地处理外部时钟。

PLL能用于：
•Generate clocks necessary for the S/PDIF receiver to lock on to and recover S/PDIF data
from an incoming S/PDIF data stream.
从引入的s/pdif数据流中去跟踪时钟和恢复S/PDIF数据，从而产生S/PDIF接受器所
需要的时钟信号。

•Generate clocks which may be used to drive the MCLK and/or CLKOUT pins.
•Generate clocks which may be used by the S/PDIF transmitter to encode and transmit a
S/PDIF data stream.
*产生的时钟用于驱动MCLK和/或CLKOUT脚。

*产生的时钟可作为S/PDIF传输器，去编码和传输S/PDIF数据流。

The PLL can be enabled or disabled using the PLLPD register bit as shown in Table 1.
PLL能用PLLPD寄程器位打开或关闭，见表1，（表20）
The PLL has two modes of operation: PLL有两种操作模式。

•S/PDIF Receive Mode (Automatic PLL Mode – Selected if S/PDIF Receiver Enabled)
* S/PDIF接收模式（自动的PLL，如果S/PDIF接收使能）
In S/PDIF receive mode, the PLL is automatically controlled by the S/PDIF receiver to allow the
receiver to use the PLL to lock on to and track the incoming S/PDIF data stream.
Please refer to the S/PDIF Receiver section within the Internal Clocking description for full details.
If the CLKOUT or MCLK clocks are sourced from either CLK1 or CLK2 in this mode, the frequency
of these signals will be modified based on the clock rate of the incoming S/PDIF data stream. If the
sample rate of the incoming stream is changed, the MCLK and CLKOUT signals will continue to be
output, but will not be valid until the S/PDIF receiver has locked to the incoming stream at the new
sample rate. If the incoming S/PDIF stream stops, the PLL N and K values will be frozen and the
output clocks will continue at the frequency set by the last recovered S/PDIF stream. If the S/PDIF
input stream is removed then it is possible for the PLL to detect small pulse as the data is being
removed. This may result in the output clocks changing to an invalid frequency. Note also that if the
device is power-on and configured with no S/PDIF input data stream, then the PLL will default to
approximately 24MHz.
在接收模式下，由s/pdif接收器自动地控制PLL并允许接收器使用PLL去跟踪和锁
定引入的S/PDIF
数据流。

请参考S/PDIF接收器内部同步详细的描述部分。

在这种模式下，若CLKOUT或MCLK来源于CLK1或CLK2两者之一，这些信号频率被引入
S/PDIF数据流的时钟频率所调制。

如果引入的取样数据流速率改变了，MCLK和CLKOUT信号
仍旧被输出，但是要S/PDIF接收器锁定新的取样速率才行。

如果引入的S/PDIF数据流停止了，
PLL的N和K值将被冻结，输出时钟将会继续其频率靠以前恢复的S/PDIF数据流设定。

假如输入
的S/PDIF数据流被远离了，Pll就会侦测到很小的么冲如同数据的偏移一样。

这将导致输出时钟改
变到一个无效的频率。

注意如果pll上电和被配置时，没有S/PDIF输入数据流，那时pll将被定在
缺省值大约24M。

•User Mode (Manual PLL Mode – Selected if S/PDIF Receiver Disabled) 用户模式
In user mode, the user has full control over the PLL function and operation. In this mode, the user
can accurately specify the PLL N and K multiplier values (using the PLL_N and PLL_K registers),
divider values (PRESCALE and FREQMODE) and can hence control the generated CLK1 and CLK2
frequencies. Refer to Table 21 for details of the registers available for configuration in this mode.
在用户模式，用户能充分的控制pll功能和操作。

在这种模式下，用户能准确地指定pll N
和K乘数的值（使用PLL_N和PLL_K寄程器）。

除法器的值（PRESCALE和FREQMODE）由此去
控制CLK1和CLK2的频率。

在这种模式下参考表21有效寄程器详尽的配置。

PLL CONFIGURATION
The PLL performs a configurable frequency multiplication of the input clock signal (f1). The
multiplication factor of the PLL (denoted by ‘R’) is variable and is defined by the relationship: R = (f2 ÷
f1).
PLL执行可配置的输入时钟信号（f1)的倍频，pll倍频因子(用R表示）是一个变量，并定
义它与R=(f2/f1)相关联.
The multiplication factor is set using register bits PLL_N and PLL_K (refer to Table 21). The
multiplication effect of both the N and K multipliers are additive (i.e. if N is configured to provide a
multiplication factor of 8 and K is configured to provide a multiplication factor of 0.192, the overall
multiplication factor is 8 + 0.192 = 8.192).
这个倍频因子用寄程器PLL_K和PLL-N设置（参考表21）。

这个倍频因子由N 加k产生（例如：
N是8，k是0.192，全部的倍频因子是8+0.192=8.192）。

In order to choose and configure the correct values for PLL_N and PLL_K, multiplication factor R
must first be calculated. Once value R is calculated, the value of PLL_N is the integer (whole
number) value of R, ignoring all digits to the right of the decimal point. For example, if R is calculated
to be 8.196523, PLL_N is simply 8.
为了便于PLL_N和PLL_K选择和配置一个正确值，必须首先估算出倍频因子R，一旦值R
被估算出，PLL-N的值是R的整数部分，完全忽略小数点右边的所有的数。

例如：计算出
R为8.196523，PLL就为8.
Once PLL_N is calculated, the PLL_K value is simply the integer value of (222 (R-PLL_N)). For
example, if R is 8.196523 and PLL_N is 8, PLL_K is therefore (222 (8.196523-8)), which is 824277
(ignoring all digits to the right of the decimal point).
一旦估算出pll_N，pll-k值非常简单它是R-PLL_N的2的22次方分之一，例如若R是8.196523
以及pll-N是8，因此pll_K是(222 (8.196523-8)),它是824277，（忽略所有整数部分保留小数点右边
的部分）。

Note: the PLL is designed to operate with best performance (shortest lock time and optimum
stability) when f2 is between 90 and 100MHz and PLL_N is 8. However, acceptable PLL_N values lie
in the range 5 ≤PLL_N ≤13. Do not use values outwith this range and it is recommended that the
chosen value of PLL_N is as close to 8 as possible for optimum performance.
注意：当f2在90到100MHz之间并且pll_N是8，PLL具有最好的性能，然而可接受地pll_N
值得范围是5《pll_N<13.不能超出这个范围以外和建议选择的pll_N的值尽可能接近8为获得最佳性能。

An output divider is provided to allow the f2 clock signal to be divided to a frequency suitable for use
as the source for the MCLK, CLKOUT or S/PDIF transmitter. The divider output is configurable and is
set by the FREQMODE bits. The PLL is also equipped with a pre-scale divider which offers
frequency divide by one or two before the OSCCLK signal is fed to the PLL. Please refer to Table 22
for details.
注意：输出的除法器提供了从容许的f2时钟信号，它将分离出适当的频率源如MCLK，CLKOUT或S/PDIF 数据流。

除法器的输出由FREQMODE位来确定其配置和设定，在OSCCLK信号到pll之前，pll 还配备一个1或2的
分频器。

细节请参考表22.。