LM4863_IcpdfCom_1318331

合集下载

LM4863低电压AB类2.2W立体声音频功放IC应用原理及设计

LM4863低电压AB类2.2W立体声音频功放IC应用原理及设计注意事项LM4863典型应用图应用信息裸露DAP封装PCB装置考虑事项裸露DAP封装必须连接到地。

LM4863裸露DAP封装需要特别注意它的散热设计。

如果没有适当的处理散热设计问题，LM4863在驱动4Ω阻值时将进入热关断。

在LM4863底部的裸露DAP封装必须焊接到电路板的铜衬垫上。

裸露DAP封装的热量通过一个铜面传开。

如果铜面不在电路板的顶层表面上，需要使用8-10个直径小于或等于0.013英寸的通孔来把裸露DAP封装热耦合到铜平面上。

由于铜面是用来把裸露DAP封装中的热量散发出去，所以它应当尽可能的大一些。

如果散热片和放大器共用同一层PCB板，5V电压下驱动4Ω的负载，至少需要使用2.5in2面积的散热片。

不放在同一PCB层的LM4863在相同负载和工作电压下则需要5in2。

如果周围环境温度大于25℃，需要增大散热片的面积或使用风扇来确保LM4863的结温低于150℃的关断温度。

在功率特征曲线中有更多的说明。

当LM4863驱动3Ω负载情况时需要另加风扇。

当环境温度很高时，需要更大风力的风扇或更大面积的散热片以避免器件进入热关断。

驱动3Ω和4Ω负载时PCB布局及注意事项由于使用了低阻抗的负载，LM4863输出管脚连线电阻的大小会对输出功率有非常大的影响。

从LM4863的输出端到负载或负载连接器的连线必须尽可能宽。

输出连线的任何电阻都会降低输出功率。

举例来说，在输出使用一个4Ω的负载以及0.1Ω的连线电阻，那么负载的输出功率会从2.2W降低到2.0W。

输出功率的大小还取决于基准电源。

为了在大输出功率的情况下避免电源电压降低，电源连线也应当尽可能宽。

桥式配置说明如上图所示，LM4863内部有两对运放。

第一个放大器的增益是外部配置结构决定的，而第二个放大器是内部固定增益为单位增益，构成倒相装置。

第一个放大器的闭环增益是通过调节R f 与R i之间的比率来确定的，而第二个放大器的增益是通过两个20KΩ的内连电阻来固定的。

lm4863芯片工作原理

lm4863芯片工作原理
LM4863是一款双声道音频功率放大器芯片，适用于低压供应
电源应用。

以下为其工作原理：
1. 输入信号：LM4863中包含两个独立的音频放大器通道，每
个通道都有一个差分输入阶段。

输入信号经过输入电容耦合进入差动放大器，同时通过调整输入电阻来控制输入信号的增益。

2. 差分放大器：输入信号经过差分放大器，将差模信号（即信号的正负号之差）放大，并且抑制共模信号（即信号的正负号之和）。

这有助于提高信号的动态范围和抑制对地的共模噪声。

3. 功率驱动器：放大的信号经过一个功率输出级别的引脚，通常为一个电容和电感组成的滤波网络。

这个网络用于减小输出的直流偏置，并限制短路电流。

这可以保护芯片和外部连接设备。

4. 输出级：放大后的信号通过输出级提供给连接的扬声器或耳机。

这个级别通常包含一个功率输出晶体管和一个负反馈网络，用于提高放大器的稳定性和线性度。

5. 供电电源：LM4863通过一个电源引脚从供电电源获取所需
的电源电压。

芯片内部包含一个负压电源调整电路和一个正压电源调整电路，将输入电源电压稳定为所需的工作电压。

综上所述，LM4863芯片通过差动放大器和输出级来放大输入
信号，并通过电源引脚提供所需的供电电压。

它适用于低压供应电源应用，如便携式音频设备和汽车音频系统。

LN4863功放

LN4863采用表面贴片式封装，仅需很少的外部元件，专用于高品质音频功率放大。为简化音频系统设计，LN4863将双桥扬声器功放和立体声耳机功放集成到一款芯片上。
LN4863内置了低功耗待机电路和过热保护电路，同时内置了杂音消除电路，可以消除芯片启动和关断过程中的咔嗒声或噼噗声。
■ 关键指标
功率输出@1% THD+N & VDD=5V LN4863LQ ,RL=3Ω，4Ω LN4863MTE，RL= 3Ω，4Ω LN4863MTE，RL=8Ω LN4863，RL=8Ω
单端耳机模式 THD+N@75mW into 32 Ω 关断电流供电电压
■ 产品特点
立体声耳机放大器模式 “咔嗒声和噼噗声”抑制电路稳定的固定增益热关断功能超小型封装：SOP,SOIC，TSSOP,LLP等
■ 用途
多媒体监听器笔记本和台式电脑便携电视
2.2 W双声道立体声集成耳机模式BTL音频功率放大器 LN4863系列
上海南麟电子有限公司
- 11 -

2.2W BTL音频功率放大器双声道立体声 & 耳机模式
2.2 W双声道立体声集成耳机模式BTL音频功率放大器 LN4863系列
LN4863 系列
■ 产品概述
LN4863为双声道桥接音频功率放大电路，在5V输入电压条件下，能够为4Ω负载提供2.2W功率的稳定输出,为3Ω负载提供2.5W功率的稳定输出，总谐波失真和噪声不超过1%。耳机输入端允许在驱动立体声耳机时采用单端模式。
■ 功能框图
2.2 W双声道立体声集成耳机模式BTL音频功率放大器 LN4863系列
图 1 LN4863 功能框图
■ 绝对最大额定值

L4863L-S18-T中文资料

UNISONIC TECHNOLOGIES CO., LTDL4863 CMOS ICDUAL 2.2W AUDIO AMPLIFIER PLUS STEREO HEADPHONE FUNCTIONDESCRIPTIONThe UTC L4863 is a dual bridge-connected audio power amplifier. It combines dual bridge speaker amplifiers and stereo headphone amplifiers on one chip to simplify audio system design.In addition, the headphone input pin allows the amplifiers to operate in single-ended mode when driving stereo headphones. The IC could deliver different power by packages as below (when connected to a 5V supply with less than 1.0% THD+N.): - HTSSOP-20, 4Ω load: 2.2W - HTSSOP-20, 3Ω load: 2.5W(with forced-air cooled) - SOP/DIP , 8Ω load: 1.1W.The UTC L4863 features an externally controlled, low-power consumption shutdown mode, a stereo headphone amplifier mode, and thermal shutdown protection. It also utilizes circuitry to reduce “clicks and pops” during device turn-on.FEATURES* “Click and pop” suppression * Thermal shutdown protection * Unity-gain stable* Stereo headphone amplifier mode*Pb-free plating product number: L4863LORDERING INFORMATIONOrder NumberNormal Lead Free PlatingPackage PackingL4863-D16-T L4863L-D16-T DIP-16 Tube L4863-S16-R L4863L-S16-R SOP-16 Tape Reel L4863-S16-T L4863L-S16-T SOP-16 TubeL4863-S18-R L4863L-S18-R SOP-18 Tape Reel L4863-S18-T L4863L-S18-T SOP-18 Tube L4863-N20-R L4863L-N20-R HTSSOP-20Tape Reel L4863-N20-T L4863L-N20-T HTSSOP-20TubePIN CONFIGURATIONTHERMAL DATAPARAMETER SYMBOL RATINGS UNITSOP-16 80 ℃/WSOP-18 90 ℃/WDIP-16 63 ℃/W Thermal resistance (Junction to Ambient)HTSSOP-20θJA90 ℃/WSOP-16 20 ℃/WSOP-18 2 ℃/WDIP-16 20 ℃/W Thermal resistance (Junction to Case)HTSSOP-20θJC2 ℃/WABSOLUTE MAXIMUM RATINGPARAMETER SYMBOL RATINGS UNITSupply Voltage V DD 6.0 V Recommended Supply Voltage Range V DD 2.0 ~ 5.5 V Input Voltage V IN -0.3 ~ V DD +0.3 VPower Dissipation P D Internally limitedJunction Temperature T J +125 ℃Operating Temperature T OPR -40 ~ +85 ℃Storage Temperature T STG -65 ~ +150 ℃Note Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied.ELECTRICAL CHARACTERISTICS (Notes 1)(V DD =5V, Ta =25, ℃unless otherwise specified)PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITFOR ENTIRE ICSupply Voltage V DD 2 5.5V V IN =0V, I OUT =0A, HP-IN=0V6 11.5 20Quiescent Power Supply Current (Note 2) I DDV IN =0V, I OUT =0A, HP-IN=4V 5.8 mA Shutdown Current I SD V DD applied to the SHUTDOWN pin2 0.7 μA High V IH4 V Headphone Input VoltageLow V IL0.8VFOR BRIDGED-MODE OPERATION Output Offset VoltageV O(OFF)V IN =0V 5 50mVR L =3Ω 2.5THD=1%, f=1kHzR L =4Ω 2.2R L =3Ω 3.2 HTSSOP-20 THD+N=10%, f=1kHzR L =4Ω 2.7 WTHD=1%, f=1kHz R L =8Ω 1.0 1.1THD+N=10%, f=1kHz R L =8Ω 1.5WOutput Power(measured at the device terminals) SOP/DIP P OUT THD+N=1%, f=1kHz, RL=32Ω 0.34 W HTSSOP-20 R L =4Ω, P OUT =2W0.3 Total Harmonic Distortion + Noise SOP/DIP THD+N 20Hz ≤f ≤20kHz, A VD =2 R L =8Ω, P OUT =1W 0.3 %Power Supply Rejection Ratio PSRRV DD =5V, V RIPPLE =200mV RMS , R L =8Ω,C B =1.0μF67 dB Channel Separation X TALK f =1kHz, C B =1.0μF 90 dB Signal To Noise Ratio SNR V DD =5V, P OUT =1.1W, R L =8Ω 98 dB FOR SINGLE-ENDED OPERATION Output Offset Voltage V O(OFF)V IN =0V 5 50mVTHD=0.5%, f=1kHz, R L =32Ω 75 85THD+N=1%, f=1kHz, R L =8Ω 340Output Power P OUT THD+N=10%, f=1kHz, R L =8Ω 440 mW Total Harmonic Distortion + Noise THD+N A V =-1, P OUT =75mW,20Hz ≤f ≤20kHz, R L =32Ω0.2%Power Supply Rejection Ratio PSRR C B =1.0μF, V RIPPLE =200mV RMS, f =1kHz 52 dB Channel Separation X TALK f =1kHz, C B =1.0μF 60 dB Signal To Noise Ratio SNR V DD =5V, P OUT =340mW, R L =8Ω 95 dB Note:1. All voltages are measured with respect to the ground (GND) pins, unless otherwise specified.2. Depends on the offset voltage when a practical load is connected to the amplifier.3. When driving 3Ω or 4Ω and operating on a 5V supply, the HTSSOP-20 package must be mounted to the circuit board that has a minimum of 2.5 in 2 of exposed, uninterrupted copper area connected to the exposed-DAP.TYPICAL APPLICATION CIRCUITAudioInputAudioInputNote: Pin out shown for DIP-16 and SOP-16 packages. Refer to the PIN CONFIGURATION for the pin out of other packages.Figure 1.Typical Audio Amplifier Application CircuitEXTERNAL COMPONENTS DESCRIPTIONComponents FunctionalDescriptionR I The inverting input resistance, along with R F, set the closed-loop gain. R I, along with C I form a high pass filter with fc=1/(2πR I C I)C I The input coupling capacitor blocks DC voltage at the amplifier’s input terminals. C I, along with R I, create a high pass filter with fc=1/(2πR I C I). Refer to the section. Selecting Proper External Components, for an explanation of determine the value of C I.R F The feedback resistance, along with R I, set the closed-Ioop gain.C S The supply bypass capacitor. Refer to the Power Supply Bypassing section for information about properly placing and selecting the value of, this capacitor.C B The capacitor, C B, filters the half-supply voltage present on the Bypass pin. Refer to the Selecting Proper External Components section for information concerning proper placement and selecting C B’S value.TYPICAL CHARACTERISTICS(For HTSSOP-20)THD+N(%)THD+N(%)THD+N vs Output PowerTHD+N(%)10m0.01100.1Level (W)THD+N vs FrequencyTHD+N(%)200.011100.11001k10k20k BW<80kHz P OUT=2.0W, BW<80kHzFrequency (Hz) PowerDissipation(W)TYPICAL CHARACTERISTICS(Cont.)(For DIP-16, SOP-16 and SOP-18)T H D +N (%)T H D +N (%)T H D +N (%)T H D +N (%)T H D +N (%)T H D +N (%)TYPICAL CHARACTERISTICS(Cont.)THD+N vs Output PowerTHD+N(%)10m1100.112Level (W)THD+N vs FrequencyTHD+N(%)201100.11001k10k20kFrequency (Hz) THD+N(%)THD+N(%)Output Power vs Load ResistanceLoad Resistance (Power Dissipation vs Supply VoltagePower Out (mW) f=1kHz, BW<80kHzTYPICAL CHARACTERISTICS(Cont.)O u t p u t P o w e r (W )O u t p u t P o w e r (W )O u t p u tPow er (W)O u t p u t P o w e r (W )10140Output Power vs Load resistance700.80.60.40.21% THD+N 10% THD+N20305060Load Resistance (Ω)22.500.70.75Output Power vs Supply Voltage1.25Output Power (W)0.60.50.40.30.2R L =160.51V DD =5V f=1kHzTHD+N Bridged Load BW<80kHzL =32ΩR L =8TYPICAL CHARACTERISTICS(Cont.)P o w e r D i s s i p a t i o n (W )O u t p u t N o i s e V o l t a g e (μv )O u t p u t L e v e l (d B )O u t p u t L e v e l (d B )P S R R (d B )G A I N (d B )P h a s e ( )oTYPICAL CHARACTERISTICS(Cont.)15Supply Current vs Supply VoltageSupply Voltage (V)SupplyCurrent(mA)12963DropoutVoltage(V)UTC assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all UTC products described or contained herein. UTC products are not designed for use in life support appliances, devices or systems where。

LM4863中文说明书完整

封装外形图二：（LM4863D）DIP16
第五页共六页
封装外形图三：（LM4863F）TSSOP 20
LM4863
第六页共六页
第二页共六页
LM4863
最大额定值（TA=25℃）
参数名称
符号
数值
单位
工作电压
Vdd
6.0
V
存储温度
Tstg
-65 to +150
℃
输入电压功率消耗
-0.3 to +(0.3+Vdd)
V
PD
见附注 1
W
结温度
150
℃
蒸发状态(60 秒)
215
℃
红外线 (15 秒)
220
℃
附注 1：最大功耗取决于三个因素：TJMAX，TA，θJA 它的计算公式 PDMAX=(TJMAX-TA)/θJA ,CSC4863 的 TJMAX=150℃. TA 为外部环境的温度，θJA 取决于不同的封装形式。（TSSOP 封装形式的为 20℃/W）
0.3
%
RL=8Ω
0.3
%
Vdd=4.9V to 5.1V
52
dB
最小谐波失真电源抑制比
THD
PSR R
f=1kHz,CB=1uF Vdd=5V, Po=1.1W
CB=1.0uF， VPIPPLE=200mVRMS,f=1khz
60
dB
95
dB
52
dB
通道隔离度
XTAL
K
f=1khz, CB=1.0uF
电特性
（除非特别说明，VCC=5V，RL=8Ω，f=1kHz，Tamb=25℃）

LX4863产品说明书

2005.8 第 1 页共 17 页≡LX≡ 2.2W 带立体声耳机输出模式的双声道音频功率放大器一．概述LX 是一种带立体声耳机输出模式的双声道音频功率放大芯片。

工作电压 5V ，负载为4Ω电阻时平均输出功率为2.2W ；负载为3Ω电阻时平均输出功率为2.5W ，且最大失真率低于1.0%。

另外，当驱动立体声耳机时，放大器可工作在单端模式。

本音频功率放大器只需要很少的外围设备，便可以提供高品质的输出功率，极大简化音频系统设计，在一块芯片上集合了双通道的桥式扬声器和立体声耳机。

采用外部控制的低功耗关断模式，立体耳机放大模式，以及内部热敏关断保护机制，并利用电路的特性减小噪声（滴答声及爆裂声）和失真度。

二．重要规格1．当输入信号频率为1kHz ，取THD+N 值为1％时，输出功率P O4863M/4863N/4863MTE ，接3Ω∕4Ω负载 2.5W(典型) ∕2.2W(典型) 4863MT ，接8Ω负载 1.2W(典型)2．单端模式，接32Ω负载，当平均输出功率为75mW 时，THD+N 0.5%(最大) 3．关断电流 0.1µA (典型) 4．电源电压范围 2.0V ～5.5V 三．特征1. 实现外围控制2. 低功率损耗与关断模式3. 立体声耳机放大器模式和热阻保护4. 通过电路设计滴答声抑制5. TSSOP-20/SOP-16/DIP-16封装形式四．应用1．多媒体监听器2．便携式计算机与台式计算机 3．便携式电视机、DVD 等LX4863LX4863LX4863LX4863LX LX LX LX2005.8 第 2 页共 17 页五．芯片封装引脚分布图1 、SOP16和DIP 封装图2 、TSSOP20封装说明：4863M （SOP16封装），4863N （DIP 封装），4863MT （TSSOP20封装）, 4863MTE （TSSOP20带散热片封装）。

IC datasheet pdf-OPA363,OPA2363,OPA364,OPA2364,OPA4364,pdf(1.8V, 7MHz, 90dB CMRR, Single-Supply Rail

DESCRIPTION
The OPA363 and OPA364 families are high-performance CMOS operational amplifiers optimized for very low voltage, single-supply operation. These miniature, low-cost amplifiers are designed to operate on single supplies from 1.8V (±0.9V) to 5.5V (±2.75V). Applications include sensor amplification and signal conditioning in battery-powered systems. The OPA363 and OPA364 families offer excellent CMRR without the crossover associated with traditional complimentary input stages. This results in excellent performance for driving Analog-to-Digital (A/D) converters without degradation of differential linearity and THD. The input commonmode range includes both the negative and positive supplies. The output voltage swing is within 10mV of the rails. The OPA363 family includes a shutdown mode. Under logic control, the amplifiers can be switched from normal operation to a standby current that is less than 1µA. The single version is available in the MicroSIZE SOT23-5 (SOT23-6 for shutdown) and SO-8. The dual version is available in MSOP-8, MSOP-10, and SO-8 packages. Quad packages are available in TSSOP-14 and SO-14 packages. All versions are specified for operation from –40°C to +125°C.

A7533 Datasheet v0[1].7(Preliminary)

A7533A/B <Preliminary> 4X2 Switch Matrix with Tone/Polarity ControllerDocument TitleData sheet of A7533.Revision HistoryRev. No.History Issue Date Remark0.1Initial issue.Jun. 25th, 2007Preliminary0.2Logo changed.Oct. 18th, 20070.3Change DC spec, truth table Dec. 7th , 20070.4Add B type Jan. 16th, 20080.5Modify ordering information, add top marking info., reflow profile Apr. 17th, 20080.6Change pin definition Jul, 15, 20080.7Modify typo of Pin 14 and Pin 16, add remark of application ckt. Jul, 08, 2009Important Notice:AMICCOM reserves the right to make changes to its products or to discontinue any integrated circuit product or service without notice. AMICCOM integrated circuit products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. Use of AMICCOM products in such applications is understood to be fully at the risk of the customer.A7533A/BTable of Contents1 Typical Applications (1)2 General Description (1)3 Pin Assignments (1)4 Block Diagram (2)5 Pin Configurations (3)6 Electrical Specifications (4)7 Absolute Maximum Ratings (4)8 Applications Circuit (5)9 Truth Table (6)10 Ordering Information (8)11 Package Information (9)12 Top Marking Information (10)13 Reflow Profile (12)14 Tape Reel Information (13)15 Product Status (16)A7533A/B<Preliminary> 4X2 Switch Matrix with Tone/Polarity Controller1 Typical Applications4*2 Switch Matrix for 0.2 -3.0 GHz Applications:n LNB n CATVn Cellular Systems n DBS2 General DescriptionA7533 is a low-cost 4 x 2 switch matrix with tone detector in a 20-lead QFN package for use in RF multiplexing applications from 200 to 3000 MHz. A positive voltage controlled 4 bit decoder and tone/polarity detector are both integrated on the switch with DiSEqC control signals rejection. A7533 is ok to be used in 50/75 ohm systems.Switch outputs (OP1 & OP2) can be independentlyselected from any of the four inputs (HH, HL, VH, VL) or simultaneously select the same inputs. Note that the switch is bi-directional and input/output functionality may be interchanged.3 Pin AssignmentsHLN.C.V2T2A75331234567891015141312112019181716N.C.T1VLN.C.V1N.C.OP2DC2OP1DC1VDDN.C.N.C.VHVHMHHA7533 QFN Package Top View4 Block Diagram1645 Tone/Polarity Controll CircuitV HV LO P 11O P 2V 2T 2DC1DC2H HH L2205 Pin ConfigurationsPin No.Pin NameFunction1112T1V1Tone and Polarity detector input.54V2T2Tone and Polarity detector input.1416202VL VH HH HL RF input pin106OP1OP2RF output pin9VDDPower pin, Connect to 3.6V power.1313151719N.C.No connection, Connect to PCB ground.18VHM Vertical-Horizontal Mirror.Connect to ground à Normal Leave open à Mirror.79DC2DC1By-pass , Connect to by-pass capacitor Back side paddleGNDConnect to ground.6 Electrical SpecificationsTypical condition: T A = +25°C, VDD= +3.3V, 50 ohm System. All RF port are terminated to 50 ohm .Parameter Condition Min.Typ.Max.Units SwitchInsertion Loss200 - 950 MHz950 - 1450 MHz1450 - 2150 MHz2150 - 3000 MHz666.576.56.57.598.57.5811dBIsolation200 - 950 MHz950 - 1450 MHz1450 - 2150 MHz2150 - 3000 MHz3531292337333125dBReturn Loss (Input; VL, HL, VH, HH)200 - 3000 MHz1215dB Return Loss (Output; OP1, OP2)200 - 3000 MHz1015dB Output IP3200 - 3000 MHz20dBm Input Power for 1 dB Compression200 - 3000 MHz15dBm Switching On/Off Speedt RISE / t FALL (10/90% RF)200 - 3000 MHz10ms Polarity and Tone DetectorPolarity Threshold With external 62KΩ1414.7515.5V Tone Signal Frequency-40~85℃, 650mVpp72278KHz Tone Signal Duty Cycle-40~85℃405060% Tone Signal Amplitude Threshold With external 62KΩand 500pF0.10.17Vpp Power supplySupply Voltage-40~85℃3 3.3 4.2V Current Consumption-40~85℃ 1.5 2.2 3.2mA Note:Tone/Polarization threshold could be tuned by change the value of external R,C. Please contact AMICCOM FAE for specified application.7 Absolute Maximum RatingsParameter RatingBias Voltage Range (VDD)+5 VDCStorage Temperature-65 to +150°COperating Temperature-40 to +85°CMaximum Input Power+17 dBm (200 - 3000 MHz)8 Applications CircuitNote 162K ohm resistors shall be kept in 1% tolerance.Note 2If 500 pF is not available, 470 pF is also acceptable.Note 3All capacitors shall be within 10 % tolerance. But, 5 % tolerance is preferred.9 Truth TableAbove figure show the function of VHM. (Vertical/Horizontal mirror)Above figure show the different between 7533A and 7533B (High/Low band upside down) V1,V2 = 0 means DC voltage =9.5~14V, V1, V2=1 means DC voltage =15.5~19VT1, T2=0 means 22KHz tone disappeared. T1, T2=1 means 22KHz tone appeared.A7533A When pin 18 “VHM” connected to GNDControl Input Outputto Input StateState V1T1V2T2OP1OP210000HH HH20001HH HL30010HH VH40011HH VL50100HL HH60101HL HL70110HL VH80111HL VL91000VH HH101001VH HL111010VH VH121011VH VL131100VL HH141101VL HL151110VL VH161111VL VLA7533A When pin 18 “VHM” open. Vertical and Horizontal will be mirror.Control Input Outputto Input StateState V1T1V2T2OP1OP210000VH VH20001VH VL30010VH HH40011VH HL50100VL VH60101VL VL70110VL HH80111VL HL91000HH VH101001HH VL111010HH HH121011HH HL131100HL VH141101HL VL151110HL HH161111HL HLA7533B When pin 18 “VHM” connected to GNDControl Input Outputto Input StateState V1T1V2T2OP1OP210000HL HL20001HL HH30010HL VL40011HL VH50100HH HL60101HH HH70110HH VL80111HH VH91000VL HL101001VL HH111010VL VL121011VL VH131100VH HL141101VH HH151110VH VL161111VH VHA7533A/B A7533B When pin 18 “VHM” open. Vertical and Horizontal will be mirror.Control Input Outputto Input StateState V1T1V2T2OP1OP210000VL VL20001VL VH30010VL HL40011VL HH50100VH VL60101VH VH70110VH HL80111VH HH91000HL VL101001HL VH111010HL HL121011HL HH131100HH VL141101HH VH151110HH HL161111HH HH10 Ordering InformationPart No.Package Units Per Reel / TrayA75X33AQF/Q QFN20L, Pb Free, Tape & Reel, -40℃〜85℃3KA75X33AQF QFN20L, Pb Free, Tray, -40℃〜85℃490EAA75X33BQF/Q QFN20L, Pb Free, Tape & Reel, -40℃〜85℃3KA75X33BQF QFN20L, Pb Free, Tray, -40℃〜85℃490EA11 Package InformationQFN 20L (4 X 4 X 0.8mm) Outline Dimensionsunit: inches/mm10615E 2e162051e bC 0.10M A B106L TOP VIEWBOTTOM VIEWCA 3A0.10//Cy CSeating PlaneDimensions in inches Dimensions in mm SymbolMin Nom Max Min Nom Max A 0.0280.0300.0320.700.750.80A 10.0000.0010.0020.000.020.05A 30.008 REF 0.203 REF b 0.0070.0100.0120.180.250.30D 0.1540.1580.161 3.90 4.00 4.10D 20.0750.0790.083 1.90 2.00 2.10E 0.1540.1580.161 3.90 4.00 4.10E 20.0750.0790.083 1.90 2.00 2.1012 Top Marking Information A75X33AQF¡Part No. :A75X33AQF ¡Pin Count :20¡Package Type :QFN¡Dimension :4*4 mm¡Mark Method :Laser Mark ¡Character Type :ArialA75X33BQF¡Part No. :A75X33BQF ¡Pin Count :20¡Package Type :QFN¡Dimension :4*4 mm¡Mark Method :Laser Mark ¡Character Type :Arial13 Reflow ProfileActual Measurement Graph14 Tape Reel InformationCover / Carrier Tape Dimension11 EA IC60cm ±4cmTYPE P A0B0P0P1D0D1E F W 20 QFN 4*48 4.35 4.35 4.0 2.0 1.5 1.5 1.75 5.51224 QFN 4*48 4.4 4.4 4.0 2.0 1.5 1.5 1.75 5.51232 QFN 5*58 5.25 5.25 4.0 2.0 1.5 1.5 1.75 5.51248 QFN 7*7127.257.25 4.0 2.0 1.5 1.5 1.757.516DFN-104 3.2 3.2 4.0 2.0 1.5- 1.75 1.9820 SSOP 128.27.5 4.0 2.0 1.5 1.5 1.757.51624 SSOP 128.28.8 4.0 2.0 1.5 1.5 1.757.51628 SSOP (150mil)86104.0 2.0 1.5 1.5 1.757.516TYPE K0K1t COVER TAPE WIDTH20 QFN (4X4) 1.1-0.39.224 QFN (4X4) 1.4-0.39.232 QFN (5X5) 1.1-0.39.248 QFN (7X7) 1.1-0.313.3DFN-100.75-0.25820 SSOP 2.5-0.313.324 SSOP 2.1-0.313.328 SSOP (150mil) 2.5-0.312.5A 040mil.NO COMPONENT LEADER LENGTH500minPP 1P 0D 0FWD 1Unit : mmREEL DIMENSIONSUNIT IN mmTYPE G N T M D K L R20 QFN(4X4)24 QFN(4X4) 32 QFN(5X5)DFN-1012.8+0.6/-0.4100 REF18.2(MAX)1.75±0.2513.0+0.5/-0.22.0±0.5330＋0.00/-1.020.248 QFN(7X7)16.8+0.6/-0.4100 REF22.2(MAX)1.75±0.2513.0+0.5/-0.22.0±0.5330＋0.00/-1.020.228 SSOP (150mil)20.4+0.6/-0.4100 REF25(MAX) 1.75±0.2513.0+0.5/-0.22.0±0.5330＋0.00/-1.020.220 SSOP24 SSOP16.4+2.0/-0.0100 REF22.4(MAX)1.75±0.2513.0+0.2/-0.21.9±0.4330＋0.00/-1.020.2MDTKUSE OF THE REEL FOR ‘/Q’ TYPEIC IC20 QFN(4X4); 32 QFN(5X5); 48QFN(7X7);SSOP28(150mil)RF ICs AMICCOM15 Product StatusData Sheet Identification Product StatusDefinitionObjectivePlanned or Under DevelopmentThis data sheet contains the design specifications for product development. Specifications may change in any manner without notice.PreliminaryEngineering Samples and First ProductionThis data sheet contains preliminary data, and supplementary data will be published at a later date.AMICCOM reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.No Identification Noted Full ProductionThis data sheet contains the final specifications.AMICCOM reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.Obsolete Not In ProductionThis data sheet contains specifications on aproduct that has been discontinued by AMICCOM.The data sheet is printed for reference information only.Headquarter5F, No.2, Li-Hsin Rd. 6, Hsinchu Science Park ,Taiwan 30078Tel: 886-3-5785818Taipei Office7F, No.407, Rueiguang Rd., Nei-Hu, Taipei,Taiwan 11492。

ML4823中文资料

May 1997ML4823High Frequency Power Supply ControllerFEATURESs Practical operation at switching frequencies to 1.0MHz s High current (2A peak) totem pole output s Wide bandwidth error amplifiers Fully latched logic with double pulse suppression s Pulse-by-pulse current limitings Soft start and max. duty cycle control s Under voltage lockout with hysteresis s 5.1V trimmed bandgap references Low start-up current (1.1mA)s Pin compatible improved replacement for UC3823s Fast shut down path from current limit to output s Soft start latch ensures full soft start cycle sOutputs pull low for undervoltage lockoutGENERAL DESCRIPTIONThe ML4823 High Frequency PWM Controller is an IC controller optimized for use in Switch Mode Power Supply designs running at frequencies to 1MHz.Propagation delays are minimal through the comparators and logic for reliable high frequency operation while slew rate and bandwidth are maximized on the error amplifier.This controller is designed for single-ended applications using voltage or current mode and provides for input voltage feed forward.A 1V threshold current limit comparator provides cycle-by-cycle current limit and exceeding a 1.4V threshold initiates a soft-start cycle. The soft start pin doubles as a maximum duty cycle clamp. All logic is fully latched to provide jitter-free operation and prevent multiple pulsing.An under-voltage lockout circuit with 800mV of hysteresis assures low startup current and drives the outputs low during fault conditions.This controller is an improved second source for the UC3823 controller; however, the ML4823 includesfeatures not found on the 3823. These features are set in italics.BLOCK DIAGRAM (Pin Configuration Shown for 16-Pin Version)ML4823 ABSOLUTE MAXIMUM RATINGSAbsolute maximum ratings are those values beyond whichthe device could be permanently damaged. Absolutemaximum ratings are stress ratings only and functionaldevice operation is not implied.Supply Voltage (V C, V CC) (30V)OUTPUT Current, Source or Sink DC.......................................................................0.5APulse (0.5µs).........................................................2.0AAnalog Inputs(INV, NI, RAMP, SS, I LIM)..................GND –0.3V to 6V CLOCK OUTPUT Current......................................–5mA F/A OUT Current......................................................5mA SOFT START Sink Current.......................................20mA R T Charging Current...............................................–5mA OPERATING CONDITIONSTemperature RangeML4823C..................................................0°C to 70°C ML4823I................................................–40°C to 85°C Junction Temperature............................................125°C Storage Temperature Range.....................–65°C to 150°C Lead Temperature (Soldering 10 sec.)....................260°C Thermal Resistance (θJA)Plastic DIP.......................................................80°C/W Plastic SOIC...................................................105°C/W Plastic Chip Carrier (PLCC)..............................78°C/WELECTRICAL CHARACTERISTICSUnless otherwise specified, R T = 3.65kΩ, C T = 1000pF, T A = Operating Temperature Range, V CC = 15V. (Note 1) PARAMETER CONDITIONS MIN TYP MAX UNITS OSCILLATORInitial Accuracy T J = 25°C,360400440kHz Voltage Stability10V ≤ V CC≤ 30V,0.22% Temperature Stability5% Total Variation Line, temp.340460kHz Clock Out High 3.9 4.5V Clock Out Low 2.3 2.9V Ramp Peak 2.6 2.8 3.0V Ramp Valley0.7 1.0 1.25V Ramp Valley to Peak 1.6 1.8 2.0V REFERENCEOutput Voltage T J = 25°C, I O = 1mA 5.025 5.10 5.175V Line Regulation10V ≤ V CC≤ 30V220mV Load Regulation1mA ≤ I O≤ 10mA520mV Temperature Stability–40°C ≤ T J≤ 150°C,0.20.4% Total Variation Line, load, temp. 4.975 5.225V Output Noise Voltage10Hz to 10kHz50µV Long Term Stability T J = 125°C, 1000 hrs,525mV Short Circuit Current V REF = 0V–15–50–100mA ERROR AMPLIFIERInput Offset Voltage±30mV Input Bias Current0.63µA Input Offset Current0.11µA Open Loop Gain 1 ≤ V O≤ 4V5095dBML4823ELECTRICAL CHARACTERISTICS (Continued)PARAMETER CONDITIONS MIN TYP MAX UNITS ERROR AMPLIFIER (Continued)CMRR 1.5 ≤ V CC≤ 5.5V5080dB PSRR10 ≤ V CC≤ 30V70100dB Output Sink Current V E/A OUT = 1V1 2.5mA Output Source Current V E/A OUT = 4V–0.5–1.3mA Output High Voltage I E/A OUT = –0.5mA 4.0 4.7 5.0V Output Low Voltage I E/A OUT = 1mA00.5 1.0V Unity Gain Bandwidth3 5.5MHz Slew Rate612V/µs PWM COMPARATORRAMP Bias Current V RAMP = 0V–1–5µA Duty Cycle Range080% E/A OUT Zero DC Threshold V RAMP = 0V 1.1 1.25V Delay to Output5080ns SOFT STARTCharge Current V SOFT START = 0.5V3920µA Discharge Current V SOFT START = 1V1mA CURRENT LIMIT/SHUTDOWNI LIM Bias Current0V ≤ I LIM≤ 4V±10µA Current Limit Offset I LIM REF = 1.1V015mV I LIM REF Common Mode Range 1.0 1.25V Shutdown Threshold 1.25 1.40 1.55V Delay to Output5080ns OUTPUTOutput Low Level I OUT = 20mA0.250.40VI OUT = 200mA 1.2 2.2V Output High Level I OUT = –20mA12.813.5VI OUT = –200mA12.013.0V Collector Leakage V C = 30V100500µA Rise/Fall Time C L = 1000pF3060ns UNDER VOLTAGE LOCKOUTStart Threshold8.89.29.7V UVLO Hysteresis0.40.8 1.2V SUPPLYStart Up Current V CC = 8V 1.1 2.5mA I CC INV, RANP, I LIM = 0V2233mANI = 1VNote 1:Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.ML4823 SOFT START AND CURRENT LIMITThe ML4823 employs two current limits. When thevoltage at I LIM/SD exceeds the I LIM REF threshold on I LIMREF, the outputs are immediately shut off and the cycle isterminated for the remainder of the oscillator period byresetting the RS flip flop.If the output current is rising quickly (usually due totransformer saturation) such that the voltage on pin 9reaches 1.4V before the outputs have turned off, a softstart cycle is initiated. The soft start capacitor is dischargedand outputs are held “off” until the voltage at SS reaches1V, ensuring a complete soft start cycle. The duty cycle onstart up is limited by limiting the output voltage of theerror amplifier voltage to the voltage at the SS pin.。

仕芯LM4863中文说明

0.3
%
RL=8Ω
0.3
%
Vdd=4.9V to 5.1V
52
dB
最小谐波失真电源抑制比
THD
PSR R
f=1kHz,CB=1uF Vdd=5V, Po=1.1W
CB=1.0uF， VPIPPLE=200mVRMS,f=1khz
60
dB
95
dB
52
dB
通道隔离度
XTAL
K
f=1khz, CB=1.0uF
-0.3 to +(0.3+Vdd)
V
PD
见附注 1
W
结温度
150
℃
蒸发状态(60 秒)
215
℃
红外线 (15 秒)
220
℃
附注 1：最大功耗取决于三个因素：TJMAX，TA，θJA 它的计算公式 PDMAX=(TJMAX-TA)/θJA ,CSC4863 的 TJMAX=150℃. TA 为外部环境的温度，θJA 取决于不同的封装形式。（TSSOP 封装形式的为 20℃/W）
封装外形图三：（LM4863F）TSSOP 20
LM4863
深圳仕芯半导体有限公司
ＴＥＬ：１３４８０７４３０５０ＱＱ２５４３４３２６２
第六页共六页
/04863
双通道立体声音频功率放大器
LM4863
概述与特点
LM4863 是一个双路音频功率放大器.它能够在 5V 电源电压下给一个 4Ω负载提供 THD 小于 10%、最大平均值为 2.46W 的输出功率。另外,在驱动立体声耳机时耳机输入引脚可以使放大器工作在单边模式。
LM4863 是为提供高保真音频输出而专门设计的.它仅仅需要少量的外围元件,为了简化音频系统设计， LM4863 集双路桥式扬声器放大器和立体声耳机放大器与一体。LM4863 还有外部控制的关闭模式，立体声耳机放大器模式和热保护关闭模式，还有减少开机噪声功能。

CS4863中文说明书

编号：CS4863-AX-BJ-39
1、概述
CS4863 是双桥接的音频功率放大器。当电源电压为 5V 时，在保证总谐波失真、噪声失真之和小于 1.0%的情况下，可向 4Ω负载提供 2.2W 的输出功率或者可向 3Ω负载提供 2.5W 的输出功率。另外，当驱动立体声耳机时，耳机输入端允许放大器工作在单端模式。
201201b1电气参数电路工作在桥接模式vdd5vta25cs4863符号参数条件典型极限单位极限os输出偏移电压50mvmax输出功率thdn1f1khzcs4863mtethdn10f1khzcs4863mter322525222211323227271503410thdn总谐波失真和噪20hzf20khzavd2wcs4863lq2wcs48631w030303psrr电源纹波抑制比dd5vripple200mvrms67dbtalk通道隔离度f1khzc10f90dbsnr信噪比dd5vr11w98db电气参数电路工作在单端模式vdd5vta25cs4863符号参数条件典型极限单位极限os输出偏移电压50mvmax输出功率thdn05f1khz32thdn1f1khzthdn10f1khz8534044075mwminmwmwthdn总谐波失真和噪75mw02psrr电源纹波抑制比ripple200mvrmsf1khzc10f52dbtalk通道隔离度f1khzc10f60dbsnr信噪比dd5vr340mw95dbtstab上电稳定时间033ufvdd5v240ms无锡中微爱芯电子有限公司wuxiicoreelectronicsco
应用信息
1.桥式配置说明
如图(1)所示，CS4863 内部有两对运算放大器，形成两个通道（通道 A 和通道 B）的立体声放大器。（以下为 A 通道的论述，同时也适合于 B 通道。）放大器 Amp1A 的增益是外部配置结构决定，闭环增益通过配置 Rf 和 Ri 的来决定，而放大器 Amp2A 被两个 20kΩ的内部电阻固定增益为-1，构成倒相

LM4863中文资料

LM4863Dual 2.2W Audio Amplifier Plus Stereo Headphone FunctionGeneral DescriptionThe LM4863is a dual bridge-connected audio power ampli-fier which,when connected to a 5V supply,will deliver 2.2W to a 4Ωload (Note 1)or 2.5W to a 3Ωload (Note 2)with less than 1.0%THD+N.In addition,the headphone input pin al-lows the amplifiers to operate in single-ended mode to drive stereo headphones.Boomer audio power amplifiers were designed specifically to provide high quality output power from a surface mount package while requiring few external components.To sim-plify audio system design,the LM4863combines dual bridge speaker amplifiers and stereo headphone amplifiers on one chip.The LM4863features an externally controlled,low-power consumption shutdown mode,a stereo headphone amplifier mode,and thermal shutdown protection.It also utilizes cir-cuitry to reduce “clicks and pops”during device turn-on.Note 1:An LM4863MTE which has been properly mounted to the circuit board will deliver 2.2W into 4Ω.The other package options for the LM4863will deliver 1.1W into 8Ω.See the Application Information section for LM4863MTE usage information.Note 2:An LM4863MTE which has been properly mounted to the circuit board and forced-air cooled will deliver 2.5W into 3Ω.Key Specificationsn P O at 1%THD+Ninto 3Ω(LM4863MTE) 2.5W(typ)into 4Ω(LM4863MTE) 2.2W(typ)into 8Ω(LM4863)1.1W(typ)n Single-ended mode -THD+N at 75mW into 32Ω0.5%(max)n Shutdown current0.7µA(typ)Featuresn Stereo headphone amplifier mode n “Click and pop”suppression circuitry n Unity-gain stablen Thermal shutdown protection circuitrynExposed-DAP TSSOP ,TSSOP ,SOIC and DIP packaging availableApplicationsn Multimedia monitorsn Portable and desktop computers n Portable televisionsTypical ApplicationBoomer ®is a registered trademark of National Semiconductor Corporation.DS012881-1*Refer to the section Proper Selection of External Components,for a detailed discussion of C B size.FIGURE 1.Typical Audio Amplifier Application CircuitOctober 1999LM4863Dual 2.2W Audio Amplifier Plus Stereo Headphone Function©1999National Semiconductor Corporation Connection DiagramsDS012881-28Top ViewOrder Number LM4863M,LM4863N See NS Package Number M16B for SO See NS Package Number N16A for DIPDS012881-2Top ViewOrder Number LM4863MTESee NS Package Number MXA20A for Exposed-DAP TSSOPL M 4863 2Absolute Maximum Ratings(Note4)If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.Supply Voltage 6.0V Storage Temperature−65˚C to+150˚C Input Voltage−0.3V to V DD+0.3V Power Dissipation(Note10)Internally limited ESD Susceptibility(Note11)2000V ESD Susceptibility(Note12)200V Junction Temperature150˚C Solder InformationSmall Outline PackageVapor Phase(60sec.)215˚C Infrared(15sec.)220˚C See AN-450“Surface Mounting and their Effects onProduct Reliablilty”for other methods of soldering surfacemount devices.Thermal ResistanceθJC(typ)—M16B20˚C/W θJA(typ)—M16B80˚C/W θJC(typ)—N16A20˚C/W θJA(typ)—N16A63˚C/W θJC(typ)—MTC2020˚C/W θJA(typ)—MTC2080˚C/W θJC(typ)—MXA20A2˚C/W θJA(typ)—MXA20A41˚C/W(Note7)θJA(typ)—MXA20A51˚C/W(Note5)θJA(typ)—MXA20A90˚C/W(Note6) Operating RatingsTemperature RangeT MIN≤T A≤T MAX−40˚C≤T A≤85˚C Supply Voltage 2.0V≤V DD≤5.5VElectrical Characteristics for Entire IC(Notes3,4)The following specifications apply for V DD=5V unless otherwise noted.Limits apply for T A=25˚C.Symbol Parameter Conditions LM4863Units(Limits)Typical Limit(Note13)(Note14)V DD Supply Voltage2V(min)5.5V(max)I DD Quiescent Power Supply Current V IN=0V,I O=0A(Note15),HP-IN=0V11.520mA(max)6mA(min)V IN=0V,I O=0A(Note15),HP-IN=4V 5.8mAI SD Shutdown Current V PIN1=V DD0.72µA(min) V IH Headphone High Input Voltage4V(min) V IL Headphone Low Input Voltage0.8V(max)Electrical Characteristics for Bridged-Mode Operation(Notes3,4)The following specifications apply for V DD=5V unless otherwise specified.Limits apply for T A=25˚C.Symbol Parameter Conditions LM4863Units(Limits)Typical Limit(Note 13)(Note 14)V OS Output Offset Voltage V IN=0V550mV(max) P O Output Power(Note9)THD=1%,f=1kHzLM4863MTE,R L=3Ω(Note7)2.5WLM4863MTE,R L=4Ω(Note8) 2.2WLM4863,R L=8Ω 1.1 1.0W(min)THD+N=10%,f=1kHzLM4863MTE,R L=3Ω(Note7) 3.2WLM4863MTE,R L=4Ω(Note8) 2.7LM4863,R L=8Ω 1.5WTHD+N=1%,f=1kHz,R L=32Ω0.34W THD+N Total Harmonic Distortion+Noise20Hz≤f≤20kHz,A VD=2LM4863MTE,R L=4Ω,P O=2W0.3LM4863,R L=8Ω,P O=1W0.3%PSRR Power Supply Rejection Ratio V DD=5V,V RIPPLE=200mV RMS,R L=8Ω,C B=1.0µF 67dBLM48633Electrical Characteristics for Bridged-Mode Operation (Notes 3,4)(Continued)The following specifications apply for V DD =5V unless otherwise specified.Limits apply for T A =25˚C.SymbolParameterConditionsLM4863Units (Limits)Typical Limit (Note 13)(Note 14)X TALK Channel Separation f =1kHz,C B =1.0µF90dB SNRSignal To Noise Ratio V DD =5V,P O =1.1W,R L =8Ω98dBElectrical Characteristics for Single-Ended Operation (Notes 3,4)The following specifications apply for V DD =5V unless otherwise specified.Limits apply for T A =25˚C.SymbolParameterConditionsLM4863Units (Limits)Typical Limit (Note 13)(Note 14)V OS Output Offset Voltage V IN =0V550mV (max)P OOutput PowerTHD =0.5%,f =1kHz,R L =32Ω8575mW (min)THD+N =1%,f =1kHz,R L =8Ω340mW THD+N =10%,f =1kHz,R L =8Ω440mW THD+N Total Harmonic Distortion+Noise A V =−1,P O =75mW,20Hz ≤f ≤20kHz,R L =32Ω0.2%PSRR Power Supply Rejection Ratio C B =1.0µF,V RIPPLE =200mV RMS ,f =1kHz52dB X TALK Channel Separation f =1kHz,C B =1.0µF60dB SNRSignal To Noise RatioV DD =5V,P O =340mW,R L =8Ω95dB Note 3:All voltages are measured with respect to the ground pins,2,7,and 15,unless otherwise specified.Note 4:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.Operating Ratings indicate conditions for which the device is func-tional,but do not guarantee specific performance limits.Electrical Characteristics state DC and AC electrical specifications under particular test conditions which guar-antee specific performance limits.This assumes that the device is within the Operating Ratings.Specifications are not guaranteed for parameters where no limit is given,however,the typical value is a good indication of device performance.Note 5:The θJA given is for an MXA20A package whose exposed-DAP is soldered to an exposed 2in 2piece of 1ounce printed circuit board copper.Note 6:The θJA given is for an MXA20A package whose exposed-DAP is not soldered to any copper.Note 7:When driving 3Ωloads from a 5V supply,the LM4863MTE must be mounted to the circuit board and forced-air cooled (450linear-feet per minute).Note 8:When driving 4Ωloads from a 5V supply,the LM4863MTE must be mounted to the circuit board.Note 9:Output power is measured at the device terminals.Note 10:The maximum power dissipation must be derated at elevated temperatures and is dictated by T JMAX ,θJA ,and the ambient temperature T A .The maximum allowable power dissipation is P DMAX =(T JMAX −T A )/θJA .For the LM4863,T JMAX =150˚C.For the θJA s for different packages,please see the Application Informa-tion section or the Absolute Maximum Ratings section.Note 11:Human body model,100pF discharged through a 1.5k Ωresistor.Note 12:Machine model,220pF–240pF discharged through all pins.Note 13:Typicals are measured at 25˚C and represent the parametric norm.Note 14:Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).Note 15:The quiescent power supply current depends on the offset voltage when a practical load is connected to the amplifier.Truth Table for Logic InputsSHUTDOWNHP-IN LM4863MODELow Low Bridged Low High Single-Ended High Low LM4863Shutdown HighHighLM4863ShutdownL M 4863 4External Components Description(Figure 1)Components Functional Description1.R i Inverting input resistance which sets the closed-loop gain in conjunction with R f .This resistor also forms a high pass filter with C i at f c =1/(2πR i C i ).2.C iInput coupling capacitor which blocks the DC voltage at the amplifier’s input terminals.Also creates ahighpass filter with R i at f c =1/(2πR i C i ).Refer to the section,Proper Selection of External Components ,for an explanation of how to determine the value of C i .3.R f Feedback resistance which sets the closed-loop gain in conjunction with R i .4.C s Supply bypass capacitor which provides power supply filtering.Refer to the Power Supply Bypassing section for information concerning proper placement and selection of the supply bypass capacitor.5.C BBypass pin capacitor which provides half-supply filtering.Refer to the section,Proper Selection of External Components ,for information concerning proper placement and selection of C B .Typical Performance Characteristics MTE Specific CharacteristicsNote 16:These curves show the thermal dissipation ability of the LM4863MTE at different ambient temperatures given these conditions:500LFPM +JEDEC board:The part is soldered to a 1S2P 20-lead exposed-DAP TSSOP test board with 500linear feet per minute of forced-air flow across it.Board information -copper dimensions:74x74mm,copper coverage:100%(buried layer)and 12%(top/bottom layers),16vias under the exposed-DAP .500LFPM +2.5in 2:The part is soldered to a 2.5in 2,1oz.copper plane with 500linear feet per minute of forced-air flow across it.2.5in 2:The part is soldered to a 2.5in 2,1oz.copper plane.Not Attached:The part is not soldered down and is not forced-air cooled.LM4863MTETHD+N vs Output PowerDS012881-97LM4863MTETHD+N vs FrequencyDS012881-99LM4863MTETHD+N vs Output PowerDS012881-96LM4863MTETHD+N vs FrequencyDS012881-98LM4863MTEPower Dissipation vs Power OutputDS012881-90LM4863MTE (Note 16)Power Derating CurveDS012881-95LM48635Non-MTE Specific CharacteristicsTHD+N vs FrequencyDS012881-3THD+N vs FrequencyDS012881-4THD+N vs FrequencyDS012881-5THD+N vs Output Power DS012881-6THD+N vs Output Power DS012881-7THD+N vs Output PowerDS012881-8THD+N vs Output Power DS012881-87THD+N vs Frequency DS012881-89THD+N vs Output PowerDS012881-88Output Power vs Load ResistanceDS012881-84Power Dissipation vs Supply VoltageDS012881-85L M 4863 6Non-MTE Specific Characteristics(Continued)Output Power vs Supply VoltageDS012881-9Output Power vs Supply VoltageDS012881-10Output Power vs Supply VoltageDS012881-11Output Power vs Load Resistance DS012881-12Output Power vs Load Resistance DS012881-13Power Dissipation vs Output PowerDS012881-14Dropout Voltage vs Supply VoltageDS012881-15Power Derating CurveDS012881-16Power Dissipation vs Output PowerDS012881-17Noise Floor DS012881-18Channel Separation DS012881-19Channel SeparationDS012881-20LM48637Non-MTE Specific Characteristics(Continued)Application InformationEXPOSED-DAP MOUNTING CONSIDERATIONSThe exposed-DAP must be connected to ground.The exposed-DAP package of the LM4863MTE requires special attention to thermal design.If thermal design issues are not properly addressed,an LM4863MTE driving 4Ωwill go into thermal shutdown.The exposed-DAP on the bottom of the LM4863MTE should be soldered down to a copper pad on the circuit board.Heat is conducted away from the exposed-DAP by a copper plane.If the copper plane is not on the top surface of the cir-cuit board,8to 10vias of 0.013inches or smaller in diameter should be used to thermally couple the exposed-DAP to the plane.For good thermal conduction,the vias must be plated-through and solder-filled.The copper plane used to conduct heat away from the exposed-DAP should be as large as pratical.If the plane is on the same side of the circuit board as the exposed-DAP ,2.5in 2is the minimum for 5V operation into 4Ω.If the heat sink plane is buried or not on the same side as the exposed-DAP ,5in 2is the minimum for 5V operation into 4Ω.If the am-bient temperature is higher than 25˚C,a larger copper plane or forced-air cooling will be required to keep the LM4863MTE junction temperature below the thermal shut-down temperature (150˚C).See the power derating curve for the LM4863MTE for derating information.The LM4863MTE requires forced-air cooling when operating into 3Ω.With the part attached to 2.5in 2of exposed copper,with a 3Ωload,and with an ambient temperature of 25˚C,450linear-feet per minute kept the part out of thermal shut-down.In higher ambient temperatures,higher airflow rates and/or larger copper areas will be required to keep the part out of thermal shutdown.See DEMOBOARD CIRCUIT LAYOUT for an example of an exposed-DAP TSSOP circuit board layout.3Ω&4ΩLAYOUT CONSIDERATIONSWith low impedance loads,the output power at the loads is heavily dependent on trace resistance from the output pins of the LM4863.Traces from the output of the LM4863MTE to the load or load connectors should be as wide as practical.Any resistance in the output traces will reduce the power de-livered to the load.For example,with a 4Ωload and 0.1Ωof trace resistance in each output,output power at the load drops from 2.2W to 2.0WOutput power is also dependent on supply regulation.To keep the supply voltage from sagging under full output power conditions,the supply traces should be as wide as practical.BRIDGE CONFIGURATION EXPLANATIONAs shown in Figure 1,the LM4863has two pairs of opera-tional amplifiers internally,allowing for a few different ampli-fier configurations.The first amplifier’s gain is externally con-figurable,while the second amplifier is internally fixed in a unity-gain,inverting configuration.The closed-loop gain of the first amplifier is set by selecting the ratio of R f to R i while the second amplifier’s gain is fixed by the two internal 20k Ωresistors.Figure 1shows that the output of amplifier one serves as the input to amplifier two which results in both am-plifiers producing signals identical in magnitude,but out of phase 180˚.Consequently,the differential gain for each channel of the IC isA VD =2*(R f /R i )By driving the load differentially through outputs +OutA and −OutA or +OutB and −OutB,an amplifier configuration com-monly referred to as “bridged mode”is established.Bridged mode operation is different from the classical single-ended amplifier configuration where one side of its load is con-nected to ground.A bridge amplifier design has a few distinct advantages over the single-ended configuration,as it provides differential drive to the load,thus doubling the output swing for a speci-fied supply voltage.Four times the output power is possible as compared to a single-ended amplifier under the same conditions.This increase in attainable output power as-sumes that the amplifier is not current limited or clipped.In order to choose an amplifier’s closed-loop gain without caus-ing excessive clipping,please refer to the Audio Power Am-plifier Design section.A bridge configuration,such as the one used in LM4863,also creates a second advantage over single-ended amplifi-ers.Since the differential outputs,+OutA,−OutA,+OutB,and −OutB,are biased at half-supply,no net DC voltage ex-ists across the load.This eliminates the need for an output coupling capacitor which is required in a single supply,single-ended amplifier configuration.If an output coupling capacitor is not used in a single-ended configuration,the half-supply bias across the load would result in both in-creased internal IC power dissipation as well as permanent loudspeaker damage.Power Supply Rejection RatioDS012881-21Open LoopFrequency ResponseDS012881-22Supply Current vs Supply Voltage 8Application Information(Continued)POWER DISSIPATIONWhether the power amplifier is bridged or single-ended, power dissipation is a major concern when designing the amplifier.Equation1states the maximum power dissipation point for a single-ended amplifier operating at a given supply voltage and driving a specified load.P DMAX=(V DD)2/(2π2R L):Single-Ended(1) However,a direct consequence of the increased power de-livered to the load by a bridge amplifier is an increase in in-ternal power dissipation.Equation2states the maximum power dissipation point for a bridge amplifier operating at the same given conditions.P DMAX=4*(V DD)2/(2π2R L):Bridge Mode(2) Since the LM4863is a dual channel power amplifier,the maximum internal power dissipation is2times that of Equa-tion1or Equation2depending on the mode of operation. Even with this substantial increase in power dissipation,the LM4863does not require heatsinking.The power dissipation from Equation2,assuming a5V power supply and an8Ωload,must not be greater than the power dissipation that re-sults from Equation3:P DMAX=(T JMAX−T A)/θJA(3) For packages M16A and MTA20,θJA=80˚C/W,and for package N16A,θJA=63˚C/W.T JMAX=150˚C for the LM4863.Depending on the ambient temperature,T A,of the system surroundings,Equation3can be used to find the maximum internal power dissipation supported by the IC packaging.If the result of Equation2is greater than that of Equation3,then either the supply voltage must be de-creased,the load impedance increased,or the ambient tem-perature reduced.For the typical application of a5V power supply,with an8Ωbridged load,the maximum ambient tem-perature possible without violating the maximum junction temperature is approximately48˚C provided that device op-eration is around the maximum power dissipation point and assuming surface mount packaging.Internal power dissipa-tion is a function of output power.If typical operation is not around the maximum power dissipation point,the ambient temperature can be increased.Refer to the Typical Perfor-mance Characteristics curves for power dissipation infor-mation for different output powers.POWER SUPPLY BYPASSINGAs with any power amplifier,proper supply bypassing is criti-cal for low noise performance and high power supply rejec-tion.The capacitor location on both the bypass and power supply pins should be as close to the device as possible.The effect of a larger half supply bypass capacitor is improved PSRR due to increased half-supply stability.Typical applica-tions employ a5V regulator with10µF and a0.1µF bypass capacitors which aid in supply filtering.This does not elimi-nate the need for bypassing the supply nodes of the LM4863.The selection of bypass capacitors,especially C B, is thus dependent upon desired PSRR requirements,click and pop performance as explained in the section,Proper Selection of External Components,system cost,and size constraints.SHUTDOWN FUNCTIONIn order to reduce power consumption while not in use,the LM4863contains a shutdown pin to externally turn off the amplifier’s bias circuitry.This shutdown feature turns the am-plifier off when a logic high is placed on the shutdown pin.The trigger point between a logic low and logic high level istypically half supply.It is best to switch between ground andthe supply V DD to provide maximum device performance.Byswitching the shutdown pin to V DD,the LM4863supply cur-rent draw will be minimized in idle mode.While the devicewill be disabled with shutdown pin voltages less than V DD,the idle current may be greater than the typical value of0.7µA.In either case,the shutdown pin should be tied to adefinite voltage to avoid unwanted state changes.In many applications,a microcontroller or microprocessoroutput is used to control the shutdown circuitry which pro-vides a quick,smooth transition into shutdown.Another solu-tion is to use a single-pole,single-throw switch in conjunctionwith an external pull-up resistor.When the switch is closed,the shutdown pin is connected to ground and enables theamplifier.If the switch is open,then the external pull-up re-sistor will disable the LM4863.This scheme guarantees thatthe shutdown pin will not float,thus preventing unwantedstate changes.HP-IN FUNCTIONThe LM4863possesses a headphone control pin that turnsoff the amplifiers which drive+OutA and+OutB so thatsingle-ended operation can occur and a bridged connectedload is muted.Quiescent current consumption is reducedwhen the IC is in this single-ended mode.Figure2shows the implementation of the LM4863’s head-phone control function using a single-supply headphone am-plifier.The voltage divider of R1and R2sets the voltage atthe HP-IN pin(pin16)to be approximately50mV when thereare no headphones plugged into the system.This logic-lowvoltage at the HP-IN pin enables the LM4863and places it inbridged mode operation.Resistor R4limits the amount ofcurrent flowing out of the HP-IN pin when the voltage at thatpin goes below ground resulting from the music coming fromthe headphone amplifier.The output coupling capacitors pro-tect the headphones by blocking the amplifier’s half supplyDC voltage.When there are no headphones plugged into the system andthe IC is in bridged mode configuration,both loads are es-sentially at a0V DC potential.Since the HP-IN threshold isset at4V,even in an ideal situation,the output swing cannotcause a false single-ended trigger.When a set of headphones are plugged into the system,thecontact pin of the headphone jack is disconnected from thesignal pin,interrupting the voltage divider set up by resistorsR1and R2.Resistor R1then pulls up the HP-IN pin,en-abling the headphone function.This disables the secondside of the amplifier thus muting the bridged speakers.Theamplifier then drives the headphones,whose impedance isin parallel with resistors R2and R3.Resistors R2and R3have negligible effect on output drive capability since thetypical impedance of headphones are32Ω.Also shown inFigure2are the electrical connections for the headphonejack and plug.A3-wire plug consists of a Tip,Ring andSleave,where the Tip and Ring are signal carrying conduc-tors and the Sleave is the common ground return.One con-trol pin contact for each headphone jack is sufficient to indi-cate to control inputs that the user has inserted a plug into ajack and that another mode of operation is desired.The LM4863can be used to drive both a pair of bridged8Ωspeakers and a pair of32Ωheadphones without using theHP-IN pin.In this case the HP-IN would not be connected tothe headphone jack but to a microprocessor or a switch.Byenabling the HP-IN pin,the8Ωspeakers can be muted.LM48639Application Information(Continued)PROPER SELECTION OF EXTERNAL COMPONENTS Proper selection of external components in applications us-ing integrated power amplifiers is critical to optimize device and system performance.While the LM4863is tolerant to avariety of external component combinations,consideration to component values must be used to maximize overall sys-tem quality.The LM4863is unity-gain stable,giving the designer maxi-mum system performance.The LM4863should be used in low gain configurations to minimize THD+N values,and maximize the signal to noise ratio.Low gain configurations require large input signals to obtain a given output power.In-put signals equal to or greater than 1Vrms are available from sources such as audio codecs.Please refer to the sec-tion,Audio Power Amplifier Design ,for a more complete explanation of proper gain selection.Besides gain,one of the major considerations is the closed-loop bandwidth of the amplifier.To a large extent,the bandwidth is dictated by the choice of external components shown in Figure 1.The input coupling capacitor,C i ,forms a first order high pass filter which limits low frequency re-sponse.This value should be chosen based on needed fre-quency response for a few distinct reasons.CLICK AND POP CIRCUITRYThe LM4863contains circuitry to minimize turn-on transients or “clicks and pops”.In this case,turn-on refers to either power supply turn-on or the device coming out of shutdown mode.When the device is turning on,the amplifiers are inter-nally configured as unity gain buffers.An internal current source ramps up the voltage of the bypass pin.Both the in-puts and outputs ideally track the voltage at the bypass pin.The device will remain in buffer mode until the bypass pin has reached its half supply voltage,1/2V DD .As soon as the bypass node is stable,the device will become fully opera-tional,where the gain is set by the external resistors.Although the bypass pin current source cannot be modified,the size of C B can be changed to alter the device turn-on time and the amount of “clicks and pops”.By increasing amount of turn-on pop can be reduced.However,the tradeoff for using a larger bypass capacitor is an increase in turn-on time for this device.There is a linear relationship be-tween the size of C B and the turn-on time.Here are some typical turn-on times for a given C B :C B T ON 0.01µF 20ms 0.1µF 200ms 0.22µF 420ms 0.47µF 840ms 1.0µF2SecIn order eliminate “clicks and pops”,all capacitors must be discharged before turn-on.Rapid on/off switching of the de-vice or the shutdown function may cause the “click and pop”circuitry to not operate fully,resulting in increased “click and pop”noise.In a single-ended configuration,the output cou-pling capacitor,C O ,is of particular concern.This capacitor discharges through the internal 20k Ωresistors.Depending on the size of C O ,the time constant can be relatively large.To reduce transients in single-ended mode,an external 1k Ω–5k Ωresistor can be placed in parallel with the internal 20k Ωresistor.The tradeoff for using this resistor is an in-crease in quiescent current.The value of C I will also reflect turn-on pops.Clearly,a cer-tain size for C I is needed to couple in low frequencies without excessive attenuation.But in many cases,the speakers used in portable systems,whether integral or external,have little ability to reproduce signals below 100Hz to 150Hz.In this case,using a large input and output capacitor may not increase system performance.In most cases,choosing a small value of C I in the range of 0.1µF to 0.33µF),along with C B equal to 1.0µF should produce a virtually clickless and popless turn-on.In cases where C I is larger than 0.33µF,it may be advantageous to increase the value of C B .Again,it should be understood that increasing the value of C B will reduce the “clicks and pops”at the expense of a longer device turn-on time.DS012881-24FIGURE 2.Headphone CircuitL M 486310Application Information(Continued)NO-LOAD DESIGN CONSIDERATIONSIf the outputs of the LM4863have a load higher than10kΩ,the LM4863may show a small oscillation at high output lev-els.To prevent this oscillation,place5kΩresistors from thepower outputs to ground.AUDIO POWER AMPLIFIER DESIGNDesign a1W/8ΩBridged Audio AmplifierGiven:Power Output:1WrmsLoad Impedance:8ΩInput Level:1VrmsInput Impedance:20kΩBandwidth:100Hz−20kHz±0.25dBA designer must first determine the minimum supply rail toobtain the specified output power.By extrapolating from theOutput Power vs Supply Voltage graphs in the Typical Per-formance Characteristics section,the supply rail can beeasily found.A second way to determine the minimum sup-ply rail is to calculate the required V opeak using Equation3and add the dropout ing this method,the mini-mum supply voltage would be(V opeak+(2*V od)),where V odis extrapolated from the Dropout Voltage vs Supply Voltagecurve in the Typical Performance Characteristics section.(4)Using the Output Power vs Supply Voltage graph for an8Ωload,the minimum supply rail is3.9V.But since5V is a stan-dard supply voltage in most applications,it is chosen for thesupply rail.Extra supply voltage creates headroom that al-lows the LM4863to reproduce peaks in excess of1W with-out producing audible distortion.At this time,the designermust make sure that the power supply choice along with theoutput impedance does not violate the conditions explainedin the Power Dissipation section.Once the power dissipation equations have been addressed,the required differential gain can be determined from Equa-tion4.(5)R f/R i=A VD/2(6)From equation4,the minimum A VD is2.83;use A VD=3Since the desired input impedance was20kΩ,and with aA VD of3,a ratio of1.5:1of R f to R i results in an allocation ofR i=20kΩand R f=30kΩ.The final design step is to ad-dress the bandwidth requirements which must be stated as apair of−3dB frequency points.Five times away from a polegives0.17dB down from passband response,which is betterthan the required±0.25dB specified.f L=100Hz/5=20Hzf H=20kHz x5=100kHzAs stated in the External Components section,R i in con-junction with C i create a highpass filter.C i≥1/(2π*20kΩ*20Hz)=0.397µF;use0.33µFThe high frequency pole is determined by the product of thedesired high frequency pole,f H,and the differential gain,AVD.With a A VD=3and f H=100kHz,the resulting GBWP=150kHz which is much smaller than the LM4863GBWP of3.5MHz.This figure displays that if a designer has a need todesign an amplifier with a higher differential gain,theLM4863can still be used without running into bandwidthproblems.DEMOBOARD CIRCUIT LAYOUTThe demoboard circuit layout is provided here as an ex-ample of a circuit using the LM4863.If an LM4863MTE isused with this layout,the exposed-DAP is soldered down tothe copper pad beneath the part.Heat is conducted awayfrom the part by the two large copper pads in the upper cor-ners of the demoboard.This demoboard provides enough heat dissipation ability toallow an LM4863MTE to output2.2W into4Ωat25˚C.DS012881-94All LayersDS012881-93Silk Screen LayerLM486311。

A43L2616AV-6中文资料

Preliminary 1M X 16 Bit X 4 Banks Synchronous DRAMDocument Title1M X 16 Bit X 4 Banks Synchronous DRAMRevision HistoryDate Remark Rev. No. History Issue issue November 30, 2004 Preliminary0.0 InitialA43L2616APreliminary1M X 16 Bit X 4 Banks Synchronous DRAMFeatureJEDEC standard 3.3V power supplyLVTTL compatible with multiplexed address Four banks / Pulse RAS MRS cycle with address key programs - CAS Latency (2,3)- Burst Length (1,2,4,8 & full page) - Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Clock Frequency: 166MHz @ CL=3 143MHz @ CL=3Burst Read Single-bit Write operationDQM for masking Auto & self refresh 64ms refresh period (4K cycle) Commercial Temperature Operation : 0°C~70°C Industrial Temperature Operation : -40°C~85°C for –U grade 54 Pin TSOP (II) and 54 Balls CSP (8mm x 8mm)General DescriptionThe A43L2616A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 X 1,048,576 words by 16 bits, fabricated with AMIC’s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock.I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.Pin ConfigurationTSOP (II)V S SD Q 15V S S QD Q 14D Q 13V D D QD Q 12D Q 11V S S QD Q 10D Q 9V D D QD Q 8V S SU D Q MC KC K EN CA 9A 8A 7A 6A 5A 4V S SV D DD Q 0V D D QD Q 1D Q 2V S S QD Q 3D Q 4V D D QD Q 5D Q 6V S S QD Q 7V D DL D Q MW EC A SR A SC SA 10/A PB S 1B S 0A 0A 1A 2A 3V D DA 11N CPin Configuration (continued)54 Balls CSP (8 mm x 8 mm)Top ViewBlock DiagramCLKADDDQiPin DescriptionsAbsolute Maximum Ratings*Voltage on any pin relative to VSS (Vin, Vout ) . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +4.6V Voltage on VDD supply relative to VSS (VDD, VDDQ ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to +4.6V Storage Temperature (T STG ) . . . . . . . . . . -55°C to +150°C Soldering Temperature X Time (T SLODER ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C X 10sec Power Dissipation (P D ) . . . . . . . . . . . . . . . . . . . . . . . . .1W Short Circuit Current (Ios) . . . . . . . . . . . . . . . . . . . . 50mA *CommentsPermanent device damage may occur if “Absolute Maximum Ratings” are exceeded.Functional operation should be restricted to recommended operating condition.Exposure to higher than recommended voltage for extended periods of time could affect device reliability.Capacitance (T A =25°C, f=1MHz)DC Electrical CharacteristicsRecommend operating conditions (Voltage referenced to VSS = 0V, T A = 0ºC to +70ºC or T A = -40ºC to +85ºC)Parameter Symbol Min Typ Max Unit NoteSupply Voltage VDD,VDDQ 3.0 3.3 3.6 VInput High Voltage V IH 2.0 3.0 VDD+0.3 VInput Low Voltage V IL -0.3 0 0.8 V Note 1 Output High Voltage V OH 2.4 --V I OH = -2mAOutput Low Voltage V OL - - 0.4 V I OL = 2mA Input Leakage Current I IL -5 - 5 µA Note 2 Output Leakage Current I OL -5 - 5 µANote 3Output Loading ConditionSee Figure 1Note: 1. V IL (min) = -1.5V AC (pulse width ≤ 5ns).2. Any input 0V ≤ VIN ≤ VDD + 0.3V, all other pins are not under test = 0V3. Dout is disabled, 0V ≤ Vout ≤ VDDDecoupling Capacitance Guide LineRecommended decoupling capacitance added to power line at board.Parameter Symbol Value UnitDecoupling Capacitance between VDD and VSS C DC1 0.1 + 0.01 µF Decoupling Capacitance between VDDQ and VSSQC DC20.1 + 0.01µFNote: 1. VDD and VDDQ pins are separated each other.All VDD pins are connected in chip. All VDDQ pins are connected in chip. 2. VSS and VSSQ pins are separated each otherAll VSS pins are connected in chip. All VSSQ pins are connected in chip.DC Electrical Characteristics(Recommended operating condition unless otherwise noted, T A = 0°C to 70°C T A = -40ºC to +85ºC) Note: 1. Measured with outputs open. Addresses are changed only one time during t CC (min).2. Refresh period is 64ms. Addresses are changed only one time during t CC (min).3. I CC6 normal version: A43L2616AV-6, A43L2616AV-7.4. I CC6 low self refresh current version: A43L2616AV-6V, A43L2616AV-7V.AC Operating Test Conditions(VDD = 3.3V ±0.3V, T A = 0°C to +70°C or T A = -40ºC to +85ºC)Parameter ValueAC input levelsV IH /V IL = 2.4V/0.4V Input timing measurement reference level 1.4VInput rise and all time (See note3)tr/tf = 1ns/1ns Output timing measurement reference level 1.4V Output load conditionSee Fig.2Output(Fig. 1) DC Output Load Circuit ΩTT =1.4V (Fig. 2) AC Output Load CircuitAC Characteristics(AC operating conditions unless otherwise noted)-6 -7Symbol Parameter CAS Latency Min Max Min MaxUnit Notet CC CLK cycle time 6 1000 7 1000 ns 1t SACCLK to valid Output delay- 5 - 5.4 ns 1,2 t OH Output data hold time 2.5-2.7-ns2t CH CLK high pulse width 32.5 - 2.5 - ns 3 t CL CLK low pulse width 2.5 - 2.5 - ns 3 t SS Input setup time 2 - 2 - ns 3 t SH Input hold time 1 - 1 - ns 3 t SLZ CLK to output in Low-Z 1-1-ns2t SHZCLK to output In Hi-Z3- 5.5 - 6 ns*All AC parameters are measured from half to half.Note : 1. Parameters depend on programmed CAS latency.2. If clock rising time is longer than 1ns, (tr/2-0.5) ns should be added to the parameter.3. Assumed input rise and fall time (tr & tf) = 1ns.If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.Operating AC Parameter(AC operating conditions unless otherwise noted)Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer.2. Minimum delay is required to complete write.Simplified Truth Table(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low) Note : 1. OP Code: Operand CodeA0~A11, BS0, BS1: Program keys. (@MRS)2. MRS can be issued only at both banks precharge state.A new command can be issued after 2 clock cycle of MRS.3. Auto refresh functions as same as CBR refresh of DRAM.The automatical precharge without Row precharge command is meant by “Auto”.Auto/Self refresh can be issued only at both precharge state.4. BS0, BS1 : Bank select address.If both BS1 and BS0 are “Low” at read, write, row active and precharge, bank A is selected.If both BS1 is “Low” and BS0 is “High” at read, write, row active and precharge, bank B is selected.If both BS1 is “High” and BS0 is “Low” at read, write, row active and precharge, bank C is selected.If both BS1 and BS0 are “High” at read, write, row active and precharge, bank D is selected.If A10/AP is “High” at row precharge, BS1 and BS0 is ignored and all banks are selected.5. During burst read or write with auto precharge, new read write command cannot be issued.Another bank read write command can be issued at every burst length.6. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0) butmasks the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2)Mode Register Filed Table to Program ModesRegister Programmed with MRS AddressBS0, BS1A11, A10A9A8A7A6A5A4A3A2A1A0FunctionRFURFU W.B.L TM CAS Latency BT Burst Length(Note 1)(Note 2)Test ModeCAS LatencyBurst TypeBurst LengthA8 A7TypeA6 A5 A4Latency A3TypeA2A1 A0 BT=0BT=10 0 Mode Register Set0 0 0Reserved0Sequential 00 0 1 1 0 1 0 0 1- 1Interleave 00 1 2 2 1 0 0 1 0 2 0 1 0 4 4 1 1Vendor Use Only0 1 1 3 0 1 188 Write Burst Length 1 0 0Reserved 10 0 Reserved Reserved A9 Length 1 0 1Reserved10 1 ReservedReserved0 Burst 1 1 0Reserved 1 1 0 Reserved Reserved 1 Single Bit 1 1 1Reserved11 1 256(Full)ReservedPower Up Sequence1. Apply power and start clock, Attempt to maintain CKE = “H”, DQM = “H” and the other pins are NOP condition at inputs.2. Maintain stable power, stable clock and NOP input condition for a minimum of 200µs.3. Issue precharge commands for all banks of the devices.4. Issue 2 or more auto-refresh commands.5. Issue a mode register set command to initialize the mode register. cf.) Sequence of 4 & 5 may be changed.The device is now ready for normal operation.Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.Burst Sequence (Burst Length = 4)Initial addressSequential Interleave A1 A00 0 0 1 2 3 0 1 2 30 1 1 2 3 0 1 0 3 21 023 0 1 2 3 0 11 1 3 0 123 2 1 0Burst Sequence (Burst Length = 8)Initial addressSequential Interleave A2 A1 A00 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 70 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 60 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 50 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 41 0 0 4 5 6 7 0 1234567 0 1 2 31 0 1 5 6 7 0 12345 4 76 1 0 3 21 1 0 6 7 0 1234567 4 5 2 3 0 11 1 1 7 0 1234567 6 5 4 3 2 1 0Device OperationsClock (CLK)The clock input is used as the reference for all SDRAM operations. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between V IL and V IH. During operation with CKE high all inputs are assumed to be in valid state (low or high) for the duration of set up and hold time around positive edge of the clock for proper functionality and ICC specifications.Clock Enable (CLK)The clock enable (CKE) gates the clock onto SDRAM. If CKE goes low synchronously with clock (set-up and hold time same as other inputs), the internal clock is suspended form the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. All other inputs are ignored from the next clock cycle after CKE goes low. When both banks are in the idle state and CKE goes low synchronously with clock, the SDRAM enters the power down mode form the next clock cycle. The SDRAM remains in the power down mode ignoring the other inputs as long as CKE remains low. The power down exit is synchronous as the internal clock is suspended. When CKE goes high at least “t SS + 1 CLOCK” before the high going edge of the clock, then the SDRAM becomes active from the same clock edge accepting all the input commands.Bank Select (BS0, BS1)This SDRAM is organized as 4 independent banks of 1,048,576 words X 16 bits memory arrays. The BS0, BS1 inputs is latched at the time of assertion of RAS and CASto select the bank to be used for the operation. The bank select BS0, BS1 is latched at bank activate, read, write mode register set and precharge operations.Address Input (A0 ~ A11)The 20 address bits required to decode the 262,144 word locations are multiplexed into 12 address input pins (A0~A11). The 12 bit row address is latched along with RAS, BS0 and BS1 during bank activate command. The 8 bit column address is latched along with CAS, WE, BS0 and BS1during read or write command.NOP and Device DeselectWhen , CAS and WE are high, the SDRAM performs no operation (NOP). NOP does not initiate any new operation, but is needed to complete operations which require more than single clock like bank activate, burst read, auto refresh, etc. The device deselect is also a NOP and is entered by asserting CS high. CS high disables the command decoder so that RAS, CAS and WE, and all the address inputs are ignored.Power-UpThe following sequence is recommended for POWER UP 1. Power must be applied to either CKE and DQM inputs topull them high and other pins are NOP condition at the inputs before or along with VDD (and VDDQ) supply.The clock signal must also be asserted at the same time.2. After VDD reaches the desired voltage, a minimumpause of 200 microseconds is required with inputs in NOP condition.3. Both banks must be precharged now.4. Perform a minimum of 2 Auto refresh cycles to stabilizethe internal circuitry.5. Perform a MODE REGISTER SET cycle to program theCAS latency, burst length and burst type as the default value of mode register is undefined.At the end of one clock cycle from the mode register set cycle, the device is ready for operation.When the above sequence is used for Power-up, all the out-puts will be in high impedance state. The high impedance of outputs is not guaranteed in any other power-up sequence.cf.) Sequence of 4 & 5 may be changed.Mode Register Set (MRS)The mode register stores the data for controlling the various operation modes of SDRAM. It programs the CAS latency, addressing mode, burst length, test mode and various vendor specific options to make SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after power up to operate the SDRAM. The mode register is written by asserting low on CS,RAS, CAS,(The SDRAM should be in active mode with CKE already high prior to writing the mode register). The state of address pins A0~A11, BS0 and BS1 in the same cycle as CS,,CAS,WE going low is the data written in the mode register. One clock cycle is required to complete the write in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as both banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length field uses A0~A2, burst type uses A3, addressing mode uses A4~A6, A7~A8, A11, BS0 and BS1 are used for vendor specific options or test mode. And the write burst length is programmed using A9. A7~A8, A11, BS0 and BS1 must be set to low for normal SDRAM operation.Refer to table for specific codes for various burst length, addressing modes and CAS latencies.Device Operations (continued)Bank ActivateThe bank activate command is used to select a random row in an idle bank. By asserting low on RAS and CS with desired row and bank addresses, a row access is initiated. The read or write operation can occur after a time delay of t RCD(min) from the time of bank activation. t RCD(min) is an internal timing parameter of SDRAM, therefore it is dependent on operating clock frequency. The minimum number of clock cycles required between bank activate and read or write command should be calculated by dividing t RCD(min) with cycle time of the clock and then rounding off the result to the next higher integer. The SDRAM has two internal banks on the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the activation of both banks immediately. Also the noise generated during sensing of each bank of SDRAM is high requiring some time for power supplies recover before the other bank can be sensed reliably. t RRD(min) specifies the minimum time required between activating different banks. The number of clock cycles required between different bank activation must be calculated similar to t RCD specification. The minimum time required for the bank to be active to initiate sensing and restoring the complete row of dynamic cells is determined by t RAS(min) specification before a precharge command to that active bank can be asserted. The maximum time any bank can be in the active state is determined by t RAS(max). The number of cycles for both t RAS(min) and t RAS(max) can be calculated similar to t RCD specification.Burst ReadThe burst read command is used to access burst of data on consecutive clock cycles from an active row in an active bank. The burst read command is issued by asserting low on CS and CAS with WE being high on the positive edge of the clock. The bank must be active for at least t RCD(min) before the burst read command is issued. The first output appears CAS latency number of clock cycles after the issue of burst read command. The burst length, burst sequence and latency from the burst read command is determined by the mode register which is already programmed. The burst read can be initiated on any column address of the active row. The address wraps around if the initial address does not start from a boundary such that number of outputs from each I/O are equal to the burst length programmed in the mode register. The output goes into high-impedance at the end of the burst, unless a new burst read was initiated to keep the data output gapless. The burst read can be terminated by issuing another burst read or burst write in the same bank or the other active bank or a precharge command to the same bank. The burst stop command is valid at every page burst length. Burst WriteThe burst write command is similar to burst read command, and is used to write data into the SDRAM consecutive clock cycles in adjacent addresses depending on burst length and burst sequence. By asserting low on CS,CAS and WE with valid column address, a write burst is initiated. The data inputs are provided for the initial address in the same clock cycle as the burst write command. The input buffer is deselected at the end of the burst length, even though the internal writing may not have been completed yet. The writing can not complete to burst length. The burst write can be terminated by issuing a burst read and DQM for blocking data inputs or burst write in the same or the other active bank. The burst stop command is valid only at full page burst length where the writing continues at the end of burst and the burst is wrap around. The write burst can also be terminated by using DQM for blocking data and precharging the bank “t RDL” after the last data input to be written into the active row. See DQM OPERATION also.DQM OperationThe DQM is used to mask input and output operation. It works similar to OE during read operation and inhibits writing during write operation. The read latency is two cycles from DQM and zero cycle for write, which means DQM masking occurs two cycles later in the read cycle and occurs in the same cycle during write cycle. DQM operation is synchronous with the clock, therefore the masking occurs for a complete cycle. The DQM signal is important during burst interrupts of write with read or precharge in the SDRAM. Due to asynchronous nature of the internal write, the DQM operation is critical to avoid unwanted or incomplete writes when the complete burst write is not required.PrechargeThe precharge operation is performed on an active bank by asserting low on CS,RAS,WE and A10/AP with valid BA of the bank to be precharged. The precharge command can be asserted anytime after t RAS(min) is satisfied from the bank activate command in the desired bank. “t RP” is defined as the minimum time required to precharge a bank. The minimum number of clock cycles required to complete row precharge is calculated by dividing “t RP” with clock cycle time and rounding up to the next higher integer. Care should be taken to make sure that burst write is completed or DQM is used to inhibit writing before precharge command is asserted. The maximum time any bank can be active is specified by t RAS(max). Therefore, each bank has to be precharged within t RAS(max) from the bank activate command. At the end of precharge, the bank enters the idle state and is ready to be activated again.Entry to Power Down, Auto refresh, Self refresh and Mode register Set etc, is possible only when both banks are in idle state.Device Operations (continued)Auto PrechargeThe precharge operation can also be performed by usingauto precharge. The SDRAM internally generates thetiming to satisfy t RAS(min) and “t RP” for the programmedburst length and CAS latency. The auto prechargecommand is issued at the same time as burst read or burstwrite by asserting high on A10/AP. If burst read or burstwrite command is issued with low on A10/AP, the bank isleft active until a new command is asserted. Once autoprecharge command is given, no new commands arepossible to that particular bank until the bank achieves idlestate.Four Banks PrechargeBoth banks can be precharged at the same time by using Precharge all command. Asserting low on CS,RAS and WE with high on A10/AP after both banks have satisfied t RAS(min) requirement, performs precharge on both banks.At the end of tRP after performing precharge all, bothbanks are in idle state.Auto RefreshThe storage cells of SDRAM need to be refreshed every64ms to maintain data. An auto refresh cycle accomplishesrefresh of a single row of storage cells. The internalcounter increments automatically on every auto refreshcycle to refresh all the rows. An auto refresh command is issued by asserting low on CS,RAS and CAS with high on CKE and WE. The auto refresh command can only be asserted with both banks being in idle state and the deviceis not in power down mode (CKE is high in the previouscycle). The time required to complete the auto refresh operation is specified by “t RC(min)”. The minimum number of clock cycles required can be calculated by driving “t RC” with clock cycle time and then rounding up to the next higher integer. The auto refresh command must be followed by NOP’s until the auto refresh operation is completed. Both banks will be in the idle state at the end of auto refresh operation. The auto refresh is the preferred refresh mode when the SDRAM is being used for normal data transactions. The auto refresh cycle can be performed once in 15.6us or a burst of 4096 auto refresh cycles once in 64ms.Self RefreshThe self refresh is another refresh mode available in the SDRAM. The self refresh is the preferred refresh mode for data retention and low power operation of SDRAM. In self refresh mode, the SDRAM disables the internal clock and all the input buffers except CKE. The refresh addressing and timing is internally generated to reduce power consumption.The self refresh mode is entered from all banks idle state by asserting low on CS,RAS,CAS and CKE with high on WE. Once the self refresh mode is entered, only CKE state being low matters, all the other inputs including clock are ignored to remain in the self refresh.The self refresh is exited by restarting the external clock and then asserting high on CKE. This must be followed by NOP’s for a minimum time of “t RC” before the SDRAM reaches idle state to begin normal operation. If the system uses burst auto refresh during normal operation, it is recommended to used burst 4096 auto refresh cycles immediately after exiting self refresh.Basic feature And Function Descriptions1. CLOCK SuspendNote: CLK to CLK disable/enable=1 clock2. DQM Operation* Note : 1. DQM makes data out Hi-Z after 2 clocks which should masked by CKE “L”.2. DQM masks both data-in and data-out.3. CAS Interrupt (I)Note : 1. By “Interrupt”, It is possible to stop burst read/write by external command before the end of burst.By “CAS Interrupt”, to stop burst read/write by CAS access; read, write and block write.2. t CCD : CAS to CAS delay. (=1CLK)3. t CDL : Last data in to new column address delay. (= 1CLK).4. CAS Interrupt (II) : Read Interrupted Write & DQM* Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.2. To prevent bus contention, DQM should be issued which makes a least one gap between data in and data out.5. Write Interrupted by Precharge & DQMNote : 1. To inhibit invalid write, DQM should be issued.2. This precharge command and burst write command should be of the same bank, otherwise it is not prechargeinterrupt but only another bank precharge of dual banks operation.6. Precharge7. Auto Precharge* Note : 1. The row active command of the precharge bank can be issued after t RP from this point.The new read/write command of other active bank can be issued from this point.At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.8. Burst Stop & Interrupted by Precharge9. MRSNote : 1. t RDL : 1CLK 2. t BDL : 1CLK; Last data in to burst stop delay.Read or write burst stop command is valid at every burst length.3. Number of valid output data after row precharge or burst stop: 1,2 for CAS latency = 2, 3 respectively.4. PRE: All banks precharge if necessary.MRS can be issued only when all banks are in precharged state.10. Clock Suspend Exit & Power Down Exit11. Auto Refresh & Self Refresh* Note : 1. Active power down : one or more bank active state.2. Precharge power down : both bank precharge state.3. The auto refresh is the same as CBR refresh of conventional DRAM.No precharge commands are required after Auto Refresh command.During t RC from auto refresh command, any other command can not be accepted.4. Before executing auto/self refresh command, both banks must be idle state.5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.6. During self refresh mode, refresh interval and refresh operation are performed internally.After self refresh entry, self refresh mode is kept while CKE is LOW.During self refresh mode, all inputs expect CKE will be don’t cared, and outputs will be in Hi-Z state.During t RC from self refresh exit command, any other command can not be accepted.Before/After self refresh mode, burst auto refresh cycle (4K cycles ) is recommended.12. About Burst Type ControlSequential counting At MRS A3=”0”. See the BURST SEQUENCE TABE.(BL=4,8) BL=1,2,4,8 and full page wrap around.BasicMODEInterleave counting At MRS A3=” 1”. See the BURST SEQUENCE TABE.(BL=4,8) BL=4,8 At BL=1,2 Interleave Counting = Sequential CountingRandom MODE Random column Accesst CCD = 1 CLKEvery cycle Read/Write Command with random column address can realizeRandom Column Access.That is similar to Extended Data Out (EDO) Operation of convention DRAM.13. About Burst Length ControlPower On Sequence & Auto RefreshCKECSRASCASADDRBS0, BS1A10/APWEDQMDQ(A-Bank)Single Bit Read-Write-Read Cycles (Same Page) @CAS Latency=3, Burst Length=1CLOCKCKECSRASCASADDRBS0, BS1A10/APWEDQMDQ* Note : 1. All inputs can be don’t care when CS is high at the CLK high going edge.2. Bank active & read/write are controlled by BS0, BS1.BS1 BS0 Active & Read/WriteA0 0 BankB0 1 BankC1 0 BankD1 1 Bank3. Enable and disable auto precharge function are controlled by A10/AP in read/write command.A10/AP BS1 BS0Operation0 0 Disable auto precharge, leave bank A active at end of burst.0 1 Disable auto precharge, leave bank B active at end of burst.1 0 Disable auto precharge, leave bank C active at end of burst.1 1 Disable auto precharge, leave bank D active at end of burst.0 0 Enable auto precharge, precharge bank A at end of burst.0 1 Enable auto precharge, precharge bank B at end of burst.11 0 Enable auto precharge, precharge bank C at end of burst.1 1 Enable auto precharge, precharge bank D at end of burst.4. A10/AP and BS0, BS1 control bank precharge when precharge command is asserted.A10/AP BS1 BS0 PrechargeA0 0 0 BankB0 0 1 BankC0 1 0 BankD0 1 1 BankBanks1 X X All。

LM4863中文资料

深圳市联拓辉电子有限公司
4863 双声道音频功率放大器-----4863
概述与特点
� 4863 是一款双音桥音频功率放大器芯片，采用 5.0V 电源供电，在 THD+N 小于 1.0％情况下，能为一个 3 Ω的负载持续提供 3W 的功率此外，当接立体耳机时，芯片可以单终端工作模式驱动立体耳机； � 4863 双通道音频功率放大器是为需要输出高质量音频功率的系统设计的，它采用表面贴装技术，只需少量的外围设备，便使系统具备高质量的音频输出功率。4863 采用双通道设计使芯片具有了桥式联接扬声器放大和单终端立体耳机放大两种工作模式，简化了音频系统的外围电路设计； � 4863 采用外部控制的低功耗关断模式，立体耳机放大模式，及内部热敏关断保护机制。并利用电路的特性减小噪声（滴答声与爆裂声）和失真度。
引脚分布图
4863-DIP/SOP 管脚分布图
4863-TSSOP20 管脚分布图
主要特性
� � � � � THD+N 为 1.0％时的输出功率为 3W
单端模式，负载为 32Ω，输出功率为 75mW 时，THD+N≤0.5％。关断漏电流 0.7μA 工作电压 2.0V～5.5V 高品质（典型）
深圳市联拓辉电子有限公司
封装原理图
典深圳市联拓辉电子有限公司

PFC IC tda4863-2_v2-1升级版

Datasheet, Version 2.1, 22 Feb 2005 PFC-DCM ICBoost ControllerTDA4863-2/TDA4863-2G Power-Factor Controller (PFC)IC for High Power Factorand Low THDPower Management & SupplyEdition 2005-02-22Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München© Infineon Technologies AG 1999. All Rights Reserved.Attention please!The information herein is given to describe certain components and shall not be considered as warranted charac-teristics.Terms of delivery and rights to technical change reserved.We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein.Infineon Technologies is an approved CECC rmationFor further information on technology, delivery terms and conditions and prices please contact your nearest Infi-neon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list).WarningsDue to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office.Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at CoolMOST™, CoolSET™ are trademarks of Infineon Technologies AG.TDA4863-2/TDA4863-2GRevision History:2005-02-22DatasheetPrevious Version: V2.0PageSubjects ( major changes since last revision )Update package informationTDA4863-2Table of Contents Page 1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2Improvements Referred to TDA 4862 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.5Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2IC Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3Voltage Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4Overvoltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.5Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.6Current Sense Comparator, LEB and RS Flip-Flop . . . . . . . . . . . . . . . . . . 10 2.7Zero Current Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.8Restart Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.9Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.10Gate Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.11Signal Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3Electrical Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1Results of THD Measurements with Application Board P out = 110 W . . . . 22 5Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Type Ordering Code PackageTDA4863-2 Q67040-S4620 PG-DIP-8-4TDA4863-2G Q67040-S4621 PG-DSO-8-3Power-Factor Controller (PFC) IC for High Power Factor and Low THD TDA4863-2Final DataBoost Controller1Overview1.1Features•IC for sinusoidal line-current consumption •Power factor achieves nearly 1•Controls boost converter as active harmonic filter for low THD•Start up with low current consumption •Zero current detector for discontinuous operation mode•Output overvoltage protection •Output undervoltage lockout •Internal start up timer • Totem pole output with active shut down • Internal leading edge blanking LEB • Pb-free lead plating ; RoHS compliant1.2Improvements Referred to TDA 4862 and TDA 4863• Suitable for universal input applications with low THD at low load conditions •Very low start up current•Accurate OVR and V ISENSEmax threshold •Competition compatible V CC thresholds •Enable threshold referred to V VSENSE•Compared to TDA4863 a bigger MOS Transistor can be driven (see 2.10)Figure 1Typical application1.3DescriptionThe TDA4863-2 IC controls a boost converter in a way that sinusoidal current is taken from the single phase line supply and stabilized DC voltage is available at the output. This active harmonic filter limits the harmonic currents resulting from the capacitor pulsed charge currents during rectification. The power factor which decibels the ratio between active and apparent power is almost one. Line voltage fluctuations can be compensated very efficiently.1.4Pin ConfigurationFigure 2Pin Configuration of TDA4863-2Pin Definitions and FunctionsPin Symbol Description1VSENSE Voltage Amplifier Inverting InputVSENSE is connected via a resistive divider to the boost converteroutput. With a capacitor connected to VAOUT the internal erroramplifier acts as an integrator.2VAOUT Voltage Amplifier OutputV VAOUT is connected internally to the first multiplier input. To preventovershoot the input voltage is clamped internally at 5 V. If V VAOUT isless then 2.2 V the gate driver is inhibited. If the current flowing intothis pin exceeds an internal threshold the multiplier output voltage isreduced to prevent the MOSFET from overvoltage damage.3MULTIN Multiplier InputMULTIN is the second multiplier input and is connected via a resistivedivider to the rectifier output voltage.4ISENSE Current Sense InputISENSE is connected to a sense resistor controlling the MOSFETsource current. The input is internally clamped at -0.3 V to preventnegative input voltage interaction. A leading edge blanking circuitrysuppresses voltage spits when turning the MOSFET on.5DETIN Zero Current Detector InputDETIN is connected to an auxiliary winding monitoring the zerocrossing of the inductor current.6GND Ground7GTDRV Gate Driver OutputGTDRV is the output of a totem-pole circuitry for direct driving aMOSFET. Compared with TDA4863 the TDA4863-2 can drive 20AMOSFETS. To achieve this the gate output voltage V GTL at I GT =0A hasbeen set to 0.85V. An active shutdown circuitry ensures that GTDRVis set to low if the IC is switched off.8VCC Positive Voltage SupplyIf V CC excees the turn-on threshold the IC is switched on. When Vccfalls below the turn-off threshold the IC is switched off. In switch offmode power consumption is very low. Two capacitors should beconnected to Vcc. An electrolytic capacitor and 100nF cermaniccapacitor which is used to absorb fast supply current spikes. Makesure that the electrolytic capacitor is discharged before the IC isplugged into the application board.1.5Block DiagramFigure 3Internal Bolck Diagram2Functional Description2.1IntroductionConventional electronic ballasts and switch mode power supplies are designed with a bridge rectifier and a bulk capacitor. Their disadvantage is that the circuit draws power from the line when the instantaneous AC voltage exceeds the capacitors voltage. This occurs near the line voltage peak and causes a high charge current spike with following characteristics: The apparent power is higher than the real power that means low power factor condition, the current spikes are non sinusoidal with a high content of harmonics causing line noise, the rectified voltage depends on load condition and requires a large bulk capacitor, special efforts in noise suppression are necessary.With the TDA4863-2 preconverter a sinusoidal current is achieved which varies in direct instantaneous proportional to the input voltage half sine wave and so provides a power factor near 1. This is due to the appearance of almost any complex load like a resistive one at the AC line. The harmonic distortions are reduced and comply with the IEC555 standard requirements.2.2IC DescriptionThe TDA4863-2 contains a wide bandwidth voltage amplifier used in a feedback loop, an overvoltage regulator, an one quadrant multiplier with a wide linear operating range, a current sense comparator, a zero current detector, a PWM and logic circuitry, a totem-pole MOSFET driver, an internal trimmed voltage reference, a restart timer and an undervoltage lockout circuitry.2.3Voltage AmplifierWith an external capacitor between the pins VSENSE and VAOUT the voltage amplifier acts like an integrator. The integrator monitors the average output voltage over several line cycles. Typically the integrator´s bandwidth is set below 20 Hz in order to suppress the 100 Hz ripple of the rectified line voltage. The voltage amplifier is internally compensated and has a gain bandwidth of 5 MHz (typ.) and a phase margin of 80 degrees. The non-inverting input is biased internally at 2.5 V. The output is directly connected to the multiplier input.The gate drive is disabled when VSENSE voltage is less than 0.2 V or VAOUT voltage is less than 2.2 V.If the MOSFET is placed nearby the controller switching interferences have to be taken into account. The output of the voltage amplifier is designed in a way to minimize these inteferences.2.4Overvoltage RegulatorBecause of the integrator´s low bandwidth fast changes of the output voltage can’t be regulated within an adequate time. Fast output changes occur during initial start-up, sudden load removal, or output arcing. While the integrator´s differential input voltage remains zero during this fast changes a peak current is flowing through the external capacitor into pin VAOUT. If this current exceeds an internal defined margin the overvoltage regulator circuitry reduces the multiplier output voltage. As a result the on time of the MOSFET is reduced.2.5MultiplierThe one quadrant multiplier regulates the gate driver with respect of the DC output voltage and the AC half wave rectified input voltage. Both inputs are designed to achieve good linearity over a wide dynamic range to represent an AC line free from distortion. Special efforts are made to assure universal line applications with respect to a 90 to 270 V AC range.The multiplier output is internally clamped at 1.3 V. So the MOSFET is protected against critical operating during start up.2.6Current Sense Comparator, LEB and RS Flip-FlopThe source current of the MOS transistor is transferred into a sense voltage via the external sense resistor. The multiplier output voltage is compared with this sense voltage. Switch on time of the MOS transistor is determined by the comparison result. To protect the current comparator input from negative pulses a current source is inserted which sends current out of the ISENSE pin every time when V ISENSE-signal is falling below ground potential. An internal RC-filter is connected to the ISENSE pin which smoothes the switch-on current spike. The remaining switch-on current spike is blanked out via a leading edge blanking circuit with a blanking time of typ. 200 ns.The RS Flip-Flop ensures that only one single switch-on and switch-off pulse appears at the gate drive output during a given cycle (double pulse suppression).2.7Zero Current DetectorThe zero current detector senses the inductor current via an auxiliary winding and ensures that the next on-time of the MOSFET is initiated immediately when the inductor current has reached zero. This reduces the reverse recovery losses of the boost converter diode to a miniumum. The MOSFET is switched off when the voltage drop of the shunt resistor reaches the voltage level of the multiplier output. So the boost current waveform has a triangular shape and there are no deadtime gaps between the cycles. This leads to a continuous AC line current limiting the peak current to twice of the average current.To prevent false tripping the zero current detector is designed as a Schmitt-Trigger with a hysteresis of 0.5 V. An internal 5 V clamp protects the input from overvoltage breakdown, a 0.6 V clamp prevents substrate injection. An external resistor has to be used in series with the auxiliary winding to limit the current through the clamps.2.8Restart TimerThe restart timer function eliminates the need of an oscillator. The timer starts or restarts the TDA4863-2 when the driver output has been off for more than 150 µs after the inductor current reaches zero.2.9Undervoltage LockoutAn undervoltage lockout circuitry switches the IC on when V CC reaches the upper threshold V CCH and switches the IC off when V CC is falling below the lower threshold V CCL. During start up the supply current is less then 100 µA.An internal voltage clamp has been added to protect the IC from V CC overvoltage condition. When using this clamp special care must be taken on power dissipation. Start up current is provided by an external start up resistor which is connected from the AC line to the input supply voltage V CC and a storage capacitor which is connected from V CC to ground. Be aware that this capacitor is discharged before the IC is plugged into the application board. Otherwise the IC can be destroyed due to the high capacitor voltage.Bootstrap power supply is created with the previous mentioned auxiliary winding and a diode (see “Application Circuit” on Page 21).2.10Gate DriveThe TDA4863-2 totem pole output stage is MOSFET compatible. An internal protection ciruitry is activated when V CC is within the start up phase and ensures that the MOSFET is turned off. The totem pole output has been optimized to achieve minimized cross conduction current during high speed operation.Compared to TDA4863 a bigger MOS Transistor can be driven by the TDA4863-2. When a big MOSFET is used in applications with TDA4863, for example SPP20N60C3, the falling edge of the gate drive voltage can swing under GND and can cause false triggering of the IC. To prevent false traiggering the gate drive voltage of theTDA4863-2 at low state and gate current I GT = 0mA is set to V GTL= 0.85V (TDA4863: V GTL=0.25V). The difference between TDA4863-2 and TDA4863 is also depicted in the diagram: gate drive voltage low state on page 20.2.11Signal DiagramsFigure 4Typical signals3Electrical Characteristics3.1Absolute Maximum RatingsParameter Symbol Limit Values Unit Remarksmin.max.Supply + Zener Current I CCH + I Z20mASupply Voltage V CC-0.3V Z V V Z = ZenerVoltageI CC+I Z = 20 mA Voltage at Pin 1,3,4-0.3 6.5Current into Pin 2I VAOUT-1030mA V VAOUT = 4 V,V VSENSE = 2.8 VV VAOUT = 0 V,V VSENSE = 2.3 Vt < 1 msCurrent into Pin 5I DETIN-1010DETIN > 6 VDETIN < 0.4 Vt < 1 msCurrent into Pin 7I GTDRV-500500t < 1 msESD Protection2000V MIL STD 883Cmethod 3015.6,100 pF,1500 ΩStorage Temperature T stg-50150°COperating Junction Temperature T J-40150Thermal Resistance Junction-Ambient R thJA100180K/W PG-DIP-8-4PG-DSO-8-33.2CharacteristicsUnless otherwise stated, -40°C < T j < 150°C, V CC = 14.5 VParameter Symbol Limit Values Unit Test Conditionmin.typ.max.Start-Up circuitZener Voltage V Z182022V I CC + I Z = 20 mA Start-up Supply Current I CCL20100µA V CC = V CCON -0.5 V Operating Supply Current I CCH46mA Output lowV CC Turn-ON Threshold V CCON1212.513VV CC Turn-OFF Threshold V CCOFF9.51010. 5V CC Hysteresis V CCHY 2.5Voltage AmplifierVoltage feedback InputV FB 2.45 2.5 2.55VThresholdLine Regulation V FBLR5mV V CC = 12 V to 16 V Open Loop Voltage Gain1)G V100dBUnity Gain Bandwidth1)B W5MHzPhase Margin1)M80DegrBias Current VSENSE I BVSENSE-1.0-0.3µAEnable Threshold V VSENSE0.170.20.25VInhibit Threshold Voltage V VAOUTI 2.1 2.2 2.3V ISENSE = -0.38 V Inhibit Time Delay t dVA3µs V ISENSE = -0.38 V Output Current Source I VAOUTH-6mA V VAOUT = 0 VV VSENSE = 2.3 V,t < 1 msOutput Current Sink I VAOUTL30V VAOUT = 4 VV VSENSE = 2.8 V,t < 1 msUpper Clamp Voltage V VAOUTH 4.8 5.4 6.0V V VSENSE = 2.3 V,I VAOUT = -0.2 mA Lower Clamp Voltage V VAOUTL0.8 1.1 1.4V V VSENSE = 2.8 V,I VAOUT = 0.5 mA1)Guaranteed by design, not testedOvervoltage Regulator Threshold Current I OVR354045µAT j = 25°C , V VAOUT = 3.5 V Current Comparator Input Bias Current I BISENSE -1-0.21µA V ISENSE = 0 V Input Offset Voltage (T j = 25 °C)V ISENSEO 25mV V VAOUT = 2.7 V V MULTIN = 0 V Max Threshold Voltage V ISENSEM 0.95 1.0 1.05VThreshold at OVR V ISENOVR 0.05I OVR = 50 µALeading Edge Blanking t LEB 100200300ns Shut Down Delay t dISG80130DetectorUpper Threshold Voltage V DETINU 1.5 1.6V Lower Threshold Voltage V DETINL 0.95 1.1Hysteresis V DETINHY 0.250.40.55Input Current I BDETIN-1-0.21µA V DETIN = 2 VInput Clamp Voltage High State Low StateV DETINHC V DETINLC4.5 0.14.9 0.45.3 0.7VI DETIN = 5 mA I DETIN = -5 mAMultiplier Input bias current I BMULTIN -1-0.21µA V MULTIN = 0 V Dynamic voltage range MULTINV MULTIN 0 to 4VV VAOUT = 2.75 V Dynamic voltage range VAOUT V VAOUTV FB to V FB +1.5V MULTIN = 1 VMultiplier GainK lowK high0.3 0.7V VAOUT < 3 V, V MULTIN = 1 V V VAOUT > 3.5V, V MULTIN = 1 VK = delta V ISENSE / d elta V VAOUT at V MULTIN = constant3.2Characteristics (cont’d)Unless otherwise stated, -40°C < T j < 150°C, V CC = 14.5 VParameterSymbolLimit Values UnitTest Conditionmin.typ.max.Restart Timer Restart time t RES100160250µs Gate DriveGate drive voltage low stateV GTL 0.85V I GT = 0 mA V GTL 1.0VI GT = 2 mA 1.7I GT = 20 mA 2.2I GT = 200 mA Gate drive voltage high state V GTH10.8I GT = -5 mA, see “Gate Drive Voltage High State versus V cc ” on Page 20Output voltage active shut down V GTSD 1 1.25I GT = 20 mA, V CC = 9 V Rise time t rise 80130nsC GT = 4.7 nF V GT = 2...8 VFall timet fall551303.2Characteristics (cont’d)Unless otherwise stated, -40°C < T j < 150°C, V CC = 14.5 VParameterSymbolLimit Values UnitTest Conditionmin.typ.max.3.3Electrical DiagramsI cc versus V cc00,511,522,533,544,5505101520Vcc/VI c c / m AI ccl versus V cc051015202530354045500246810121416Vcc / VI c c l / u AV CCON/OFFversus Temperature7891011121314-404080120160Tj / °CV c c /VI CCL versus Temperature, V CC = 10 V-404080120160Tj / °CI C C L / u AV FB versus Temperature (pin1 connected to pin2)2,452,462,472,482,492,52,512,522,532,542,55-404080120160Tj / °CV F B / VOvervoltage Regulator V ISENSE versus Threshold Voltage00,20,40,60,811,2353739414345Iovp / uAV I S E N S E / VOpen Loop Gain and Phase versus Frequency020406080100120f/kHz20406080100120140160180Phi/deg G V /dB Leading Edge Blanking versus Temperature050100150200250300-4004080120160Tj / °CL E B / n s1234V MULTIN / V Restart Time versus Temperature100120140160180200220-404080120160Tj / °Ct r s t / u s2,533,544,5V VAOUT / VTDA4863-2Electrical CharacteristicsGate Drive Rise Time and Fall Time versus TemperatureGate Drive Voltage High State versus V cc020*********120140-4004080120160Tj / °Cr i s e t i m e / n s88,599,51010,51111,512111315Vcc / VV G T H / VTDA4863-2Application Circuit 4Application CircuitFigure5P out = 110 W, Universal Input V in = 90-270V ACVersion 2.1 21 22 Feb 20054.1Results of THD Measurements with Application Board P out = 110 W (Measurements according to IEC61000-3-2.150% limit (red line): Momentary measured value must be below this limit.100% limit (blue line): Average of measured values must be below this limit.The worst measured momentary value is shown in the diagrams.)Figure 6THD Class C:P max = 110 W, V inac = 90 V, I out = 250 mA, V out = 420 V, PF = 0.998Figure 7THD Class C:P max = 110 W, V inac = 220 V, I out = 250 mA, V aout = 420 V, PF = 0.992 Version 2.1 2222 Feb 2005Version 2.1 2322 Feb 2005Figure 8THD Class C:P max = 110 W, V inac = 270 V, I out = 250 mA, V aout= 420 V, PF = 0.978Figure 9THD Class C:P max = 110 W, V inac = 90 V, I out = 140 mA, V aout = 420 V, PF = 0.999Version 2.1 2422 Feb 2005Figure 10THD Class C:P max = 110 W, V inac = 220 V, I out = 140 mA, V aout = 420 V, PF = 0.975Figure 11THD Class C:P max = 110 W, V inac = 270 V, I out = 140 mA, V aout = 420 V, PF = 0.8835Package OutlinesFigure 12Version 2.1 25 22 Feb 2005Figure 13You can find all of our packages, sorts of packing and others in ourInfineon Internet Page “Products”: /products.Dimensions in mm Version 2.1 2622 Feb 2005Qualität hat für uns eine umfassende Bedeutung. Wir wollen allen Ihren Ansprüchen in der bestmöglichen Weise gerecht werden. Es geht uns also nicht nur um die Produktqualität – unsere Anstrengungen gelten gleichermaßen der Lieferqualität und Logistik, dem Service und Support sowie allen sonstigen Beratungs- und Betreuungsleistungen.Dazu gehört eine bestimmte Geisteshaltung unserer Mitarbeiter. Total Quality im Denken und Handeln gegenüber Kollegen, Lieferanten und Ihnen, unserem Kunden. Unsere Leitlinie ist jede Aufgabe mit …Null Fehlern“ zu lösen – in offener Sichtweise auch über den eigenen Arbeitsplatz hinaus – und uns ständig zu verbessern.Unternehmensweit orientieren wir uns dabei auch an …top“ (Time Optimized Processes), um Ihnen durch größere Schnelligkeit den entscheidenden Wettbewerbsvorsprung zu verschaffen. Geben Sie uns die Chance, hohe Leistung durch umfassende Qualität zu beweisen.Wir werden Sie überzeugen.Quality takes on an allencompassing significance at Semiconductor Group. For us it means living up to each and every one of your demands in the best possible way. So we are not only concerned with product quality. We direct our efforts equally at quality of supply and logistics, service and support, as well as all the other ways in which we advise and attend to you. Part of this is the very special attitude of our staff. Total Quality in thought and deed, towards co-workers, suppliers and you, our customer. Our guideline is “do everything with zero defects”, in an open manner that is demonstrated beyond your immediate workplace, and to constantly improve.Throughout the corporation we also think in terms of Time Optimized Processes (top), greater speed on our part to give you that decisive competitive edge.Give us the chance to prove the best of performance through the best of quality – you will be convinced.h t t p://w w w.i n f i n e o n.c o m Total Quality Management Published by Infineon Technologies AG。

英锐芯电子 3W 双通道立体声音频功率放大器 LM4863 数据手册说明书

深圳市英锐芯电子科技有限公司3W双通道立体声音频功率放大器LM4863LM4863简介数据手册版本V1.0电话：*************82568883邮箱：**********************传真：*************网址：公司地址：深圳市福田区滨河大道联合广场A座1308深圳市英锐芯电子科技有限公司3W双通道立体声音频功率放大器LM4863芯片功能说明：实物图：ØLM4863是一双路音频功率放大器，它能够在5V电源电压下给一个4Ω负载提供THD小于10%、最大平均值为3W的输出功率。

另外，在驱动立体声耳机时耳机输入引脚可以使放大器工作在单边模式。

ØLM4863是为提供高保真音频输出而专门设计的，它仅仅需要少量的外围器件，为简化音频系统设计，LM4863集双路桥式扬声器放大器和立体声耳机放大器与一体。

LM4863还有外部控制的关断模式，立体声耳机放大模式和热保护关闭模式，还有减少开机噪音功能。

芯片功能主要特性：Ø立体声耳机放大器模式Ø开机噪声抑制系统Ø增益稳定Ø热关闭保护模式Ø待机电流33mAØ掉电模式电流190uAØ宽工作电压范围2.2V-5.5VØ在单端模式下，负载32Ω，输出平均功率为75mW时，最大失真度为0.5%芯片基本应用：Ø手提电脑Ø台式电脑Ø多媒体监视器Ø便携式视频系统LM4863内部原理框图：电话：*************82568883邮箱：**********************传真：*************网址：公司地址：深圳市福田区滨河大道联合广场A座130813W双通道立体声音频功率放大器LM4863典型应用图电话：*************82568883邮箱：**********************传真：*************网址：公司地址：深圳市福田区滨河大道联合广场A座130823W双通道立体声音频功率放大器LM4863封装引脚图LM4863引脚描述电话：*************82568883邮箱：**********************传真：*************网址：公司地址：深圳市福田区滨河大道联合广场A座130833W双通道立体声音频功率放大器LM4863极限参数电气参数桥式工作模式（如没另外说明，均为VDD=5V，T A=25℃）电话：*************82568883邮箱：**********************传真：*************网址：公司地址：深圳市福田区滨河大道联合广场A座130843W双通道立体声音频功率放大器LM4863单端工作模式电话：*************82568883邮箱：**********************传真：*************网址：公司地址：深圳市福田区滨河大道联合广场A座130853W双通道立体声音频功放LM4863芯片封装尺寸如没有特别提示，所有尺寸标注均为：（毫米）电话：*************82568883邮箱：**********************传真：*************网址：公司地址：深圳市福田区滨河大道联合广场A座13086。

LM4863电路设计要点

LM4863电路设计要点1.选取合适的电源电压：LM4863的工作电源电压范围为2.7V至5.5V，因此需要根据具体应用需求选择合适的电源电压。

2.选择合适的外围元件：根据LM4863的数据手册，可以确定所需的外围元件，如输入耦合电容、反馈电阻和配电电容等。

这些外围元件的选择应根据设计要求来确定。

3.PCB布局和绘制：考虑到LM4863是一款实现立体声功率放大的芯片，因此在PCB布局时要注意分离左、右声道。

同时，应将输入和输出信号线远离高频噪声源，以减少干扰。

另外，还需要注意地面布局和分立元件的位置以实现良好的散热效果。

4.输入和输出保护：可以使用电容耦合方式实现输入保护，避免直流偏置。

可以使用电流抑制器来保护输出级，以防止电流浪费和震荡。

5.滤波电路：可以在输入和输出端添加适当的滤波电路，以消除高频和低频噪声。

可以根据实际需求使用不同类型的滤波器电路，如低通滤波器、带通滤波器等。

6.给定电压增益：LM4863具有可调的电压增益，可以根据需求进行设置。

这样可以调整输出音频的音量。

7.散热设计：当功率放大器工作时，会产生一定的热量。

因此，在LM4863电路设计中，需要考虑散热问题。

可以在芯片周围设置散热片或散热孔，以提高散热效果。

8.稳定性考虑：在电路设计中，应该考虑到芯片的稳定性。

可以使用稳定电源电压，避免过大的输出电流，并在设计中增加反馈电路以提高稳定性。

9.输入电平控制：可以使用电位器或电子开关来控制输入音频电平。

这样可以实现音量调节或静音功能。

10.输出保护：可以使用过流保护电路来保护输出级，以防止短路和超负载。

这样可以提高功率放大器的可靠性和耐用性。

在进行LM4863电路设计时，需要根据具体的应用需求和LM4863的技术规格来考虑上述要点。

同时，也需要结合实际情况进行电路设计和测试，以确保最终的电路性能和稳定性。

LM4863是一款成熟的芯片，具有优良的音频性能，因此在电路设计时要充分发挥其特点和优势，实现高质量的音频放大。

TDA4863中文资料

Data Sheet, V1.0, May 2003Boost ControllerTDA4863Power Factor ControllerIC for High Power Factorand Low THDPower Management & SupplyEdition 2003-05Published by Infineon Technologies AG,St.-Martin-Strasse 53,81669 München, Germany © Infineon Technologies AG 2002.All Rights Reserved.Attention please!The information herein is given to describe certain components and shall not be considered as warranted characteristics.T erms of delivery and rights to technical change reserved.We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein.Infineon Technologies is an approved CECC rmationFor further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon T echnologies Representatives worldwide.WarningsDue to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon T echnologies Office.Infineon T echnologies Components may only be used in life-support devices or systems with the express written approval of Infineon T echnologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life-support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at .TDA4863Revision History:2003-05V1.0Previous Version:PageSubjects (major changes since last revision)Document’s layout has been changed: 2002-Sep.TDA4863Table of Contents Page 1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2Improvements Referred to TDA 4862 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.5Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2IC Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3Voltage Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4Overvoltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.5Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.6Current Sense Comparator, LEB and RS Flip-Flop . . . . . . . . . . . . . . . . . . 10 2.7Zero Current Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.8Restart Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.9Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.10Gate Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.11Signal Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3Electrical Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1Results of THD Measurements with Application Board P out=110W . . . . 22Type Ordering Code Package TDA4863Q67040-S4452P-DIP-8-4TDA4863GQ67040-A4451P-DSO-8-3Power Factor Controller IC for High Power Factor and Low THD TDA4863Final DataBoost Controller1Overview1.1Features•IC for sinusoidal line-current consumption •Power factor achieves nearly 1•Controls boost converter as active harmonic filter for low THD•Start up with low current consumption •Zero current detector for discontinuous operation mode•Output overvoltage protection •Output undervoltage lockout •Internal start up timer•Totem pole output with active shut down •Internal leading edge blanking LEB1.2Improvements Referred to TDA 4862•Suitable for universal input applications with low THD at low load conditions •Very low start up current•Accurate OVR and V ISENSEmax threshold •Competition compatible V CC thresholds •Enable threshold referred to V VSENSEFigure1Typical application1.3DescriptionThe TDA4863 IC controls a boost converter in a way that sinusoidal current is taken from the single phase line supply and stabilized DC voltage is available at the output. This active harmonic filter limits the harmonic currents resulting from the capacitor pulsed charge currents during rectification. The power factor which describes the ratio between active and apparent power is almost one. Line voltage fluctuations can be compensated very efficiently.1.4Pin ConfigurationFigure2Pin Configuration of TDA4863Pin Definitions and FunctionsPin Symbol Description1VSENSE Voltage Amplifier Inverting InputVSENSE is connected via a resistive divider to the boost converteroutput. With a capacitor connected to VAOUT the internal erroramplifier acts as an integrator.2VAOUT Voltage Amplifier OutputV VAOUT is connected internally to the first multiplier input. To preventovershoot the input voltage is clamped internally at 5V. If V VAOUT isless than 2.2V the gate driver is inhibited. If the current flowing intothis pin exceeds an internal threshold the multiplier output voltage isreduced to prevent the MOSFET from overvoltage damage.3MULTIN Multiplier InputMULTIN is the second multiplier input and is connected via a resistivedivider to the rectifier output voltage.4ISENSE Current Sense InputISENSE is connected to a sense resistor controlling the MOSFETsource current. The input is internally clamped at -0.3V to preventnegative input voltage interaction. A leading edge blanking circuitrysuppresses voltage spikes when turning the MOSFET on.5DETIN Zero Current Detector InputDETIN is connected to an auxiliary winding and monitors the zerocrossing of the inductor current.6GND Ground7GTDRV Gate Driver OutputGTDRV is the output of a totem-pole circuitry for direct driving aMOSFET. An active shutdown circuitry ensures that GTDRV is set tolow if the IC is switched off.8VCC Positive Voltage SupplyIf V CC exceeds the turn-on threshold the IC is switched on. When V CCfalls below the turn-off threshold the IC is switched off. In switch offmode power consumption is very low. Two capacitors should beconnected to VCC. An electrolytic capacitor and 100nF ceramiccapacitor which is used to absorb fast supply current spikes. Makesure that the electrolytic capacitor is discharged before the IC isplugged into the application board.1.5Block DiagramFigure3Internal Bolck Diagram2Functional Description2.1IntroductionConventional electronic ballasts and switch mode power supplies are designed with a bridge rectifier and a bulk capacitor. Their disadvantage is that the circuit draws power from the line when the instantaneous AC voltage exceeds the capacitors voltage. This occurs near the line voltage peak and causes a high charge current spike with following characteristics: The apparent power is higher than the real power that means low power factor condition, the current spikes are non sinusoidal with a high content of harmonics causing line noise, the rectified voltage depends on load condition and requires a large bulk capacitor, special efforts in noise suppression are necessary.With the TDA4863 preconverter a sinusoidal current is achieved which varies in direct instantaneous proportional to the input voltage half sine wave and so provides a power factor near 1. This is due to the appearance of almost any complex load like a resistive one at the AC line. The harmonic distortions are reduced and comply with the IEC555 standard requirements.2.2IC DescriptionThe TDA4863 contains a wide bandwidth voltage amplifier used in a feedback loop, an overvoltage regulator, an one quadrant multiplier with a wide linear operating range, a current sense comparator, a zero current detector, a PWM and logic circuitry, a totem-pole MOSFET driver, an internal trimmed voltage reference, a restart timer and an undervoltage lockout circuitry.2.3Voltage AmplifierWith an external capacitor between the pins VSENSE and VAOUT the voltage amplifier acts like an integrator. The integrator monitors the average output voltage over several line cycles. Typically the integrator´s bandwidth is set below 20Hz in order to suppress the 100Hz ripple of the rectified line voltage. The voltage amplifier is internally compensated and has a gain bandwidth of 5MHz (typ.) and a phase margin of 80 degrees. The non-inverting input is biased internally to 2.5V. The output is directly connected to the multiplier input.The gate drive is disabled when VSENSE voltage is less than 0.2V or VAOUT voltage is less than 2.2V.If the MOSFET is placed nearby the controller switching interferences have to be taken into account. The output of the voltage amplifier is designed in a way to minimize these inteferences.2.4Overvoltage RegulatorBecause of the integrator´s low bandwidth fast changes of the output voltage can’t be regulated within an adequate time. Fast output changes occur during initial start-up, sudden load removal, or output arcing. While the integrator´s differential input voltage remains zero during this fast changes a peak current is flowing through the external capacitor into pin VAOUT. If this current exceeds an internal defined margin the overvoltage regulator circuitry reduces the multiplier output voltage. As a result the on time of the MOSFET is reduced.2.5MultiplierThe one quadrant multiplier regulates the gate driver with respect of the DC output voltage and the AC half wave rectified input voltage. Both inputs are designed to achieve good linearity over a wide dynamic range to represent an AC line free from distortion. Special efforts have been made to assure universal line applications with respect to a 90 to 270V AC range.The multiplier output is internally clamped to1.3V. So the MOSFET is protected against critical operating during start up.2.6Current Sense Comparator, LEB and RS Flip-FlopThe source current of the MOS transistor is transferred into a sense voltage via the external sense resistor. The multiplier output voltage is compared with this sense voltage. Switch on time of the MOS transistor is determined by the comparision result To protect the current comparator input from negative pulses a current source is inserted which sends current out of the ISENSE pin every time when V ISENSE-signal is falling below ground potential. An internal RC-filter is connected at the ISENSE pin which smoothes the switch-on current spike.The remaining switch-on current spike is blanked out via a leading edge blanking circuit with a blanking time of typ. 200ns.The RS Flip-Flop ensures that only one single switch-on and switch-off pulse appears at the gate drive output during a given cycle (double pulse suppression).2.7Zero Current DetectorThe zero current detector senses the inductor current via an auxiliary winding and ensures that the next on-time of the MOSFET is initiated immediately when the inductor current has reached zero. This reduces the reverse recovery losses of the boost converter diode to a minimum. The MOSFET is switched off when the voltage drop of the shunt resistor exceeds the voltage level of the multiplier output. So the boost current waveform has a triangular shape and there are no deadtime gaps between the cycles. This leads to a continuous AC line current limiting the peak current to twice of the average current.To prevent false tripping the zero current detector is designed as a Schmitt-Trigger with a hysteresis of 0.5V. An internal 5V clamp protects the input from overvoltage breakdown, a 0.6V clamp prevents substrate injection. An external resistor has to be used in series with the auxiliary winding to limit the current through the clamps.2.8Restart TimerThe restart timer function eliminates the need of an oscillator. The timer starts or restarts the TDA4863 when the driver output has been off for more than 150µs after the inductor current reaches zero.2.9Undervoltage LockoutAn undervoltage lockout circuitry switches the IC on when V CC reaches the upper threshold V CCH and switches the IC off when V CC is falling below the lower threshold V CCL. During start up the supply current is less then 100µA.An internal voltage clamp has been added to protect the IC from V CC overvoltage condition. When using this clamp special care must be taken on power dissipation. Start up current is provided by an external start up resistor which is connected from the AC line to the input supply voltage V CC and a storage capacitor which is connected from V CC to ground. Be aware that this capacitor is discharged before the IC is plugged into the application board. Otherwise the IC can be destroyed due to the high capacitor voltage.Bootstrap power supply is created with the previous mentioned auxiliary winding and a diode (see “Application Circuit” on Page21).2.10Gate DriveThe TDA4863 totem pole output stage is MOSFET compatible. An internal protection ciruitry is activated when V CC is within the start up phase and ensures that the MOSFET is turned off. The totem pole output has been optimized to minimize cross conduction current during high speed operation.2.11Signal DiagramsFigure4Typical signals3Electrical Characteristics3.1Absolute Maximum RatingsParameter Symbol Limit Values Unit Remarksmin.max.Supply + Zener Current I CCH + I Z20mASupply Voltage V CC-0.3V Z V V Z = ZenerVoltageI CC+I Z = 20mA Voltage at Pin 1,3,4-0.3 6.5Current into Pin 2I VAOUT-1040mA V VAOUT=4V,V VSENSE=2.8VV VAOUT=0V,V VSENSE=2.3Vt<1msCurrent into Pin 5I DETIN-1010DETIN>6VDETIN<0.4Vt<1msCurrent into Pin 7I GTDRV-500500t<1msESD Protection2000V MIL STD 883Cmethod 3015.6,100pF,1500ΩStorage Temperature T stg-50150°COperating Junction Temperature T J-40150Thermal Resistance Junction-Ambient R thJA100180K/W P-DIP-8-4P-DSO-8-33.2CharacteristicsUnless otherwise stated, -40°C < T j < 150°C, V CC = 14.5VParameter Symbol Limit Values Unit Test Conditionmin.typ.max.Start-Up circuitZener Voltage V Z182022V I CC+I Z=20mA Start-up Supply Current I CCL20100µA V CC=V CCON-0.5V Operating Supply Current I CCH46mA Output lowV CC Turn-ON Threshold V CCON1212.513VV CC Turn-OFF Threshold V CCOFF9.51010. 5V CC Hysteresis V CCHY 2.5Voltage AmplifierVoltage feedback InputV FB 2.45 2.5 2.55VThresholdLine Regulation V FBLR5mV V CC=12V to 16V Open Loop Voltage Gain1)G V100dBUnity Gain Bandwidth1)B W5MHzPhase Margin1)M80DegrBias Current VSENSE I BVSENSE-1.0-0.3µAEnable Threshold V VSENSE0.170.20.25VInhibit Threshold Voltage V VAOUTI 2.1 2.2 2.3V ISENSE=-0.38V Inhibit Time Delay t dVA3µs V ISENSE=-0.38V Output Current Source I VAOUTH-6mA V VAOUT=0VV VSENSE=2.3V,t<1msOutput Current Sink I VAOUTL35V VAOUT=4VV VSENSE=2.8V,t<1msUpper Clamp Voltage V VAOUTH 4.8 5.4 6.0V V VSENSE=2.3V,I VAOUT=-0.2mA Lower Clamp Voltage V VAOUTL0.8 1.1 1.4V V VSENSE=2.8V,I VAOUT=0.5mA1)Guaranteed by design, not testedOvervoltage Regulator Threshold Current I OVR354045µAT j =25°C , V VAOUT = 3.5 V Current Comparator Input Bias Current I BISENSE -1-0.21µA V ISENSE =0V Input Offset Voltage (T j = 25 °C)V ISENSEO25mV V VAOUT =2.7V V MULTIN = 0 V Max Threshold Voltage V ISENSEM 0.95 1.0 1.05VThreshold at OVR V ISENOVR 0.05I OVR =50µALeading Edge Blanking t LEB 100200300ns Shut Down Delay t dISG80130DetectorUpper Threshold Voltage V DETINU 1.5 1.6V Lower Threshold Voltage V DETINL 0.95 1.1Hysteresis V DETINHY 0.250.40.55Input Current I BDETIN-1-0.21µA V DETIN =2VInput Clamp Voltage High State Low State V DETINHC V DETINLC 4.50.1 4.90.4 5.40.7VI DETIN =5mA I DETIN =-5mA Multiplier Input bias current I BMULTIN -1-0.21µA V MULTIN =0V Dynamic voltage range MULTINV MULTIN 0 to 4V V VAOUT =2.75V Dynamic voltage range VAOUT V VAOUTV FB to V FB +1.5V MULTIN =1V Multiplier GainK low K high0.30.7V VAOUT <3V, V MULTIN =1V V VAOUT >3.5V,V MULTIN =1VK =delta V ISENSE /delta V VAOUT at V MULTIN =constant3.2Characteristics (cont’d)Unless otherwise stated, -40°C < T j < 150°C, V CC = 14.5VParameterSymbolLimit Values UnitTest Conditionmin.typ.max.Restart Timer Restart time t RES100160250µs Gate DriveOutput voltage low state V GTL 0.3V I GT =0mA Output voltage low stateV GTL 1.0VI GT =2mA 1.7I GT =20mA 2.2I GT =200mA Output voltage high stateV GTH10.8I GT =-5mA,see “Gate Drive Voltage High State versus V cc ” on Page 20Output voltage active shut down V GTSD 1 1.25I GT =20mA, V CC =9V Rise time t rise 80130nsC GT = 4.7nF V GT =2 (8V)Fall timet fall551303.2Characteristics (cont’d)Unless otherwise stated, -40°C < T j < 150°C, V CC = 14.5VParameterSymbolLimit Values UnitTest Conditionmin.typ.max.3.3Electrical DiagramsI cc versus V ccI ccl versus V ccV CCON/OFF versus TemperatureI CCL versus Temperature, V CC = 10V00,511,522,533,544,5505101520Vcc/VI c c / m A051015202530354045500246810121416Vcc / VI c c l / uA7891011121314-404080120160Tj / °CV c c / V05101520253035404550-404080120160Tj / °CI C C L / u AVFB versus Temperature (pin1 connected to pin2)Overvoltage Regulator V ISENSE versus Threshold VoltageOpen Loop Gain and Phase versus FrequencyLeading Edge Blanking versus Temperature2,452,462,472,482,492,52,512,522,532,542,55-404080120160Tj / °CV F B / V00,20,40,60,811,2353739414345Iovp / uAV I S E N S E / V020406080100120f/kHz20406080100120140160180Phi/deg G V /dB 050100150200250300-4004080120160Tj / °CL E B / n sRestart Time versus Temperature1234V MULTIN / V 100120140160180200220-404080120160Tj / °Ct r s t / u s2,533,544,5V VAOUT / VGate Drive Rise Time and Fall Time versus TemperatureGate Drive Voltage High State versus V cc020406080100120140-404080120160Tj / °Cr i s e t i m e / n s88,599,51010,51111,512111315Vcc / VV G T H / V4Application CircuitFigure5P out = 110 W, Universal Input V in = 90-270V AC4.1Results of THD Measurements with Application Board P out=110W (Measurements according to IEC61000-3-2.150% limit (red line): Momentary measured value must be below this limit.100% limit (blue line): Average of measured values must be below this limit.The worst measured momentary value is shown in the diagrams.)Figure6THD Class C:P max=110W, V inac=90V, I out=250mA, V out=420V, PF=0.998Figure7THD Class C:P max=110W, V inac=220V, I out=250mA, V aout=420V, PF=0.992Figure8THD Class C:P max=110W, V inac=270V, I out=250mA, V aout=420V, PF=0.978Figure9THD Class C:P max=110W, V inac=90V, I out=140mA, V aout=420V, PF=0.999Figure10THD Class C:P max=110W, V inac=220V, I out=140mA, V aout=420V, PF=0.975Figure11THD Class C:P max=110W, V inac=270V, I out=140mA, V aout=420V, PF=0.8835Package OutlinesFigure12Figure13You can find all of our packages, sorts of packing and others in ourInfineon Internet Page “Products”: /products.Dimensions in mmInfineon goes for Business Excellence “Business excellence means intelligent approaches and clearly defined processes, which are both constantly under review and ultimately lead to good operating results.Better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction.”Dr. Ulrich Schumacherw w w.i n f i n e o n.c o m。

PFC控制芯片TDA4862／4863及其应用

高功率因数控制器TDA4862/63及其应用1. 引言TDA4862是德国西门子公司（Simens AG）推出的高功率因数控制器，TDA4863是TDA4862的增强版本。

1999年4月德国英飞凌技术公司（Infineon Technologies AG）作为德国西门子公司的全资子公司在德国慕尼黑成立，西门子公司所有的半导体业务全部转入英飞凌技术公司。

现在，英飞凌技术公司已跻身全球十大半导体生产商的行列。

TDA4862和TDA4863现由英飞凌技术公司生产。

下面对TDA4862和TDA4863高功率因数控制器的特点、引脚功能、电气参数、工作原理以及典型应用进行介绍。

2. 特点和引脚说明2.1 特点为便于比较，现将TDA4862和TDA4863的特点列于表1。

2.2 引脚说明TDA4862和TDA4863均采用PDIP-8和PDSO-8两种封装形式。

本文主要介绍PDIP-8引脚封装，其引脚排列如图1所示。

TDA4862和TDA4863的引脚功能简介如下：·VSENSE（引脚1）：电压放大器反相输入端。

该端通过电阻分压器与升压变换器输出端相连。

引脚2通过反馈电容与该端相连，构成反馈补偿网络；·V AOUT（引脚2）：电压放大器输出端。

该端在控制器内部与乘法器的一个输入端相连。

为避免输入电压发生过冲，该端内接5V箝位电路。

当输入电压低于2.2V时，驱动输出电路将被禁止。

如果流入该端的电流超出了阈值，乘法器的输出信号将下降，以防止升压功率MOSFET因过压故障而损坏。

·MULTIN（引脚3）：乘法器的另一个输入端。

该端通过电阻分压器与全波整流输出电压相连。

·ISENSE（引脚4）：电流检测信号输入端。

该端在控制器内部与电流检测比较器的反相输入端相连，通过外接检测电阻实现对升压功率MOSFET源极电流的控制。

为了避免负输入电压对控制器产生影响，该端被内部箝位于-0.3V。

TC4863(音频功放IC)

手提设备，台式电脑五、功能说明桥路设置TC4863由2个运放电路组成，形成双通道（通道A和通道B）立体放大器。

针对A的说明，B原理相同。

外部电阻RF和RI 设置构成AMP1A的闭环增益，而2个内置的20kΩ电阻形成AMP2A为-1的增益。

TC4863通过连接2个放大器输出端口：VO2b和VO1b，来驱动负载。

AMP1A的输出同时供AMP2A的输入，而且两个运放产生的信号幅度相同，相位相反。

利用相位的不同，在VO2b和VO1b和桥式模式下放置一个负载，因此TC4863增益如下：A VD = 2×(Rf/Ri)为驱动负载，运放设置成桥接方式。

桥接方式不同于一些常见的运放电路把负载的一边接到地，在同等条件下能使负载产生4倍的输出功率。

第 2 页共 13 页第 3 页共 13 页以免进入错误的状态。

在很多应用场合，关断端口的电平转换都是由处理器来完成的，但是也可以用单向闸刀开关来实现。

外接一个上拉电阻，合上开关，因为关断端连接到地运放即开始工作。

打开开关，外接上拉电阻的关系将使TC4863不工作。

这样就能保证TC4863不在错误的状态下工作。

六、极限参数（Ta = 25℃）特性符号范围单位工作电压 V DD 6.0 V 输入电压 V IN -0.3～V DD +0.3 V 储存温度 T STG -65～+150 ℃ 环境温度 T A -40～+85 ℃ 节点温度T J 150 ℃七、电气参数（VDD = 5V ，Ta = 25℃）适用于全部IC名称符号最小值典型值最大值单位测试条件工作电压V DD 2.0 -- 5.5 V --6.0 11.5 2.0 V IN = 0V, I O = 0mA, HP-IN = 0V静态电流 I DD -- 5.8 -- mAV IN = 0V, I O = 0mA, HP-IN = 4V关断电流 I SD -- 0.7 2 uA VDD 连接到关断端口耳机输入高电平 V IH 4 -- -- V -- 耳机输入低电平 V IL 0.8 -- -- V --第 4 页共 13 页名称符号最小值典型值最大值单位测试条件输出偏压V OS -- 5.0 50mV V IN = 0V75 85 --THD+N = 0.5%，f = 1KHz ，R L = 32Ω -- 340 --THD+N = 1%，f = 1KHz ，R L = 8Ω 输出功率 P O -- 440 --mW THD+N = 10%，f = 1KHz ，R L = 8Ω 总谐波失真+噪音 THD+N -- 0.2 -- %A V = -1，P O = 75mW ，R L = 32Ω,20Hz ≤f ≤20KHz电源抑制比 PSRR -- 52 -- dB C B = 1.0uF, V RIPPLE = 200mV RMS , f = 1KHz 通道分离 X TALK -- 60 -- dB f = 1KHz, C B = 1.0uF 信噪比 SNR -- 95 -- dB V DD = 5V, P O = 340mW, R L = 8Ω第 5 页共 13 页第 6 页共 13 页第 7 页共 13 页第 8 页共 13 页第 9 页共 13 页第 10 页共 13 页第 11 页共 13 页SOP16(W)第 12 页共 13 页第 13 页共 13 页。