3_19_gate_run_design
Retiming with interconnect and gate delay
Retiming with Interconnect and Gate Delay Chris Chu∗,Evangeline F.Y.Young†,Dennis K.Y.Tong†,and Sampath Dechu‡∗Dept.of Electrical and Computer Engineering,Iowa State University,Ames,IA50011†Dept.of Computer Science and Engineering,The Chinese University of Hong Kong,Hong Kong ‡Physical Design Automation Group,Micron Technology,Inc.,Boise,ID83707AbstractIn this paper,we study the problem of retiming of sequential circuits with both interconnect and gate delay.Most retiming algorithms have assumed ideal conditions for the non-logical portions of the data paths,which are not sufficiently accurate to be used in high perfor-mance circuits today.In our modeling,we assume that the delay of a wire is directly proportional to its length.This assumption is rea-sonable since the quadratic component of a wire delay is significantly smaller than its linear component when the more accurate Elmore de-lay model is used.A simple experiment is conducted to illustrate the validity of this assumption.We present two approaches to solve this problem,both of which have polynomial time complexity.Thefirst one can compute the optimal clock period while the second one is an improvement over thefirst one in terms of practical applicability. The second approach gives solutions very close to the optimal(0.13% more than the optimal on average)but in a much shorter runtime.A circuit with more than22K gates and32K wires can be optimally retimed in83.56seconds by a PC with an1.8GHz Intel Xeon proces-sor.1IntroductionRetiming[1]is a useful and popular technique for performance optimization of sequential circuits.It relocates registers to re-duce the cycle time while preserving the functionality of the circuit.Much effort has been made to apply this technique in different areas like power reduction[2,3],testability[4,5], logic resynthesis[6],circuit partitioning[7–9]and physical planning[10].Some extended its applicability in large practi-cal circuits efficiently[11–18].However,most retiming algo-rithms have assumed ideal conditions for the non-logical por-tions of the data paths,specifically ignoring the interconnect delay.As process technology gets down to deep sub-micron, interconnect delay becomes a major factor of path delay.With-out including this delay component,existing retiming algo-rithms are not sufficiently accurate to be used in practical high performance circuits.The choice of an accurate interconnect delay model and an appropriate retiming algorithm are important.In some previ-ous works[19,20],interconnect delay was incorporated into the retiming process,but simplified assumptions were made such that the interconnect delay between adjacent registers on the same wire was neglected.Another approach to integrate retiming into detailed placement was presented in[21].After an initial placement and routing,heuristics were used to es-timate interconnect delay.Retiming and post-retiming place-ment were then performed to optimize the circuit performance.A recent paper[22]by Tabbara et al.applied retiming in the DSM domain and interconnect delay was considered.It was done by having a lower bound on the number of registers on each wire e uv,while the delays at nodes were irrelevant.Regis-ters could be retimed into a node that represented a component and affected the total area of the component.Retiming was performed to satisfy the constraint on the number of registers on each wire while minimizing the total area of the compo-nents.Another paper[13]by Deokar et ed a combination of clock skew and retiming tofind a retiming solution which was guaranteed to be at most one gate delay larger than the optimal clock period.In their work,a clock skew solution cor-responding to an optimal clock period was converted into a retiming solution.However,their current approach to perform this conversion considered only gate delays.In this paper,we study the problem of retiming with both in-terconnect and gate delay.In our modeling,the delay of a wire is assumed to be directly proportional to its length.When a wire is short,the quadratic component of the wire delay is sig-nificantly smaller than its linear component.For a long wire, buffer insertion can be performed to break the wire into short segments.A simple experiment is conducted to illustrate the validity of this assumption and the result is shown in Figure1. In this experiment,the Elmore delay model is used and the parameters are based on the0.07µm technology.This graph shows the relationship between wire delay(y-axis)and wire length(x-axis).If the wire is shorter than1.46mm,the error of using a linear approximation is at most5.48%.If the wire is longer than1.46mm,the delay can be reduced by inserting a buffer and the error resulted is even less.We present two approaches in this paper both of which have polynomial time complexity.Thefirst one is extended from the MILP approach in the paper[1]and can solve the prob-lem optimally,i.e.,relocating the registers to give the smallest possible clock period.The second one transforms the prob-lem into a single-source longest paths problem and then ap-plies a technique to reduce the size of the graph for longest path computation.It is an improvement over thefirst one in terms of practical applicability.It gives solutions very close to the optimal(0.13%more than the optimal on average)but in a much shorter runtime.Experimental results showed that a circuit with more than22K gates and32K wires could be retimed in83.56seconds by a PC with an1.8GHz Intel Xeon processor.These retiming techniques will alsofind applica-tions inflip-flop dropping in placement by estimating the best possible register positions to optimize the circuit performance.Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are n ot made or distributed for profit or commercial advan tage an d that copies bear this n otice an d the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists,No buffer One buffer Linear Approx.Delay (ps)Wire length (mm)5010015020025030035040045050055000.51.01.52.02.5Figure 1:A simple experiment to illustrate the relationship be-tween wire delay and wire length.The original placement solution will be modified to relocate the registers according to the retiming solution.However the effect will be minor if the original solution is not very densely placed.This is a reasonable assumption today as area is not a major concern while routability and congestion are the impor-tant factors for circuit performance.Register relocations can then be done by making use of the empty space or by shifting the placed cells a little bit.The remainder of this paper is organized as follows.We present the problem statement in Section 2.The optimal ap-proach and the fast approach are presented in Section 3and Section 4,respectively.Experimental results are shown and discussed in Section 5.A conclusion follows in Section 6.2Problem FormulationA sequential circuit can be represented by a directed graph G (V ,E ),where each node v corresponds to a combinational gate,and each directed edge e uv represents a connection from the output of gate u to the input of gate v ,through zero or more registers.Without loss of generality,we assume that G is strongly connected.If not,we can add a source node s and connect it to all primary inputs,add a target node t and connect all primary outputs to it,and connect t to s .Then the resulting graph is strongly connected.If we set the delay of s ,t and all the added edges to zero,and set the number of registers on e ts to one and that on the other added edges to zero,a retiming solution S of the modified graph will also be a valid retiming solution of the original graph as long as e ts still has one regis-ter in S .Let w uv be the number of registers of edge e uv .Let d uv be the interconnect delay of edge e uv if all the registers are removed.Note that the delay of an interconnect segment is as-sumed to be proportional to the length of the segment.Let d u be the gate delay of node u.Traditionally,interconnect delay is ignored during retiming.Figure 2:An example to illustrate the meaning of a (v ).A retiming solution can be viewed as a labeling of the nodes r :V →Z ,where Z is the set of integers [1].The retiming label r (v )for a node v represents the number of registers moved from its outputs toward its inputs.After retiming,the number ofregisters ˆw uv on an edge e uv is given by ˆwuv =r (v )+w uv −r (u ).As interconnect delay is dominating in the VDSM technol-ogy,the exact position of each register will affect the clock period.A retiming solution should specify both the retiming label r (v )for each node v and the exact positions of the ˆw uv registers on each edge e uv .Retiming should be formulated as a problem of determining a feasible retiming solution,i.e.,a solution in which the number of registers ˆw uv on each edge e uv is non-negative,such that the clock period of the retimed cir-cuit is minimized.In the following,we show how to check whether a particular clock period T can be achieved by a fea-sible retiming solution.The minimum achievable clock period T opt can then be found by binary search.3An Optimal ApproachThis approach is extended from the mixed integer linear pro-gramming (MILP)approach in [1].In the original formulation,only gate delay is considered and there is thus no difference be-tween having one or more than one registers on a wire.Their technique can be extended to solve the problem with both gate and interconnect delay optimally by modifying some of the constraint formulation.In order to formulate the problem as an MILP,for each gate v ,we need to define a term a (v )that represents the maximum arrival time at the output of gate v .An example to illustrate this definition is shown in Figure 2.We can then formulate the problem as the following MILP:d v ≤a (v )∀v ∈V (1)a (v )≤T ∀v ∈V(2)r (v )+w uv −r (u )≥0∀e uv ∈E(3)a (v )≥a (u )+d uv +d v −T (r (v )+w uv −r (u ))∀e uv ∈E(4)where T is the clock period that we want to check whether it is achievable.Since a (v )is the longest delay to the output of gate v from a register connected directly to an input of v ,this delay must be at least the delay of gate v ,so d v ≤a (v )as stated in (1).Besides,this delay cannot exceed the clock period T as required in (2).Constraint (3)is needed for a feasible retiming solution.Constraint (4)is to ensure that enough registers are on each edge e uv to achieve a clock cycle T .As the largest possible delay between two adjacent registers is T ,the right-hand side of constraint (4)is reduced by T for each register onedge e uv.Note that this constraint also captures the scenario when there is no registers on edge e uv.In that case,the arrival time at node u contributes directly to the arrival time at node v. By introducing a variable R(v)at each node v that is defined as a(v)/T+r(v),the above set of constraints(1)–(4)can be rewritten as a set of difference constraints as follows:R(v)−r(v)≥d vT∀v∈V(5)R(v)−r(v)≤1∀v∈V(6) r(u)−r(v)≤w uv∀e uv∈E(7)R(v)−R(u)≥d uvT+d vT−w uv∀e uv∈E(8)Notice that(5)–(8)is a set of difference constraints involving both integer and real variables.There are|V|real variables R(v),|V|integer variables r(v),and2|V|+2|E|constraints. This can be solved in polynomial time of O(|V||E|lg|V|+ |V|2lg2|V|)if Fibonacci heap is used as the data structure[23].If the above set of constraints is solvable,the values of r(v) and a(v)for all v∈V are known.We can thenfind the exact position of each register on a wire one by one as follows.For each edge e uv,if there are registers retimed on it,i.e.,r(v)+ w uv−r(u)>0,thefirst register on this edge will be placed at a distance of delay T−a(u)from the output of gate u.Other registers are then placed as far from each other as possible,i.e., at a distance of delay T from the previous one,until reaching the gate v.All the remaining registers on this edge are then placed right before v.4A Fast Near-Optimal ApproachIn this approach,wefirst replace each gate by a wire of the same delay and then solve the problem with only interconnect delay optimally and efficiently.Those registers retimed“into”a gate are moved either to the input or the output wires of the gate.The exact positions of the registers on the wires are then determined by a linear program to minimize the clock period. The solution obtained by this approach is very close to the op-timal on average as shown by the experimental results.In the following,wefirst show how the retiming problem with inter-connect delay only can be solved optimally.Then we describe in details how gate delay can be handled simultaneously.4.1Retiming with Interconnect Delay OnlyIn this subsection,we assume d v=0for all v∈V.Wefirst show that the clock period feasibility problem can be reduced to a single-source longest paths problem.We then present a fast algorithm to solve the longest paths problem.4.1.1Reduction to Single-Source Longest Paths Problem We solve the set of constraints(5)–(8)with the help of the fol-lowing lemma.Lemma1Given R(v)for all v∈V satisfying constraint(8), we can obtain a solution to constraints(5)–(8)by setting r(v)= R(v) for all v∈V.Proof:It is clear that0≤R(v)− R(v) <1for all v∈V. Therefore,(5)and(6)are satisfied.For any e uv∈E, r(u)−r(v)≤R(u)−r(v)as r(u)≤R(u)≤(d uvT+R(u))−r(v)as d uvT>0≤(w uv+R(v))−r(v)by constraint(8)<w uv+1as R(v)−r(v)<1As r(u)−r(v)is an integer,it must be less than or equal to w uv.Hence,constraint(7)is also satisfied.2 Lemma1implies that we canfirst solve constraint(8)tofind R(v)and it is then easy tofind r(v)to satisfy the other three constraints.Notice that if d v=0for some v∈V,Lemma1 does not hold as constraint(5)is not satisfied.In other words, this idea cannot be applied to the retiming problem with both interconnect and gate delay discussed in Section3.The problem offinding R(v)for all v∈V to satisfy con-straint(8)can be viewed as a single-source longest paths prob-lem on G with length l uv equals d uv/T−w uv for each e uv∈E. As G is strongly connected,we can pick an arbitrary node as the source node s.1Note that edge lengths can be positive.If G has a positive cycle,the set of constraints has no solutions. It means that the clock period T is infeasible.The solution to this problem is presented in the following subsection.4.1.2Fast Single-Source Longest Paths AlgorithmThe single-source longest paths problem in Section4.1.1can be solved by the Bellman-Ford algorithm[24].The time com-plexity is O(|V||E|),which is at least a factor ofΘ(lg|V|)faster than the optimal algorithm in Section3.In practice,it is a fac-tor ofΘ(lg2|V|)faster as|E|=O(|V|).However,this algo-rithm may still be slow in practice.In this section,we present a single-source longest paths algorithm which is faster in prac-tice.The basic idea is to reduce the size of G by compacting some paths into edges before the Bellman-Ford algorithm is applied.The details are given below.Wefirst transform the graph G(V,E)into a directed acyclic graph(DAG)G (V ,E )by performing a depth-first traver-sal[24]starting from the source node s.The depth-first traver-sal defines a tree in G.Those non-tree edges running from a node u to an ancestor v of u are called back edges.If we point all incoming back edges of a node v to an extra node v ,the resulting graph will be a DAG because every simple cycle in G involves exactly one back edge.Formally,we use E b to denote the set of back edges and V b to denote the set of nodes with an incoming back edge.For each node v in V b,we introduce an extra node v .The back edge e uv is removed from the graph and the edge e uv is added.The resulting DAG is G (V ,E )where V =V∪{v |v∈V b}and E =(E−E b)∪{e u,v |e u,v∈E b}. We set the length l uv of the edge e uv to l uv.To illustrate the transformation,consider the graph G in Figure3(a)with source node A.Suppose the depth-first traversal visits the nodes in the order ACDEFB.Then E b={e DA,e CA,e FC,e FA} and V b={A,C}.We introduce two extra nodes A and C ,and replace the four edges e CA,e DA,e FA and e FC with the edges 1If the original circuit is not strongly connected,a source node s has already been added.Depth first traversalfrom node A(a) Original graph G(b) Directed acyclic graph G’Figure3:An example to illustrate the transformation to a DAG.e CA ,e DA ,e FA and e FC ,respectively.The resulting DAG isshown in Figure3(b).We then construct a graph H with node set V b.The edge setE H contains an edge e uv for u,v∈V b if there exists a path in Gwith either no back edge or one back edge at the end from uto v.The length l H uv of the edge e uv is the longest path distanceamong those paths.Note that the longest path distance in Gwith no back edge(respectively,with one back edge at the endof the path)from u to v equals the longest path distance inG from u to v(respectively,from u to v ).Hence l H uv for allu,v∈V b can be computed by solving|V b|single-source longestpaths problems in G for different source nodes in V b.As G is aDAG,each single-source longest paths problem can be solvedin linear time by visiting the nodes in topological order.Thetime complexity to construct H is therefore O(|V b||E|).It is obvious that every path in H corresponds to at least onepath in G of the same length.Therefore if H contains a positivecycle,G will also contain a positive cycle.On the other hand,if G contains a positive cycle,the cycle can be broken up into aset of paths p1,p2,...,p k such that both endpoints of each pathp i are in V b.Notice that each path p i corresponds to an edge inH of at least the same length.So H must also contain a posi-tive cycle.Therefore we can solve the positive cycle detectionproblem in H instead of in G.If H has no positive cycles,R(v)for all v∈V b can be found from H.R(v)for all v∈V−V b canthen be found in linear time by propagating R(v)for all v∈V bthrough G in topological order.4.1.3The Retiming Algorithm and Time ComplexityThe complete retiming algorithm I-Retiming()is summarizedbelow.The most time consuming steps are step7and step8inside the binary search loop.Step7can be done in O(|V b||E|)time as discussed above.Step8can be done in O(|V b||E H|)time by the Bellman-Ford algorithm.As V b contains muchfewer nodes than V and E H usually contains comparable orfewer edges than E,this technique is usually much more effi-cient than applying the Bellman-Ford algorithm to G directly.The total time complexity is O(|V b|max{|E|,|E H|}lg KεTopt),whereεis the error bound for the binary search,K is the differ-ence between the upper and lower bounds of the clockperiod(a) Original graph G(b) Transformed graph G~Figure4:Representation of gates by wires.initially,and T opt is the optimal clock period.Algorithm I-Retiming()Input:A sequential circuit C with interconnect delay onlyOutput:An optimally retimed circuit of C1.Build graph G(V,E)from C2.Build DAG G by DFS(G)3.C up=a feasible clock,C low=an infeasible clock4.Do5.T=(C up+C low)/26.Update edge lengths of G according to T7.Build graph H(V b,E H)with E H={e uv|u∈anc(v)∪anc(v )}byfinding single-source longest paths in G8.If H does not have any positive cycle then9.C up=T10.Else11.C low=T12.while(C up−C low)/C up>ε13.T=C up//C up is always a feasible clock periodpute R(v)and r(v)for each node v∈Vpute the exact position of each register on a wire4.2Retiming with Interconnect and Gate DelayIn this section,we discuss how to consider interconnect andgate delay simultaneously based on the above algorithm forinterconnect delay only.To consider gate delay,wefirst repre-sent a gate v with delay d v by a wire e v1v2with delay d v1v2=d v.This transformation for the circuit in Figure3(a)is shown inFigure4(b).We can then obtain an optimal retiming on thistransformed circuit˜G using the algorithm in Section4.1.How-ever the retiming solution obtained on˜G may not be feasiblefor the original circuit G because some registers may be re-timed into a wire that represents a gate.Therefore,we need toperform a post-processing step to get back a feasible retimingsolution for G from the optimal retiming solution for˜G.Thisis done by linear programming.First of all,we move the registers in a gate either backwardto the input wires or forward to the output wires of the gate,depending on which direction has a shorter distance.An ex-ample showing the relocation of registers is given in Figure5.After this relocation step,the number of registersˆw uv on eachedge e uv isfixed.A linear program is used to determine the(a) A retimed solution in G~(b) Registers are relocated in G Figure5:Relocation of registers retimed into a gate.exact positions of the registers on the edges.The objective of the linear program is to minimize the clock period T subject to the constraints in register count on each edge.In the fol-lowing,we use x k uv to denote the delay from the k th register to the k+1st register of the wire from node u to node v in G for k=0,1,...,ˆw uv.Notice that whenˆw uv=0,x0uv is the delay of the whole wire,and when k=0and k=ˆw uv>0,x k uv are the delays of the wire from node u to thefirst register and from the last register to node v,respectively.The linear program is formulated as follows:Minimize TSubject to∑ˆw uvk=0x k uv=d uv∀e uv∈E(A)xˆw uv uv+d v≤a(v)∀e uv∈E s.t.ˆw uv>0(B)a(u)+x0uv≤T∀e uv∈E s.t.ˆw uv>0(C)a(u)+d uv≤a(v)∀e uv∈E s.t.ˆw uv=0(D) For the circuit in Figure5(b),example constraints are x0CD+ x1CD=d CD for type(A),x1CD+d D≤a(D)for type(B),a(C)+ x0CD≤T for type(C),and a(B)+d BD≤a(D)for type(D). We can solve this linear program to obtain the best possible clock period T∗under the register count constraint on each edge.The overall algorithm IG-Retiming()to handle both in-terconnect and gate delay is summarized as follows: Algorithm IG-Retiming()Input:A sequential circuit C with both interconnect and gate delay Output:A retimed circuit of C1.Build graph G from C2.Build˜G by replacing each gate in G by a wire of the same delay3.Solve the retiming problem of˜G by I-Retiming()4.Move registers away from wires that represent gates5.Set up a linear program based on the register count on each edge6.Solve the linear program to obtain a feasible retiming solutionand the smallest possible clock period T∗5Experimental ResultsWe implemented the two approaches in a1.8GHz Intel Xeon PC with512KB cache and512MB RAM.We tested them with circuits from the ISCAS89benchmark suite.In our ex-periments,we implement the circuits in a0.25µm process.We layout the circuits by Silicon Ensemble.Wire delays are then extracted according to the layout.In our current implementa-tion,the lower and upper bounds of the binary search are setto0and100ns respectively.In the near-optimal approach,weperform the procedure I-Retiming()with an error bound of1%.After assigning the registers retimed into a gate to the appro-priate wires,a linear program is set up to relocate the registerson the wires to get the smallest possible clock period T∗.Inthe optimal approach,binary search is performed until an errorbound of0.01%is obtained.We call the resulting clock periodT opt.Notice that we do not need to obtain a very accurate re-sult from I-Retiming()because the solution is optimized by thelinear program afterwards.On average,the number of binarysearch iterations is9.6for the near-optimal approach and16.5for the optimal approach.The results are shown in Table1.The second and thirdcolumns give the number of nodes and the number of edgesin the graph G,respectively.Notice that all circuits are notstrongly connected.The number of nodes and edges listed arethose after the addition of the source node,the target node,andthe associated edges.The fourth andfifth columns show thenumber of nodes and the number of edges in the reduced graphH,respectively.These two values are dependent on the node chosen as the root in the depth-first traversal.In our current im-plementation,we always pick the additional node s as the root.We notice that using other nodes as the root does not changethe result significantly.The speedup of the Bellman-Ford al-gorithm by the graph reduction approach in Section4.1.2is (|V||E|)/(|V b||E H|),which is given in the sixth column.The graph reduction approach is faster in all circuits except s38584.On average,it is faster by30.61times.However,the speedupis less(may even be less than one)for larger circuits.The rea-son is that|E H|is roughly quadratic in|V b|.For the circuits in Table1,the ratio of|E H|to|V b|2is from0.11to0.86with an average of0.41.Therefore,the graph reduction approach may not be useful for large circuits.We can avoid a slowdown of the Bellman-Ford algorithm by determining whether to use G or H based on the ratio(|V||E|)/(|V b||E H|).|V b|and|E H|can be found in O(|V b||E|)time.Moreover,we only need to per-form this checking once for each circuit.Hence,the runtime overhead is insignificant compared with the total runtime. The seventh,eighth,and ninth columns show the runtime of the I-Retiming()procedure,the time taken to solve the linear program,and the total runtime,respectively.The tenth col-umn shows the runtime for the optimal approach.We can see that the near-optimal approach is much more efficient than the optimal approach(especially for large circuits).The eleventh and twelfth columns show the clock period T∗and T opt ob-tained by the near-optimal approach and the optimal approach, respectively.The last column is the percentage increase of T∗over T opt.The clock period produced by the near-optimal ap-proach is only0.13%more than that by the optimal approach on average.The optimal clock period is found in seven out of thirteen circuits.6ConclusionWe have presented two elegant approaches to perform retim-ing on sequential circuits with both interconnect and gate de-lay.This is a pioneer work in solving this problem as far as weNo.of No.of No.of No.of CPU Time Clock Period Circuit Nodes Edges Nodes Edges|V||E|I-Retiming+LP=IG-Retiming Optimal T∗T opt T∗−T optT opt in V in E in V b in E H|V b||E H|(sec)(sec)(sec)(sec)(ns)(ns)(%) s148865514052762754.360.090.190.28 5.6218.8518.820.16 s149464914113074940.750.090.160.25 4.3720.7820.780.00 s327115742707112336011.320.380.71 1.0933.7010.2410.240.00 s33301791289056120077.020.130.370.5043.1427.0527.050.00 s33841687278298204123.460.160.580.7425.1924.2124.160.21 s48632344409315420413 3.05 2.130.99 3.1287.7523.5823.580.00 s53782781426166255470.300.550.61 1.16138.6827.2727.250.07 s666930825399671876132.380.36 1.55 1.91177.5923.0722.96 1.00 s92345599800532526570 5.19 2.69 1.39 4.08512.8642.7342.730.00 s1320779531130255044825 3.65 6.45 1.668.111161.0772.3472.340.00 s15850977413794603100738 2.2221.42 2.6024.021545.5967.8267.820.00 s359321606728590884163945 3.1754.59 6.6661.258644.2729.5929.540.17 s3841722181321351657308790 1.3972.6410.9283.567680.7936.5336.520.03 s385841925533010192411158680.30433.8211.81445.63>1500094.26Table1:The runtime of the algorithms and the clock periods obtained.know.Most traditional retiming algorithms have neglected in-terconnect delay.Ourfirst approach is extended from the MILP approach in the paper[1]and can solve the problem optimally. Our second approach is an improvement over thefirst one in terms of practical applicability.The main idea is to transform the problem into a single-source longest paths problem in a reduced graph.We have implemented both algorithms,and compared their performance on ISCAS89benchmark circuits. Experimental results show that the second approach gives so-lutions that are only0.13%larger than the optimal on average but in a much shorter runtime.References[1]Charles E.Leiserson and James B.Saxe.Retiming SynchronousCircuitry.Algorithmica,6:5–35,1991.[2] C.V.Schimpfle,Sven Simon,and Josef A.Nossek.OptimalPlacement of Registers in Data Paths for Low Power Design.In Proc.ISCAS,pages2160–2163,1997.[3]J.Monteiro,S.Devadas,and A.Ghosh.Retiming SequentialCircuits for Low Power.In Proc.ICCAD,pages398–402,1993.[4] A.El-Maleh,T.E.Marchok,J.Rajski,and W.Maly.Behaviorand Testability Preservation under the Retiming Transformation.IEEE TCAD,16:528–542,1997.[5]S.Dey and S.Chakradhar.Retiming Sequential Circuits to En-hance Testability.In Proc.IEEE VLSI Test Symposium,pages 28–33,1994.[6]Rajeev K.Ranjan,Vigyan Singhal,Fabio Somenzi,andRobert K.Brayton.On the Optimization Power of Retiming and Resynthesis Transformation.In Proc.ICCAD,pages402–407, 1998.[7]Peichen Pan,Arvind K.Karandikar,and C.L.Liu.OptimalClock Period Clustering for Sequential Circuits with Retiming.IEEE TCAD,17(6):489–498,1998.[8]Jason Cong,Honching Li,and Chang Wu.Simultaneous Cir-cuit Partitioning/Clustering with Retiming for Performance Op-timization.In Proc.DAC,pages460–465,1999.[9]Jason Cong,Sung Kyu Lim,and Chang Wu.PerformanceDriven Multi-level and Multiway Partitioning with Retiming.In Proc.DAC,pages274–279,2000.[10]Jason Cong and Sung Kyu Lim.Physical Planning with Retim-ing.In Proc.ICCAD,pages2–7,2000.[11]N.Shenoy and R.Rudell.Efficient Implementation of Retiming.In Proc.ICCAD,pages226–233,1994.[12]N.Shenoy,R.K.Brayton,and A.Sangiovanni-Vincentelli.Re-timing of Circuits with Single Phase Transparent Latches.In Proc.ICCAD,pages86–89,1991.[13]Rahul B.Deokar and Sachin S.Sapatnekar.A Fresh Look atRetiming via Clock Skew Optimization.In Proc.DAC,pages 310–315,1995.[14]Marios C.Papaefthymiou.Asymptotically Efficient Retimingunder Setup and Hold Constraints.In Proc.ICCAD,pages396–401,1998.[15]H.J.Touati and puting the Initial States ofRetimed Circuits.IEEE TCAD,12:157–162,1993.[16]I.Karkowski and R.H.J.M.Otten.Retiming Synchronous Cir-cuitry with Imprecise Delay.In Proc.DAC,pages322–326, 1995.[17]Vigyan Singhal,Sharad Malik,and Robert K.Brayton.TheCase for Retiming with Explicit Reset Circuitry.In Proc.IC-CAD,pages618–625,1996.[18]N.Maheshwari and S.S.Sapatnekar.An Improved Algorithmfor Minimum-area Retiming.In Proc.DAC,pages2–7,1997.[19]T.Soyata and E.G.Friedmann.Retiming with nonzero clockskew,variable register and interconnect delay.In Proc.ICCAD, pages234–241,1994.[20]Kumar lgudi and Marios C.Papaefthymiou.DELAY:AnEfficient Tool for Retiming with Realistic Delay Modeling.In Proc.DAC,pages304–309,1995.[21]Tzu-Chieh Tien,Hsiao-Pin Su,and Yu-Wen Tsay.IntegratingLogic Retiming and Register Placement.In Proc.ICCAD,pages 136–139,1998.[22]Abdallah Tabbara,Robert K.Brayton,and A.Richard Newton.Retiming for DSM with Area-Delay Trade-offs and Delay Con-straints.In Proc.DAC,pages725–730,1999.[23] C.E.Leiserson and James B.Saxe.A Mixed-Integer Program-ming Problem Which is Efficiently Solvable.Journal of Algo-rithms,9:114–128,1988.[24]Thomas H.Cormen and Charles E.Leiserson and Ronald L.Rivest.Introduction to Algorithms.McGraw Hill,eighth edi-tion,1992.。
NuMicro N9H30系列开发板用户手册说明书
NuMicro®FamilyArm® ARM926EJ-S BasedNuMaker-HMI-N9H30User ManualEvaluation Board for NuMicro® N9H30 SeriesNUMAKER-HMI-N9H30 USER MANUALThe information described in this document is the exclusive intellectual property ofNuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.Nuvoton is providing this document only for reference purposes of NuMicro microcontroller andmicroprocessor based system design. Nuvoton assumes no responsibility for errors or omissions.All data and specifications are subject to change without notice.For additional information or questions, please contact: Nuvoton Technology Corporation.Table of Contents1OVERVIEW (5)1.1Features (7)1.1.1NuMaker-N9H30 Main Board Features (7)1.1.2NuDesign-TFT-LCD7 Extension Board Features (7)1.2Supporting Resources (8)2NUMAKER-HMI-N9H30 HARDWARE CONFIGURATION (9)2.1NuMaker-N9H30 Board － Front View (9)2.2NuMaker-N9H30 Board － Rear View (14)2.3NuDesign-TFT-LCD7 － Front View (20)2.4NuDesign-TFT-LCD7 － Rear View (21)2.5NuMaker-N9H30 and NuDesign-TFT-LCD7 PCB Placement (22)3NUMAKER-N9H30 AND NUDESIGN-TFT-LCD7 SCHEMATICS (24)3.1NuMaker-N9H30 － GPIO List Circuit (24)3.2NuMaker-N9H30 － System Block Circuit (25)3.3NuMaker-N9H30 － Power Circuit (26)3.4NuMaker-N9H30 － N9H30F61IEC Circuit (27)3.5NuMaker-N9H30 － Setting, ICE, RS-232_0, Key Circuit (28)NUMAKER-HMI-N9H30 USER MANUAL3.6NuMaker-N9H30 － Memory Circuit (29)3.7NuMaker-N9H30 － I2S, I2C_0, RS-485_6 Circuit (30)3.8NuMaker-N9H30 － RS-232_2 Circuit (31)3.9NuMaker-N9H30 － LCD Circuit (32)3.10NuMaker-N9H30 － CMOS Sensor, I2C_1, CAN_0 Circuit (33)3.11NuMaker-N9H30 － RMII_0_PF Circuit (34)3.12NuMaker-N9H30 － RMII_1_PE Circuit (35)3.13NuMaker-N9H30 － USB Circuit (36)3.14NuDesign-TFT-LCD7 － TFT-LCD7 Circuit (37)4REVISION HISTORY (38)List of FiguresFigure 1-1 Front View of NuMaker-HMI-N9H30 Evaluation Board (5)Figure 1-2 Rear View of NuMaker-HMI-N9H30 Evaluation Board (6)Figure 2-1 Front View of NuMaker-N9H30 Board (9)Figure 2-2 Rear View of NuMaker-N9H30 Board (14)Figure 2-3 Front View of NuDesign-TFT-LCD7 Board (20)Figure 2-4 Rear View of NuDesign-TFT-LCD7 Board (21)Figure 2-5 Front View of NuMaker-N9H30 PCB Placement (22)Figure 2-6 Rear View of NuMaker-N9H30 PCB Placement (22)Figure 2-7 Front View of NuDesign-TFT-LCD7 PCB Placement (23)Figure 2-8 Rear View of NuDesign-TFT-LCD7 PCB Placement (23)Figure 3-1 GPIO List Circuit (24)Figure 3-2 System Block Circuit (25)Figure 3-3 Power Circuit (26)Figure 3-4 N9H30F61IEC Circuit (27)Figure 3-5 Setting, ICE, RS-232_0, Key Circuit (28)Figure 3-6 Memory Circuit (29)Figure 3-7 I2S, I2C_0, RS-486_6 Circuit (30)Figure 3-8 RS-232_2 Circuit (31)Figure 3-9 LCD Circuit (32)NUMAKER-HMI-N9H30 USER MANUAL Figure 3-10 CMOS Sensor, I2C_1, CAN_0 Circuit (33)Figure 3-11 RMII_0_PF Circuit (34)Figure 3-12 RMII_1_PE Circuit (35)Figure 3-13 USB Circuit (36)Figure 3-14 TFT-LCD7 Circuit (37)List of TablesTable 2-1 LCD Panel Combination Connector (CON8) Pin Function (11)Table 2-2 Three Sets of Indication LED Functions (12)Table 2-3 Six Sets of User SW, Key Matrix Functions (12)Table 2-4 CMOS Sensor Connector (CON10) Function (13)Table 2-5 JTAG ICE Interface (J2) Function (14)Table 2-6 Expand Port (CON7) Function (16)Table 2-7 UART0 (J3) Function (16)Table 2-8 UART2 (J6) Function (16)Table 2-9 RS-485_6 (SW6~8) Function (17)Table 2-10 Power on Setting (SW4) Function (17)Table 2-11 Power on Setting (S2) Function (17)Table 2-12 Power on Setting (S3) Function (17)Table 2-13 Power on Setting (S4) Function (17)Table 2-14 Power on Setting (S5) Function (17)Table 2-15 Power on Setting (S7/S6) Function (18)Table 2-16 Power on Setting (S9/S8) Function (18)Table 2-17 CMOS Sensor Connector (CON9) Function (19)Table 2-18 CAN_0 (SW9~10) Function (19)NUMAKER-HMI-N9H30 USER MANUAL1 OVERVIEWThe NuMaker-HMI-N9H30 is an evaluation board for GUI application development. The NuMaker-HMI-N9H30 consists of two parts: a NuMaker-N9H30 main board and a NuDesign-TFT-LCD7 extensionboard. The NuMaker-HMI-N9H30 is designed for project evaluation, prototype development andvalidation with HMI (Human Machine Interface) function.The NuMaker-HMI-N9H30 integrates touchscreen display, voice input/output, rich serial port serviceand I/O interface, providing multiple external storage methods.The NuDesign-TFT-LCD7 can be plugged into the main board via the DIN_32x2 extension connector.The NuDesign-TFT-LCD7 includes one 7” LCD which the resolution is 800x480 with RGB-24bits andembedded the 4-wires resistive type touch panel.Figure 1-1 Front View of NuMaker-HMI-N9H30 Evaluation BoardNUMAKER-HMI-N9H30 USER MANUAL Figure 1-2 Rear View of NuMaker-HMI-N9H30 Evaluation Board1.1 Features1.1.1 NuMaker-N9H30 Main Board Features●N9H30F61IEC chip: LQFP216 pin MCP package with DDR (64 MB)●SPI Flash using W25Q256JVEQ (32 MB) booting with quad mode or storage memory●NAND Flash using W29N01HVSINA (128 MB) booting or storage memory●One Micro-SD/TF card slot served either as a SD memory card for data storage or SDIO(Wi-Fi) device●Two sets of COM ports:–One DB9 RS-232 port with UART_0 used 75C3232E transceiver chip can be servedfor function debug and system development.–One DB9 RS-232 port with UART_2 used 75C3232E transceiver chip for userapplication●22 GPIO expansion ports, including seven sets of UART functions●JTAG interface provided for software development●Microphone input and Earphone/Speaker output with 24-bit stereo audio codec(NAU88C22) for I2S interfaces●Six sets of user-configurable push button keys●Three sets of LEDs for status indication●Provides SN65HVD230 transceiver chip for CAN bus communication●Provides MAX3485 transceiver chip for RS-485 device connection●One buzzer device for program applicationNUMAKER-HMI-N9H30 USER MANUAL●Two sets of RJ45 ports with Ethernet 10/100 Mbps MAC used IP101GR PHY chip●USB_0 that can be used as Device/HOST and USB_1 that can be used as HOSTsupports pen drives, keyboards, mouse and printers●Provides over-voltage and over current protection used APL3211A chip●Retain RTC battery socket for CR2032 type and ADC0 detect battery voltage●System power could be supplied by DC-5V adaptor or USB VBUS1.1.2 NuDesign-TFT-LCD7 Extension Board Features●7” resolution 800x480 4-wire resistive touch panel for 24-bits RGB888 interface●DIN_32x2 extension connector1.2 Supporting ResourcesFor sample codes and introduction about NuMaker-N9H30, please refer to N9H30 BSP:https:///products/gui-solution/gui-platform/numaker-hmi-n9h30/?group=Software&tab=2Visit NuForum for further discussion about the NuMaker-HMI-N9H30:/viewforum.php?f=31 NUMAKER-HMI-N9H30 USER MANUALNUMAKER-HMI-N9H30 USER MANUAL2 NUMAKER-HMI-N9H30 HARDWARE CONFIGURATION2.1 NuMaker-N9H30 Board － Front View Combination Connector (CON8)6 set User SWs (K1~6)3set Indication LEDs (LED1~3)Power Supply Switch (SW_POWER1)Audio Codec(U10)Microphone(M1)NAND Flash(U9)RS-232 Transceiver(U6, U12)RS-485 Transceiver(U11)CAN Transceiver (U13)Figure 2-1 Front View of NuMaker-N9H30 BoardFigure 2-1 shows the main components and connectors from the front side of NuMaker-N9H30 board. The following lists components and connectors from the front view:NuMaker-N9H30 board and NuDesign-TFT-LCD7 board combination connector (CON8). This panel connector supports 4-/5-wire resistive touch or capacitance touch panel for 24-bits RGB888 interface.Connector GPIO pin of N9H30 FunctionCON8.1 - Power 3.3VCON8.2 - Power 3.3VCON8.3 GPD7 LCD_CSCON8.4 GPH3 LCD_BLENCON8.5 GPG9 LCD_DENCON8.7 GPG7 LCD_HSYNCCON8.8 GPG6 LCD_CLKCON8.9 GPD15 LCD_D23(R7)CON8.10 GPD14 LCD_D22(R6)CON8.11 GPD13 LCD_D21(R5)CON8.12 GPD12 LCD_D20(R4)CON8.13 GPD11 LCD_D19(R3)CON8.14 GPD10 LCD_D18(R2)CON8.15 GPD9 LCD_D17(R1)CON8.16 GPD8 LCD_D16(R0)CON8.17 GPA15 LCD_D15(G7)CON8.18 GPA14 LCD_D14(G6)CON8.19 GPA13 LCD_D13(G5)CON8.20 GPA12 LCD_D12(G4)CON8.21 GPA11 LCD_D11(G3)CON8.22 GPA10 LCD_D10(G2)CON8.23 GPA9 LCD_D9(G1) NUMAKER-HMI-N9H30 USER MANUALCON8.24 GPA8 LCD_D8(G0)CON8.25 GPA7 LCD_D7(B7)CON8.26 GPA6 LCD_D6(B6)CON8.27 GPA5 LCD_D5(B5)CON8.28 GPA4 LCD_D4(B4)CON8.29 GPA3 LCD_D3(B3)CON8.30 GPA2 LCD_D2(B2)CON8.31 GPA1 LCD_D1(B1)CON8.32 GPA0 LCD_D0(B0)CON8.33 - -CON8.34 - -CON8.35 - -CON8.36 - -CON8.37 GPB2 LCD_PWMCON8.39 - VSSCON8.40 - VSSCON8.41 ADC7 XPCON8.42 ADC3 VsenCON8.43 ADC6 XMCON8.44 ADC4 YMCON8.45 - -CON8.46 ADC5 YPCON8.47 - VSSCON8.48 - VSSCON8.49 GPG0 I2C0_CCON8.50 GPG1 I2C0_DCON8.51 GPG5 TOUCH_INTCON8.52 - -CON8.53 - -CON8.54 - -CON8.55 - -NUMAKER-HMI-N9H30 USER MANUAL CON8.56 - -CON8.57 - -CON8.58 - -CON8.59 - VSSCON8.60 - VSSCON8.61 - -CON8.62 - -CON8.63 - Power 5VCON8.64 - Power 5VTable 2-1 LCD Panel Combination Connector (CON8) Pin Function●Power supply switch (SW_POWER1): System will be powered on if the SW_POWER1button is pressed●Three sets of indication LEDs:LED Color DescriptionsLED1 Red The system power will beterminated and LED1 lightingwhen the input voltage exceeds5.7V or the current exceeds 2A.LED2 Green Power normal state.LED3 Green Controlled by GPH2 pin Table 2-2 Three Sets of Indication LED Functions●Six sets of user SW, Key Matrix for user definitionKey GPIO pin of N9H30 FunctionK1 GPF10 Row0 GPB4 Col0K2 GPF10 Row0 GPB5 Col1K3 GPE15 Row1 GPB4 Col0K4 GPE15 Row1 GPB5 Col1K5 GPE14 Row2 GPB4 Col0K6GPE14 Row2GPB5 Col1 Table 2-3 Six Sets of User SW, Key Matrix Functions●NAND Flash (128 MB) with Winbond W29N01HVS1NA (U9)●Microphone (M1): Through Nuvoton NAU88C22 chip sound input●Audio CODEC chip (U10): Nuvoton NAU88C22 chip connected to N9H30 using I2Sinterface–SW6/SW7/SW8: 1-2 short for RS-485_6 function and connected to 2P terminal (CON5and J5)–SW6/SW7/SW8: 2-3 short for I2S function and connected to NAU88C22 (U10).●CMOS Sensor connector (CON10, SW9~10)–SW9~10: 1-2 short for CAN_0 function and connected to 2P terminal (CON11)–SW9~10: 2-3 short for CMOS sensor function and connected to CMOS sensorconnector (CON10)Connector GPIO pin of N9H30 FunctionCON10.1 - VSSCON10.2 - VSSNUMAKER-HMI-N9H30 USER MANUALCON10.3 - Power 3.3VCON10.4 - Power 3.3VCON10.5 - -CON10.6 - -CON10.7 GPI4 S_PCLKCON10.8 GPI3 S_CLKCON10.9 GPI8 S_D0CON10.10 GPI9 S_D1CON10.11 GPI10 S_D2CON10.12 GPI11 S_D3CON10.13 GPI12 S_D4CON10.14 GPI13 S_D5CON10.15 GPI14 S_D6CON10.16 GPI15 S_D7CON10.17 GPI6 S_VSYNCCON10.18 GPI5 S_HSYNCCON10.19 GPI0 S_PWDNNUMAKER-HMI-N9H30 USER MANUAL CON10.20 GPI7 S_nRSTCON10.21 GPG2 I2C1_CCON10.22 GPG3 I2C1_DCON10.23 - VSSCON10.24 - VSSTable 2-4 CMOS Sensor Connector (CON10) FunctionNUMAKER-HMI-N9H30 USER MANUAL2.2NuMaker-N9H30 Board － Rear View5V In (CON1)RS-232 DB9 (CON2,CON6)Expand Port (CON7)Speaker Output (J4)Earphone Output (CON4)Buzzer (BZ1)System ResetSW (SW5)SPI Flash (U7,U8)JTAG ICE (J2)Power ProtectionIC (U1)N9H30F61IEC (U5)Micro SD Slot (CON3)RJ45 (CON12, CON13)USB1 HOST (CON15)USB0 Device/Host (CON14)CAN_0 Terminal (CON11)CMOS Sensor Connector (CON9)Power On Setting(SW4, S2~S9)RS-485_6 Terminal (CON5)RTC Battery(BT1)RMII PHY (U14,U16)Figure 2-2 Rear View of NuMaker-N9H30 BoardFigure 2-2 shows the main components and connectors from the rear side of NuMaker-N9H30 board. The following lists components and connectors from the rear view:● +5V In (CON1): Power adaptor 5V input ●JTAG ICE interface (J2) ConnectorGPIO pin of N9H30Function J2.1 - Power 3.3V J2.2 GPJ4 nTRST J2.3 GPJ2 TDI J2.4 GPJ1 TMS J2.5 GPJ0 TCK J2.6 - VSS J2.7 GPJ3 TD0 J2.8-RESETTable 2-5 JTAG ICE Interface (J2) Function●SPI Flash (32 MB) with Winbond W25Q256JVEQ (U7); only one (U7 or U8) SPI Flashcan be used●System Reset (SW5): System will be reset if the SW5 button is pressed●Buzzer (BZ1): Control by GPB3 pin of N9H30●Speaker output (J4): Through the NAU88C22 chip sound output●Earphone output (CON4): Through the NAU88C22 chip sound output●Expand port for user use (CON7):Connector GPIO pin of N9H30 FunctionCON7.1 - Power 3.3VCON7.2 - Power 3.3VCON7.3 GPE12 UART3_TXDCON7.4 GPH4 UART1_TXDCON7.5 GPE13 UART3_RXDCON7.6 GPH5 UART1_RXDCON7.7 GPB0 UART5_TXDCON7.8 GPH6 UART1_RTSCON7.9 GPB1 UART5_RXDCON7.10 GPH7 UART1_CTSCON7.11 GPI1 UART7_TXDNUMAKER-HMI-N9H30 USER MANUAL CON7.12 GPH8 UART4_TXDCON7.13 GPI2 UART7_RXDCON7.14 GPH9 UART4_RXDCON7.15 - -CON7.16 GPH10 UART4_RTSCON7.17 - -CON7.18 GPH11 UART4_CTSCON7.19 - VSSCON7.20 - VSSCON7.21 GPB12 UART10_TXDCON7.22 GPH12 UART8_TXDCON7.23 GPB13 UART10_RXDCON7.24 GPH13 UART8_RXDCON7.25 GPB14 UART10_RTSCON7.26 GPH14 UART8_RTSCON7.27 GPB15 UART10_CTSCON7.28 GPH15 UART8_CTSCON7.29 - Power 5VCON7.30 - Power 5VTable 2-6 Expand Port (CON7) Function●UART0 selection (CON2, J3):–RS-232_0 function and connected to DB9 female (CON2) for debug message output.–GPE0/GPE1 connected to 2P terminal (J3).Connector GPIO pin of N9H30 Function J3.1 GPE1 UART0_RXDJ3.2 GPE0 UART0_TXDTable 2-7 UART0 (J3) Function●UART2 selection (CON6, J6):–RS-232_2 function and connected to DB9 female (CON6) for debug message output –GPF11~14 connected to 4P terminal (J6)Connector GPIO pin of N9H30 Function J6.1 GPF11 UART2_TXDJ6.2 GPF12 UART2_RXDJ6.3 GPF13 UART2_RTSJ6.4 GPF14 UART2_CTSTable 2-8 UART2 (J6) Function●RS-485_6 selection (CON5, J5, SW6~8):–SW6~8: 1-2 short for RS-485_6 function and connected to 2P terminal (CON5 and J5) –SW6~8: 2-3 short for I2S function and connected to NAU88C22 (U10)Connector GPIO pin of N9H30 FunctionSW6:1-2 shortGPG11 RS-485_6_DISW6:2-3 short I2S_DOSW7:1-2 shortGPG12 RS-485_6_ROSW7:2-3 short I2S_DISW8:1-2 shortGPG13 RS-485_6_ENBSW8:2-3 short I2S_BCLKNUMAKER-HMI-N9H30 USER MANUALTable 2-9 RS-485_6 (SW6~8) FunctionPower on setting (SW4, S2~9).SW State FunctionSW4.2/SW4.1 ON/ON Boot from USB SW4.2/SW4.1 ON/OFF Boot from eMMC SW4.2/SW4.1 OFF/ON Boot from NAND Flash SW4.2/SW4.1 OFF/OFF Boot from SPI Flash Table 2-10 Power on Setting (SW4) FunctionSW State FunctionS2 Short System clock from 12MHzcrystalS2 Open System clock from UPLL output Table 2-11 Power on Setting (S2) FunctionSW State FunctionS3 Short Watchdog Timer OFFS3 Open Watchdog Timer ON Table 2-12 Power on Setting (S3) FunctionSW State FunctionS4 Short GPJ[4:0] used as GPIO pinS4Open GPJ[4:0] used as JTAG ICEinterfaceTable 2-13 Power on Setting (S4) FunctionSW State FunctionS5 Short UART0 debug message ONS5 Open UART0 debug message OFFTable 2-14 Power on Setting (S5) FunctionSW State FunctionS7/S6 Short/Short NAND Flash page size 2KBS7/S6 Short/Open NAND Flash page size 4KBS7/S6 Open/Short NAND Flash page size 8KBNUMAKER-HMI-N9H30 USER MANUALS7/S6 Open/Open IgnoreTable 2-15 Power on Setting (S7/S6) FunctionSW State FunctionS9/S8 Short/Short NAND Flash ECC type BCH T12S9/S8 Short/Open NAND Flash ECC type BCH T15S9/S8 Open/Short NAND Flash ECC type BCH T24S9/S8 Open/Open IgnoreTable 2-16 Power on Setting (S9/S8) FunctionCMOS Sensor connector (CON9, SW9~10)–SW9~10: 1-2 short for CAN_0 function and connected to 2P terminal (CON11).–SW9~10: 2-3 short for CMOS sensor function and connected to CMOS sensorconnector (CON9).Connector GPIO pin of N9H30 FunctionCON9.1 - VSSCON9.2 - VSSCON9.3 - Power 3.3VCON9.4 - Power 3.3V NUMAKER-HMI-N9H30 USER MANUALCON9.5 - -CON9.6 - -CON9.7 GPI4 S_PCLKCON9.8 GPI3 S_CLKCON9.9 GPI8 S_D0CON9.10 GPI9 S_D1CON9.11 GPI10 S_D2CON9.12 GPI11 S_D3CON9.13 GPI12 S_D4CON9.14 GPI13 S_D5CON9.15 GPI14 S_D6CON9.16 GPI15 S_D7CON9.17 GPI6 S_VSYNCCON9.18 GPI5 S_HSYNCCON9.19 GPI0 S_PWDNCON9.20 GPI7 S_nRSTCON9.21 GPG2 I2C1_CCON9.22 GPG3 I2C1_DCON9.23 - VSSCON9.24 - VSSTable 2-17 CMOS Sensor Connector (CON9) Function●CAN_0 Selection (CON11, SW9~10):–SW9~10: 1-2 short for CAN_0 function and connected to 2P terminal (CON11) –SW9~10: 2-3 short for CMOS sensor function and connected to CMOS sensor connector (CON9, CON10)SW GPIO pin of N9H30 FunctionSW9:1-2 shortGPI3 CAN_0_RXDSW9:2-3 short S_CLKSW10:1-2 shortGPI4 CAN_0_TXDSW10:2-3 short S_PCLKTable 2-18 CAN_0 (SW9~10) Function●USB0 Device/HOST Micro-AB connector (CON14), where CON14 pin4 ID=1 is Device,ID=0 is HOST●USB1 for USB HOST with Type-A connector (CON15)●RJ45_0 connector with LED indicator (CON12), RMII PHY with IP101GR (U14)●RJ45_1 connector with LED indicator (CON13), RMII PHY with IP101GR (U16)●Micro-SD/TF card slot (CON3)●SOC CPU: Nuvoton N9H30F61IEC (U5)●Battery power for RTC 3.3V powered (BT1, J1), can detect voltage by ADC0●RTC power has 3 sources:–Share with 3.3V I/O power–Battery socket for CR2032 (BT1)–External connector (J1)●Board version 2.1NUMAKER-HMI-N9H30 USER MANUAL2.3 NuDesign-TFT-LCD7 －Front ViewFigure 2-3 Front View of NuDesign-TFT-LCD7 BoardFigure 2-3 shows the main components and connectors from the Front side of NuDesign-TFT-LCD7board.7” resolution 800x480 4-W resistive touch panel for 24-bits RGB888 interface2.4 NuDesign-TFT-LCD7 －Rear ViewFigure 2-4 Rear View of NuDesign-TFT-LCD7 BoardFigure 2-4 shows the main components and connectors from the rear side of NuDesign-TFT-LCD7board.NuMaker-N9H30 and NuDesign-TFT-LCD7 combination connector (CON1).NUMAKER-HMI-N9H30 USER MANUAL 2.5 NuMaker-N9H30 and NuDesign-TFT-LCD7 PCB PlacementFigure 2-5 Front View of NuMaker-N9H30 PCB PlacementFigure 2-6 Rear View of NuMaker-N9H30 PCB PlacementNUMAKER-HMI-N9H30 USER MANUALFigure 2-7 Front View of NuDesign-TFT-LCD7 PCB PlacementFigure 2-8 Rear View of NuDesign-TFT-LCD7 PCB Placement3 NUMAKER-N9H30 AND NUDESIGN-TFT-LCD7 SCHEMATICS3.1 NuMaker-N9H30 － GPIO List CircuitFigure 3-1 shows the N9H30F61IEC GPIO list circuit.Figure 3-1 GPIO List Circuit NUMAKER-HMI-N9H30 USER MANUAL3.2 NuMaker-N9H30 － System Block CircuitFigure 3-2 shows the System Block Circuit.NUMAKER-HMI-N9H30 USER MANUALFigure 3-2 System Block Circuit3.3 NuMaker-N9H30 － Power CircuitFigure 3-3 shows the Power Circuit.NUMAKER-HMI-N9H30 USER MANUALFigure 3-3 Power Circuit3.4 NuMaker-N9H30 － N9H30F61IEC CircuitFigure 3-4 shows the N9H30F61IEC Circuit.Figure 3-4 N9H30F61IEC CircuitNUMAKER-HMI-N9H30 USER MANUAL3.5 NuMaker-N9H30 － Setting, ICE, RS-232_0, Key CircuitFigure 3-5 shows the Setting, ICE, RS-232_0, Key Circuit.NUMAKER-HMI-N9H30 USER MANUALFigure 3-5 Setting, ICE, RS-232_0, Key Circuit3.6 NuMaker-N9H30 － Memory CircuitFigure 3-6 shows the Memory Circuit.NUMAKER-HMI-N9H30 USER MANUALFigure 3-6 Memory Circuit3.7 NuMaker-N9H30 － I2S, I2C_0, RS-485_6 CircuitFigure 3-7 shows the I2S, I2C_0, RS-486_6 Circuit.NUMAKER-HMI-N9H30 USER MANUALFigure 3-7 I2S, I2C_0, RS-486_6 Circuit3.8 NuMaker-N9H30 － RS-232_2 CircuitFigure 3-8 shows the RS-232_2 Circuit.NUMAKER-HMI-N9H30 USER MANUALFigure 3-8 RS-232_2 Circuit3.9 NuMaker-N9H30 － LCD CircuitFigure 3-9 shows the LCD Circuit.NUMAKER-HMI-N9H30 USER MANUALFigure 3-9 LCD Circuit3.10 NuMaker-N9H30 － CMOS Sensor, I2C_1, CAN_0 CircuitFigure 3-10 shows the CMOS Sensor,I2C_1, CAN_0 Circuit.NUMAKER-HMI-N9H30 USER MANUALFigure 3-10 CMOS Sensor, I2C_1, CAN_0 Circuit3.11 NuMaker-N9H30 － RMII_0_PF CircuitFigure 3-11 shows the RMII_0_RF Circuit.NUMAKER-HMI-N9H30 USER MANUALFigure 3-11 RMII_0_PF Circuit3.12 NuMaker-N9H30 － RMII_1_PE CircuitFigure 3-12 shows the RMII_1_PE Circuit.NUMAKER-HMI-N9H30 USER MANUALFigure 3-12 RMII_1_PE Circuit3.13 NuMaker-N9H30 － USB CircuitFigure 3-13 shows the USB Circuit.NUMAKER-HMI-N9H30 USER MANUALFigure 3-13 USB Circuit3.14 NuDesign-TFT-LCD7 － TFT-LCD7 CircuitFigure 3-14 shows the TFT-LCD7 Circuit.Figure 3-14 TFT-LCD7 CircuitNUMAKER-HMI-N9H30 USER MANUAL4 REVISION HISTORYDate Revision Description2022.03.24 1.00 Initial version NUMAKER-HMI-N9H30 USER MANUALNUMAKER-HMI-N9H30 USER MANUALImportant NoticeNuvoton Products are neither intended nor warranted for usage in systems or equipment, anymalfunction or failure of which may cause loss of human life, bodily injury or severe propertydamage. Such applications are deemed, “Insecure Usage”.Insecure usage includes, but is not limited to: equipment for surgical implementation, atomicenergy control instruments, airplane or spaceship instruments, the control or operation ofdynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all typesof safety devices, and other applications intended to support or sustain life.All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claimsto Nuvoton as a result of customer’s Insecure Usage, custome r shall indemnify the damagesand liabilities thus incurred by Nuvoton.。
DC2359A demo 说明书
Description High Efficiency Synchronous Step-Down Regulator with Ultralow Quiescent CurrentDemonstration circuit 2359A is a synchronous step-down regulator using L TC®3624HMSE monolithic buck regulator. The DC2359A operates from an input voltage range of 2.7V to 17V and provides and adjustable output voltage range from 1.2V to 5V (V OUT < V IN) at 2A of continuous output current. A user-selectable mode input is provided with the following options: Burst Mode® operation provides the highest efficiency at light loads, while Pulse-Skipping mode (PS) provides the lowest output voltage ripples. Forced Continuous mode (FC) is also available for low EMI and noise interference.The MODE/SYNC pin can also be used to synchronize the switching frequency to an external clock signal. The switching frequency is fixed at 1MHz with a ±40% synccapture range.The regulator features ultralow quiescent current and high efficiencies over a wide V IN and V OUT range. DC2359A L, L T, L TC, L TM, Linear Technology, the Linear logo and Burst Mode are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.performance summaryuses very low profile surface mount components and allceramic output capacitor solutions. The compact 12-leadMSE (5mm × 4mm × 1mm) thermally enhanced packagemakes LTC3624HMSE an excellent choice for batterypowered equipment, emergency radio and general pur-pose step-down power supplies. The H-Grade version isspecified over an operating junction temperature rangeof –40°C to 150°C, typically required for automotive, in-dustrial and military applications that are subject to highambient temperatures.It is recommended to read the data sheet and demo manualof LTC3624 prior using or making any changes to DC2359A.Design files for this circuit board are available at/demo/DC2359A Specifications are at T A = 25°CPARAMETER CONDITIONS VALUEInput Voltage Range 2.7V to 17VOn Board User Selectable Output Voltages V IN = 2.7V to 17V, I OUT = 2A(V OUT < V IN)1.2V, 1.8V,2.5V,3.3V and 5VDefault Mode Setting JP2Burst Mode (“BM” on Circuit Board)Fixed Switching Frequency Internally Programmed Frequency1MHz ±20%Default Output Voltage V OUT V IN = 12V, V OUT = 5V, I OUT = 0A to 2A5V ±2%Maximum Continuous Output Current I OUT2AOutput Voltage Ripples (Peak to Peak)V IN = 12V, V OUT = 5V, I OUT = 2A8.8mV (Figure 7)Load T ransient Response V IN = 12V, V OUT = 5V, I OUT_STEP = 1A to 2A,C OUT = 1 × 47µF219mV (Figure 8)Thermal Performance V IN = 12V, V OUT = 5V, I OUT = 2A,f SW = 1MHz, T A = 25°CFigure 9Efficiency V IN = 12V, V OUT = 5V, I OUT = 2A, BM,f SW = 1MHz, T A = 25°C89.7% (Figure 3)1dc2359afbQuick start proceDureDemonstration circuit 2359A is easy to set up to evaluate the performance of the LTC3624HMSE. Please refer to Figure 1 for proper measurement equipment setup and follow the procedure below:1. Place jumpers in the following positions for a typical 5V output application:Table 1. Typical 5V Output Voltage Jumper SelectionJP1JP2JP7RUN MODE/SYNC V OUTON BM 5.0V2. With power off, connect the input power supply at V IN (E1) and GND (E2)3. Connect the Load between V OUT (E8) and GND (E9). Preset the load to 0A.4. Connect the DMMs to the input and output to monitor the input voltage and output voltage.5. Turn on the power supply at the input. The RUN pin jumper should be at “ON” position. Measure and make sure the input supply voltage is 12V. The output voltage should be 5V ±2%.6. Once the input and output voltages are properly es-tablished, adjust the loads within the operating range (0A to 2A Max) and observe the output voltage regula-tion, output voltage ripple, switch node waveform and other parameters. Refer to Figure 2 for proper output voltage ripple measurement.7. To select other output voltages, use the on board user selectable output voltage jumpers. Shutting down LTC3624HMSE by placing RUN pin jumper (JP1) to the OFF position or turn off the input power supply. Refer to the following table (Table 2) for the output voltage selection and repeat step 2 to 6.Table 2. Output Voltage Jumper SelectionJP3JP4JP5JP6JP7JP8*1.2V 1.8V2.5V3.3V5V User Select*If JP8 is selected, R6 needs to be calculated and inserted to obtain the desired output voltage.NOTE 1: To measure the input/output voltage ripple prop-erly, do not use the long ground lead on the oscilloscope probe. See Figure 2 for the proper scope probe technique. Short, stiff leads need to be soldered to the (+) and (–) terminals of an output capacitor. The probe’s ground ring needs to touch the (–) lead and the probe tip needs to touch the (+) lead.NOTE 2: The DC2359A can also be used to evaluate the LTC3624HMSE-2 (2.25MHz) by simply replacing U1 with the LTC3624HMSE-2 and changing inductor L1 to 1.5µH (Coilcraft XAL4020-152ME).2dc2359afb3dc2359afbFigure 2. Scope Probe Placement for Measuring Output Voltage RippleFigure 1. Proper Measurement Equipment SetupQuick start proceDure4dc2359afbFigure 5. Burst Mode – Efficiency vs Load Current at 5V INFigure 6. Forced Continuous Mode – Efficiency vs Load Current at 5V INFigure 3. Burst Mode – Efficiency vs Load Current at 12V INFigure 4. Forced Continuous Mode – Efficiency vs Load Current at 12V INQuick start proceDureLOAD CURRENT (A)70E F F I C I E N C Y (%)75808590DC2359a F036560555095100LOAD CURRENT (A)E F F I C I E N C Y (%)10095857565559080706050DC2359a F04LOAD CURRENT (A)E F F I C I E N C Y (%)10095857565559080706050DC2359a F06LOAD CURRENT (A)70E F F I C I E N C Y (%)75808590DC2359a F0565605550951005dc2359afbQuick start proceDureFigure 7. Measured Output Voltage Ripplet(1µs/DIV)DC2359a F07V OUT 20mV/DIVVSW 10V/DIVf SW = 1MHz V IN = 12V V OUT = 5V I LOAD = 2A L = 3.3µHC OUT = 1x 47µF/6.3V/X5R/120620MHz BW LIMITV P-P = 8.8mV6dc2359afbFigure 8. Load T ransient ResponseQuick start proceDuret(50µs/DIV)V OUT 200mV/DIVI OUT 1A/DIVf SW = 1MHz V IN = 12V V OUT = 5VI LOAD = 1A TO 2A L = 3.3µHC OUT = 1x 47µF/6.3V/X5R/1206CFF = 15pF20MHz BW LIMITV P-P = 219mV1A TO 2ADC2359a F087dc2359afbQuick start proceDureFigure 9. Thermal PerformanceV IN = 12V V OUT = 5V I LOAD = 2A L = 3.3µH f SW = 1MHzNO FORCED AIRFLOW T A= 25°CDC2359a F09parts ListITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER Required Circuit Components11CFF CAP, 0402 15pF 1% 50V NPO AVX 04025U150FAT2A21CIN CAP, 47μF 20% 20V 33mΩPANASONIC OSCON 20SVPA47M32C2, C3CAP, 1206 22μF 10% 25V X5R MURATA GRM31CR61E226KE15L41C4CAP, 1206 47μF 20% 6.3V X5R TAIYO YUDEN JMK316BJ476ML-T51C8CAP, 0603 2.2μF 10% 10V X5R AVX 0603ZD225KAT2A61L1IND, 3.3μH XAL4030-332ME72R1, RSET RES, 0402 619kΩ 1% 1/16W VISHAY CRCW0402619KFKED81R2RES, 0402 309kΩ 1% 1/16W VISHAY CRCW0402309KFKED91R3RES, 0402 196kΩ 1% 1/16W VISHAY CRCW0402196KFKEA101R4RES, 0402 137kΩ 1% 1/16W VISHAY CRCW0402137KFKED111R5RES, 0402 84.5kΩ 1% 1/16W VISHAY CRCW040284K5FKED122R7, R12RES, 0402 0Ω JUMPER VISHAY CRCW04020000Z0ED131R11RES, 0402 1MΩ 5% 1/16W VISHAY CRCW04021M00JNEDLINEAR TECH LTC3624HMSE#PBF 141U1IC, MONOLITHIC SYNCHRONOUS BUCKREGULATORAdditional Demo Board Circuit Components10C5CAP, 1206 22μF 20% 6.3V X5R OPTION TAIYO YUDEN EMK316BJ226ML-T OPTION 20C6CAP, 1210 OPTION OPTION30C7CAP, 0402 OPTION OPTION40R6, R8, R9, R10RES, 0402 OPTION OPTIONHardwareTURRET MILL-MAX 2501-2-00-80-00-00-07-0 110E1, E2, E3, E4, E5, E6, E7, E8,E9, E1021JP1HEADER, 3-PIN, 2mm SAMTEC TMM-103-02-L-S31JP2HEADER, 4-PIN, 2mm SAMTEC TMM-104-02-L-S46JP3, JP4, JP5, JP6, JP7, JP8HEADER, 2-PIN, 2mm SAMTEC TMM 102-02-L-S54MH1, MH2, MH3, MH4STANDOFF, SNAP ON KEYSTONE 883363XJP1, XJP2, XJP7SHUNT, 2mm SAMTEC 2SN-BK-G8dc2359afb9dc2359afbInformation furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.schematic Diagram10dc2359afbLinear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 ● FAX : (408) 434-0507 ● www.linear .com© LINEAR TECHNOLOGY CORPORA TION 2015LT 1015 REV B • PRINTED IN USADEMONSTRATION BOARD IMPORTANT NOTICELinear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions:This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations.If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or agency certified (FCC, UL, CE, etc.).No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive .Please read the DEMO BOARD manual prior to handling the product . Persons handling this product must have electronics training and observe good laboratory practice standards. Common sense is encouraged .This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC application engineer.Mailing Address:Linear Technology 1630 McCarthy pitas, CA 95035Copyright © 2004, Linear Technology Corporation。
SRAM 设计介绍2007
Static Read Access Memory (SRAM) DesignAbhinandan Majumdar MS. Computer Engineering am2993@Srinivas Satish MS. Computer Engineering ssn2111@December 10, 2007Final ProjectEE 4321VLSI Circuits Prof. Azeez BhavnagarwalaI DEX1.I TRODUCTIO (1)1.1 Design (1)1.2 SRAM Operation (2)1.3 Applications and Uses (3)2.DESIG (5)2.1 Block Diagram (5)2.2 Decoder (6)2.2.1 2 Input And Gate Design (7)2.2.2 3 Input And Gate Design (11)2.2.3 3x8 Decoder (13)2.2.4 6x64 Decoder (14)2.2.5 Decoder Resizing (15)2.3 SRAM Cell and Array Design (17)2.3.1 Precharge Circuitry (17)2.3.2 SRAM Cell (18)2.3.3 Read Sensing Circuit (19)2.3.4 Write Driver (19)2.3.5 SRAM Array (20)2.3.6 SRAM Cell with Decoder (20)2.3.7 Read Stability (21)2.4 DC Simulation (22)2.4.1 Static Noise Margin (SNM) (21)2.4.2 Cell Read Current (23)2.4.3 Effect of Threshold Voltage (V t) (24)YOUT (27)3.1 Decoder (27)3.1.1 AND2 Gate (27)3.1.2 AND3 Gate (28)3.1.3 3x8 Decoder (29)3.1.4 6x64 Decoder (29)3.2 SRAM (30)3.2.1 Precharge (30)3.2.2 Read Sensing Circuit (31)3.2.3 SRAM 64x64 Array (32)4.RESULTS (35)4.1 Simulation Results (35)4.1.1 Simulation of One SRAM Cell (35)4.1.2 Simulation of 64x64 SRAM Array (36)4.2 DRC & LVS Results (37)5.CO CLUSIO (38)6.REFERE CES (39)1.I TRODUCTIOStatic random access memory (SRAM) is a type of semiconductor memory. The word "static" indicates that the memory retains its contents as long as power remains applied, unlike dynamic RAM (DRAM) that needs to be periodically refreshed.DesignFig 1.1 A six-transistor CMOS SRAM cell.Random access means that locations in the memory can be written to or read from in any order, regardless of the memory location that was last accessed.Each bit in an SRAM is stored on four transistors that form two cross-coupled inverters. This storage cell has two stable states which are used to denote 0 and 1. Two additional access transistors serve to control the access to a storage cell during read and write operations. It thus typically takes six MOSFETs to store one memory bit.Access to the cell is enabled by the word line (WL in figure) which controls the two access transistors M5 and M6 which, in turn, control whether the cell should be connected to the bit lines: BL and BL’. They are used to transfer data for both read and write operations. While it's not strictly necessary to have two bit lines, both the signal and its inverse are typically provided since it improves noise margins.During read accesses, the bit lines are actively driven high and low by the inverters in the SRAM cell. This improves SRAM speed compared to DRAMs—in a DRAM, the bit line is connected to storage capacitors and charge sharing causes the bitline to swing upwardsor downwards. The symmetric structure of SRAMs also allows for differential signaling, which makes small voltage swings more easily detectable. Another difference with DRAM that contributes to making SRAM faster is that commercial chips accept all address bits at a time. By comparison, commodity DRAMs have the address multiplexed in two halves, i.e. higher bits followed by lower bits, over the same package pins in order to keep their size and cost down.The size of an SRAM with m address lines and n data lines is 2m words, or 2m × n bits.1.2. SRAM operationA SRAM cell has three different states it can be in: standby where the circuit is idle, reading when the data has been requested and writing when updating the contents. The three different states work as follows:a) StandbyIf the word line is not asserted, the access transistors M5 and M6 disconnect the cell from the bit lines. The two cross coupled inverters formed by M1 – M4 will continue to reinforce each other as long as they are disconnected from the outside world.b) ReadingAssume that the content of the memory is a 1, stored at Q. The read cycle is started by precharging both the bit lines to a logical 1, then asserting the word line WL, enabling both the access transistors. The second step occurs when the values stored in Q and Q are transferred to the bit lines by leaving BL at its precharged value and discharging BL through M1 and M5 to a logical 0. On the BL side, the transistors M4 and M6 pull the bit line toward VDD, a logical 1. If the content of the memory was a 0, the opposite would happen and BL would be pulled toward 1 and BL toward 0.c) WritingThe start of a write cycle begins by applying the value to be written to the bit lines. If we wish to write a 0, we would apply a 0 to the bit lines, i.e. setting BL to 1 and BL to 0. This is similar to applying a reset pulse to a SR-latch, which causes the flip flop to change state. A 1 is written by inverting the values of the bit lines. WL is then asserted and the value that is to be stored is latched in. Note that the reason this works is that the bit line input-drivers are designed to be much stronger than the relatively weak transistors in the cell itself, so that they can easily override the previous state of the cross-coupledinverters. Careful sizing of the transistors in a SRAM cell is needed to ensure proper operation.1.3. Applications and Usesa) CharacteristicsSRAM is a little more expensive, but faster and significantly less power hungry (especially idle) than DRAM. It is therefore used where either speed or low power, or both, are of prime interest. SRAM is also easier to control (interface to) and generally more truly random access than modern types of DRAM. Due to a more complex internal structure, SRAM is less dense than DRAM and is therefore not used for high-capacity, low-cost applications such as the main memory in personal computers.b) Clock speed and powerThe power consumption of SRAM varies widely depending on how frequently it is accessed; it can be as power-hungry as dynamic RAM, when used at high frequencies, and some ICs can consume many watts at full speed. On the other hand, static RAM used at a somewhat slower pace, such as in applications with moderately clocked microprocessors, draw very little power and can have a nearly negligible power consumption when sitting idle — in the region of a few microwatts.Static RAM exists primarily as:(i) General purpose products•with asynchronous interface, such as the 28 pin 32Kx8 chips (usually named XXC256), and similar products up to 16 Mb per chip•with synchronous interface, usually used for caches and other applications requiring burst transfers, up to 18 Mb (256Kx72) per chip(ii) Integrated on chip•as RAM or cache memory in microcontrollers (usually from around 32 bytes up to 128 kilobytes)•as the primary caches in powerful microprocessors, such as the x86 family, and many others (from 8 KB, up to several megabytes)•on application specific ICs, or ASICs (usually in the order of kilobytes)•in FPGAs and CPLDs (usually in the order of a few kilobytes or less)c) Uses(i) Embedded UseMany categories of industrial and scientific subsystems, automotive electronics, and similar, contains static RAM. Some amounts (kilobytes or less) is also embedded in practically all modern appliances, toys, etc that implements an electronic user interface. Several megabytes may be used in complex products such as digital cameras, cell phones, synthesizers, etc. SRAM in its dual-ported form is sometimes used for realtime digital signal processing circuits.(ii)In computersSRAM is also used in personal computers, workstations, routers and peripheral equipment: internal CPU caches and external burst mode SRAM caches, hard disk buffers, router buffers, etc. LCD screens and printers also normally employ static RAM to hold the image displayed (or to be printed). Small SRAM buffers are also found in CDROM and CDRW drives; usually 256 KB or more are used to buffer track data, which is transferred in blocks instead of as single values. The same applies to cable modems and similar equipment connected to computers. The so called "CMOS RAM" on PC motherboards was originally a battery-powered SRAM chip, but is today more often implemented using EEPROM or Flash.2.DESIG2.1 Block DiagramThere are two major blocks to be designed:•Address decoder: The address decoder takes in the 6 address lines a4:0 coming from the latch, and decodes them to generate 64 wordlines WL0-63 for the SRAM array.•SRAM array: Consists of an array of 64 x 64 bit SRAM cells. In addition to these blocks, the array also contains circuitry that allows data to be written intothe array, and for precharging the bitlines to V DD before the read operation; these circuits are not shown in figure.2.2 DECODERTo construct a 64x64 bit SRAM, we need 6x64 Address Decoder to select one of the word lines of 64 rows, each containing 64 1b SRAM cells. Hence we need to make the decoder logic fastest so as it doesn’t become the bottleneck of our whole design. Hence considering speed and layout issues, we are taking up Domino Logic for all the intermediate nodes being used.For designing a 6x64 Decoder, we can either have three 2x4 decoders in 1st stage and perform ANDING of the corresponding outputs to have a 6x64 decoder logic, or we can have two 3x8. But for the former case, we need 64 three input AND gate and 12 two input AND gate and which is designed through domino logic, while the later design has 64 two input AND gates and 16 three input AND gate, hence considering the space limitations as three input AND gate takes much more area and offer higher gate capacitance, we choose the later design for 6x64 decoder.Fig 2.2: 6x64 Decoder using 2x4 decodersFig 2.2: 6x64 Decoder design using two 3x8 decoders2.2.1 2 Input A D Gate Design – We designed 2 Input AND gate using DominoLogic. Here is the schematic of the designFig 2.3: Schematic Design of AND2 Gatei)Frequency Calculation. We kept input A & B at 1.2V, and saw how fast canit be operated at higher frequency, and we found that it atleast needs 0.4ns or2.5Ghz.Fig 2.4: Frequency Variation for AND2 Gateii)PFET size calculation. We tried to simulate for varying Pfet size and found that we need to keep pfet minimal as well as optimum to charge the bitline faster at a given frequency of 2.5Ghz. We decided upon pfet size to be 715nm so as precharges at a faster rate.Fig 2.5: Pfet width variation for AND2 Gateiii)Sizing of nfets – We try to scale the nfet array so as the propagation delay could be minimized. Increasing the scaling decreases the propagation delay, hence decided upon a = 1.3Fig 2.6: NFET Size variation for NFETiv)Keeper PFET sizing – Keeper PFET is the one whose gate is driven by the output of the inverter, and prevents the voltage drop across the intermediate capacitance to drop below the V M of the inverter during evaluation stage. First graph is that of clock. Second graph shows that if we don’t have any pfet, the output voltage rises by mV. If we connect it to a pfet and increase its size by b*(sum of the width of nfet array), we see the outout to be stable at 0 and randomness decreases by increase in b. Hence we find b = 0.15.Fig 2.7: Keeper PFET sizing for AND2 gatev)Inverter Sizing. Though we should make the nfet stronger than pfet so as the voltage drop across intermediate capacitance is greater than VM of inveter.But making nfet stronger adds delay, so by adding a Keeper Pfet so as to keep the intermediate capacitance charged, we can increase our pfet to have same rise and fall time. Hence we find the beta ratio to be 2.45.Fig 2.8: Inverter size variation for AND2 Gate2.2.2 3 I PUT A D GATE. The ratios which we got for 2 INPUT AND Gate arekept same for 3 INPUT too, but the confusion should we use 2 cascadedAND2 gate for a 3 Input AND or single 3 INPUT AND. Hence we computedthe propagation delay, and found following things. AND2_1 and AND2_2 iscascade 2 AND with changing line in 1st and 2nd AND respectively.Gate High to Low Low to High PropagationDelayAND2 0 1.15ns 0.575nsAND2_1 (cascaded) 0 1.18ns 0.59nsAND2_2 (cascaded) 0 1.19ns 0.595nsAND3 0 1.46ns 0.73nsHence cascaded AND2 would make our design faster but could make it asymmetrical, hence we chose AND3.AND2 (Only one 2 Input AND) AND2_1 (Cascaded 2 Input AND)AND2_2 (Cascaded 2 Input AND) AND3 (3 Input AND)2.2.33x8 DECODER – Here is the schematic for the Decoder.Fig 2.9: 3x8 Decoder SchematicAnd, here is the simulation graph,Fig 2.10: Simulation of 3x8 Decoder2.2.46x64 Decoder – We used two 3x8 decoders and used 2 AND for having the64x6 decoder logic. Here is the schematicFig 2.11: Schematic of 6x64 DecoderWe kept all inputs A1-A5 at 0 and sweeped A0 from 0 to 1.2V, and saw that Y0 dropping out and Y1 rising to 1.2V.Fig 2.12: Propagation Delay at the Critical Path for 6x64 Decoder2.2.5Decoder Resizing.The delay what we got after designing was 5.177ns – 5.025ns = 0.152ns when running at 1Ghz and driving a capacitance of 39.931fF. We computed the end capacitance having the value of gate capacitance as 1fF/um and width capacitance as0.2fF/um. In this case the AND3 nfets have W1 = 1u and rest being size by the ratio1.3, inveter nfet has W2 = 1um, AND2 nfets have W3 = 1u and sized accordingly with ratio 1.3 and inverter has W4 = 1um.To have minimal delay so as to have equal rise time and fall time, we optimized the sizes as follows,For AND3,NFET Array: 2u, 2.6u, 3.38u, 4.395uPFET: 3uKeeper PFET: 800nmInverter: NFET – 3uPFET – 2.9uFor AND2,NFET Array: 5.8u, 7.54u, 9.8uPFET: 3.2uKeeper PFET: 2.2uInverter: NFET – 3uPFET – 2.9uHere’s the critical pathFig 2.13: Schematic of Critical Path in 6x64 DecoderWe obtained a fall and rise time for the four stages as follows 33.94ps, 34,94ps, 33.23ps, 34.99ps. By this, our propagation delay got reduced from 152ps to 89ps (1.594ns – 1.505ns = 89ps). Hence we stick to this sizes.Fig 2.14: Propagation of Critical Path in 6x64 Decoder after Optimization2.3 SRAM cell and array design2.3.1 Precharge circuitryThe schematic of the precharge circuit is shown below. The pfet are of 1um width. This large width of the pfet is required to be able to charge the bitline quickly during the pre-charge phase. The huge width ensures that the bit-line BIT and BIT_B are charged to VDD in half the clock cycle.Fig 2.15: Schematic of Precharge Circuit2.3.2SRAM Cell.Schematic of the cell is shown below. The sizes of the access transistors, inverternfet, pfet widths are as per the ones given in the layout.Fig 2.16: Schematic of SRAM Cell2.3.3 Read Sense CircuitSchematic of the read large sense circuit is shown below. The basic NAND gate is sized with nfet=280nm and pfet width of 560nm a ratio of 4.8:1. This is the required ratio in the 90nm process with channel length=80nm for achieving ideal rise and fall times.Fig 2.17: Schematic of Read Sense Circuit2.3.4 Write driverThe write driver is enabled by a Write_enable line. The schematic is shown below.Fig 2.18: Schematic of Write Circuit2.3.5 The complete SRAM ArrayFollowing is the schematic of 64x64 bit SRAM cellFig 2.19: Schematic of SRAM Array2.3.6 SRAM Array with DecoderHere is the schematic of the complete SRAM with DECODER,Fig 2.20: Schematic of SRAM Array with 6X64 Decoder2.3.7 Read StabilityThis is an important characteristic of the SRAM Cell. During a read-operation one of the bitlines either BIT or BIT_B is discharged though the access transistor and an nfet of the inverter. During this discharge process, a large amount of current flows through node A ( shown below). Read stability is a measure of the potential at node A, this potential should not exceed the switching threshold of the other inverter. If it does then the state of the SRAM has changed. An analogous analysis was done in identifying tradeoffs in Read Current and Static Noise Margin.Following is the READ STABILITY Graph.Fig 2.21: Simulation of Read Stability2.4DC SIMULATIO2.4.1STATIC OISE MARGIHere is the schematic of the SRAM for Static Noise Margin Measurement. We sweep the left voltage and measure the right voltage and do vice versa and find the min edge of the max box that can fit into the butterfly curve.Fig 2.22: Schematic of SRAM Array with 6X64 Decoder(i)HOLD operation. We keep the gate of the pass transistors at GND and getthe following curve. The SNM for this is 0.4604.Fig 2.23: Hold operation(ii)READ - The SNM we got was 0.1616V. The graph is as follows.Fig 2.24: Static Noise Margin estimation of SRAM Cell2.4.2Cell Read CurrentCell read current equals the current that flows through the pass gate nfet connected to the BL draining charge on the BL into the cell ground terminal. The larger the current the faster BL gets discharged and develops a signal for the sensing circuit to detect. Having a very large Read Current flowing through the discharge path from bit line to the ground could result in the exceeding the read stability threshold. This can be avoided by optimally choosing the sizing of the access nfet and the discharge nfet of the respective inverted during a read operation cycle.Fig 2.25: Cell Read Current Simulation2.4.3 Effect of Threshold Voltage (V t )We change Vt by 25mV, 50mV, 100mV and 200mV by adding a –ve voltage to the gate and got following values. Vt Pass nfet Pull down nfet Pfet 25mV 0.1638 0.1626 0.1518 50mV 0.1725 0.1655 0.1483 100mV 0.1900 0.1732 0.1422 200mV 0.2246 0.1778 0.1252Fig 2.26 - Effect of SNM by increasing V t at pass nfetFig 2.27- Effect of SNM on increasing V t at pull down nfetFig 2.28- Effect of increasing V t at one end of pfet and measuring other side.YOUT3.1 DECODER3.1.1 A D2 Gate.Here is the layout of AND2 gate which passes both DRC and LVSFig 3.1- DRC and LVS results for AND2 Gate along with layout.3.1.2 A D3 Gate.Here is the layout of AND3 gate which passes both DRC and LVSFig 3.2- DRC and LVS results for AND3 Gate along with layout.3.1.3 3x8 DECODERHere is the layout of 3x8 Decoder which passes both DRC and LVSFig 3.3- DRC and LVS results for 3x8 Decoder along with layout.3.1.4 6x64 DECODERHere is the layout of 3x8 Decoder which passes both DRC and LVSFig 3.4- DRC and LVS results for 6x64 Decoder along with layout.3.2 SRAM3.2.1 Precharge circuit layoutThe width of the entire precharge circuit layout should be equal to the width between the two bit lines BIT and BIT_B. Below is an image of our layout of this circuit with its DRC and LVS results.Fig 3.5- DRC and LVS results for Precharge Circuit along with layout3.2.2Read Sense Amp CircuitIn the layout of the read circuit, care has to be taken to ensure that it fits exactly in between the two bitlines. The symmetric lateral reflection layout of the SRAM cells adds some degree of complexity, this being due to the fact that now we would have a series of BIT, BIT_B, BIT_B, BIT followed by the same pattern. For a read it is sufficient to sense one of the bit lines, either BIT or BIT_B. Two read sense amps would have to be fit between the two BIT lines. The LVS results and the layout of the Read Sense amp can be found in the image below.Fig 3.6 DRC and LVS results for Read Sense Amplifier along with layout3.2.3SRAM 64 X 64 arrayUsing the SRAM Cell provided from the standard library, we created a symmetrical and laterally inverted 2 X 2 network of SRAM cells. This was done to achieve a good sharing of the power rails and to reduce the bit line noise reduction. Though not done in our layout cross coupling bit lines would reduce the bit line noise to a very good extent.Using an instance of 2 X 2 SRAM cells the entire array of 64 X 32 top half and 64 X 32 bottom halves as shown in the schematic of phase two was laid out. Following this is the insertion of the Read Sense Amplifiers in between the top half and bottom halves of theentire SRAM array layout. To the left of the image below is the layout of the 2 X 2 network of SRAM cells and to the right the 64 X 64 layout of SRAM cells.Fig 3.7- Array of SRAM Cells, 2 X 2 and 64 X 64 arrays.Image below shows the DRC test results:Fig 3.8: DRC results for the 64 X 64 SRAM arrayHere’s the complete layout of SRAM cell with decoder.Fig 3.9: 64 X 64 SRAM array along with 6x64 Decoder4.RESULTS4.1 Simulation Results4.1.1 Simulation for One Cell SRAMWe simulated a single cell SRAM with following schematicFig 4.1 – One Cell SRAM SchematicBelow is a graph showing the Write – 1 Read – 1 Write – 0 simulation on a single SRAM cell.Fig 4.2 – One Cell SRAM Simulation4.1.2Simulation for 64x64 bit SRAM ArrayHere is the schematic used for 64x64 bit SRAM ArrayFig 4.3 –64x64 SRAM Arrayand here are the simulation results, when din<0> = 1, din<1> = 0, and din<2> = 1 with address line as 000000, and clock running at 1 Ghz.Fig 4.4 – Simulation for complete 64x64 SRAM cell Array4.2 DRC and LVS ResultsThe DRC and LVS were checked for each component individually. The following is a summary of the results:Functional Component DRC LVS6 X 64 Decoder Passed PassedPrecharge Passed PassedRead Sense Amp Passed Passed64 X 64 SRAM array Errors ErrorsPlease find all reports to these tests at the following location on/home/user5/fall07/ssn2111/LVS_FinalReports/home/user5/fall07/ssn2111/DRC_FinalReports5.CO CLUSIOAs a SRAM project for EE 4321 VLSI course, we designed 64x64 bit SRAM cell both at the schematic and layout level. We attempted to design the 6x64 decoder using 3x8 decoder using two and three input AND gates using Domino Logic. We could successfully simulate and verify the functionality of the components which we targeted to design. Though we couldn’t successfully pass the DRC and LVS of entire unit because of the primary reason that the unit cell being provided to us failed at DRC and LVS level, but we could successfully pass the DRC and LVS of other individual components including Pre-Charge, Read Sensing Circuit and 6x64 Decoder.The experience on working for such a design oriented project gave us a thorough insight what all critical issues we need to consider while designing a simple unit. This also made us familiar with the different approaches to implement the same design and decide what the tradeoffs between different alternatives are. Also, it made us aware of the critical physical implementation issues which we not only have to consider during actual layout but also during schematic level design. It also gave a hand-on experience upon CAD tools like Cadence, Virtuoso, Spice and Spectre widely used both at industrial and academic level for circuit designing. Overall, it was a nice experience both at learning, practicing and designing a most critical part of processor unit widely used in any Computer Architecture.6.REFERE CES1./wiki/Static_random_access_memory2.Cmos Logic – Uyemura3.CMOS VLSI Design – Weste & Harris4.Static-Noise Margin Analysis of CMOS SRAM Cells EVERT SEEVINCK,SENIOR MEMBER, IEEE, FRANS J. LIST, AND JAN LOHSTROH, MEMBER, IEEE.5.Analyzing Static Noise Margin for Subthreshold SRAM in 65nm CMOS BentonH. Calhoun and Anantha Chandrakasan6.Transistor Sizing for Reliable Domino Logic Design in Dual Threshold VoltageTechnologies by Seong-Ook Jung, Ki-Wook Kim, Sung-Mo (Steve) Kang。
STM32固件库使用手册的中文翻译版
因为该固件库是通用的，并且包括了所有外设的功能，所以应用程序代码的大小和执行速度可能不是最优 的。对大多数应用程序来说，用户可以直接使用之，对于那些在代码大小和执行速度方面有严格要求的应 用程序，该固件库驱动程序可以作为如何设置外设的一份参考资料，根据实际需求对其进行调整。
1.3.1 变量 ................................................................................................................................................ 28 1.3.2 布尔型 ............................................................................................................................................ 28 1.3.3 标志位状态类型 ........................................................................................................................... 29 1.3.4 功能状态类型 .............................................................................................................
MOLDFLOW认证练习题1
MOLDFLOW认证练习题1Autodesk MoldflowIntroductionSection 1Section 1 has questions that relate to the use of Synergy, using various Autodesk Moldflow Insight flow analyses and results interpretation.Ensure you have the answer sheet which is an excel file called BronzeA_Answers.xlsx.Place your answers on the Sect1_Answers sheet.For each question, choose the BEST answer.Each question is worth 1 point for a total of 70 points.No reference materials may be used during this portion of the exam.Plan on section one taking 40-50 minutes to complete. You may have as much time as you like, but don’t taketoo much time, you will need it to complete section 2.Append your name to the beginning of the answer sheet file name, such as John_Doe_BronzeA_Answers.xlsx. Section 2 Section 2 is a hands-on.You are given 5 study files to compare the results.You are given a study file and directions for creating a feed system.You are given several MFR files to interpret molding window and Fill + Pack analysis results.This section is worth 205 points in total.For this section you can use the on-line help as a reference.GradingThere are a total of 275 possible points in this exam. To passthis test, you must score an 80% or 220points minimum.Return the necessary files to Autodesk for grading. Instructions for returning the files are on page 34.The entire test should take between 5 to 6 hours to complete. The test is limited to 6 hours.Section 11.In general, the largest component of the cycle time is:A.Fill time.B.Pack time.C.Cooling time.D.Clamp open time.2.Due to fountain flow, the highest velocity in the cross section is located at the:A.Center of the cross section.B.Plastic/metal interface also called the mold surface.C.Half way between the center and plastic metal interface.3.During filling, the maximum shear rate in the cross section is located at the:A.Center of the cross section.B.Plastic/metal interface.C.Molten layer/frozen layer interface.4.Shrinkage for a fiber filled material is usually greatest:A.Perpendicular to the flow direction.B.Parallel to the flow direction.C.The shrinkage is uniform in all directions.5.The flow balancing principle states:A.There is a balance between the cavity volume and runner volume.B.Each flow path in the model fills at the same time andpressure.C.The runners should be the same diameter to ensure the parts will fill equally.6.The primary criteria to determine if maximum shear stress in a part is acceptable is the:A.Elastic modulus of the material.B.Shear modulus of the material.C.Shear stress limit for the material.7. A meld line is formed when:A.Two flow fronts hit head on.B.Two flow fronts meet then flow in the same direction.C.When two flow fronts meet at the end of fill from two different gates.8.The highest shear stress in the plastic cross section is:A.Within the frozen layer.B.At the center of the cross section.C.At the frozen/molten interface.D.Could be anywhere.9.When the cavity and core side mold temperatures are different, the plastic part will:A.Shrink more on the cold side causing it to bow towards the cold side.B.Shrink more on the hot side causing it to bow towards the hot side.C.Shrink flat as mold temperature makes no difference in the shrinkage.D.None of the above.10.The magnitude of molecular orientation can be defined by:A.Shear stress.B.Shear rate.C.Shear modulus.11.When underflow “moves” a weld line:A.The weld line gets weaker.B.The weld line is eliminated.C.The weld line can move to a structurally weak area of the part.D.The weld line strength is not influenced by being moved.12.Flow leaders are:A.Local reductions in thickness from the part's nominal wall.B.Local increases in thickness from the part's nominal wall.C.Ribs designed to promote the flow.13.Flow leaders are designed to:A.Stiffen the part.B.Reduce volume of the part.C.Balance the filling pattern of the part.14.The best plot to use to look for a constant pressure gradient for filling the part is:A.Pressure at the injection location.B.Pressure, plotted as a shaded image.C.Pressure at V/P switchover, plotted as a shaded image.15.If the clamp force exceeds the limit of the molding machine by 50% what could be done to reduce theclamp force below the limit of the molding machine:A.Increase the melt temperature.B.Add gates to the part.C.Inject faster.D.None of the above.16.Race tracking can best be interpreted by:A. A high pressure gradient.B. A narrow band of high bulk temperature.C. A band of high shear stress.D. A wide spacing of the fill time contours.17.When interpreting molding window results, a possible interpretation of the results could be:A.An additional gate should be added to reduce the pressure.B.The packing time should be increased to 10 seconds.C.The pack pressure should be set to 50% of the fill pressure.D.None of the above.18.Which the following statements about the Zone(molding window) 2D Slice Plot is true:A.The cut axis for the Zone plot is moved with the Move cutting plane tool.B.The Zone plot can be examined to find the optimum processing conditions.C.The Zone plot indicates the recommended processing conditions.19.When interpreting the Temperature at flow front minimum (molding window):XY plot, with injection time as the X-axis, an optimum injection time can be found by:A.The time that has a temperature 10oC above the melt temperature.B.The time that has a temperature 50oC above the transition temperature.C.The time that has a temperature equal to the melt temperature.D.None of the above.20.An analysis sequence that should be done before the first fill analysis includes:A. A Material selection analysis.B. A Molding window analysis.C.Neither A nor B.D.Both A & B.21.A non-manifold edge is:A.An edge of an element that does not touch another element edge.B.An element edge that touches exactly two element edges.C.An element edge that touches three or more element edges.D.None of the above.22.The recommended maximum aspect ratio of both midplane and Dual Domain models is:A.4:1.B.6:1.C.10:1.D.25:1.23.For the weld line prediction algorithm, a coarse mesh has:A.No influence on the prediction of the weld line.B. A small influence on the prediction of the weld line.C. A major influence on the prediction of the weld line.24.Small radii in the corner of a rib of a midplane or Dual Domain model:A.Has no effect on the analysis run time.B.Should not be modeled as they add nothing to the analysis.C.Must be modeled to get an accurate pressure drop.25.The MOST important part geometry to model for an accurate pressure prediction is:A.Thickness.B.Flow Length.C.Volume.D.True size and shape.E.All are critical.26.The best way to eliminate a lot of high aspect ratio elements in a model and keep the element count low is to:A.Have no small radii in the CAD model that is translated into Synergy.B.Set a shorter Global edge length when meshing the part.C.Manually remove the high aspect ratio elements with the mesh tools.27.Autodesk Moldflow Design Link must be used to import what type of file:A.STL.B.IGES.C.Step.28.Changing the options of how an STL file is written in a CAD program:A.Has no effect on the ability to import and mesh the CAD file.B.Can have a significant influence on the mesh quality.29.Mesh diagnostic plots:A.Show problems with the mesh.B.Highlight ways to fix errors in the mesh.C.Always put corrected elements on a new layer.30.A Dual Domain mesh should always be oriented:A.So the bottom side of the element is visible.B.So the red side of the element is visible.C.So the top sides of the elements are visible.D.So the mesh is consistent. It does not matter if the top or bottom side is showing.31.A Dual Domain model must have the followingcharacteristics except:A.One connectivity region.B.No free edges.C.No manifold edges.D. A mesh match ratio above 85%.32.The thickness of a Dual Domain model:A.Must be set by the user.B.Is automatically determined during import or mesh creation.C.On the edge is 50% of the adjacent wall thickness.D.Is not definable by the user.33.Two mesh tools that are most commonly used to fix high aspect ratio problems are:A.Auto and Remesh area.B.Match nodes and Align nodes.C.Insert and Fill hole.D.Swap Edge and Merge.34.The material database can be searched using all except the following:A.The manufacture's name.B.The Moldflow viscosity index.C.Cost per pound.D.Filler content./doc/55c4a113534de518964bcf84b9d 528ea80c72f41.html paring materials can be done by:A.Plotting viscosity data from more than one material.B.Sorting a search results column.C.Searching by a critical property such as filler.D.All of the above.E.None of the above.36.From the list of material properties below, which property is NOT required to run a flow analysis?A.Melt temperature.B.Ejection temperature.C.Transition temperature.D.Moldflow viscosity Index.E.Thermal conductivity.37.The default viscosity model for most materials in the data base is:A.Cross-WLF.B.Second order.C.First Order.D.None of the above.38.Criteria for choosing the gate location on the part includes the following except:A.Balanced filling.B.Place gates near thin areas of the part.C.The machine injection pressure limit.D.Unidirectional fill.39.According to the unidirectional flow principle:A. A gate on one end of the part generally creates uniform orientation in one direction.B.The filling pattern should radiate out from the gate.C. A fan gate is needed to produce unidirectional filling.D.None of the above.40.According to gate placement guidelines:A.Adding a second gate is only done to reduce the pressure to fill.B.Gates should be placed in thinner areas of the part to get them to fill.C.Add a second gate to prevent over packing.D.None of the above.41.To fill out thinner ribs, the gate:A.Should be placed close to the thin region.B.Should be placed as far away as possible to the thin region.C.Placement does not matter.D.Placement only depends on the type of tool being designed.42.Adding gates to a part lowers the pressure to fill by:A.Decreasing the flow rate in an individual gate.B.Reducing the flow length within a part.C.Decreasing the fill time.D.None of the above.43.A molding window can help evaluate:A.The number of gates needed for the part.B.The pressure required to fill the part.C.The wall thickness for the part.D.All of the above.E.None of the above.44.Process settings for a molding window analysis include all but the following:A.Molding machine.B.Mold temperature.C.Injection time.D.Velocity/pressure switchover.45.For the Zone (molding window) 2D slice plot, the best cut axis for determining the optimumprocessing conditions is:A.Injection time.B.Melt temperature.C.Mold temperature.46.As the melt temperature increases, the optimum injection time:A.Stays the same.B.Increases.C.Decreases.D.Decreases for amorphous materials and increases for semi-crystalline materials.47.On a Dual Domain model, edge gate with a width to thickness ratio of 3:1 must be modeled with:A.Triangular elements.B.Beam elements.C.Beam or triangular elements.D.Tetrahedral elements.48.A valve gate is closely related to what gate type?A. A hot drop.B. A pin gate.C.An edge gate.D. A tunnel gate.49.The primary criteria for sizing the gate is:A.Shear stress limit.B.Shear heat.C.Shear rate limit.D.Pressure drop in the gate.50.To use the Runner System Wizard the parting plane must be the:A.XY plane.B.YZ plane.C.ZX plane.D.Any plane is OK.51.When creating runners manually, runners can be created by:A.Defining a curve first then assigning a property, finally meshing the curve.B.Creating nodes then beam elements directly with the properties defined.C.Both ways will work.D.Neither way will work.52.When balancing runners, the size of the runners:A.Must be constrained by indicating the smallest and largest acceptable size.B.The initial runner dimensions must be set to undefined.C.Should not be constrained to allow for the optimal runner sizing.53.For a runner balance analysis, the target pressure should be set so:A.The pressure will be at the machine maximum pressure.B.The smallest runner will have a diameter half of the largest runner.C.The runner volume will be reduced to 50% from the original runner volume.D.The smallest runner produced will have a cooling time about equal to the part.54.The best way to determine if the runner sizes produced by the runner balance analysis is acceptable is to:A.Check if the runner sizes are a standard size.B.Make sure the largest runner has a cooling time that is less than 200% of the part cooling time.C.Run a packing analysis and make sure the volumetric shrinkage in the parts is similar.D.Ensure the smallest runner is at least 1.5 mm larger than the part's nominal wall.E.Any of the above is acceptable depending on the runner balance objectives.55.Single data set results are defined as:A.Results with one value for the filling or packing phase.B. A result with one value for the entire part such as the maximum pressure.C. A result recorded at a single user defined time, such as0.25 seconds.56.Intermediate profiled results define:A.The packing profile in several stages.B.The injection profile and packing profile in several stages.C.Variables recorded through the thickness of the plastic cross section and through time.57.Single dataset results include for a Dual Domain analysis:A.Average velocity and Frozen layer fraction.B.Pressure at end of fill, Fill time, Temperature at flow front.C.Temperature, shear rate, velocity.D.None of the Above.58.Intermediate profiled results can be animated over:A.Time.B.Single dataset.C.Normalized thickness.D.All of the above.E.None of the above.59.Scaling a result with the option per frame refers to:A.Determining the plot scale by a user selected animation frame (time).B.Changing the scale for every new animation frame (timestep) displayed.60.What key can you click when viewing an analysis result to get more information on that plot definitionand interpretation?A.F1.B.F2.C.F4.D.F1261.The maximum clamp force developed during the injection molding cycle is calculated in the flow solver by:A.The maximum injection pressure during the cycle times the projected area based on the XY plane.B.The pressure and the projected area of each element based on the XZ plane then adding up the clampforce in each element.C.The pressure and the projected area of each element based on the XY plane then adding up the clampforce in each element.62.Packing pressure is defined as:A.The magnitude of pressure applied to the plastic while the mold is closed.B.The maximum hydraulic pressure used during the molding cycle.C.The pressure profile applied to the plastic after the V/P Switch-over.D.None of the above.63.The cooling time field on the Process Settings Wizard Flow page is:A.The entire time the polymer is cooling in the mold.B.Time after the packing phase and before the mold opens.C.The entire cycle time minus the clamp open time.64.The maximum packing pressure that should be used in a packing analysis is determined by:A.The pressure capacity of the machine.B. A pressure that produces a clamp force of about 80% the machine limit and is less than themachine’s p ressure capa city.C.100% of the fill pressure of the part.D.75% of the fill pressure of the part.65.The pack time for a part:A.Should be less than the time required for the gate to freeze.B.Should be just longer than the gate freeze time.C.Should be 5 times the injection time.D.Should be 25% of the total cycle time.66.The main reason to run a fiber flow analysis is to:A.Accurately predict the fill pressure of a fiber filled material.B.Determine how molecular orientation is influenced by the fiber distribution.C.Determine the mechanical properties of the material to be passed on to a warpage analysis foraccurate warpage predictions.D.None of the above.67.Studies used to create reports:A.Must be in the open project.B.Must be an open document.C.Can be anywhere in the network.68.Hesitation can be best interpreted by:A. A high shear stress gradient in a small area of the part.B. A narrow spacing of fill contour lines.C. A pressure spike.69.Air traps caused by a thin area surrounded by a thick area can best be removed by which ofthe following options:A.Increasing the injection time.B.Increase the melt temperature.C.Decreasing the injection time.D.Decrease the melt temperature.70.The best result for determining when a gate is frozen and the part can't be packed any more for a midplanepart, is:A.Bulk temperature.B.Pressure.C.Frozen layer fraction.D.Time to freeze.Autodesk Moldflow Insight Bronze Certification Section 2Read all instructions and information before starting this section.IntroductionYou are provided with 6 study files you will:1.Create a project.2.Import the 6 studies into the project./doc/55c4a113534de518964bcf84b9d 528ea80c72f41.html pare the meshes.4.Cleanup the mesh for one study.5.Create a runner system, with the provided study, based on the given gate location and tool layout.You will use Autodesk Moldflow Communicator to read in results and interpret the results on a given part.Starting on the following page, detailed instructions are listed for this section. Keep in mind the following:For the multiple choice questions, pick the BEST answer possible.Place your answers on the Sec2_Answers tab of the spreadsheet.Your project files and answer sheets will be returned to Autodesk per the instructions on page 34.Follow the steps below:ImportImport the studies Lid Mesh 1 to Lid Mesh 5 into a new project called Yourname_Bronze.Use metric units for the entire problem.The questions below compare the meshes between various studies.Meshing and mesh quality (17 points)Open in Synergy the studies mentioned in the questions below to pick the BEST answer for the following questions related meshing and mesh quality. You may copy the studies and re-mesh the part if necessary. Each question is worth one point.1.Looking at the studies Lid Mesh 1 and Lid Mesh 2, what study most closely represents the IGES file andhas the fewest/least severe mesh problems? (2)A. Lid Mesh 1B.Lid Mesh 22.Looking at the studies Lid Mesh 1 and Lid Mesh 2, what is the difference in mesh settings between thetwo studies? (2)A.Global edge lengthB.Merge toleranceC.Match meshD.Surface mesherE.Chord height3.What does the Chord height control do? (2)A.Change the average height of elements. As the chord height increases, the average height increases.B.Change the mesh density around curved features. As the chord height goes down, the number ofelements goes down.C.Divides curves into more divisions as the chord height goes down.D.None of the above.4.As the Global edge length gets smaller, (2)A.The number of elements increases.B.The number of elements decreases.C.The average element aspect ratio goes up for most models.D.The chord height gets smaller.5.Looking at the studies Lid Mesh 2 and Lid Mesh 3, what is the difference in mesh settings between thetwo studies? (2)A.Global edge lengthB.Merge toleranceC.Match meshD.Surface mesherE.Chord height6.Looking at the studies Lid Mesh 2 and Lid Mesh 3, what study has the BEST mesh settings for a DualDomain model? (2)A.Lid Mesh 2B.Lid Mesh 37.What are the problems with the mesh for Lid Mesh 3? (2)A.Manifold edges and Maximum aspect ratio.B.Connectivity regions and Reciprocal percentage.C.Connectivity regions and Average aspect ratio.D.Match percentage and Maximum aspect ratio.E.All of the above.F.None of the above./doc/55c4a113534de518964bcf84b9d 528ea80c72f41.html paring Lid Mesh 2 and Lid Mesh 4, which has the best overall mesh and easiest to clean up? (2)A.Lid Mesh 2B.Lid Mesh 49.What is not a problem with the mesh for Lid Mesh 5? (2)A.Connectivity regions.B.Free edges.C.Manifold edges.D.Non-manifold edges.E.Element not oriented.F.Element intersections.G.Maximum aspect ratio.Repair Problems (17 points)Save a copy of Lid Mesh 5 and name it YourInitials_Lid_Fixed.sdy Fix all the problems with the study. Each question is worth one point. Determine the mesh statistics when the mesh is completely fixed for the following and enter the number on the answer key:10.Connectivity regions. (1)11.Free edges. (1)12.Manifold edges. (1)13.Non-manifold edges. (1)14.Elements not oriented. (1)15.Element intersections. (1)16.Fully overlapping elements. (1)17.Duplicate beams(1)18.Maximum aspect ratio. (1)19.Average aspect ratio. (1)20.Match percentage. (1)21.Reciprocal percentage. (1)22.What were the most commonly used mesh repair tools you used.(1) A. Merge Nodes, Insert Nodes, Swap Edge.B.Auto repair, Fix Aspect ratio, Insert Nodes.C.Create Elements, Delete Elements, Merge Nodes.D.Align Nodes, Orient Elements, Fill Hole.E.None of the above.Figure 1 Side of lid23.What is the thickness of the nominal wall, in the study, YourInitials_Lid_Fixed.sdy as defined in Figure 1? (1)A.0.40 mmB.0.62 mmC. 1.50 mmD. 1.56 mm24.What is the average thickness of the rim, in the study, YourInitials_Lid_Fixed.sdy as defined in Figure 1? (1)A.0.40 mmB.0.62 mmC. 1.50 mmD. 1.56 mm25.What problem is shown in the thickness diagnostic for the study YourInitials_Lid_Fixed.sdy? (2)A.Rim has non-uniform thickness.B.Corners have non-uniform thickness.C.Bosses have non-uniform thickness.Gate Location (12 points)Determine the gate location for the part. Refer to Figure 2, and the file BronzeA_Gate_Locs.mfr, for the gate locations.The mold is a 2-plate tool. The cavity layout is shown in Figure 3on page 20.Consider the location of the parting line for this part.The sprue will be in the center of the tool.The runners are round.The gate used must be a tunnel gate.For the questions below, refer to the gate by number, shown in Figure 2 and use answers A to G. Each question is worth one point.A.This location is not eliminated; it is the best gate location.B.The filling pattern is not balanced.C.Packing is difficult from this location.D.The gat e location can’t be reached with the type of tool bei ng used.E. A tunnel gate can’t be used, or is not practical with this location.F.The flow length is too long.26.What is the BEST reason for eliminating gate location 1?(1)27.What is the BEST reason for eliminating gate location 2?(1)28.What is the BEST reason for eliminating gate location 3?(1)29.What is the BEST reason for eliminating gate location 4?(1)30.What is the BEST reason for eliminating gate location 5?(1)31.What is the BEST reason for eliminating gate location 6?(1)32.What is the BEST reason for eliminating gate location 7?(1)Figure 2, Proposed gate locations33. What is the BEST reason for eliminating gate location 8?(1)34.What is the main reason why your chosen location is best?(2)A.There is no underflow with a gate at this location.B.There is minimal hesitation from this location.C.The flow pattern is mostly unidirectional.D.The part is easy to de-gate.E.None of the above.35.What is a disadvantage(s) of the chosen gate location? (2)A.There is some underflow at this location.B.There is hesitation from this location.C.The pressure drop is high compared to most other locations.D.All of the above.E.None of the above.Model 4‐Cavity toolModel runners to represent a 4-cavity tool using the tool layout shown in Figure 3 on page 20 using the study Lid Model Runners.sdy.Import the file Lid Model Runners.sdy .Save the study as YourInitials_Runners.Use the gate location as indicated by the injection location on the imported study.Use the single part and occurrence numbers to represent the four cavities.The sprue orifice is 4.0 mm, included angle 2.5o, length 60 mm.Create the runners on the correct parting line location.Make the primary runner 5 mm and the secondary 3.5 mm.Use a tunnel gate, with the angle to mold face is 45o as shown to the right.Make the gate orifice 75% of the wall it is going into, and the other end the diameter of the runner feeding it. Modeling correctness (36points)The model will be graded for correctness on the following items.36.Occurrence numbers. (5)37.Runners. (5)38.Gates. (5)39.Sprue. (5)40.Parting line. (5)/doc/55c4a113534de518964bcf84b9d 528ea80c72f41.html yer organization. (5)Have the nodes, triangles, and runners/gates on different layers.Do not have any diagnostic layers.。
应用碳纳米管技术的高效电流模式全加器设计(IJMECS-V10-N4-6)
I.J. Modern Education and Computer Science, 2018, 4, 43-50
44
Design of an Efficient Current Mode Full-Adder Applying Carbon Nanotube Technology
II. TRANSISTORS BASED ON CARBON NANOTUBES The delay in circuits designed through CMOS is a common phenomenon due to the application of middle capacitors in cumulative circuits, leading to the low performance of the whole circuit. By considering this issue, due to the low streaming capacity of gates which drive the capacitor loads, the speed reduces in circuits designed through CMOS in a significant manner; thus, a disadvantage in these integrated circuits design [2]. By downscaling the electrical chipsets to nano size, the CMOSs face serious disadvantages like high power consumption and short channel effects. These disadvantages cause restrictions in application of CMOS technology for low power and high efficiency [10, 11]. Among the possible alternatives like QCA, SET, reversible circuits and CNTFET, the CNTFET is more reliable due to its similarities with MOSFET in terms of efficiency and internal characteristics [2, 3, 12]. In general, CNTFET has high efficiency and low power consumption compared to MOSFET and is appropriate for low voltage and high frequency applications [13]. The P_CNTFET and N_CNTFET types with identical dimensions have the capability of identical current flowing and are essential in sizing the transistors in complex circuits. Full-adders are among the most essential parts in digital circuits; hence, proposing a better design of this element compared to the previous circuits would contribute to the improvement of output parameters of these circuits in a significant manner [14]. The most essential construction parts in nano devices are Carbon nanotubes (CNT). CNT is a tubular graphite sheet with few nanometers diameter [2, 14]. Based on the number of coaxial tubes shaping the nanotubes, they are categorized as single-wall (SWCNT) or multi-wall (MWCNT) each has distinguished properties for different applications. A single-walled carbon nanotube (SWCNT) can be visualized as a single sheet of graphite which is rolled up and joined together along a wrapping vector Ch n1.a1 n2 .a2 , where a1 , a2 , are the lattice unit
APQPGateReview
5
GM Global APQP 理解
▶Global APQP 17 Task
Task 1: 产品定点策略会 Task 2: 技术评 Task 3:ＡＰＱＰ风险评估与定点 Task 4: 供应商项目评审(GR) Task 5:进度表／问题清单 Task 6:QSB Task 7:过程流程图 Task 8: DFMEA Task 9:设计评审(D/R) Task 10:量具、工装与设备评审 Task 11: Gage Development Process Task 12: PFMEA Task 13: Control Plan Task 14: GP-12 Task 15: PPAP Task 16: Run @ Rate Task 17:经验教训
Run@Rate (最终期限 -1)
阶段评审 关 键 交付物
APQP 供应商状态工作表GM1927-34(SGM) 启动会议检查清单 GM1927-14(SGM)
分供方状态更新 GM1927-25
验证计划 - A/D/V P&R GM1829
4
阶段评审交付物 (必须评估信息有效性 )
售后数据/下降计划 GM和供应商项目联系 清单GM1927-17(SGM) 分供方管理计划草案
好 的 开 始 是 成 功 的 一 半， 从 一 开 始 做 好 正 确 的 事 情 …
3
GM Global APQP 理解
全球APQP项目计划(整车项目)
= Repeat previous activity
GM GVDP 5.0 33/20 全球APQP任务
概 念 整车 工程释放 (CVER) 产 品 释放
▶ Production Control Plan
synopsys-dc中文教程(比较详细)
ASIC design flow
IP and Library Models
Verified RTL
Design Constraints
Logic Synthesis optimization&scan insertion Static Timing Analysis
no Time ok?
Floorplan placement, CT Insertion&Global routing
-output active_design+”.sdf” write_constraints –format sdf –cover_design\
-output constraints.sdf
ASIC design flow
Verification
利用SDF文件进行动态时序仿真:利用功能仿真时。用verilog 编写的test_bench 文件 形式验证:利用数学算法检查设计的逻辑的等效性，静态验证，需要的时间比动态仿真少，
方案。我们就以下几个方面对DC做以介绍：
script文件：由DC的命令构成，可使DC自动完成综合的整个过程。 DC支持的对象、变量、属性 DC支持的文件格式及类型 DC在HDL代码中的编译开关，控制综合过程
Translate_off/translate_on:指示DC终止或开始verilog 源代码转换的位置。 full_case:阻止case语句在不完全条件下生成latch。
பைடு நூலகம்
ASIC design flow
Compile and scan insert的scripts,采用bottom_up的编译方法
set_fix_multiple_port_net –buffer_constants –all compile –scan check_test create_test_pattern –sample 10 preview_scan insert_scan check_test 如果模块内的子模块具有dont_touch 属性需添加如下命令，因要插入扫描 remove_attribute find(-hierarchy design,”*”)dont_touch
新教材高中英语课时作业9Unit3UsingLanguage新人教版选择性必修第一册(含答案)
新教材高中英语新人教版选择性必修第一册：课时作业(九) Unit 3 Section ⅢUsing Language层级一课时跟踪检测维度1 单词拼写1．The exhibition gives local artists an opportunity to ________ (展示，显示) their work.2．To introduce Chinese traditional culture, our school will hold a ________ (主题) class meeting, which will be exhibited on the English website.3．We are going to meet at the school gate at 7 am and ________ (骑自行车) to the nearby mountain where we can go hiking and enjoy a picnic.4．Potentially one day I can attend an international competition of ________ (时尚) design.5．When I came across him, he was ________ (闲逛) aimlessly in the street.6．I walked up to the top of the hill with my friends, where we enjoyed a ________ (壮丽的) view of the lake.7．I have to make an effort to work up an ________ (强烈欲望) for reading.8．His research has contributed ________ (极大地) to our understanding of this disease.9．So I often ask my friend Tom to go with me and sometimes I ask my father to ________ (陪伴).维度2 单句语法填空1．It wasn't until the train pulled into the station ________ he found that his suitcase was gone.2．She was ________ incredible mom throughout my childhood, getting us through tough times and making them not tough at all.3．I'm familiar ________ this type of computer. That is to say, this type of computer is familiar ________ me.4．I like that way of life, nothing to worry, have fun ________friends regardless of time.5．I had several children and books were our main source of ________ (entertain).6．Whenever people make decisions when they are in panic, the consequences are ________ (rare) pretty.7．David ________ (wander) in the street alone when someone patted him on the shoulder.8．________ is interested in watching the coming volleyball game should book the ticket in advance.9．Come to Dollywood to have fun ________ (learn) all about America's historical southeastern culture!10．Chinese young generations have a growing appetite ________ online English learning.维度3 完成句子1．直到我读了她的信后，我才意识到她发生了什么事情。
模具术语翻译
模具名词中英文对照表序号中文名英文名1 一、水口gate2 进水位gate location3 水口形式gate type4 大水口edge gate5 细水口 pin-point gate6 水口大小gate size7 转水口switching gate8 唧嘴口径sprue diameter9 二、流道runner10 热流道hot runner11 冷流道cold runner12 唧嘴直流direct sprue gate13 圆形流道round runner14 模流分析mold flow analysis15 流道平衡runner balance16 热嘴hot sprue17 热流道板hot manifold18 发热管cartridge heater19 探针thermocouples20 插头connector plug21 插座 connector socket22 密封/封料 seal23 三、运水water line24 喉塞line pug25 喉管tube26 塑胶管plastic tube27 快速接头jiffy quick connector plug28 四、模具零件mold components29 三板模three-plate mold模具名词中英文对照表序号中文名英文名30 二板模two-plate mold31 边钉/导边leader pin/guide pin32 边司/导套bushing/guide bushing33 顶针板ejector retainer plate34 托板support plate35 螺丝 screw36 管钉dowel pin37 开模槽ply bar score38 内模管位core/cavity inter-lock39 顶针ejector pin40 司筒ejector sleeve41 司筒针ejector pin42 推板stripper plate43 缩呵movable core44 扣机（尼龙拉勾） nylon latch lock45 斜顶lifter46 模胚（架） mold base47 母模cavity insert48 公模core insert49 行位（滑块） slide50 镶件insert51 压座/斜鸡wedge52 耐磨板/油板wedge wear plate53 压条plate54 撑头support pillar55 唧嘴 sprue bushing56 挡板stop plate57 定位圈locating ring58 锁扣latch模具名词中英文对照表序号中文名英文名59 扣鸡parting lock set60 推杆push bar61 栓打螺丝S.H.S.B62 顶板ejector plate63 活动臂lever arm64 水口司bush65 垃圾钉stop pin66 隔片buffle67 弹弓柱spring rod68 弹弓die spring69 镶针pin70 销子dowel pin71 波子弹弓ball catch72 喉塞pipe plug73 锁模块lock plate74 斜顶angle from pin75 斜顶杆angle ejector rod76 尼龙拉勾parting locks77 复位键、提前回杆early return bar78 气阀valves79 斜导边angle pin80 模排气parting line venting81 模总高超出啤机规格mold base shut height82 模胚原身出料位cavity direct cut on A-plate，coredirect cut on B-plate.83 不准用镶件Do not use (core/cavity) insert84 用铍铜做镶件use beryllium copper insert85 强度不够insufficient rigidity86 公差tolerance87 铜公(电极) copper electrode动模 Movable Mould Moving Half定模座板 Fixed Clamp Plate Top Clamping Plate Top Plate动模座板 Moving Clamp Plate Bottom Clamping Plate Bottom Plate 上模座板 Upper Clamping Plate下模座板 Lower Clamping Plate凹模固定板 Cavity-retainer Plate型芯固定板 Mould Core-retainer Plate凸模固定板 Punch-retainer Plate模套 Die Body Die Sleeve Die Blank支承板 Backing Plate Support Plate垫块 Spacer Parallel支架 Ejector Housing Mould Base Leg模头 Die Head根据国家标准，以下为部分压铸模具术语的标准翻译。
Kitronik ARCADE游戏板使用说明说明书
Programming from MakeCode Arcade:Connect the ARCADE via the micro USB port to acomputer. If the board was already running then press the reset button. The display of the ARCADE will now show the download screen, and a removable drive (labelled KIT-ARCD) will appear. Pressing the Download button in MakeCode Arcade will produce a .UF2 file, which needs to be saved onto the removable drive. For more details see later in this datasheet.Board Layout:On/Off SwitchDebug portIntroduction: The ARCADE is a programmable gamepad for use with MakeCode Arcade. It features a full colour LCD screen, a piezo buzzer for audio feedback, a vibration motor for haptic feedback, 6 input buttons, a menu button and a reset button. The ARCADE is supplied complete in a transparent protective case, which allows the electronics to be seen.The ARCADE is powered by either 3xAA batteries or via the micro USB connector. The battery holders are located on the rear of the PCB. Insert the batteries with the negative side onto the spring connection of the battery holder. The ARCADE produces a regulated supply for the on-board processor.The ARCADE is designed for MakeCode Arcade (https:///)Button ALCD DisplayButton BPiezo BuzzerVibration MotorJoypad UpJoypad RightJoypad LeftJoypad DownRear: 3 x AA Battery HoldersPower LEDMenu ButtonReset Buttonmicro USB portExpansion Port1 & 2Examples: For some starter games and ideas for what else you could do, go to: /arcadeProgramming the ARCADE from Microsoft MakeCode Arcade Blocks EditorThe ARCADE is programmed using the Microsoft MakeCode Arcade Editor.To use MakeCode Arcade navigate to https:// in a web browser (such as Edge, Chrome, or Safari).There are numerous sample games and tutorials on the MakeCode website. To open them click on the various tiles.To create your own game from scratch click on the New Project button (other projects previously created are also shown on thishome screen). The editor will ask to give the project a name. Type in an appropriate name (such as “My first game”)There is an example game on the next page.When you have created your code and want to load it on the ARCADE:Make sure the ARCADE is switched off and connect a micro-USB lead from the ARCADE to the Computer.On first connection the Computer may require installation of drivers, this will be done automatically.Once complete a notification should appear on your Computer.On the ARCADE a download screen will appear and a drive will appear on the Computer (similar to other devices like USB sticks, phonesand BBC micro:bit).Whenever a micro USB lead is inserted, connecting the ARCADE to a Computer, pressing the reset button on the ARCADE will switchbetween the currently loaded code and the download mode.To get the code from the editor to the ARCADE, click on the download button.The first time this is done the editor will ask you to select which compatible device you have.Select the Kitronik ARCADE from the list. If the Kitronik ARCADE is not listed then select the D5 option.Then select where to save the .UF2 file (select KIT-ARCD on the device list), or if the file has already been saved inyour downloads folder, simply drag and drop the file into KIT-ARCD.The ARCADE power LED will flash as the transfer occurs. Once complete, the code will start running.Should the download fail then the ARCADE may only display a blank screen, and the power LED will pulse. In this casereconnect to the Computer and press the reset button. This will put the ARCADE back into download mode.Microsoft MakeCode Arcade Blocks Editor CodeThis program was created in the Microsoft MakeCode Arcade Blocks Editor (https://).The game shows Kit –The Kitornik Robot as the player. The aim is to move around the screen collecting batteries, with every battery gaining points.On Start block: First, the background colour is set. Then a player and a food icon are created to display on screen. The Player is in the shape of Kit, and the food is in the shape of a battery. The move block connects the player icon to the gamepad keys, to allow the player to move the robot around.Finally a 10 second countdown is started, this limits the length of the game.On sprite block:This block runs once Kit gets to the battery. It detects that there is an overlap in their positions.The blocks inside increase the score, for the collection of the battery, and then redraws a new battery to collect at a random place on the screen.This example can be loaded from https:///_7w71T5emyPH0Note: There are additional tutorials on the MakeCode Arcade home page (link above).Electrical InformationProcessor Atmel SAMD51J19AOperating Voltage (Vcc)3xAA –Alkaline or NiMH/NiCad (3.6-4.5V) or USB (typically 5V) LCD screen resolution160 x 128LCD screen size 1.77 inch (diagonal)Typical Current Draw Approx. 80mA (depending on use)Typical Battery life (based on 3xAA 1500mAh batteries)Approx. 20 hours (depending on use)Debugging and Expansion Port Information for Expert usersAlso included on the ARCADE are 2 expansion ports. These are connected directly to themicroprocessor pins. Enabling these ports requires reconfiguration and programming of the ARCADE bootloader. The bootloader source can be found at:https:///KitronikLtd/kitronik-arcade-uf2-bootloaderPin 1Pin 2Pin 3Pin 4Pin 5Pin 6Pin 7Pin 8 Expansion Port 1PA08PA09PA10PA110V0V0V0V Expansion Port 2PA12PA13PA14PA150V0V0V0VFor more advanced use, the debug port allows the user to customise the processor bootloader code, using a SWD programmer. The port is designed for 2.54mm (0.1”) pitch standard pin header.For more information see: https:///hardware/dbgPin 1Pin 2Pin 3Pin 4Pin 5 Debugging Port0V SWCLK3V3SWDIO0VNote:Kitronik do not take any responsibility for changes users make to the bootloader code on the processor.EN 55032:2015, EN55035:2017, EN IEC 63000:2018The expansion port is designed to take 2.54mm (0.1”) dual pin headers.Paired with each IO pin on the expansion port is a 0V connection. The IO pins are rated to 3V max. See the pinout table for connections from the expansion ports to the microprocessor.。
DLP Design DDLLPP-FFPPG USB-FPGA Module User Manua
D L P-F P G ALEAD-FREEUSB - FPGA MODULEAPPLICATIONS:- Rapid Prototyping- Educational Tool- Industrial/ProcessControlFEATURES:- Training Manual/Tutorial Available- Built-In Configuration Loader—Writes Bit File Directlyto SPI Flash via Full-Speed USB Interface- 40 I/O Channels: 27 Input/Output; 13 Input Only- Xilinx XC3S250E-4TQ144 FPGA- On-Board 128K x 8, 70nS SRAM- USB Port Powered- USB 1.1 and 2.0 Compatible Interface- Small Footprint: 2.8 x 1.-Inch PCB- Standard 50-Pin, 0.9-Inch DIP Interface1.0 INTRODUCTIONThe DLP-FPGA Module is a low-cost, compact prototyping module that can be used for rapid proof of concept or for educational environments. The module is based on the Xilinx Spartan 3E and Future Technology Devices International’s FT2232D Dual-Channel USB IC. Used by itself or with the optional 200-page training manual, the DLP-FPGA provides both the beginner as well as the experienced engineer with a rapid path to developing FPGA-based designs. When combined with the free WebPACK™ Tools from Xilinx, this module is more than sufficient for creating anything from basic logical functions to a highly complex system controller.As a bonus feature, one channel of the dual-channel USB interface is used to load user bit files directly to the SPI Flash—no external programmer is required. This represents a savings of as much as $200 in that no additional programming cable is required for configuring the FPGA. All that is needed to load bit files to the DLP-FPGA is a Windows software utility (free with purchase), a Windows PC and a USB cable. The module can also be programmed from within the Xilinx ISE tool environment using a Xilinx programming cable (purchased separately).The DLP-FPGA is fully compatible with the free ISE™ WebPACK™ tools from Xilinx. ISE WebPACK offers the ideal development environment for FPGA designs with HDL synthesis and simulation, implementation, device fitting and JTAG programming.The DLP-FPGA has on-board voltage regulators that generate all required power supply voltages from a single 5-volt source. Power for the module can be taken from either the host USB port or from a user-supplied, external 5-volt power supply.Connection to user electronics is made via a 50-pin, 0.9-inch wide, industry-standard 0.025 square inch post DIP header. Other on-board features include a 128K x 8 static RAM IC for user projects, and both JTAG and SPI Flash interface ports for connection to Xilinx programming tools.2.0 TRAINING MANUALA 200+ page training manual for the DLP-FPGA is also available. While this manual is designed to provide entry-level instruction for those new to designing with FPGAs, it is recommended for developers who have some experience with FPGA products and associated development tools. An ISE™ WebPACK™Software installation DVD is included with the manual.The manual is comprised of 5 Chapters and 4 Labs as outlined below:Chapter 1: Installing the Xilinx ISE WebPACK tools and Understanding the Design FlowChapter 2: Lab 1: Implementing a Simple AND Gate: Create a New Project, Implement the Design, View the Synthesized Design, View the Placed and Routed DesignChapter 3: Lab 2: Heartbeat: Understanding the Digital Clock Manager (DCM), Methods of Starting ISE Project Navigator, VHDL Module Structure, Utilizing Hierarchy, Adding the DCM Component, Adding the Heartbeat Component, Connecting the Components, Synthesizing the Design Using XST, Simulating the Design Using the ISE Simulator, Adding the User Constraint File, Implementing the Design, Download the Design to the FPGAChapter 4: Lab 3: Memory Test: Block Diagram, DCM Design, SRAM State Machine, Bi-Directional Buffers, Test Failed Indicator, User Constraint File, Synthesize the Memory Test Design, Simulate the Memory Test Design, Implementing the Design, Download the Design to the FPGAChapter 5: Lab 4: USB Loopback: Initial Design, USB State Machine Module, Language Template, Bi-Directional Buffers, Synthesize, Simulate, Pin Constraints, Implement, Download the Design to the FPGA(The completed design files for each lab are available for download from the DLP Design website upon purchase of the DLP-FPGA and Lab Manual.)3.0 FPGA SPECIFICATIONSThe FPGA device used on the DLP-FPGA is the Xilinx Spartan 3E: XC3S250E-4VQ100.•Part Number: XC3S250E•System Gates: 250K•Equivalent Logic Cells: 5,508• CLB Arrayo Rows: 34o Columns: 26o Total CLB’s: 612o Total Slices: 2,448•Distributed RAM Bits: 38K•Block RAM Bits: 216K•Dedicated Multipliers: 12•DCM’s: 44.0 BITLOADAPP SOFTWAREWindows software is provided for use with the DLP-FPGA that will load an FPGA configuration (.bit) file directly to the SPI Flash device via the USB interface. This app (shown below) will allow the user to erase the flash, verify the erasure and then program and verify the flash:5.0 JTAG INTERFACEThe easiest way to load an FPGA configuration (bit file) to the FPGA is to run the BitLoadApp software, then select and program a file from the local hard drive directly to the SPI flash. Once written to the SPI flash, the configuration will load to the FPGA and execute. Alternatively, a traditional JTAG header location is provided on the DLP-FPGA giving the user access to the pins on the FPGA required by the development tools. (Refer to the schematic at the end of this datasheet for details.)6.0 EEPROM SETUP / MPROGThe DLP-FPGA has a dual-channel USB interface to the host PC. Channel A is used exclusively to load an FPGA configuration (bit file) to the SPI flash. This configuration data is automatically transferred to the FPGA when power is applied to the module. Channel B is used for communication between the FPGA and host PC at run time. A 93C56B EEPROM connected to the USB interface IC is used to store the setup for the two channels. The parameters stored in the EEPROM include the Vendor ID (VID), Product ID (PID), Serial Number, Description String, driver selection (VCP or D2XX) and port type (UART serial or FIFO parallel).As mentioned above, Channel A is used exclusively for loading the FPGA’s configuration to the SPI flash, and Channel B is used for communication between the host PC and the DLP-FPGA. As such, the D2XX drivers and FIFO mode must be selected in the EEPROM for Channel A. Channel B must use the FIFO mode, but can use either the VCP or D2XX drivers. The VCP drivers make the DLP-FPGA appear as an RS232 port to the host app. The D2XX drivers provide faster throughput, but require working with a .lib or .dll library in the host app.The operational modes and other EEPROM selections are written to the EEPROM using the MPROG utility. This utility and its manual are available for download from the bottom of the page at.7.0 TEST BIT FILEA test file is provided as a download from the DLP Design website that provides rudimentary access to the I/O features of the DLP-FPGA.The following features are provided:• Ping•Read the High/Low State of the Input-Only Pins•Drive I/O Pins High/Low or Read their High/Low State•Simple Loopback on Channel B•Simple Read/Write of Each Address in the SRAMThis bit file is available from the DLP-FPGA’s download page.8.0 USB DRIVERSUSB drivers for the following operating systems are available for download from the DLP Design website at :W i n d o w s X P x 64 M a c O S X W i n d o w s S e r v e r 2003M a c O S 9 W i n d o w s 2000 M a c O S 8 W i n d o ws 98, M EL i n u xNotes:1. The bit file load utility only runs on the Windows platforms.2. The bit file load utility requires the use of USB channel A, and channel A is dedicated to this function.3. If you are using the dual-mode drivers from FTDI (CDM2.02.04) and wish to use the VirtualCOM Port (VCP) drivers for Channel B communications, then it may be necessary to disable the D2XX drivers first via Device Manager. To do so, right click on the Channel B entry under USB Controllers that appears when the DLP-FPGA is connected, select Properties, select the Advanced tab, check the option for “Load VCP” and click OK. Once you unplug and then replug the DLP-FPGA, a COM port should appear in Device Manager under Ports (COM & LPT).9.0 USING THE DLP-FPGASelect a power source via Header Pins 23 and 24, and connect the DLP-FPGA to the PC to initiate the loading of USB drivers. The easiest way to do this is to connect Pins 23 and 24 to each other. This will result in operational power being taken from the host PC. Once the drivers are loaded, the DLP-FPGA is ready for use.Pin 25Top View (Interface Headers on bottom of PCB)Pin 50T A B L E1NN (dec)* NN (hex)* Name FPGA Pin JP2 Pin0 0 user_io(0) U5 Pin 58 JP2 Pin 21 1 user_io(1) U5 Pin 59 JP2 Pin 42 2 user_io(2) U5 Pin 93 JP2 Pin 53 3 user_io(3) U5 Pin 94 JP2 Pin 64 4 user_io(4) U5 Pin 96 JP2 Pin 75 5 user_io(5) U5 Pin 97 JP2 Pin 86 6 user_io(6) U5 Pin 103 JP2 Pin 97 7 user_io(7) U5 Pin 104 JP2 Pin 108 8 user_io(8) U5 Pin 105 JP2 Pin 129 9 user_io(9) U5 Pin 106 JP2 Pin 1310 A user_io(10) U5 Pin 112 JP2 Pin 1411 B user_io(11) U5 Pin 113 JP2 Pin 1512 C user_io(12) U5 Pin 116 JP2 Pin 1613 D user_io(13) U5 Pin 117 JP2 Pin 1714 E user_in(14) [INPUT ONLY!] U5 Pin 119 JP2 Pin 1815 F user_in(15) [INPUT ONLY!] U5 Pin 120 JP2 Pin 1916 10 user_io(16) U5 Pin 122 JP2 Pin 2017 11 user_io(17) U5 Pin 123 JP2 Pin 2118 12 user_io(18) U5 Pin 124 JP2 Pin 2219 13 user_io(19) U5 Pin 125 JP2 Pin 2720 14 user_io(20) U5 Pin 126 JP2 Pin 2921 15 user_io(21) U5 Pin 130 JP2 Pin 3022 16 user_io(22) U5 Pin 131 JP2 Pin 3123 17 user_io(23) U5 Pin 132 JP2 Pin 3224 18 user_io(24) U5 Pin 134 JP2 Pin 3325 19 user_io(25) U5 Pin 135 JP2 Pin 3426 1A user_io(26) U5 Pin 139 JP2 Pin 3527 1B user_io(27) U5 Pin 140 JP2 Pin 3628 1C user_io(28) U5 Pin 142 JP2 Pin 3730 1E user_in(0) U5 Pin 10 JP2 Pin 4931 1F user_in(1) U5 Pin 12 JP2 Pin 4832 20 user_in(2) U5 Pin 29 JP2 Pin 4733 21 user_in(3) U5 Pin 31 JP2 Pin 4634 22 user_in(4) U5 Pin 36 JP2 Pin 4535 23 user_in(5) U5 Pin 38 JP2 Pin 4436 24 user_in(6) U5 Pin 41 JP2 Pin 4337 25 user_in(7) U5 Pin 47 JP2 Pin 4238 26 user_in(8) U5 Pin 48 JP2 Pin 4139 27 user_in(9) U5 Pin 66 JP2 Pin 3940 28 user_in(10) U5 Pin 69 JP2 Pin 38Read: 29,>40 Read:1D,>29Returns Read Pin Error E4 n/a n/aWrite: 14, 15, >30 Write: E, F,>1EReturns Write Pin Error E2 for PinClear (low), or E3 for Pin Set(high)n/a n/aGround 1,11,25,26,40,50FPGA_RESET 1283 5VIN – Module power source 23PORTVCC – Power from Host PC 24VCCSW – 5V power after hostenumerates the USB port28*N o t e:This is the I/O number for use with the Test Bit File described in Section 7.10.0 MECHANICAL DIMENSIONS IN INCHES (MM) (PRELIMINARY)11.0 DISCLAIMER© DLP Design, Inc., 2007Neither the whole nor any part of the information contained herein nor the product described in this manual may be adapted or reproduced in any material or electronic form without the prior written consent of the copyright holder.This product and its documentation are supplied on an as-is basis, and no warranty as to their suitability for any particular purpose is either made or implied. DLP Design, Inc. will not accept any claim for damages whatsoever arising as a result of the use or failure of this product. Your statutory rights are not affected. This product or any variant of it is not intended for use in any medical appliance, device, or system in which the failure of the product might reasonably be expected to result in personal injury.This document provides preliminary information that may be subject to change without notice.12.0 CONTACT INFORMATIONDLP Design, Inc.1605 Roma LaneAllen, TX 75013Phone: 469-964-8027Fax: 415-901-4859Email Sales: *******************EmailSupport:*********************Website URL: 。
2019年安徽省中考英语试卷以及解析答案
2019年安徽省中考英语试卷第一部分听力（共五大题，满分5分）I．关键词语选择（共5小题；每小题1分，满分5分）你将听到五个句子。
请在每小题所给的A、B、C三个选项中选出一个你所听到的单词或短语。
每个句子读两遍。
1．（1分）A．partB．passC．place2．（1分）A．farmB．filmC．form3．（1分）A．wordB．worldC．water4．（1分）A．luckyB．lonelyC．lovely5．（1分）A．throw awayB．put awayC．take awayⅡ．短对话理解（共10小题；每小题1分，满分10分）你将听到十段对话，每段对话后有一个小题。
请在每小题所给的A、B、C三个选项中选出一个最佳选项．每段对话读两遍。
6．（1分）What does the man want to buy？7．（1分）What is the weather like now？8．（1分）What would the man like to drink？9．（1分）How does Grace go to school these days？10．（1分）What does the man want to be？11．（1分）When does the movie start？A．At 7：00．B．At 8：00．C．At 9：00．12．（1分）What color jacket does the man prefer？A．Black．B．Blue．C．Brown．13．（1分）What is the woman's name？A．Moira．B．Maria．C．Meryl．14．（1分）Where does the conversation probably take place？A．In a library．B．In a bank．C．On a bus．15．（1分）What will the woman do tonight？A．Watch a football game．B．Finish her report．C．Do the housework．Ⅲ．长对话理解（共2题；满分5分）你将听到两段对话，每段对话后有几个小题。
Intel SoC FPGA Embedded Development Suite (SoC EDS
Intel® SoC FPGA Embedded Development Suite (SoC EDS) Standard Version 19.1 Release NotesUpdated for Intel® Quartus® Prime Design Suite: 19.1SubscribeSend FeedbackRN-SOCEDS-STD | 2020.02.07 Latest document on the web: PDF | HTMLContents ContentsIntel® SoC FPGA Embedded Development Suite (SoC EDS) Standard Version 19.1 Release Notes (3)What's New (3)Tool Versions (3)Resolved Issues (4)Known Issues (4)Intel SoC FPGA Embedded Development Suite Archives (4)Revision History for Intel SoC FPGA Embedded Development Suite (SoC EDS) Release Notes (4)Intel® SoC FPGA Embedded Development Suite (SoC EDS) Standard VersionSend Feedback 19.1 Release Notes2Intel ® SoC FPGA Embedded Development Suite (SoC EDS)Standard Version 19.1 Release NotesThis document provides up-to-date information about the SoC EDS Standard Edition version 19.1 release for the of the Intel ® SoC FPGA Embedded Development Suite (SoC EDS) software.The SoC EDS Standard Edition targets the Cyclone ® V, Arria ® V, and Intel Arria 10devices and must be used only with FPGA projects created in Intel Quartus ® Prime Standard Edition.For more information, refer to the Intel SoC FPGA Embedded Development Suite User Guide .For earlier versions of these release notes, refer to the Intel SoC FPGA Embedded Development Suite Archives section.Related Information •Intel SoC FPGA Embedded Development Suite Archives on page 4Provides a list of user guides for previous versions of the SoC FPGA EDS IP core.•Intel SoC FPGA Embedded Development Suite User GuideWhat's New•Intel Agilex ™ support:—Added the Intel Agilex Golden Hardware Reference Designs for SoC FPGA Development Kits (GHRD).—U-Boot, UEFI, and Arm* Trusted Firmware (ATF) are no longer part of Intel SoC FPGA EDS, but are available on GitHub .For information about how to build the bootloaders, refer to .Related Information Tool VersionsTable 1.Std Edition Tool Version UpdatesRN-SOCEDS-STD | 2020.02.07Send FeedbackIntel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.*Other names and brands may be claimed as the property of others.ISO9001:2015RegisteredToolsVersionLinux* Compiler 4.8.3 (Linaro* GCC 7.2-2017.11)Arm Compiler 5 5.06Arm Compiler 66.10.1Resolved Issues•arm-altera-eabi-gdb removed to eliminate security vulnerabilities•cygwin_setup folder included on Windows* to facilitate your manual CygwininstallationKnown IssuesTable 2.SoC EDS Standard Edition version 19.1 for Windows requires a patch.Description:SoC EDS version 19.1 for Windows requires a patch.Note: SoC GHRD is also removed from Intel SoC FPGA EDS because GHRD is missingfrom /embedded/examples/hardware .Workaround:To use the SoC EDS Standard Edition version 19.1 on Windows, download and install this patch , available in the Intel FPGA Knowledge Base.Intel SoC FPGA Embedded Development Suite ArchivesIntel Quartus Prime VersionRelease Notes (PDF)18.1Intel SoC FPGA Embedded Development Suite Release Notes (18.1)These release notes cover Intel Quartus Prime versions 18.0 through 18.1.18.0Intel SoC FPGA Embedded Development Suite Release Notes (18.0)These release notes cover Intel Quartus Prime versions 17.0 through 18.0.Revision History for Intel SoC FPGA Embedded Development Suite (SoC EDS) Release NotesIntel ® SoC FPGA Embedded Development Suite (SoC EDS) Standard Version 19.1 Release NotesRN-SOCEDS-STD | 2020.02.07Intel ® SoC FPGA Embedded Development Suite (SoC EDS) Standard Version 19.1 Release Notes Send Feedback4Document VersionChanges2017.12.05Added new features, bug fixes, enhancements, and known issues during the Intel Quartus Prime 17.1 release of the SoC FPGA EDS software - Standard and Pro editions.2017.05.08Release Notes divided into a Pro and Standard section.2016.11.07Added clarity to the early IO release feature.2016.05.09Added new features, bug fixes, enhancements, and known issues during theIntel Quartus Prime 16.0 release updates2016.01.22Added new features, bug fixes, enhancements, and known issues during the Intel Quartus Prime 15.1.1 release updates2015.11.02Added new features, bug fixes, enhancements, and known issues during the Intel Quartus Prime 15.1 release updates2015.06.05Added new features, bug fixes, enhancements, and known issues during the Intel Quartus Prime 15.0.1 release updates2015.05.01Added new features, bug fixes, enhancements, and known issues during the Intel Quartus Prime 15.0 release updatesIntel ® SoC FPGA Embedded Development Suite (SoC EDS) Standard Version 19.1 Release Notes RN-SOCEDS-STD | 2020.02.07Send FeedbackIntel ® SoC FPGA Embedded Development Suite (SoC EDS) Standard Version19.1 Release Notes5。
14浇口及流道设计3_19_GATE_RUN_DESIGN
設定分析
Advanced . . . Runner Balance
尺寸修改裕度(Mill tolerance) 最大重複計算次數(Maximum iterations) 時間收斂裕度(Time Convergence tolerance) 壓力收斂裕度(Pressure Convergence tolerance)
複製模型
選擇整個模型 轉換
Vector 75 Copy 1
建立主流道
建立Beams
設有建立規範 • Circle, 5 mm dia. Occur 2 對於次流道之間採用 10 個元素 豎膠道採用5 個元素
建立豎膠道
建立豎膠道節點 建立曲線
第一個節點為豎膠道頂點
建立設定規範
Sprue Orifice 5.56 mm Taper 2.38º
直接澆口(Elements in a Gate) 直接澆口
澆口至少要有三個元素才能精確預測
澆口凝固時間 剪切率 壓力
澆口尺寸
澆口尺寸將會影響剪切率大小值 剪切率指引可在材料資料庫中發現 若超過則改變澆口形式; 放大、加厚，射慢改
澆口尺寸
最好保持澆口剪切率在材料物性極限以 下 如果澆口尺寸允許,剪切率最好控制在 20,000 1/sec.透明件要求6000以下。 大的澆口較容易降低剪切率,如邊緣澆口 、扇形澆口、薄膜澆口，熱流道可降剪 切應力 香蕉形澆口與熱澆道加工較困難 不可能就用針點澆口
QUEST果獲得 衡性與2%的壓力不平衡性 衡性與 的壓力不平衡性
修改流道尺寸
在案例中如執行流道平衡分析，將會自動修改流道 尺寸且會在分析子目錄後面註解(runner balance)有 能造成保壓不均
檢查平衡時的保壓
小学上册第五次英语第三单元寒假试卷
小学上册英语第三单元寒假试卷英语试题一、综合题(本题有100小题，每小题1分，共100分.每小题不选、错误，均不给分)1.The ________ grows in water and floats.2.The __________ is a famous city in the Netherlands known for its tulips. (阿姆斯特丹)3.How do you feel when you win a game?A. SadB. HappyC. AngryD. Tired4.What do we call the process of changing from a liquid to a solid?A. MeltingB. FreezingC. BoilingD. EvaporatingB5.The tortoise is slow but very _______ (聪明).6. A ________ is a low area of land between hills or mountains.7.The _____ (生物多样性) is crucial for a healthy ecosystem.8.What do we call the fourth planet from the Sun?A. VenusB. EarthC. MarsD. Jupiter9.I have a _____ of stickers in my book. (collection)10.The surface of a leaf can be ______ (光滑) or rough.11.The cat is ___ (purring/meowing).12.The rabbit hops around the _________ (草地).13.Oxygen supports _______ in fire.14.What is the name of the star at the center of our solar system?A. MoonB. SunC. EarthD. MarsB15.What do you call a person who studies animals?A. ZoologistB. BiologistC. NaturalistD. All of the aboveD16.What do we call the process of breathing out?A. InhaleB. ExhaleC. BreatheD. Respire17.How many hours are there in a day?A. 12B. 24C. 36D. 4818.What is the name of the famous bridge in San Francisco?A. Brooklyn BridgeB. Golden Gate BridgeC. London BridgeD. Sydney Harbour BridgeB Golden Gate Bridge19.My brother is a ______. He enjoys playing the guitar.20.The country known for tulips is ________ (以郁金香闻名的国家是________).21. A __________ is formed by the accumulation of sediments in a coastal area.22. A _______ (小兔子) has long ears and likes to eat carrots.23.The __________ was a movement to end slavery in the United States. (废奴运动)24.I have a toy _______ that can blow bubbles into the air.25.The wind is _______ (whistling) through the trees.26. A solution that can dissolve more solute is called ______.27.What do we call a young lion?A. CubB. PuppyC. KittenD. Calf28.In _____ (印度), the monsoon season brings heavy rains.29.What do we call the traditional game played with a ball and net?A. CricketB. BaseballC. TennisD. Soccer30.What do you call a person who studies the weather?A. MeteorologistB. ClimatologistC. GeologistD. HydrologistA31.I love to design my own _________ (玩具) for my friends.32.What is the capital of Libya?A. TripoliB. BenghaziC. MisrataD. Sabha33.The _____ (植物适应性) ensures survival in changing climates.34. A ______ (蜗牛) leaves a trail of slime behind.35.The __________ is a region known for its rice fields.36. A chemical reaction that produces water is called a ______ reaction.37.The __________ (历史的延续) defines narrative.38.What do you wear on your feet?A. HatB. GlovesC. ShoesD. ScarfC39.What do we call the outer layer of the Earth?A. CoreB. MantleC. CrustD. Atmosphere40.What do we need to do before crossing the street?A. RunB. LookC. JumpD. Close eyes41.The clock is ________ ticking.42. A compound is made up of two or more different ______.43.I have a _____ (新) bike.44. A ______ helps in protecting plants from pests and diseases. (良好的护理可以保护植物免受害虫和疾病的侵害。
Garden City and its neighbours Unit 3知识点记忆-牛津上海版英语
Unit 3 A visit to Garden City（记忆版）1. a visit to Garden City 参观花园市这里的visit 是名词visit Garden City 参观花园市这里的visit 是动词They paid a visit to Shanghai Museum last week. 他上周参观了上海博物馆。
= They visited Shanghai Museum last week.2. the Li family 李家3. teach maths in a school 在一个学校教数学The person who teaches maths in our school is Miss Guo.那个在我们学校教数学的是郭小姐。
Miss Guo teaches us maths in our school. 郭小姐教我们数学。
4. be an architect（an engineer ）= work as an architect （an engineer ）担任（建筑师）工程师一职He has been an architect for 4 years. 他担任建筑师已经4年了。
= He has worked as an architect for 4 years.5. quite a few (years) 好几（年）(跟可数名词)He has made quite a few friends since he came here.自从他来到这里已经交了好几个朋友了。
quite a little （news ）好些新闻(跟不可数名词)He has collected quite a little useful news since he surfed the net. 自从他上网以来，已经收集了好多有用的信息了。
6. for 12 years 12年for several years 好几年since 12 years ago 自从12年起since several years ago 好几年前起7. draw plans of buildings 画建筑图8. design machines 设计机器9．deliver letters 送信10. train someone in sport 在体育方面训练某人11. drive a bus 开车12. be in charge of a school 负责主管一个学校be in the charge of a school 由。
小学上册J卷英语第三单元自测题(有答案)
小学上册英语第三单元自测题(有答案)英语试题一、综合题(本题有100小题，每小题1分，共100分.每小题不选、错误，均不给分)1.My dad listens to ____ (music) while he works.2.古代的________ (artifacts) 帮助我们了解过去的文化。
3.My cousin is a ______. She enjoys participating in debates.nd use planning) balances development and conservation. The ____5.I have a pet ______ (猫), and she is very ______ (可爱). She loves to play with______ (球) in the garden.6.Carbon dioxide is produced during ______ respiration.7. A ______ (城市花园) can beautify neighborhoods.8.I have a pet ______ (fish).9.We live in a ________ (城市) near the river.10.sustainability report) evaluates progress. The ____11.When I grow up, I want to design my own _________ (玩具).12.What do you call a solid that has no definite shape?A. LiquidB. GasC. SolidD. Plasma答案:A13. A __________ can provide insights into natural disasters.14.The chemical symbol for palladium is ______.15.The milk is in the ___ (fridge).16. A lunar eclipse happens when the Earth comes between the Sun and the ______.17.We visit the ______ (音乐会) to enjoy live performances.18.What is the name of the famous bridge in San Francisco?A. Brooklyn BridgeB. Golden Gate BridgeC. London BridgeD. Tower Bridge答案:B19.My _____ (阿姨) loves to cook and bake delicious treats. 我阿姨喜欢烹饪和烘焙美味的点心。
Design_compiler经典教程
微电子学实验室实验教程ASIC综合器软件——Design Compiler实验2006-7Design Compiler实验前言Design Compiler（简称DC）是synopsys公司的ASIC综合器产品，它可以完成将硬件描述语言所做的RTL级描述自动转换成优化的门级网表。
DC得到全球60多个半导体厂商、380多个工艺库的支持。
Synopsys的逻辑综合工具DC占据91%的市场份额。
DC是工业界标准的逻辑综合工具，也是Synopsys最核心的产品。
它使IC设计者在最短的时间内最佳的利用硅片完成设计。
它根据设计描述和约束条件并针对特定的工艺库将输入的VHDL或者Verilog的RTL描述自动综合出一个优化的门级电路。
它可以接受多种输入格式，如硬件描述语言、原理图和网表等，并产生多种性能报告，在缩短设计时间的同时提高设计性能。
本实验对DC软件的使用进行简单的介绍，熟悉和掌握综合器软件使用中的基本概念和术语，了解如何对数字电路施加约束，掌握同步数字电路设计、约束和优化的方法，了解时钟的概念，理解同步电路静态时序分析（STA）的方法和时序报告。
西安交通大学微电子学实验室实验1setup和synthesis流程实验准备有两种界面可以运行Design Compiler：1)命令行界面，dc_shell-xg-t；2)图形用户界面(GUI)，Design Vision。
本次实验主要运用GUI模式。
图1.1给出了RTL逻辑综合的直观概念和简要流程。
图1.1 RTL逻辑综合的直观概念和简要流程。
在DC中，总共有8种设计对象：z设计(Design)：一种能完成一定逻辑功能的电路。
设计中可以包含下一层的子设计。
z单元(Cell)：设计中包含的子设计的实例。
z参考(Reference)：单元的参考对象，即单元是参考的实例。
z端口(Port)：设计的基本输入输出口。
z管脚(Pin)：单元的输入输出口。
z连线(Net)：端口间及管脚间的互连线。
- 1、下载文档前请自行甄别文档内容的完整性，平台不提供额外的编辑、内容补充、找答案等附加服务。
- 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
- 3、如文档侵犯您的权益，请联系客服反馈,我们会尽快为您处理(人工客服工作时间：9:00-18:30)。
設定分析
Advanced . . . Runner Balance
尺寸修改裕度(Mill tolerance) 最大重複計算次數(Maximum iterations) 時間收斂裕度(Time Convergence tolerance) 壓力收斂裕度(Pressure Convergence tolerance)
建立設定規範
網格長度為 6 mm
指定進膠點
儲存完成模型
儲存新名稱
Snap Cover 2 cav
QUESTIONS?
為何要平衡流道?
擔保產品充填一致性 (平衡) 擔保保壓一致性 保持可接受的壓力範圍 使流道體積減到最小
流道平衡限制
對於流動平衡可約束流道屬性性質 內定設定是不受約束 流道平衡分析將不會改變澆口與豎澆道尺寸
觀看流道平衡結果
壓力平衡
壓力在模穴之間均等嗎? 如不行,如何修改?
時間平衡
在一定時間內足夠充滿模穴?
流道尺寸是否得宜? 他們能夠均勻分佈或在標準尺寸範圍嗎? 冷卻時間建議保壓問題 決定流道系統80%最小冷卻時間或產品冷卻時間
流道尺寸
冷卻時間
時間 vs.壓力結果
如果沒壓力平衡與它 有關係嗎?時間比率低 於 0.04 秒!!
使用在三板模模具 非常小的孔洞 模型建立使用Beams 孔洞直徑約為0.25~ 1.5 mm
Drop blue Gate, Yellow
熱澆道(Hot drop)
直接將熔膠材料送到產品 熱澆道形式決定了澆口幾 何造型與尺寸 孔口尺寸是重要關鍵,它控 制噴口塑料不會流出 模型建立使用Beams
4
4
剩下的模穴將已 occurrence 數目來代表
4 2
4 2
1
4 OCC代表模穴,澆口及次流道 2 OCC帶表 主要流道 1 OCC帶表 豎流道
Snap Cover 描述
Snap Cover 流動平衡
執行充填分析決定流動平衡輸入參數 決定平衡壓力 導引流道平衡 重新探討結果 如有需要可重新執行流道平衡分析
QUESTIONS?
流道形式
兩種常見形式
魚骨型排列 按幾何學原理平衡排列
流道尺度規格
依據不同材料物性所定流道尺寸標準 可靠資料來源
經驗 材料供應商 參考書
典型寬廣範圍
流道尺度規格
設計出發點 流道長度 材料黏度 產品所需要的壓力 如果沒有做流道分析,通常流道尺寸往往比實 際需求更大 材料 成型時間 錢!!
Lesson 14
澆口及流道設計
澆口形式
手動整理澆口
自動脫模澆口
Edge Tab Sprue Diaphragm Ring Fan Flash
Submarine Cashew Pin Hot drop Valve
邊緣澆口(Edge Gate)
普通常用的手動整理澆口形式 約為產品厚度 50% ~ 75% 可能是固定厚度或者逐漸減少厚度
流道建立範例
Wear cap
多模穴複製精靈(Cavity duplication wizard) 流道建立精靈(Runner Creation Wizard) 多模穴複製 手動建立流道系統 使用形狀因子建立對稱形多模穴模具
Snap cover
建立Wear Cap 工具
打開Wear Cap檔案
重複計算欄列
Look for
將時間和壓力的不 平衡性變得更小值
Time Convergence Tolerance Pressure Convergence Tolerance
3.0000 % 2.0000 MPa
Iteration Time Imbalance Pressure Imbalance (%) (MPa) 1 3.5262 18.4370 2 1.4612 6.1110 3 1.0999 2.0560 4 0.4596 1.3920
Flow channel
Gate geometry varies widely depending on drop style and usage
閥澆口(Valve Gate)
與熱澆道類似, 但是由一個銷釘關閉這個澆口孔口 在週期期間銷釘能夠控制不同時間之開與關 模型建立使用Beams
Diameter mm inch PET 3.0-8.0 1/8-5/16 Polyethylene 2.0-10.0 1/16-3/8 Polypropylene 5.0-10.0 3/16-3/8 Polystyrene 3.0-10 1/8-3/8 PVC 6.0-16 1/4-5/8 Material
NOTE: 預設流道系統精 靈設定為潛伏式澆口,如要 建立邊緣澆口則必須將分 模面設定在澆口平面為零, 下一步驟必須設定正確之 尺寸與形式
澆口設定
將澆口區域放大，按右鍵選擇屬性功能，設定 形狀因子與尺寸
建立 Snap Cover 工具打開Snap Cover
指定澆口位置
手動建立流道系統與多模穴複製 設定形狀因子與建立 對稱形多模穴模具
執行保壓分析此時可用內定保壓設定模式 設定開關在回到自動設定
QUESTIONS?
Gate Land
環形澆口(Ring Gate)
看似隔膜澆口但是在產品的外圍 不建議
難獲得均勻流動性
模型建立是由薄殼及Beams組成
扇形澆口(Fan Gate)
寬闊的邊緣澆口 平衡流動波前平穩進入產品 模型建立是由薄殼及Beams組成
薄膜澆口(Flash Gate)
類似環形與扇形澆口 故意設計流動波前平行進入產品
決定壓力平衡
使用充填分析結果
設定分析壓力切換點在100%
平衡壓力決定流道的尺寸 觀看注射點位置壓力
壓力是由開始點到充滿模穴末端止 • 如果注射位置壓力陳現巨大起伏，或許使用壓 力平衡可以降低充填所需壓力
較高的平衡壓力將減少體積,但是或許會使得 流道變的太小
入口壓力vs.時間
膠口入口點壓力曲線分佈圖,F/P切換點100%
建立Beams
流道有9個有限元素 設定正確的形狀因子, 尺寸與Occ數目(4)
Note: Beams can be created 2 ways, by first creating regions then meshing, or by creating an end node(s) then creating the beams directly. The first method is best for tapered geometry so each element will be the correct size.
Valve pin
直接澆口(Elements in a Gate)
澆口至少要有三個元素才能精確預測
澆口凝固時間 剪切率
壓力
澆口尺寸
澆口尺寸將會影響剪切率大小值 剪切率指引可在材料資料庫中發現
澆口尺寸
保持澆口剪切率在材料物性極限以下 如果澆口尺寸允許,剪切率最好控制在 20,000 1/sec. 大的澆口較容易降低剪切率,如邊緣澆口 、扇形澆口、薄膜澆口 香蕉形澆口與熱澆道加工較困難 不可能就針點澆口
指定產品形狀因子與建立對稱形多模穴
選擇整個產品 按滑鼠右鍵 > Properties 在表列將所有屬性形狀因子(Occurence)設定為4
建立澆口
放大塑膠入口點區域 刪除塑膠入口點 建立澆口曲線
Relative 0, -3.175, –3.175 設定建立冷流道澆口 • 圓形, 1 mm 25º • Occ 4
指定澆口位置
使用多模穴複製精靈 使用流道系統精靈
Gate
模穴複製
一模八穴 兩列
行間隔調節50 列間隔調節60
建構流道
定立豎膠道位置 以澆口面建立產品分模面
將使用邊緣澆口
流道建立
輸入豎膠道資料
現行豎膠道設定是DME標準採 用,可自訂修改
輸入流道資料
流道建立
輸入澆口資訊
難以達成
不建議 模型建立是由薄殼及Beams組成
潛伏式澆口(Submarine Gate)
圓錐形澆口, 與分模線以下的產品相交 典型常用 入口直徑約為平均厚度25% ~ 75%
Parting Line
香蕉形澆口(Cashew Gate)
彎曲潛入式澆口 加工困難
針點式澆口(Pin Gate)
這個充填平衡足 夠好嗎?
這結果獲得3% 的時間不平 衡性與2%的壓力不平衡性
修改流道尺寸
在案例中如執行流道平衡分析，將會自動修改流道 尺寸且會在分析子目錄後面註解(runner balance)
檢查平衡時的保壓
體積收縮在兩模穴間應該均勻的. 這將指示出 流道系統是否設計的太小.
練習
Wear cap,建立流道系統
複製模型
選擇整個模型 轉換