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LM2578AM资料

LM2578A/LM3578A Switching RegulatorGeneral DescriptionThe LM2578A is a switching regulator which can easily be set up for such DC-to-DC voltage conversion circuits as the buck,boost,and inverting configurations.The LM2578A fea-tures a unique comparator input stage which not only has separate pins for both the inverting and non-inverting inputs, but also provides an internal1.0V reference to each input, thereby simplifying circuit design and p.c.board layout.The output can switch up to750mA and has output pins for its collector and emitter to promote design flexibility.An external current limit terminal may be referenced to either the ground or the V in terminal,depending upon the application.In addi-tion,the LM2578A has an on board oscillator,which sets the switching frequency with a single external capacitor from<1 Hz to100kHz(typical).The LM2578A is an improved version of the LM2578,offer-ing higher maximum ratings for the total supply voltage and output transistor emitter and collector voltages.Featuresn Inverting and non-inverting feedback inputsn 1.0V reference at inputsn Operates from supply voltages of2V to40Vn Output current up to750mA,saturation less than0.9V n Current limit and thermal shut downn Duty cycle up to90%Applicationsn Switching regulators in buck,boost,inverting,and single-ended transformer configurationsn Motor speed controln Lamp flasherConnection Diagram and Ordering InformationDual-In-Line Package00871129Order Number LM3578AM,LM2578AN or LM3578ANSee NS Package Number M08A or N08E February2005LM2578A/LM3578A Switching Regulator©2005National Semiconductor Corporation Functional Diagram00871101L M 2578A /L M 3578A 2Absolute Maximum Ratings(Note1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.Total Supply Voltage50V Collector Output to Ground−0.3V to+50V Emitter Output to Ground(Note2)−1V to+50V Power Dissipation(Note3)Internally limited Output Current750mA Storage Temperature−65˚C to+150˚C Lead Temperature(soldering,10seconds)260˚C Maximum Junction Temperature150˚CESD Tolerance(Note4)2kVOperating RatingsAmbient Temperature RangeLM2578A−40˚C≤T A≤+85˚C LM3578A0˚C≤T A≤+70˚C Junction Temperature RangeLM2578A−40˚C≤T J≤+125˚C LM3578A0˚C≤T J≤+125˚CElectrical CharacteristicsThese specifications apply for2V≤V IN≤40V(2.2V≤V IN≤40V for T J≤−25˚C),timing capacitor C T=3900pF,and25%≤duty cycle≤75%,unless otherwise specified.Values in standard typeface are for T J=25˚C;values in boldface type apply for operation over the specified operating junction temperature range.LM2578A/Symbol Parameter Conditions Typical LM3578A Units(Note5)Limit(Note6) OSCILLATORf OSC Frequency20kHz24kHz(max)16kHz(min)∆f OSC/∆T Frequency Drift with Temperature−0.13%/˚C Amplitude550mV p-p REFERENCE/COMPARATOR(Note7)V R Input Reference I1=I2=0mA and 1.0V Voltage I1=I2=1mA±1%(Note8) 1.050/1.070V(max)0.950/0.930V(min)∆V R/∆V IN Input Reference Voltage LineRegulationI1=I2=0mA and0.003%/VI1=I2=1mA±1%(Note8)0.01/0.02%/V(max) I INV Inverting Input Current I1=I2=0mA,duty cycle=25%0.5µALevel Shift Accuracy Level Shift Current=1mA 1.0%10/13%(max)∆V R/∆t Input Reference Voltage Long TermStability100ppm/1000h OUTPUTV C(sat)Collector Saturation Voltage I C=750mA pulsed,Emittergrounded 0.7V0.90/1.2V(max)V E(sat)Emitter Saturation Voltage I O=80mA pulsed, 1.4VV IN=V C=40V 1.7/2.0V(max)I CES Collector Leakage Current V IN=V CE=40V,Emitter grounded,Output OFF 0.1µA200/250µA(max)BV CEO(SUS)Collector-Emitter Sustaining Voltage I SUST=0.2A(pulsed),V IN=060V50V(min) CURRENT LIMITV CL Sense Voltage Shutdown Level Referred to V IN or Ground110mV(Note9)80mV(min)160mV(max)LM2578A/LM3578A3Electrical Characteristics(Continued)These specifications apply for 2V ≤V IN ≤40V (2.2V ≤V IN ≤40V for T J ≤−25˚C),timing capacitor C T =3900pF,and 25%≤duty cycle ≤75%,unless otherwise specified.Values in standard typeface are for T J =25˚C;values in boldface type apply for operation over the specified operating junction temperature range.LM2578A/Symbol ParameterConditionsTypical LM3578A Units(Note 5)Limit (Note 6)CURRENT LIMIT ∆V CL /∆T Sense Voltage Temperature Drift 0.3%/˚C I CLSense Bias CurrentReferred to V IN 4.0µA Referred to ground0.4µA DEVICE POWER CONSUMPTION I SSupply CurrentOutput OFF,V E =0V2.0mA3.5/4.0mA (max)Output ON,I C =750mA pulsed,14mAV E =0VNote 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.DC and AC electrical specifications do not apply when operating the device beyond its rated operating conditions.Note 2:For T J ≥100˚C,the Emitter pin voltage should not be driven more than 0.6V below ground (see Application Information).Note 3:At elevated temperatures,devices must be derated based on package thermal resistance.The device in the 8-pin DIP must be derated at 95˚C/W,junction to ambient.The device in the surface-mount package must be derated at 150˚C/W,junction-to-ambient.Note 4:Human body model,1.5k Ωin series with 100pF.Note 5:Typical values are for T J =25˚C and represent the most likely parametric norm.Note 6:All limits guaranteed at room temperature (standard type face)and at temperature extremes (bold type face).Room temperature limits are 100%production tested.Limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC)methods.All limits are used to calculate AOQL.Note 7:Input terminals are protected from accidental shorts to ground but if external voltages higher than the reference voltage are applied,excessive current will flow and should be limited to less than 5mA.Note 8:I 1and I 2are the external sink currents at the inputs (refer to Test Circuit).Note 9:Connection of a 10k Ωresistor from pin 1to pin 4will drive the duty cycle to its maximum,typically 90%.Applying the minimum Current Limit Sense Voltage to pin 7will not reduce the duty cycle to less than 50%.Applying the maximum Current Limit Sense Voltage to pin 7is certain to reduce the duty cycle below 50%.Increasing this voltage by 15mV may be required to reduce the duty cycle to 0%,when the Collector output swing is 40V or greater (see Ground-Referred Current Limit Sense Voltage typical curve).Typical Performance CharacteristicsOscillator Frequency Changewith TemperatureOscillator Voltage Swing0087113200871133L M 2578A /L M 3578A 4Typical Performance Characteristics(Continued)Input Reference Voltage Drift with TemperatureCollector Saturation Voltage(Sinking Current,Emitter Grounded)0087113400871135Emitter Saturation Voltage(Sourcing Current,Collector at V in )Ground ReferredCurrent Limit Sense Voltage0087113600871137Current Limit Sense Voltage Drift with Temperature Current Limit Response Time for Various Over Drives0087113800871139LM2578A/LM3578A5Typical Performance Characteristics(Continued)Current Limit Sense Voltagevs Supply VoltageSupply Current0087114000871141Supply CurrentCollector Current with Emitter Output Below Ground0087114200871143Test Circuit*Parameter tests can be made using the test circuit shown.Select the desired V in ,collector voltage and duty cycle with adjustable power supplies.A digital volt meter with an input resistance greater than 100M Ωshould be used to measure the following:Input Reference Voltage to Ground;S1in either position.Level Shift Accuracy (%)=(T P3(V)/1V)x 100%;S1at I 1=I 2=1mAInput Current (mA)=(1V −T p3(V))/1M Ω:S1at I 1=I 2=0mA.Oscillator parameters can be measured at T p4using a fre-quency counter or an oscilloscope.The Current Limit Sense Voltage is measured by connecting an adjustable 0-to-1V floating power supply in series with the current limit terminal and referring it to either the ground or the V in terminal.Set the duty cycle to 90%and monitor test point T P5while adjusting the floating power supply voltage until the LM2578A’s duty cycle just reaches 0%.This voltage is the Current Limit Sense Voltage.The Supply Current should be measured with the duty cycle at 0%and S1in the I 1=I 2=0mA position.*LM2578A specifications are measured using automated test equipment.This circuit is provided for the customer’s convenience when checking parameters.Due to possible variations in testing conditions,the measured values from these testing procedures may not match those of the factory.L M 2578A /L M 3578A 6Test Circuit*(Continued)00871103 Op amp supplies are±15VDVM input resistance>100MΩ*LM2578max duty cycle is90%Definition of TermsInput Reference Voltage:The voltage(referred to ground) that must be applied to either the inverting or non-inverting input to cause the regulator switch to change state(ON or OFF).Input Reference Current:The current that must be drawn from either the inverting or non-inverting input to cause the regulator switch to change state(ON or OFF).Input Level Shift Accuracy:This specification determines the output voltage tolerance of a regulator whose output control depends on drawing equal currents from the inverting and non-inverting inputs(see the Inverting Regulator of Fig-ure21,and the RS-232Line Driver Power Supply of Figure 23).Level Shift Accuracy is tested by using two equal-value resistors to draw current from the inverting and non-inverting input terminals,then measuring the percentage difference in the voltages across the resistors that produces a controlled duty cycle at the switch output.Collector Saturation Voltage:With the inverting input ter-minal grounded thru a10kΩresistor and the output transis-tor’s emitter connected to ground,the Collector Saturation-Voltage is the collector-to-emitter voltage for a given collector current.Emitter Saturation Voltage:With the inverting input termi-nal grounded thru a10kΩresistor and the output transistor’s collector connected to V in,the Emitter Saturation Voltage is the collector-to-emitter voltage for a given emitter current. Collector Emitter Sustaining Voltage:The collector-emitter breakdown voltage of the output transistor,mea-sured at a specified current.Current Limit Sense Voltage:The voltage at the CurrentLimit pin,referred to either the supply or the ground terminal,which(via logic circuitry)will cause the output transistor toturn OFF and resets cycle-by-cycle at the oscillator fre-quency.Current Limit Sense Current:The bias current for theCurrent Limit terminal with the applied voltage equal to theCurrent Limit Sense Voltage.Supply Current:The IC power supply current,excluding thecurrent drawn through the output transistor,with the oscilla-tor operating.Functional DescriptionThe LM2578A is a pulse-width modulator designed for useas a switching regulator controller.It may also be used inother applications which require controlled pulse-width volt-age drive.A control signal,usually representing output voltage,fed intothe LM2578A’s comparator is compared with an internally-generated reference.The resulting error signal and the os-cillator’s output are fed to a logic network which determineswhen the output transistor will be turned ON or OFF.Thefollowing is a brief description of the subsections of theLM2578A.COMPARATOR INPUT STAGEThe LM2578A’s comparator input stage is unique in that boththe inverting and non-inverting inputs are available to theuser,and both contain a1.0V reference.This is accom-plished as follows:A1.0V reference is fed into a modifiedvoltage follower circuit(see FUNCTIONAL DIAGRAM).When both input pins are open,no current flows through R1LM2578A/LM3578A7Functional Description(Continued)and R2.Thus,both inputs to the comparator will have the potential of the 1.0V reference,V A .When one input,for example the non-inverting input,is pulled ∆V away from V A ,a current of ∆V/R1will flow through R1.This same current flows through R2,and the comparator sees a total voltage of 2∆V between its inputs.The high gain of the system,through feedback,will correct for this imbalance and return both inputs to the 1.0V level.This unusual comparator input stage increases circuit flex-ibility,while minimizing the total number of external compo-nents required for a voltage regulator system.The inverting switching regulator configuration,for example,can be set up without having to use an external op amp for feedback polarity reversal (see TYPICAL APPLICATIONS).OSCILLATORThe LM2578A provides an on-board oscillator which can be adjusted up to 100kHz.Its frequency is set by a single external capacitor,C 1,as shown in Figure 1,and follows the equationf OSC =8x10−5/C 1The oscillator provides a blanking pulse to limit maximum duty cycle to 90%,and a reset pulse to the internal circuitry.OUTPUT TRANSISTORThe output transistor is capable of delivering up to 750mA with a saturation voltage of less than 0.9V.(see Collector Saturation Voltage and Emitter Saturation Voltage curves).The emitter must not be pulled more than 1V below ground (this limit is 0.6V for T J ≥100˚C).Because of this limit,an external transistor must be used to develop negative output voltages (see the Inverting Regulator Typical Application).Other configurations may need protection against violation of this limit (see the Emitter Output section of the Applica-tions Information).CURRENT LIMITThe LM2578A’s current limit may be referenced to either the ground or the V in pins,and operates on a cycle-by-cycle basis.The current limit section consists of two comparators:one with its non-inverting input referenced to a voltage 110mV below V in ,the other with its inverting input referenced110mV above ground (see FUNCTIONAL DIAGRAM).The current limit is activated whenever the current limit terminal is pulled 110mV away from either V in or ground.Applications InformationCURRENT LIMITAs mentioned in the functional description,the current limit terminal may be referenced to either the V in or the ground terminal.Resistor R3converts the current to be sensed into a voltage for current limit detection.CURRENT LIMIT TRANSIENT SUPPRESSIONWhen noise spikes and switching transients interfere with proper current limit operation,R1and C1act together as a low pass filter to control the current limit circuitry’s response time.Because the sense current of the current limit terminal varies according to where it is referenced,R1should be less than 2k Ωwhen referenced to ground,and less than 100Ωwhen referenced to V in .00871104FIGURE 1.Value of Timing Capacitor vsOscillator Frequency00871115FIGURE 2.Current Limit,Ground Referred00871116FIGURE 3.Current Limit,V in ReferredL M 2578A /L M 3578A 8Applications Information(Continued)C.L.SENSE VOLTAGE MULTIPLICATIONWhen a larger sense resistor value is desired,the voltage divider network,consisting of R1and R2,may be used.This effectively multiplies the sense voltage by(1+R1/R2).Also, R1can be replaced by a diode to increase current limit sense voltage to about800mV(diode V f+110mV).UNDER-VOLTAGE LOCKOUTUnder-voltage lockout is accomplished with few external components.When V in becomes lower than the zener breakdown voltage,the output transistor is turned off.This occurs because diode D1will then become forward biased, allowing resistor R3to sink a greater current from the non-inverting input than is sunk by the parallel combination of R1 and R2at the inverting terminal.R3should be one-fifth of the value of R1and R2in parallel.MAXIMUM DUTY CYCLE LIMITINGThe maximum duty cycle can be externally limited by adjust-ing the charge to discharge ratio of the oscillator capacitor with a single external resistor.Typical values are50µA for the charge current,450µA for the discharge current,and a voltage swing from200mV to750mV.Therefore,R1is selected for the desired charging and discharging slopes and C1is readjusted to set the oscillator frequency.00871117 FIGURE4.Current Limit Transient Suppressor,Ground Referred00871118 FIGURE5.Current Limit Transient Suppressor,V in Referred00871119 FIGURE6.Current Limit Sense Voltage Multiplication,Ground Referred00871120FIGURE7.Current Limit Sense Voltage Multiplication,V in Referred00871122FIGURE8.Under-Voltage LockoutLM2578A/LM3578A9Applications Information(Continued)DUTY CYCLE ADJUSTMENTWhen manual or mechanical selection of the output transis-tor’s duty cycle is needed,the cirucit shown below may be used.The output will turn on with the beginning of each oscillator cycle and turn off when the current sunk by R2and R3from the non-inverting terminal becomes greater than the current sunk from the inverting terminal.With the resistor values as shown,R3can be used to adjust the duty cycle from 0%to 90%.When the sum of R2and R3is twice the value of R1,the duty cycle will be about 50%.C1may be a large electrolytic capacitor to lower the oscillator frequency below 1Hz.REMOTE SHUTDOWNThe LM2578A may be remotely shutdown by sinking a greater current from the non-inverting input than from the inverting input.This may be accomplished by selecting re-sistor R3to be approximately one-half the value of R1and R2in parallel.EMITTER OUTPUTWhen the LM2578A output transistor is in the OFF state,if the Emitter output swings below the ground pin voltage,the output transistor will turn ON because its base is clamped near ground.The Collector Current with Emitter Output Be-low Ground curve shows the amount of Collector current drawn in this mode,vs temperature and Emitter voltage.When the Collector-Emitter voltage is high,this current will cause high power dissipation in the output transistor and should be avoided.This situation can occur in the high-current high-voltage buck application if the Emitter output is used and the catch diode’s forward voltage drop is greater than 0.6V.A fast-recovery diode can be added in series with the Emitter output to counter the forward voltage drop of the catch diode (see Figure 2).For better efficiency of a high output current buck regulator,an external PNP transistor should be used as shown in Figure 16.SYNCHRONIZING DEVICESWhen several devices are to be operated at once,their oscillators may be synchronized by the application of an external signal.This drive signal should be a pulse waveform with a minimum pulse width of 2µs.and an amplitude from00871121FIGURE 9.Maximum Duty Cycle Limiting00871123FIGURE 10.Duty Cycle Adjustment00871124FIGURE 11.Shutdown Occurs when V L is High00871130FIGURE 12.D1Prevents Output Transistor from Improperly Turning ON due to D2’s Forward Voltage L M 2578A /L M 3578A 10Applications Information(Continued)1.5V to2.0V.The signal source must be capable of 1.)driving capacitive loads and 2.)delivering up to 500µA for each LM2578A.Capacitors C1thru CN are to be selected for a 20%slower frequency than the synchronization frequency.Typical ApplicationsThe LM2578A may be operated in either the continuous or the discontinuous conduction mode.The following applica-tions (except for the Buck-Boost Regulator)are designed for continuous conduction operation.That is,the inductor cur-rent is not allowed to fall to zero.This mode of operation has higher efficiency and lower EMI characteristics than the dis-continuous mode.BUCK REGULATORThe buck configuration is used to step an input voltage down to a lower level.Transistor Q1in Figure 14chops the input DC voltage into a squarewave.This squarewave is then converted back into a DC voltage of lower magnitude by the low pass filter consisting of L1and C1.The duty cycle,D,of the squarewave relates the output voltage to the input volt-age by the following equation:V out =D x V in =V in x (t on )/(t on +t off ).Figure 15is a 15V to 5V buck regulator with an output current,I o ,of 350mA.The circuit becomes discontinuous at 20%of I o(max),has 10mV of output voltage ripple,an effi-ciency of 75%,a load regulation of 30mV (70mA to 350mA)and a line regulation of 10mV (12≤V in ≤18V).Component values are selected as follows:R1=(V o −1)x R2where R2=10k ΩR3=V/I sw(max)R3=0.15Ωwhere:V is the current limit sense voltage,0.11VI sw(max)is the maximum allowable current thru the output transistor.L1is the inductor and may be found from the inductance calculation chart (Figure 16)as follows:Given V in =15VV o =5VI o(max)=350mA f OSC =50kHzDiscontinuous at 20%of I o(max).Note that since the circuit will become discontinuous at 20%of I o(max),the load current must not be allowed to fall below 70mA.00871125FIGURE 13.Synchronizing Devices00871105FIGURE 14.Basic Buck RegulatorLM2578A/LM3578A11Typical Applications(Continued)00871106V in =15V R3=0.15ΩV o =5V C1=1820pF V ripple =10mV C2=220µF I o =350mA C3=20pF f osc =50kHz L1=470µH R1=40k ΩD1=1N5818R2=10k ΩFIGURE 15.Buck or Step-Down RegulatorL M 2578A /L M 3578A 12LM2578A/LM3578A Typical Applications(Continued)00871131FIGURE16.DC/DC Inductance Calculator13Typical Applications(Continued)Step 1:Calculate the maximum DC current through the inductor,I L(max).The necessary equations are indicated at the top of the chart and show that I L(max)=I o(max)for the buck configuration.Thus,I L(max)=350mA.Step 2:Calculate the inductor Volts-sec product,E-T op ,according to the equations given from the chart.For the Buck:E-T op =(V in −V o )(V o /V in )(1000/f osc )=(15−5)(5/15)(1000/50)=66V-µs.with the oscillator frequency,f osc ,expressed in kHz.Step 3:Using the graph with axis labeled “Discontinuous At %I OUT ”and “I L(max,DC)”find the point where the desired maximum inductor current,I L(max,DC)intercepts the desired discontinuity percentage.In this example,the point of interest is where the 0.35A line intersects with the 20%line.This is nearly the midpoint of the horizontal axis.Step 4:This last step is merely the translation of the point found in Step 3to the graph directly below it.This is accom-plished by moving straight down the page to the point which intercepts the desired E-T op .For this example,E-T op is 66V-µs and the desired inductor value is 470µH.Since this example was for 20%discontinuity,the bottom chart could have been used directly,as noted in step 3of the chart instructions.For a full line of standard inductor values,contact Pulse Engineering (San Diego,Calif.)regarding their PE526XX series,or A.I.E.Magnetics (Nashville,Tenn.).A more precise inductance value may be calculated for the Buck,Boost and Inverting Regulators as follows:BUCKL =V o (V in −V o )/(∆I L V in f osc )BOOSTL =V in (V o −V in )/(∆I L f osc V o )INVERTL =V in |V o |/[∆I L (V in +|V o |)f osc ]where ∆I L is the current ripple through the inductor.∆I L is usually chosen based on the minimum load current expected of the circuit.For the buck regulator,since the inductor current I L equals the load current I O ,∆I L =2•I O(min)∆I L =140mA for this circuit.∆I L can also be interpreted as ∆I L =2•(Discontinuity Factor)•I Lwhere the Discontinuity Factor is the ratio of the minimum load current to the maximum load current.For this example,the Discontinuity Factor is 0.2.The remainder of the components of Figure 15are chosen as follows:C1is the timing capacitor found in Figure 1.C2≥V o (V in −V o )/(8f osc 2V in V ripple L1)where V ripple is the peak-to-peak output voltage ripple.C3is necessary for continuous operation and is generally in the 10pF to 30pF range.D1should be a Schottky type diode,such as the 1N5818or 1N5819.BUCK WITH BOOSTED OUTPUT CURRENTFor applications requiring a large output current,an external transistor may be used as shown in Figure 17.This circuit steps a 15V supply down to 5V with 1.5A of output current.The output ripple is 50mV,with an efficiency of 80%,a load regulation of 40mV (150mA to 1.5A),and a line regulation of 20mV (12V ≤V in ≤18V).Component values are selected as outlined for the buck regulator with a discontinuity factor of 10%,with the addition of R4and R5:R4=10V BE1B f /I pR5=(V in −V −V BE1−V sat )B f /(I L(max,DC)+I R4)where:V BE1is the V BE of transistor Q1.V sat is the saturation voltage of the LM2578A output transis-tor.V is the current limit sense voltage.B f is the forced current gain of transistor Q1(B f =30for Figure 17).I R4=V BE1/R4I p =I L(max,DC)+0.5∆I LL M 2578A /L M 3578A 14Typical Applications(Continued)BOOST REGULATORThe boost regulator converts a low input voltage into a higher output voltage.The basic configuration is shown in Figure 18.Energy is stored in the inductor while the transis-tor is on and then transferred with the input voltage to the output capacitor for filtering when the transistor is off.Thus,V o =V in +V in (t on /t off ).The circuit of Figure 19converts a 5V supply into a 15V supply with 150mA of output current,a load regulation of 14mV (30mA to 140mA),and a line regulation of 35mV (4.5V ≤V in ≤8.5V).R1=(V o −1)R2where R2=10k Ω.R3=V/(I L(max,DC)+0.5∆I L )where:∆I L =2(I LOAD(min))(V o /V in )∆I L is 200mA in this example.R4,C3and C4are necessary for continuous operation and are typically 220k Ω,20pF,and 0.0022µF respectively.C1is the timing capacitor found in Figure 1.C2≥I o (V o −V in )/(f osc V o V ripple ).00871108V in =15V R4=200ΩV o =5V R5=330ΩV ripple =50mV C1=1820pF I o =1.5AC2=330µFf osc =50kHz C3=20pF R1=40k ΩL1=220µH R2=10k ΩD1=1N5819R3=0.05ΩQ1=D45FIGURE 17.Buck Converter with Boosted Output Current00871109FIGURE 18.Basic Boost Regulator00871111V in =5V R4=200k ΩV o =15V C1=1820pF V ripple =10mV C2=470µF I o =140mA C3=20pF f osc =50kHz C4=0.0022µF R1=140k ΩL1=330µH R2=10k ΩD1=1N5818R3=0.15ΩFIGURE 19.Boost or Step-Up RegulatorLM2578A/LM3578A15Typical Applications(Continued)D1is a Schottky type diode such as a 1N5818or 1N5819.L1is found as described in the buck converter section,using the inductance chart for Figure 16for the boost configuration and 20%discontinuity.INVERTING REGULATORFigure 20shows the basic configuration for an inverting regulator.The input voltage is of a positive polarity,but the output is negative.The output may be less than,equal to,or greater in magnitude than the input.The relationship be-tween the magnitude of the input voltage and the output voltage is V o =V in x (t on /t off ).Figure 21shows an LM2578A configured as a 5V to −15V polarity inverter with an output current of 300mA,a load regulation of 44mV (60mA to 300mA)and a line regulation of 50mV (4.5V ≤V in ≤8.5V).R1=(|V o |+1)R2where R2=10k Ω.R3=V/(I L(max,DC)+0.5∆I L ).R4=10V BE1B f /(I L (max,DC)+0.5∆I L )where:V,V BE1,V sat ,and B f are defined in the “Buck Converter with Boosted Output Current”section.∆I L =2(I LOAD(min))(V in +|V o |)/V INR5is defined in the “Buck with Boosted Output Current”section.R6serves the same purpose as R4in the Boost Regulator circuit and is typically 220k Ω.C1,C3and C4are defined in the “Boost Regulator”section.C2≥I o |V o |/[f osc (|V o |+V in )V ripple ]L1is found as outlined in the section on buck converters,using the inductance chart of Figure 16for the invert con-figuration and 20%discontinuity.BUCK-BOOST REGULATORThe Buck-Boost Regulator,shown in Figure 22,may step a voltage up or down,depending upon whether or not the desired output voltage is greater or less than the input voltage.In this case,the output voltage is 12V with an input voltage from 9V to 15V.The circuit exhibits an efficiency of 75%,with a load regulation of 60mV (10mA to 100mA)and a line regulation of 52mV.R1=(V o −1)R2where R2=10k ΩR3=V/0.75AR4,C1,C3and C4are defined in the “Boost Regulator”section.D1and D2are Schottky type diodes such as the 1N5818or 1N5819.where:V d is the forward voltage drop of the diodes.V sat is the saturation voltage of the LM2578A output transis-tor.V sat1is the saturation voltage of transistor Q1.L1≥(V in −V sat −V sat1)(t on /I p )00871110FIGURE 20.Basic Inverting Regulator00871112V in =5V R4=190ΩV o =−15V R5=82ΩV ripple =5mV R6=220k ΩI o =300mA C1=1820pF I min =60mAC2=1000µFf osc =50kHz C3=20pF R1=160k ΩC4=0.0022µF R2=10k ΩL1=150µH R3=0.01ΩD1=1N5818FIGURE 21.Inverting RegulatorL M 2578A /L M 3578A16。

富士通 FLM7785-4F 说明书

Fujitsu recommends the following conditions for the reliable operation of GaAs FETs:1. The drain-source operating voltage (V DS ) should not exceed 10 volts.2. The forward and reverse gate currents should not exceed 16.0 and -2.2 mA respectively with gate resistance of 100Ω.G.C.P.: Gain Compression Point, S.C.L.: Single Carrier LevelDESCRIPTIONThe FLM7785-4F is a power GaAs FET that is internally matched for standard communication bands to provide optimum power and gain in a 50 ohm system.Eudyna’s stringent Quality Assurance Program assures the highest reliability and consistent performance.FEATURES• High Output Power:P 1dB = 36.5dBm (Typ.)• High Gain:G 1dB = 8.5dB (Typ.)• High PAE:ηadd = 35% (Typ.)• Low IM 3= -46dBc@Po = 25.5dBm • Broad Band:7.7 ~ 8.5GHz• Impedance Matched Zin/Zout = 50Ω• Hermetically SealedPOWER DERATING CURVE122430186050100150200Case Temperature (°C)T o t a l P o w e r D i s s i p a t i o n (W)OUTPUT POWER & IM 3 vs. INPUT POWERV DS =10V f 1= 8.5 GHz f 2 = 8.51 GHz 2-tone test121416182022Input Power (S.C.L.) (dBm)S.C.L.: Single Carrier Level21232527293133-50-40-30-20-10O u t p u t P o w e r (S .C .L .) (d B m )IM 3P outI M 3 (d B c )OUTPUT POWER vs. FREQUENCYPin=28.5dBm26.5dBm24.5dBm22.5dBm7.97.78.18.38.5Frequency (GHz)343536373833O u t p u t P o w e r (d B m )V DS =10V P1dBV DS =10V f = 8.1 GHzOUTPUT POWER vs. INPUT POWER18202224262830Input Power (dBm)343638323028304515O u t p u t P o w e r (d B m )ηaddP outηa d d (%)S-PARAMETERSV DS = 10V , I DS = 1100mAFREQUENCY S11S21S12S22(MHZ)MAG ANG MAG ANG MAG ANG MAG ANG 7500.711120.0 3.482-74.8.025-92.7.478147.97600.694109.7 3.441-86.9.031-113.4.490133.67700.67299.8 3.396-98.7.037-131.2.507120.77800.64890.0 3.354-110.3.043-143.4.525109.97900.62180.2 3.331-121.7.049-157.1.53599.88000.59170.2 3.319-133.1.055-170.0.54190.78100.55759.3 3.344-144.8.061178.8.54282.68200.51647.3 3.377-156.5.067166.5.53974.98300.47033.5 3.444-168.7.074154.9.52567.58400.41416.0 3.540178.2.080141.7.49659.78500.356-7.7 3.625163.9.089128.6.44952.98600.308-40.8 3.704148.3.097113.5.38046.98700.307-83.13.723131.3.10197.4.28243.10-j50S 0°S 21S 12Eudyna Devices Inc. products contain gallium arsenide(GaAs) which can be hazardous to the human body and the environment. For safety, observe the following procedures:CAUTION• Do not put this product into the mouth.• Do not alter the form of this product into a gas, powder, or liquidthrough burning, crushing, or chemical processing as these by-products are dangerous to the human body if inhaled, ingested, or swallowed.• Observe government laws and company regulations when discarding this product. This product must be discarded in accordance with methods specified by applicable hazardous waste procedures.For further information please contact:Eudyna Devices USA Inc.2355 Zanker Rd.San Jose, CA 95131-1138, U.S.A.TEL:(408) 232-9500FAX:(408) 428-9111Eudyna Devices Europe Ltd.Network House Norreys DriveMaidenhead, Berkshire SL6 4FJ United KingdomTEL:+44 (0) 1628 504800FAX:+44 (0) 1628 504888Eudyna Devices Asia Pte Ltd.Hong Kong BranchRm.1101, Ocean Centre, 5 Canton Rd.Tsim Sha Tsui, Kowloon, Hong Kong TEL:+852-2377-0227FAX:+852-2377-3921Eudyna Devices Inc.Sales Division1, Kanai-cho, Sakae-kuY okohama, 244-0845, Japan TEL:+81-45-853-8156FAX:+81-45-853-8170Eudyna Devices Inc.reserves the right to change products and specifications without notice.The information does not convey any license under rights of Eudyna Devices Inc.or others.©2004 Eudyna Devices USA Inc.Printed in U.S.A.。

TMS320C6655 57产品预览信息说明书

TMS320C6655/57Fixed and Floating-Point Digital Signal Processor Data ManualPRODUCT PREVIEW information applies to products in theformative or design phase of development. Characteristic dataand other specifications are design goals. Texas Instrumentsreserves the right to change or discontinue these productswithout notice.Literature Number:SPRS814March 2012SPRS814—March 2012Data Manual TMS320C6655/57Release HistoryFor detailed revision information, see ‘‘Revision History’’ on page A-226.RevisionDate Description/Comments SPRS841 March 2012Initial releaseFixed and Floating-Point Digital Signal ProcessorSPRS814—March 2012TMS320C6655/ Contents1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131.1KeyStone Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141.2Device Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141.3Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172.1Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172.2DSP Core Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182.3Memory Map Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212.4Boot Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252.5Boot Modes Supported and PLL Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252.5.1Boot Device Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262.5.2Device Configuration Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262.5.3PLL Boot Configuration Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332.6Second-Level Bootloaders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332.7Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .342.7.1Package Terminals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .342.7.2Pin Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .342.8Terminal Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .392.9Development and Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .632.9.1Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .632.9.2Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .632.10Related Documentation from Texas Instruments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .653Device Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .663.1Device Configuration at Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .663.2Peripheral Selection After Device Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .673.3Device State Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .673.3.1Device Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .703.3.2Device Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .713.3.3JTAG ID (JTAGID) Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .723.3.4Kicker Mechanism (KICK0 and KICK1) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .723.3.5LRESETNMI PIN Status (LRSTNMIPINSTAT) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .723.3.6LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .733.3.7Reset Status (RESET_STAT) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .743.3.8Reset Status Clear (RESET_STAT_CLR) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .753.3.9Boot Complete (BOOTCOMPLETE) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .753.3.10Power State Control (PWRSTATECTL) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .763.3.11NMI Event Generation to CorePac (NMIGRx) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .763.3.12IPC Generation (IPCGRx) Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .773.3.13IPC Acknowledgement (IPCARx) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .783.3.14IPC Generation Host (IPCGRH) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .783.3.15IPC Acknowledgement Host (IPCARH) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .793.3.16Timer Input Selection Register (TINPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .803.3.17Timer Output Selection Register (TOUTPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .823.3.18Reset Mux (RSTMUXx) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .833.3.19Device Speed (DEVSPEED) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .843.3.20Pin Control 0 (PIN_CONTROL_0) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .843.3.21Pin Control 1 (PIN_CONTROL_1) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .863.3.22UPP Clock Source (UPP_CLOCK) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .863.4Pullup/Pulldown Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .874System Interconnect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .884.1Internal Buses and Switch Fabrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .884.2Switch Fabric Connections Matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .894.3TeraNet Switch Fabric Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .914.4Bus Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .954.4.1Packet DMA Priority Allocation (PKTDMA_PRI_ALLOC) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .954.4.2EMAC / UPP Priority Allocation (EMAC_UPP_PRI_ALLOC) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95SPRS814—March 2012Fixed and Floating-Point Digital Signal Processor TMS320C6655/57 5C66x CorePac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .975.1Memory Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .985.1.1L1P Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .985.1.2L1D Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .995.1.3L2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .995.1.4MSM SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015.1.5L3 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015.2Memory Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015.3Bandwidth Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025.4Power-Down Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025.5C66x CorePac Revision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035.6C66x CorePac Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036Device Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046.1Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046.2Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056.3Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1066.4Power Supply to Peripheral I/O Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077Peripheral Information and Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087.1Recommended Clock and Control Signal Transition Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087.2Power Supplies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087.2.1Power-Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1097.2.2Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147.2.3Power Supply Decoupling and Bulk Capacitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147.2.4SmartReflex. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147.3Power Sleep Controller (PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1167.3.1Power Domains. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1167.3.2Clock Domains. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1177.3.3PSC Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1187.4Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1207.4.1Power-on Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1217.4.2Hard Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1227.4.3Soft Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1237.4.4Local Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1247.4.5Reset Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1247.4.6Reset Controller Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1257.4.7Reset Electrical Data / Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1257.5Main PLL and PLL Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1277.5.1Main PLL Controller Device-Specific Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1287.5.2PLL Controller Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1307.5.3Main PLL Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1367.5.4Main PLL and PLL Controller Initialization Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1377.5.5Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1377.6DD3 PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1407.6.1DDR3 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1407.6.2DDR3 PLL Device-Specific Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1417.6.3DDR3 PLL Initialization Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1417.6.4DDR3 PLL Input Clock Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1427.7Enhanced Direct Memory Access (EDMA3) Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1437.7.1EDMA3 Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1447.7.2EDMA3 Channel Controller Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1447.7.3EDMA3 Transfer Controller Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1447.7.4EDMA3 Channel Synchronization Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1457.8Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1477.8.1Interrupt Sources and Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1477.8.2CIC Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1627.8.3Inter-Processor Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1687.8.4NMI and LRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1697.8.5External Interrupts Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169Fixed and Floating-Point Digital Signal ProcessorSPRS814—March 2012TMS320C6655/57 7.9Memory Protection Unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1717.9.1MPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1747.9.2MPU Programmable Range Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1817.10DDR3 Memory Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1867.10.1DDR3 Memory Controller Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1867.10.2DDR3 Memory Controller Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1877.11I 2C Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1877.11.1I 2C Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1877.11.2I 2C Peripheral Register Description(s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1887.11.3I 2C Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1897.12SPI Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1927.12.1SPI Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1927.13HyperLink Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1957.13.1HyperLink Device-Specific Interrupt Event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1957.13.2HyperLink Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1977.14UART Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1997.15PCIe Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2007.16EMIF16 Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2017.16.1EMIF16 Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2017.17Ethernet Media Access Controller (EMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2047.17.1EMAC Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2047.17.2EMAC Peripheral Register Description(s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2057.17.3EMAC Electrical Data/Timing (SGMII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2097.18Management Data Input/Output (MDIO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2097.18.1MDIO Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2107.18.2MDIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2107.19Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2127.19.1Timers Device-Specific Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2127.19.2Timers Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2127.20Serial RapidIO (SRIO) Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2137.21General-Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2147.21.1GPIO Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2147.21.2GPIO Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2147.22Semaphore2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2147.23Emulation Features and Capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2157.23.1Advanced Event Triggering (AET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2157.23.2Trace. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2157.23.3IEEE 1149.1 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2167.24Enhanced Viterbi-Decoder Coprocessor (VCP2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2177.25Turbo Decoder Coprocessor (TCP3d). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2177.26Multichannel Buffered Serial Port (McBSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2187.26.1McBSP Peripheral Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2187.26.2McBSP Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2197.27Universal Parallel Port (UPP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2227.27.1UPP Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222A Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226B Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227B.1Thermal Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227B.2Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227。

东芝功放管资料

NEW
38
TIM1414-5-252
5
TIM1414-5L TIM1414-4UL NEW TIM1414-4LA TIM1414-4-252
TIM8596-4 TIM0910-4
NEW
TIM1213-4L TIM1011-4L TIM1011-4UL
NEW
36
TIM1213-4UL
TIM1011-2UL TIM8596-2 TIM0910-2 TIM1011-2L TIM1112-2
7
8
9
4
Output Power at 1dB Gain Compression (dBm)
40 Output Power at 1dB Gain Compression (W)
46
X-, Ku-band Internally Matched Power GaAs FETs/GaN HEMTs Pout vs. Frequency Map
5
■ GaN HEMTs
C-band Internally Matched Power GaN HEMT
BIAS CONDITIONS FREQUENCY BAND (GHz) 7.7-8.5
NEW 7-AA06A 7-AA04A
(Ta = 25 °C)
RF PERFORMANCE SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS (TYP.) Tch (°C) 250 VGSoff (V) – 4.0 PACKAGE CODE IDS (@Pin = 44.0 dBm) (A) TYP. 10.0 MAX. 12.0 G✽✽ (dB) MAX. ±0.8 Tch✽ (°C) MAX. 140 50 – 10 18.0

TIM7785-16SL中文资料

MICROWAVE POWER GaAs FETMICROWAVE SEMICONDUCTOR TIM7785-16SLTECHNICAL DATAFEATURESLOW INTERMODULATION DISTORTION HIGH GAINIM3=-45 dBc at Pout= 31.5dBm G1dB=5.5dB at 7.7GHz to 8.5GHz Single Carrier Level BROAD BAND INTERNALLY MATCHED FET HIGH POWERHERMETICALLY SEALED PACKAGEP1dB=42.5dBm at 7.7GHz to 8.5GHzRF PERFORMANCE SPECIFICATIONS ( Ta= 25°C )CHARACTERISTICS SYMBOL CONDITIONS UNITMIN. TYP.MAX. Output Power at 1dB Gain Compression PointP 1dB dBm 41.5 42.5⎯Power Gain at 1dB Gain Compression Point G 1dB dB 4.5 5.5 ⎯ Drain Current I DS1 A⎯4.45.0 Gain Flatness ΔGdB ⎯ ⎯±0.8 Power Added Efficiency ηadd VDS= 10V f= 7.7 to 8.5GHz% ⎯ 29 ⎯3rd Order Intermodulation Distortion IM3 dBc -42 -45 ⎯ Drain Current IDS2 Two-Tone Test Po=31.5dBm(Single Carrier Level) A ⎯4.45.0 Channel Temperature Rise ΔTch (VDS X IDS + Pin – P1dB)X Rth(c-c)°C ⎯ ⎯80 Recommended Gate Resistance(Rg): 100 Ω (Max.)ELECTRICAL CHARACTERISTICS ( Ta= 25°C )CHARACTERISTICS SYMBOL CONDITIONSUNITMIN. TYP.MAX.TransconductanceGm V DS = 3V I DS = 6.0AmS ⎯ 3600⎯ Pinch-off Voltage V GSoff V DS = 3VI DS = 60mAV -1.0 -2.5-4.0 Saturated Drain Current I DSS V DS = 3VV GS = 0VA⎯10.5⎯ Gate-Source Breakdown Voltage V GSO I GS = -200μA V -5 ⎯ ⎯Thermal Resistance R th(c-c) Channel to Case°C/W⎯1.52.0The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may results from its use, No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others.The information contained herein is subject to change without prior notice. It is therefor advisable to contact TOSHIBA before proceeding with design of equipment incorporating this product.ABSOLUTE MAXIMUM RATINGS ( Ta= 25°C )CHARACTERISTICS SYMBOL UNITRATINGDrain-Source Voltage V DS V 15 Gate-Source Voltage V GS V -5 Drain CurrentI DS A 14.0 Total Power Dissipation (Tc= 25 °C) P T W 75 Channel Temperature T ch °C 175 Storage TemperatureT stg°C-65 to +175PACKAGE OUTLINE (2-16G1B)Unit in mm (1) Gate (2) Source (3) DrainHANDLING PRECAUTIONS FOR PACKAGE MODELSoldering iron should be grounded and the operating time should not exceed 10 seconds at 260°C.RF PERFORMANCEOutput Power (Pout) vs. Frequency43 42 41 P o u t (d B m )407.77.98.18.38.5Frequency (GHz)Output Power(Pout) vs. Input Power(Pin)4544 43 PoutηaddPin(dBm)4241 40 39 38 37 36P o u t (d B m )80 70 ηa d d (%)60 50 40 30 201029 31 33 35 37 39POWER DISSIPATION vs. CASE TEMPERATURE906030 0 0 40 80 120 160 200Tc (°C)P T (W )IM3 vs. Output Power Characteristicsf=5MHz27-10-20 -30-40 -50 -60 I M 3(d B c )29 31 33 35 37 Pout(dBm) @Single carrier level。

AD7715资料

PRODUCT HIGHLIGHTS
1. The AD7715 consumes less than 450␣ µA in total supply current at 3 V supplies and 1␣ MHz master clock, making it ideal for use in low-power systems. Standby current is less than 10␣ µA. 2. The programmable gain input allows the AD7715 to accept input signals directly from a strain gage or transducer removing a considerable amount of signal conditioning. 3. The AD7715 is ideal for microcontroller or DSP processor applications with a three-wire serial interface reducing the number of interconnect lines and reducing the number of opto-couplers required in isolated systems. The part contains on-chip registers which allow software control over output update rate, input gain, signal polarity and calibration modes. 4. The part features excellent static performance specifications with 16-bits no missing codes, ± 0.0015% accuracy and low rms noise (<550␣ nV). Endpoint errors and the effects of temperature drift are eliminated by on-chip calibration options, which remove zero-scale and full-scale errors.

LM7815详细中文资料

LM7815中文资料目录1.lm7815介绍2.实际应用3.引脚序号、引脚功能4.lm7815应用电路5.7815电参数三端稳压集成电路lm7815。

电子产品中，常见的三端稳压集成电路有正电压输出的lm78 ×× 系列和负电压输出的lm79××系列。

顾名思义，三端IC是指这种稳压用的集成电路，只有三条引脚输出，分别是输入端、接地端和输出端。

它的样子象是普通的三极管，TO- 220 的标准封装，也有lm9013样子的TO-92封装。

1.lm7815介绍用lm78/lm79系列三端稳压IC来组成稳压电源所需的外围元件极少，电路内部还有过流、过热及调整管的保护电路，使用起来可靠、方便，而且价格便宜。

该系列集成稳压IC型号中的lm78或lm79后面的数字代表该三端集成稳压电路的输出电压，如lm7806表示输出电压为正6V，lm7909表示输出电压为负9V。

因为三端固定集成稳压电路的使用方便，电子制作中经常采用。

最大输出电流1.5A，LM78XX系列输出电压分别为5V;6V;8V;9V;10V;12V;15V;18V;24V。

2.实际应用在实际应用中，应在三端集成稳压电路上安装足够大的散热器（当然小功率7815IC内部电路图.的条件下不用）。

当稳压管温度过高时，稳压性能将变差，甚至损坏。

当制作中需要一个能输出1.5A以上电流的稳压电源，通常采用几块三端稳压电路并联起来，使其最大输出电流为N个1.5A，但应用时需注意：并联使用的集成稳压电路应采用同一厂家、同一批号的产品，以保证参数的一致。

另外在输出电流上留有一定的余量，以避免个别集成稳压电路失效时导致其他电路的连锁烧毁。

在lm78 ** 、lm79 ** 系列三端稳压器中最常应用的是TO-220 和TO-202 两种封装。

这两种封装的图形以及引脚序号、引脚功能如附图所示。

图中的引脚号标注方法是按照引脚电位从高到底的顺序标注的。

塞弗朗 7885 电视信号表计使用手册说明书

SEFRAM 7885 SeframTime is money! With its fast and expert spectrum analysis, the checksat mode with NIT, the Cell ID function, real time echoes and pre-echoes, the MER per carrier, the constellation dia-gram, the fast Autoset, GPS, Multistream capability, the LTE function to help the diagnostic of spurious filtering, no doubt that you can setup a TV receiving system in record time.To protect your TV meter, we have design a robust metal housing with a protective pouch. For your safety, we supplied an ingenious system of belts and clip and a light transporta-tion bag for non dedicated situation.A new design optimizedfor your safetyDirect access to function from the touch screen is like a game: dedicated icons, special "home" function to go back to main menu, virtual keyboard to enter your specific data, pos-sibility to export / import file on USB memory stick,… Getting started with the new SEFRAM 7885 is fast and easy.With the largest and brightest LCD of the market, using the new TV meter is possible in all conditions of light, including in sunny environment. With the 10.1" touch screen, you will use your new TV meter like a smartphone or a tablet: no need to worry where and which button to push, everything is displayed on the large screen in a clear and easy way. Incredibly user friendly!Panoramic touch screen• Panoramic LCD touch screen: 10 inches (16:9)• Display free to air programs for digital terrestrial, cable and satellite• Display High Definition TV programs MPEG4-H264 and HEVC (H265)• Display analog TV programs• All measurements for DVB-T/T2, DVB-C/C2 (J83-A and B), DVB-S, DVB-S2, DAB/DAB+, Wifi•IPTV measurements and decoding• Optical input with optical to RF converter, including Optical Power measurements• Ultra fast spectrum analysis and expert spectrum analysis • Checksat mode with NIT (satellite recognition)• LTE function to help the diagnostic of filter• Real time echoes and pre-echoes measurement with zoom • Constellation diagram with zoom• Three in one display:measurement, TV picture, mini spectrum • Graphical display of measurements• ASI TS input and output and HDMI interface• Analogue input and output• GPS• Multistream capability• Shoulder measurement• Memorize and export/import data with USB memory stick • Battery with 1 hour charging time and 4 hours autonomy • Supplied with carrying bag and protection pouch• Weight: 2,8kgState-of-Art specifications for High Definition TVThe feeling of a new way of measurementFT7885 A01 - Specifications can be updated without notice32, rue Edouard Martel - B.P. 55 - 42009 - St Etienne cedex 2Tel.+33 (0).4.77.59 36 81Supplied with:main adaptor (90-245V with European plug), user's manual on CD ROM, F/F and F/BNC adaptor, carrying protective pouch,belt clip, transportation pouch.(*): the display of digital encrypted programs is possible, if user has a valid subsciption card and if the encryption type is supported bythe TV Meter. Please check with our sales department when ordering. Dolby is a trade mark of Dolby Laboratories.978852000Transportation handcase978361000Car cigar lighter adapter978853000Audio/video cableOptional accessories: Car cigar lighterP/N 978361000Transportation hardcase P/N 978852000A/V cableP/N 978852000。

三端稳压器的参数介绍

LM7805是国家半导体开发出来比较成熟，较早的一种线性稳压半导体器件，现在仍然还有很多公司在使用，个人也用得比较多，因为很便宜且性能比较稳定。

常提到的三端稳压块7805就是指它了。

拿它作为例子很有代表性。

参数一：输出电压最简单的一个参数，就是稳压器的输出电压，能稳定在多少V，7805输出电压稳定在5V参数二：线性调整率稳压器的输入电压一般都比较宽，在该范围内，输入如果变化输出电压的变化有多大呢？该参数就是描述这种变化的一个参数。

很显然输出电压的变化是越小越好了，一般都是几毫伏。

拿7805作为例子来说吧，参考Data Sheet就可以知道，在常温，输出500mA电流的情况下，输入电压在7~25V之间变化的时候，输出电压的变化典型值为3mV，最大值为50mV参数三：负载调整率负载发生变化时，输出电压也会相应的发生变化，一般是负载越重，输出电压会有所下降，负载越轻输出电压会有所上升。

负载调整率就是反应这种变化的一个量。

看7805的Data Sheet可知，在负载变化在5mA~1.5A时，输出电压的变化范围在10~50mV参数四：静态电流对于线性稳压器来说是一个非常重要的参数。

该电流为驱动大功率调整管所必须的，它不流向负载，而是直接流向地，因此该电流是越小越好。

QS7785中文资料

MONO 10 AC 11
BYP(SDA) 12
ORDERING INFORMATION
Device QS7785PF QS7785CF
Package 48-pin QFP 48-pin QFP
I2C bus is a registered trademark of Philips Electronics N.V. Dolby and the double-D symbol are registered trademarks of Dolby Laboratories Licensing Corporation.
–
SCL
BASS
MUTE
PSAVE
VREFOUT
NC
VREFIN
LPC
CIN
COUT
SLOUT
SROUT
FLOUT
FROUT
QXBC4
QXBC3
QXBC2
QXBC1
VCC
QXAC4
QXAC3
QXAC2
QXAC1
BASC1
QS7785PF/CF
I/O
Description
O QEXPANDER C capacitor 4 I QEXPANDER D capacitor 1 O QEXPANDER D capacitor 2 I QEXPANDER D capacitor 3 O QEXPANDER D capacitor 4 – Ground – 4.5 to 5.5V digital supply I Input mode control (HIGH: parallel, LOW: serial) I Enhancement control (HIGH: high spread, LOW: low spread) I Serial data strobe (not applicable to QS7785CF) I Mono-to-stereo convert select (HIGH: mono to stereo mode, LOW: normal mode) I Center output control (HIGH: center on, LOW: center off) I Bypass control (HIGH: bypass, LOW: Qsurround) I/O Serial data input (also serves as ACK signal output for I2C bus) I Surround speaker control (HIGH: surround speaker on, LOW: off) I Serial clock signal input I Bass boost mode control (HIGH: bass boost on, LOW: bass boost off) I Mute signal control (HIGH: mute on, LOW: mute off) I Power save control (HIGH: power save on, LOW: power save off) O VCC/2 reference voltage output – No connection I VCC/2 reference voltage output (biased internally to VCC/2) I Center output lowpass ﬁlter I COUT output signal feedback input for front-channel output O Center signal output O Surround left-channel signal output O Surround right-channel signal output O Front left-channel signal output O Front right-channel signal output O QEXPANDER B capacitor 4 I QEXPANDER B capacitor 3 O QEXPANDER B capacitor 2 I QEXPANDER B capacitor 1 – 5 to 13V DC analog supply O QEXPANDER A capacitor 4 I QEXPANDER A capacitor 3 O QEXPANDER A capacitor 2 I QEXPANDER A capacitor 1 I Bass boost right-channel signal input

随身听皮带规格

随身听皮带规格机型皮带尺寸：内径/对折/截面(mm)AIWA爱华HS-G21MKII 037/058/0.7爱华HS-G330/360 037/058/0.7爱华HS-GS111 037/058/0.7爱华HS-GS112/122/183 037/058/0.7 , 027/042/0.7爱华HS-GS216 025/039/0.7 , 027/042/0.7 , 056/088/0.7爱华HS-J36/J360 071/111.5/0.7爱华HS-JS199/275W/375W/475 037/058/0.7 ,027/042/0.7 爱华HS-P102/P15 037/058/0.7爱华HS-PS110/131/140/151 /171/181 037/058/0.7 , 027/042/0.7爱华HS-PS152 037/058/0.7 ,027/042/0.7 , 033/052/0.7爱华HS-PX577 061/096/0.7爱华HS-RS360 037/058/0.7爱华HS-RX693 037/058/0.7 ,027/042/0.7爱华HS-SA30 037/058/0.7爱华HS-T110 037/058/0.7爱华HS-T20 027/042/0.7爱华HS-T21/36/210/220/260/330 037/058/0.7 , 027/042/0.7 爱华HS-T230 037/058/0.7爱华HS-TA117W 027/042/0.7爱华HS-TA133W/134W/163W/164/171/183W 037/058/0.7 , 027/042/0.7爱华HS-TA144W 037/058/0.7爱华HS-TA153W 027/042/0.7爱华HS-TA173W 037/058/0.7爱华HS-TA193 037/058/0.7 , 027/042/0.7 , 041/064/0.7爱华HS-TA203 037/058/0.7爱华HS-TA210/263/273W/283W/333W 037/058/0.7 ,027/042/0.7爱华HS-TA253/G/W 037/058/0.7爱华HS-TA353/V/W 037/058/0.7爱华HS-TA363 037/058/0.7爱华HS-TA368 037/058/0.7 , 075/118/0.7爱华HS-TA373W/381W 037/058/0.7 ,027/042/0.7爱华HS-TA453/G/W 027/042/0.7爱华HS-TA463 037/058/0.7 ,027/042/0.7 , 073/115/0.7爱华HS-TA473W/TS250W 037/058/0.7 , 027/042/0.7爱华HS-TA483W 037/058/0.7爱华HS-TS350/W 037/058/0.7爱华HS-TX376/377/386/394/406/456 037/058/0.7 ,027/042/0.7爱华HS-TX388 037/058/0.7爱华HS-TX457/476 056/088/0.7爱华HS-TX481/486/576/586/657 037/058/0.7 ,027/042/0.7 爱华HS-TX510 073/115/1.0 , 027/042/0.7 , 075/118/1.0爱华HS-TX656/676/686 069/108/0.7爱华HS-TX776/786 037/058/0.7 , 027/042/0.7爱华HJ-ST11 037/058/0.7爱华HS-719 059/093/0.7 ,059/093/0.7爱华HS-G11 037/058/0.7爱华HS-GS111 037/058/0.7爱华HS-GS112 037/058/0.7爱华HS-GS122 037/058/0.7爱华HS-GS142 037/058/0.7爱华HS-J170 053/083/0.7, 025/039/0.7爱华HS-J202/MKII 061/096/0.7爱华HS-J303 061/096/0.7, 080/126/0.7爱华HS-J470 075/118/1.0爱华HS-J505 061/096/0.7, 080/126/0.7爱华HS-J55 061/096/0.7爱华HS-J550 061/096/0.7爱华HS-J707 061/096/0.7爱华HS-J800 061/096/0.7爱华HS-J880 061/096/0.7爱华HS-J900 061/096/0.7爱华HS-JS110 061/096/0.7爱华HS-JS189 035/055/0.8爱华HS-JS199 027/042/0.7, 037/058/0.7爱华HS-JS215/W 026/041/1.0 057/089.5/1.0 爱华HS-JS216 026/041/1.0 057/089.5/1.0爱华HS-JS299 033/052/0.7爱华HS-JS303 061/096/0.7爱华HS-JS315 026/041/1.0 057/089.5/1.0爱华HS-JS345 073/115/0.7爱华HS-JS415 026/041/1.0 057/089.5/1.0爱华HS-JS445 069/108/0.7爱华HS-JS609 061/096/0.7爱华HS-JS729 063/099/0.7爱华HS-JS819 053/083/0.7爱华HS-JX101 061/096/0.7, 027/042/0.7爱华HS-JX505 056/088/0.7爱华HS-JS703 073/115/0.7爱华HS-JX707 067/105/0.7, 075/118/0.7爱华HS-P103 075/118/1.0 , 075/118/0.8爱华HS-P105/107 075/118/0.8 , 073/115/1.0 爱华HS-P202 061/096/0.7爱华HS-P25 075/118/0.8爱华HS-PC204 061/096/0.7爱华HS-PS152 034/052/0.7, 027/042/0.7, 037/058/0.7 爱华HS-PS181 037/058/0.7 , 027/042/0.7爱华HS-R07 MARK II 073/115/1.0爱华HS-R8 65/102/0.7爱华HS-SP370 075/118/0.7 ,027/042/0.7爱华HS-T19 036/056.5/1.0爱华HS-T19 MARK II 037/058/0.7爱华HS-T20/W 037/058/0.7爱华HS-T202 061/096/0.7 ,027/042/0.7爱华HS-T23MKV 037/058/0.7爱华HS-T27 073/115/1.0爱华HS-T800/900 061/096/0.7 ,027/042/0.7爱华HS-TA154W 037/058/0.7 ,027/042/0.7爱华HS-TA163 039/061/0.7爱华HS-TA193 041/064/0.7 , 027/042/0.7 , 037/058/0.7 爱华HS-TA310 080/126/0.7爱华HS-TA412 025/039/0.7 053/83/0.7爱华HS-TA453 069/0108/0.7 , 027/042/0.7爱华HS-TA463 073/115/0.7 ,027/042/0.7 , 073/115/0.7 爱华HS-TX410 073/115/0.7 ,075/118/1.0爱华HS-TX510 073/115/0.7 ,027/042/0.7 , 075/118/1.0 爱华PXM2000 021/033/0.7 043/067.5/0.7松下（NATIONAL、Panasonic）松下RQ-E15V/27V 031/049/0.7及056/088/0.7松下RQ-V450/500 067/105/0.7松下RQ-CR07 031/049/0.7及056/088/0.7松下RQ-CW05 027/042/0.7及059/093/0.7松下GX-506061/096/0.7松下GX-614 065/102/0.7松下GX-62 069/108/0.7松下PQ-NX-60 063/099/0.7松下PQ-P41 021/033/0.7 027/042/0.7松下RQ-NX-62 031/049/0.7松下RQ-SX7 067/105/0.5松下RQ-SX1V/11/33/46 067/105/0.7松下RQ-SX52 023/036/0.5松下RQ-SX53/55/56/60 025/036/0.5及031/049/0.5松下RQ-SX70V 031/049/0.5松下RQ-SX40/50V/67V/73/76/77V/80V/93 025/038/0.5及031/049/0.5松下RQ-SX88V 023/036/0.5及019/030/0.5松下RQ-SX97F 031/049/0.5松下RQ-SW30/70 056/088/0.7松下RQ-S1 065/102/0.7松下RQ-S11/15/95 067/105/0.7松下RQ-S5V 067/105/0.7松下RQ-S25 069/108/0.7松下RQ-S95松下RQ-CR07/15 056/088/0.7及031/049/0.7松下RQ-E15V/27V 031/049/0.7及056/088/0.7松下S40V 069/108/0.7松下RQ-WJ1 042/066/1.0松下RQ-XV30 065/102/1.0松下RQ-KJ1 042/066/1.0索尼磁带随身听(SONY)索尼CFT-22 053/083/1.0索尼WM-1 042/066/1.0索尼WM-2 044/069/1.0索尼WM-10/50 061/096/0.7索尼WM-11/14 036/056.5/1.0索尼WM-18 082/129/1.0索尼WM-22/24/25 037/058/1.2索尼WM-30 047/074/0.7索尼WM-35RF/45RF 033/052/0.7索尼WM-100/101 065/102/0.7索尼WM-190 067/105/1.0索尼WM-2051 056/088/1.0索尼WM-501/505/2091 073/115/0.7索尼WM-509 065/102/0.7索尼WM-701C 067/105/0.7索尼WM-A602 067/105/0.7索尼WM-AF604/AF605/BF608 067/105/0.7索尼WM-D6 C B 037/058/1.2索尼WM-D6C Driving 018/028/0.7索尼WM-ES392 056/088/0.7索尼WM-EX1 067/105/0.7索尼WM-EX1/HG 071/111.5/0.7索尼WM-EX2 069/108/0.7索尼WM-EX5 063/099/0.7索尼WM-EX7 067/105/0.7索尼WM-EX9 063/099/0.7索尼WM-EX10/102/108/120 /122/155 056/088/0.7 索尼WM-EX190/192 053/083/0.7索尼WM-EX12 053/083/1.0索尼WM-EX35/356 056/088/0.7索尼WM-EX50 067/105/0.7索尼WM-EX90 075/118/0.7索尼WM-EX372 053/083/0.7索尼WM-EX500/505/510 069/108/0.7索尼WM-EX550/552/560/572/650/652/654/655/658/660/662/668063/099/0.7索尼WM-EX608 069/108/0.7索尼WM-EX666 067/105/0.7索尼WM-EX672/674/678 069/108/0.7索尼WM-EX900 063/099/0.7索尼WM-EX922 067/105/0.7索尼WM-F1 030/047/1.0和042/066/1.0索尼WM-F2 044/069/1.0索尼WM-F5 069/108/0.7索尼WM-F6/F8 036/056.5/1.0索尼WM-F12RF 033/052/0.7索尼WM-F17 037/058/1.2索尼WM-F18 082/129/1.0索尼WM-F32/37/38 028/044/1.0索尼WM-F35RF/45RF 033/052/0.7索尼WM-F46 037/058/1.2索尼WM-F47 028/044/1.0索尼WM-F55 069/108/0.7索尼WM-F59 060/094/1.0索尼WM-F59Walkman 057/089.5/1.0索尼WM-F68 028/044/1.0索尼WM-F69 060/094/1.0索尼WM-F69Walkman 057/089.5/1.0索尼WM-F100/103/107/109 065/102/0.7索尼WM-F200/F200III 065/102/1.0索尼WM-F202/203 065/102/1.0索尼WM-F2061 053/083/1.0索尼WM-F2065 056/088/1.0索尼WM-F2095 070/110/0.7索尼WM-F2097 069/108/1.0索尼WM-F404 067/105/0.7索尼WM-F507 069/108/1.0索尼WM-F702 067/105/0.7索尼WM-FQ01056/088/0.7索尼WM-FS111 053/083/0.7索尼WM-FS393 073/115/0.7索尼WM-FS395 073/115/0.7索尼WM-FS399/400 056/088/0.7索尼WM-FS473 053/083/1.0索尼WM-FS493/495 056/088/0.7索尼WM-FS497/499 053/083/1.0索尼WM-FS593/595 056/088/0.7索尼WM-FX2 067/105/0.7索尼WM-FX5 063/099/0.7索尼WM-FX50/56 067/105/0.7索尼WM-FX10/12/21/22/23/24/29/30/32/36/38/40/41/42/43/45056/088/0.7WM-FX101/103/109/121/123/131/141/153/157/161/211/213/221/3 01/303/315/321/323/325/353/355/401/403/405/407/413/415/4 21/423/425/431/477/479/487/491/493/495 056/088/0.7 索尼WM-FX171/173/177/193/195/251/267/269/271/275/277/375/467 053/083/0.7索尼WM-FX433/435/455/463/465 053/083/1.0索尼WM-FX505 073/115/0.7索尼WM-FX509 061/096/0.7索尼WM-FX580 041/064/0.7及025/039/0.7索尼WM-FX590 019/030/0.7索尼WM-FX551/553/561/563/571/651/653/655/661/663/665/855063/099/0.7索尼WM-FX671/673/877 069/108/0.7索尼WM-FX999 029/045/0.7索尼WM-FXH2 053/083/1.0索尼WM-GX35 067/105/0.7索尼WM-GX51 069/108/1.0索尼WM-GX52/53 061/96/0.7索尼WM-GX58 067/105/0.7索尼WM-GX90 075/118/0.7索尼WM-GX100/320/322 053/083/0.7索尼WM-GX300/302 073/115/0.7索尼WM-GX508 060/094/1.0索尼WM-GX550/552 063/099/0.7索尼WM-GX612/614/615 069/108/0.7索尼WM-GX622 069/108/0.7索尼WM-GX-652/654 073/115/0.7索尼WM-GX670/674/677/680/688 065/102/0.7索尼WM-R2 044/069/1.0索尼WM-R202 065/102/0.7索尼WM-PSY01/02 053/083/1.0索尼WM-SFX33 073/115/0.7索尼WM-SX34 073/115/0.7 索尼WM-SXF39 073/115/0.7 索尼WM-SXF44 073/115/0.7。

单片机应用技术1 单片机硬件基础

复位电路
AT89S51最小系统之ROM选择
51单片机内部集成有4K字节的程序存储器（标准型），可以外接存储器芯片扩展容量。 EA=0时：不使用内部ROM，外部地址从0开始。 EA=1时：内+外。超过内部地址后自动使用外部ROM地址，内外的地址连续。根据程序编译后的代码长度考虑选择不同内部ROM容量的单片机型号。故EA固定为高电平。
AT:(美)ATMEL公司 P:(荷)Philips公司 STC:(大陆)宏晶科技 W:(台)华邦公司
0343:2003年43周制造
AT89S51封装形式
PLCC44
TQFP44式封装。 PLCC44：特殊引脚芯片塑料封装，贴片封装的一种，引脚在芯片底部向内弯曲，焊接采用回流焊工艺，在调试时有插座可用。 TQFP44：薄四方扁平封装，低成本，低高度引线框封装，适合用SMT表面安装技术。
PDIP40封装
端口的几个操作注意点
1.驱动能力不同，P0每引脚可以驱动8个TTL负载，其余端口每引脚只能带4个。
2.P0口内部无上拉电阻，其余口有弱上拉，电路设计时需要注意P0口漏极开路，做IO输出时，需外加上拉电阻才会有高电平输出。
3.P0在做数据线时才是真正的双向口 P0-P3在做输入接口时，需要先置1再读入（打开内部锁存器）
AT89S51
PDIP40 封装
AT89S51
PLCC44封装
注：NC表示该脚无用
AT89S51
TQFP44封装
注：NC表示该脚无用
AT89S51引脚功能
P0/P1/P2/P3:
4个并行端口，每口8脚，可做IO接口，也可做第二功能；
IO功能：
输入输出引脚，用户灵活DIY

UTCLM7805中文资料

UTC LM78XXLINEAR INTEGRATED CIRCUITUTC UNISONIC TECHNOLOGIES CO., LTD.1QW-R101-006,C3-TERMINAL 1A POSITIVE VOLTAGE REGULATORDESCRIPTIONThe UTC 78XX family is monolithic fixed voltageregulator integrated circuit. They are suitable for applications that required supply current up to 1 A.FEATURES*Output current up to 1.5 A*Fixed output voltage of 5V, 6V, 8V, 9V, 10V, 12V, 15V ,18V and 24V available*Thermal overload shutdown protection *Short circuit current limiting*Output transistor SOA protection1: Input 2: GND 3: OutputTEST CIRCUITINPUTZ1UTC LM78XXLINEAR INTEGRATED CIRCUITUTC UNISONIC TECHNOLOGIES CO., LTD.2QW-R101-006,CABSOLUTE MAXIMUM RATINGS( Operating temperature range applies unless otherwise specified )PARAMETER SYMBOL RATING UNITInput voltage(for Vo=5~18V)(for Vo=24V) V I 35 40V V Output CurrentI o 1 A Power DissipationPD Internally Limited W Operating Junction Temperature RangeT OPR-20+150°CStorage Temperature Range T STG -55+150 °C UTC LM7805 ELECTRICAL CHARACTERISTICS( VI=10V, Io=0.5A, Tj= 0°C - 125°C, C1=0.33uF, Co=0.1uF, unless otherwise specified )(Note 1)PARAMETERSYMBOLTEST CONDITIONSMINTYP MAX UNITTj=25°C, I O =5mA - 1.0A4.805.0 5.20 VOutput Voltage VoV I =7.5V to 20V, I O =5mA - 1.0A,PD<15W4.755.25 V Load Regulation∆Vo Tj =25°C,I O =5mA - 1.5A 50 mVTj=25°C,I O =0.25A - 0.75A 25 mVLine regulation ∆Vo V I =7V to 25V,Tj=25°C 50 mVV I =7.5V to 20V,Tj=25°C,Io=1A 50 mV Quiescent Current Iq Tj=25°C, I O =<1A 8.0 mAQuiescent Current Change ∆Iq V I =7.5V to 20V 1.0 mA∆Iq I O =5mA - 1.0A 0.5 mA Output Noise Voltage V N 10Hz<=f<=100kHz 40 µV Temperature coefficient of Vo ∆Vo/∆T Io =5mA -0.6mV/°C Ripple Rejection RR V I =8V - 18V,f=120Hz,Tj=25°C 6280 dB Peak Output Current I PK Tj=25°C 1.8 A Short-Circuit Current I SC VI=35V, Tj=25°C 250 mA Dropout Voltage Vd Tj=25°C 2.0 VUTC LM7806 ELECTRICAL CHARACTERISTICS( VI=11V, Io=0.5A, Tj= 0°C - 125°C, C1=0.33uF, Co=0.1uF, unless otherwise specified )(Note 1)PARAMETERSYMBOLTEST CONDITIONSMINTYP MAX UNITTj=25°C, I O =5mA - 1.0A5.766.0 6.24 V Output VoltageVoV I =8.5V to 21V,I O =5mA - 1.0A, PD<15W5.706.30 VLoad Regulation∆Vo Tj =25°C,I O =5mA - 1.5A 60 mVTj=25°C,I O =0.25A - 0.75A 30 mVLine regulation ∆Vo V I =8V to 25V,Tj=25°C 60 mVV I =8.5V to 21V,Tj=25°C,Io=1A 60 mV Quiescent Current Iq Tj=25°C, I O =<1A 8.0 mAQuiescent Current Change ∆Iq V I =8.5V to 21V 1.0 mA∆Iq I O =5mA - 1.0A 0.5 mA Output Noise Voltage V N 10Hz<=f<=100kHz 45 µV Temperature coefficient of Vo ∆Vo/∆T Io =5mA -0.7mV/°C Ripple RejectionRR V I =9V - 19V,f=120Hz,Tj=25°C 5975 dBUTC LM78XXLINEAR INTEGRATED CIRCUITUTC UNISONIC TECHNOLOGIES CO., LTD.3QW-R101-006,CPARAMETERSYMBOLTEST CONDITIONSMINTYP MAX UNITPeak Output Current I PK Tj=25°C 1.8 AShort-Circuit Current I SCVI=35V, Tj=25°C 250 mA Dropout Voltage VdTj=25°C 2.0 VUTC LM7808 ELECTRICAL CHARACTERISTICS( VI=14V, Io=0.5A, Tj= 0°C - 125°C, C1=0.33uF, Co=0.1uF, unless otherwise specified )(Note 1)PARAMETERSYMBOL TEST CONDITIONSMINTYP MAX UNITTj=25°C, I O =5mA - 1.0A 7.688.0 8.32 V Output VoltageVoV I =10.5V to 23V,I O =5mA - 1.0A, PD<15W7.608.40 VLoad Regulation ∆Vo Tj =25°C,I O =5mA - 1.5A 80 mVTj=25°C,I O =0.25A - 0.75A 40 mVLine regulation ∆Vo V I =10.5V to 25V,Tj=25°C 80 mVV I =10.5V to 23V,Tj=25°C,Io=1A 80 mV Quiescent Current Iq Tj=25°C, I O =<1A 8.0 mAQuiescent Current Change ∆Iq V I =10.5V to 23V 1.0 mA ∆Iq I O =5mA - 1.0A 0.5 mAOutput Noise Voltage V N 10Hz<=f<=100kHz 58 µVTemperature coefficient of Vo ∆Vo/∆T Io =5mA -0.9mV/°C Ripple Rejection RR V I =11.5V to 21.5V, f=120Hz,Tj=25°C 5672 dBPeak Output Current I PK Tj=25°C 1.8 A Short-Circuit Current I SC VI=35V, Tj=25°C 250 mA Dropout Voltage Vd Tj=25°C 2.0 VUTC LM7809 ELECTRICAL CHARACTERISTICS( VI=15V, Io=0.5A, Tj= 0°C - 125°C, C1=0.33uF, Co=0.1uF, unless otherwise specified )(Note 1)PARAMETERSYMBOLTEST CONDITIONSMINTYP MAX UNITTj=25°C, I O =5mA - 1.0A8.649.0 9.36 VOutput Voltage VoV I =11.5V to 24V, I O =5mA - 1.0A,PD<15W8.55 9.45 V Load Regulation ∆Vo Tj =25°C,I O =5mA - 1.5A 90 mVTj=25°C,I O =0.25A - 0.75A 45 mVLine regulation ∆Vo V I =11.5V to 25 V, Tj=25°C, PD<15W90 mVV I =11.5V to 24V,Tj=25°C, Io<=1A90 mV Quiescent Current Iq Tj=25°C, I O =<1A 8.0 mAQuiescent Current Change ∆Iq V I =11.5V to 24V 1.0 mA∆Iq I O =5mA – 1.0A 0.5 mA Output Noise Voltage V N 10Hz<=f<=100kHz 58 µV Temperature coefficient of Vo ∆Vo/∆T Io =5mA -1.1 mV/°C Ripple Rejection RR V I =12.5V to 22.5V, f=120Hz,Tj=25°C 5672 dBPeak Output Current I PK Tj=25°C 1.8 A Short-Circuit Current I SC VI=35V, Tj=25°C 250 mA Dropout Voltage Vd Tj=25°C 2.0 VUTC LM78XXLINEAR INTEGRATED CIRCUITUTC UNISONIC TECHNOLOGIES CO., LTD.4QW-R101-006,CUTC LM7810 ELECTRICAL CHARACTERISTICS( VI=16V, Io=0.5A, Tj= 0°C - 125°C, C1=0.33uF, Co=0.1uF, unless otherwise specified )(Note 1) PARAMETERSYMBOLTEST CONDITIONSMINTYP MAX UNITTj=25°C, I O =5mA - 1.0A9.6010.0 10.40 V Output Voltage Vo VI =12.5V to 25V,I O =5mA - 1.0A,PD<=15W9.5010.50 VLoad Regulation ∆Vo Tj =25°C,I O =5mA - 1.5A 100 mVTj=25°C,I O =0.25A - 0.75A 50 mVLine regulation ∆Vo VI =13V to 25V,Tj=25°C 100 mVVI =13V to 25V, Tj=25°C,Io<=1A 100 mVQuiescent Current Iq Tj=25°C, I O =<1A 8.0 mAQuiescent Current Change ∆Iq VI =12.6V to 25V 1.0 mA ∆Iq I O =5mA - 1.0A 0.5 mAOutput Noise Voltage V N 10Hz<=f<=100kHz 58 µVTemperature coefficient of Vo ∆Vo/∆T Io =5mA -1.1mV/°C Ripple Rejection RR VI =13V - 23V,f=120Hz,Tj=25°C 5672 dBPeak Output Current I PK Tj=25°C 1.8 A Short-Circuit Current I SC VI=35V, Tj=25°C 250 mA Dropout Voltage Vd Tj=25°C 2.0 VUTC LM7812 ELECTRICAL CHARACTERISTICS( VI=19V, Io=0.5A, Tj= 0°C - 125°C, C1=0.33uF, Co=0.1uF, unless otherwise specified )(Note 1)PARAMETER SYMBOLTEST CONDITIONS MIN TYP MAX UNITTj=25°C, I O =5mA - 1.0A 11.5212.0 12.48 VOutput Voltage VoV I =14.5V to 27V,I O =5mA - 1.0A,PD<15W11.40 12.60 V Load Regulation∆Vo Tj =25°C,I O =5mA - 1.5A 120 mVTj=25°C,I O =0.25A - 0.75A 60 mVLine regulation ∆Vo V I =14.5V to 30V,Tj=25°C 120 mVV I =14.6V to 27V,Tj=25°C, Io=1A120 mV Quiescent Current Iq Tj=25°C, I O =<1A 8.0 mAQuiescent Current Change ∆Iq V I =14.5V to 30V 1.0 mA∆Iq I O =5mA - 1.0A 0.5 mA Output Noise Voltage V N 10Hz<=f<=100kHz 75 µV Temperature coefficient of Vo ∆Vo/∆T Io =5mA -1.5mV/°C Ripple Rejection RR V I =15V - 25V,f=120Hz,Tj=25°C 5572 dB Peak Output Current I PK Tj=25°C 1.8 A Short-Circuit Current I SC VI=35V, Tj=25°C 250 mA Dropout Voltage Vd Tj=25°C 2.0 VUTC LM78XXLINEAR INTEGRATED CIRCUITUTC UNISONIC TECHNOLOGIES CO., LTD.5QW-R101-006,CUTC LM7815 ELECTRICAL CHARACTERISTICS( VI=23V, Io=0.5A, Tj= 0°C - 125°C, C1=0.33uF, Co=0.1uF, unless otherwise specified )(Note 1)PARAMETERSYMBOLTEST CONDITIONSMINTYP MAX UNITTj=25°C, I O =5mA - 1.0A14.4015.0 15.60 V Output VoltageVoV I =17.5V to 30V,I O =5mA - 1.0A,PD<15W 14.2515.75 VLoad Regulation ∆Vo Tj =25°C,I O =5mA - 1.5A 150 mVTj=25°C,I O =0.25A - 0.75A 75 mVLine regulation ∆Vo V I =18.5V to 30V,Tj=25°C 150 mVV I =17.7V to 30V, Tj=25°C, I O =1A 150 mV Quiescent Current Iq Tj=25°C, I O =<1A 8.0 mAQuiescent Current Change ∆Iq V I =17.5V to 30V 1.0 mA ∆Iq I O =5mA - 1.0A 0.5 mAOutput Noise Voltage V N 10Hz<=f<=100kHz 90 µVTemperature coefficient of Vo ∆Vo/∆T Io =5mA -1.8mV/°C Ripple Rejection RR V I =18.5V to 28.5V f=120Hz,Tj=25°C5470 dBPeak Output Current I PK Tj=25°C 1.8 A Short-Circuit Current I SC VI=35V, Tj=25°C 250 mA Dropout Voltage Vd Tj=25°C 2.0 VUTC LM7818 ELECTRICAL CHARACTERISTICS( VI=27V, Io=0.5A, Tj= 0°C - 125°C, C1=0.33uF, Co=0.1uF, unless otherwise specified )(Note 1)PARAMETERSYMBOLTEST CONDITIONSMINTYP MAX UNITTj=25°C, I O =5mA - 1.0A17.2818.0 18.72 VOutput Voltage VoV I =21V to 33V,I O =5mA - 1.0A 17.1018.90 V Load Regulation∆Vo Tj =25°C,I O =5mA - 1.5A 180 mVTj=25°C,I O =0.25A - 0.75A 90 mVLine regulation ∆Vo V I =21V to 33V,Tj=25°C 180 mVV I =21V to 33V,Tj=25°C, I O =<1A,PD<15W 180 mV Quiescent Current Iq Tj=25°C, I O =<1A 8.0 mAQuiescent Current Change ∆Iq V I =21.5V to 33V 1.0 mA∆Iq I O =5mA - 1.0A 0.5 mA Output Noise Voltage V N 10Hz<=f<=100kHz 110 µV Temperature coefficient of Vo ∆Vo/∆T Io =5mA -2.2mV/°C Ripple Rejection RR V I =22V - 32V,f=120Hz,Tj=25°C 5369 dB Peak Output Current I PK Tj=25°C 1.8 A Short-Circuit Current I SC VI=35V, Tj=25°C 250 mA Dropout Voltage Vd Tj=25°C 2.0 VUTC LM78XXLINEAR INTEGRATED CIRCUITUTC UNISONIC TECHNOLOGIES CO., LTD.6QW-R101-006,CUTC LM7824 ELECTRICAL CHARACTERISTICS( VI=33V, Io=0.5A, Tj= 0°C - 12°C, C1=0.33uF, Co=0.1uF, unless otherwise specified )(Note 1)PARAMETERSYMBOLTEST CONDITIONSMINTYP MAX UNITTj=25°C, I O =5mA - 1.0A23.0424.0 24.96 VOutput VoltageVoV I =27V to 38V,I O =5mA - 1.0A 22.8025.20 V Load Regulation ∆Vo Tj =25°C,I O =5mA - 1.5A 240 mVTj=25°C,I O =0.25A - 0.75A 120 mVLine regulation ∆Vo V I =27V to 38V,Tj=25°C 240 mVV I =27V to 38V,Tj=25°C,Io=1A 240 mV Quiescent Current Iq Tj=25°C, I O =<1A 8.0 mAQuiescent Current Change ∆Iq V I =28V to 38V 1.0 mA ∆Iq I O =5mA - 1.0A 0.5 mAOutput Noise Voltage V N 10Hz<=f<=100kHz 170 µVTemperature coefficient of Vo ∆Vo/∆T Io =5mA -2.8mV/°C Ripple Rejection RR V I =28V - 38V,f=120Hz,Tj=25°C 5066 dB Peak Output Current I PK Tj=25°C 1.8 A Short-Circuit Current I SC VI=35V, Tj=25°C 250 mA Dropout Voltage Vd Tj=25°C 2.0 VNote 1: The Maximum steady state usable output current are dependent on input voltage, heat sinking, lead lengthof the package and copper pattern of PCB. The data above represents pulse test conditions with junction temperatures specified at the initiation of test.Note 2: Power dissipation<0.5WAPPLICATION CIRCUITNote 1: To specify an output voltage, substitute voltage value for "XX".Note 2: Bypass capacitors are recommended for optimum stability and transient response and should be located asclose as possible to the regulators.。

CS5532-BSZR;CS5534-BSZR;CDB5532U;中文规格书,Datasheet资料

Copyright © Cirrus Logic, Inc. 2008CS5532/34-BS24-bit ∆Σ ADCs with Ultra-low-noise PGIAFeaturesChopper-stabilized PGIA (ProgrammableGain Instrumentation Amplifier, 1x to 64x)– 6 nV/√Hz @ 0.1 Hz (No 1/f noise) at 64x –1200pA Input Current with Gains >1 Delta-sigma Analog-to-digital Converter –Linearity Error: 0.0007% FS–Noise-free Resolution: Up to 23 bits Two- or Four-channel Differential MUX Scalable Input Span via Calibration –±5 mV to differential ±2.5VScalable V REF Input: Up to Analog Supply Simple Three-wire Serial Interface –SPI™ and Microwire™ Compatible –Schmitt Trigger on Serial Clock (SCLK) R/W Calibration Registers Per Channel Selectable Word Rates: 6.25 to 3,840 Sps Selectable 50 or 60 Hz RejectionPower Supply Configurations–VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V–VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V –VA+ = +3 V; VA- = -3 V; VD+ = +3 VGeneral DescriptionThe CS5532/34 are highly integrated ∆Σ Analog-to-Digi-tal Converters (ADCs) which use charge-balance techniques to achieve 24-bit performance. The ADCs are optimized for measuring low-level unipolar or bipolar signals in weigh scale, process control, scientific, and medical applications.To accommodate these applications, the ADCs come as either two-channel (CS5532) or four-channel (CS5534)devices and include a very low-noise, chopper-stabilized instrumentation amplifier (6 nV/√Hz @ 0.1 Hz) with se-lectable gains of 1×, 2×, 4×, 8×, 16×, 32×, and 64×.These ADCs also include a fourth-order ∆Σ modulator followed by a digital filter which provides twenty selectable output word rates of 6.25, 7.5, 12.5, 15, 25, 30, 50, 60, 100,120, 200, 240, 400, 480, 800, 960, 1600, 1920, 3200, and 3840 Sps (MCLK =4.9152MHz).To ease communication between the ADCs and a micro-controller, the converters include a simple three-wire se-rial interface which is SPI™ and Microwire™ compatible with a Schmitt-trigger input on the serial clock (SCLK).High dynamic range, programmable output rates, and flexible power supply options makes these ADCs ideal solutions for weigh scale and process control applications.ORDERING INFORMATIONSee page 47VA+C1C2VREF+VREF-VD+DIFFERENTIAL 4TH ORDER ∆ΣMODULATORPGIA 1,2,4,8,16PROGRAMMABLE SINC FIR FILTERMUX(CS5534SHOWN)AIN1+AIN1-AIN2+AIN2-AIN3+AIN3-AIN4+AIN4-SERIAL INTERFACELATCHCLOCK GENERATORCALIBRATION SRAM/CONTROLLOGICDGNDCSSDI SDO SCLKOSC2OSC1A1A0/GUARD VA-32,64OCT ‘08TABLE OF CONTENTS1.CHARACTERISTICS AND SPECIFICATIONS (4)ANALOG CHARACTERISTICS (4)TYPICAL RMS NOISE (NV) (7)TYPICAL NOISE-FREE RESOLUTION(BITS) (7)5 V DIGITAL CHARACTERISTICS (8)3 V DIGITAL CHARACTERISTICS (8)DYNAMIC CHARACTERISTICS (9)ABSOLUTE MAXIMUM RATINGS (9)SWITCHING CHARACTERISTICS (10)2.GENERAL DESCRIPTION (12)2.1.Analog Input (12)2.1.1. Analog Input Span (13)2.1.2. Multiplexed Settling Limitations (13)2.1.3. Voltage Noise Density Performance (13)2.1.4. No Offset DAC (14)2.2.Overview of ADC Register Structure and Operating Modes (14)2.2.1. System Initialization (15)2.2.2. Serial Port Interface (22)2.2.3. Reading/Writing On-Chip Registers (23)2.3.Configuration Register (23)2.3.1. Power Consumption (23)2.3.2. System Reset Sequence (23)2.3.3. Input Short (24)2.3.4. Guard Signal (24)2.3.5. Voltage Reference Select (24)2.3.6. Output Latch Pins (24)2.3.7. Offset and Gain Select (25)2.3.8. Filter Rate Select (25)2.4.Setting up the CSRs for a Measurement (27)2.5.Calibration (30)2.5.1. Calibration Registers (30)2.5.2. Performing Calibrations (31)2.5.3. Self Calibration (31)2.5.4. System Calibration (32)2.5.5. Calibration Tips (32)2.5.6. Limitations in Calibration Range (33)2.6.Performing Conversions (33)2.6.1. Single Conversion Mode (33)2.6.2. Continuous Conversion Mode (34)2.6.3. Examples of Using CSRs to Perform Conversions and Calibrations (35)ing Multiple ADCs Synchronously (36)2.8.Conversion Output Coding (36)2.9.Digital Filter (38)2.10.Clock Generator (39)2.11.Power Supply Arrangements (39)2.12.Getting Started (43)2.13.PCB Layout (43)3.PIN DESCRIPTIONS (44)4.SPECIFICATION DEFINITIONS (46)5.ORDERING INFORMATION (47)6.ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION (47)7.PACKAGE DRAWINGS (48)LIST OF FIGURESFigure 1. SDI Write Timing (Not to Scale) (11)Figure 2. SDO Read Timing (Not to Scale) (11)Figure 3. Multiplexer Configuration (12)Figure 4. Input models for AIN+ and AIN- pins (13)Figure 5. Measured Voltage Noise Density (13)Figure 6. CS5532/34 Register Diagram (14)Figure 7. Command and Data Word Timing (22)Figure 8. Guard Signal Shielding Scheme (24)Figure 9. Input Reference Model when VRS = 1 (25)Figure 10. Input Reference Model when VRS = 0 (25)Figure 11. Self Calibration of Offset (32)Figure 12. Self Calibration of Gain (32)Figure 13. System Calibration of Offset (32)Figure 14. System Calibration of Gain (32)Figure 15. Synchronizing Multiple ADCs (36)Figure 16. Digital Filter Response (WR = 60 Sps) (38)Figure 18. 120 Sps Filter Phase Plot to 120 Hz (38)Figure 17. 120 Sps Filter Magnitude Plot to 120 Hz (38)Figure 19. Z-Transforms of Digital Filters (38)Figure 20. On-chip Oscillator Model (39)Figure 21. CS5532 Configured with a Single +5 V Supply (40)Figure 22. CS5532 Configured with ±2.5 V Analog Supplies (41)Figure 23. CS5532 Configured with ±3 V Analog Supplies (41)Figure 24. CS5532 Configured for Thermocouple Measurement (42)Figure 25. Bridge with Series Resistors (42)LIST OF TABLESTable 1. Conversion Timing – Single Mode (34)Table 2. Conversion Timing – Continuous Mode (35)Table 3. Command Byte Pointer (35)Table 4. Output Coding for 24-bit CS5532 and CS5534 (37)1. CHARACTERISTICS AND SPECIFICATIONSANALOG CHARACTERISTICS(VA+, VD+ = 5 V ±5%; VREF+ = 5 V; VA-, VREF-, DGND = 0 V; MCLK = 4.9152 MHz; OWR (Output Word Rate) = 60 Sps; Bipolar Mode; Gain = 32)(See Notes 1 and 2.)Notes: 1.Applies after system calibration at any temperature within -40 °C ~ +85 °C.2.Specifications guaranteed by design, characterization, and/or test. LSB is 24 bits.3. This specification applies to the device only and does not include any effects by external parasiticthermocouples. The PGIA contributes 5 nV of offset drift, and the modulator contributes 640/G nV of offset drift, where G is the amplifier gain setting.4.Drift over specified temperature range after calibration at power-up at 25 °C.ParameterMin Typ Max Unit Accuracy Linearity Error -±0.0007±0.0015%FS No Missing Codes 24--Bits Bipolar Offset -±16±32LSB 24Unipolar Offset-±32±64LSB 24Offset Drift(Notes 3 and 4)-640/G +5-nV/°C Bipolar Full-scale Error -±8±31ppm Unipolar Full-scale Error -±16±62ppm Full-scale Drift(Note 4)-2-ppm/°CANALOG CHARACTERISTICS (Continued)(See Notes 1 and 2.)Notes: 5.The voltage on the analog inputs is amplified by the PGIA, and becomes V CM ± Gain*(AIN+ - AIN-)/2 atthe differential outputs of the amplifier. In addition to the input common mode + signal requirements for the analog input pins, the differential outputs of the amplifier must remain between (VA- + 0.1 V) and (VA+ - 0.1 V) to avoid saturation of the output stage.6.See the section of the data sheet which discusses input models.7.Input current on AIN+ or AIN- (with Gain =1), or VREF+ or VREF- may increase to 250nA if operatedwithin 50mV of VA+ or VA-. This is due to the rough charge buffer being saturated under these conditions.ParameterMin TypMaxUnitAnalog InputCommon Mode + Signal on AIN+ or AIN-Bipolar/Unipolar ModeGain = 1 Gain = 2, 4, 8, 16, 32, 64(Note 5)VA-VA- + 0.7--VA+VA+ - 1.7V V CVF Current on AIN+ or AIN-Gain = 1 (Note 6, 7)Gain = 2, 4, 8, 16, 32, 64--501200--nA pA Input Current Noise Gain = 1 Gain = 2, 4, 8, 16, 32, 64--2001--pA/√Hz pA/√Hz Input Leakage for Mux when Off (at 25 °C)-10-pA Off-channel Mux Isolation -120-dB Open Circuit Detect Current 100300-nA Common Mode Rejection dc, Gain = 1dc, Gain = 6450, 60 Hz ---90130120---dB dB dB Input Capacitance -60-pF Guard Drive Output -20-µA Voltage Reference Input Range (VREF+) - (VREF-)1 2.5(VA+)-(VA-)V CVF Current (Note 6, 7)-50-nA Common Mode Rejection dc 50, 60 Hz --120120--dB dB Input Capacitance 11-22pF System Calibration Specifications Full-scale Calibration Range Bipolar/Unipolar Mode 3-110%FS Offset Calibration Range Bipolar Mode -100-100%FS Offset Calibration Range Unipolar Mode -90-90%FSANALOG CHARACTERISTICS (Continued)(See Notes 1 and 2.)8.All outputs unloaded. All input CMOS levels.9.Power is specified when the instrumentation amplifier (Gain ≥ 2) is on. Analog supply current is reducedby approximately 1/2 when the instrumentation amplifier is off (Gain = 1).10.Tested with 100 mV change on VA+ or VA-.ParameterMinTypMaxUnitPower SuppliesDC Power Supply Currents (Normal Mode)I A+, I A-I D+- - 130.5151mA mA Power ConsumptionNormal Mode (Notes 8 and 9)Standby Sleep---70450080--mW mW µW Power Supply Rejection (Note 10)dc Positive Supplies dc Negative Supply--115115--dB dBTYPICAL RMS NOISE (nV)(See notes 11, 12, 13 and 14)Notes:11.The -B devices provide the best noise specifications.12.Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25 °C.13.For Peak-to-Peak Noise multiply by 6.6 for all ranges and output rates.14.Word rates and -3dB points with FRS = 0. When FRS = 1, word rates and -3dB points scale by 5/6.TYPICAL NOISE-FREE RESOLUTION(BITS)(See Notes 15 and 16)15.Noise-free resolution listed is for bipolar operation, and is calculated as LOG((Input Span)/(6.6xRMSNoise))/LOG(2) rounded to the nearest bit. For unipolar operation, the input span is 1/2 as large, so one bit is lost. The input span is calculated in the analog input span section of the data sheet. The noise-free resolution table is computed with a value of 1.0 in the gain register. Values other than 1.0 will scale the noise, and change the noise-free resolution accordingly.16.“Noise-free resolution” is not the same as “effective resolution”. Effective resolution is based on theRMS noise value, while noise-free resolution is based on a peak-to-peak noise value specified as 6.6 times the RMS noise value. Effective resolution is calculated as LOG((Input Span)/(RMS Noise))/LOG(2).Specifications are subject to change without notice.Output Word Rate (Sps)-3 dB Filter Frequency (Hz)Instrumentation Amplifier Gain x64x32x16x8x4x2x17.5 1.948.59101526509915 3.88121315213770139307.751718213052991966015.524252942731402771203134364259103198392240628013626051410202050409048012211319436973014502900581096023015927452310302060411082301,920390260470912181036207230145003,84078013602690538010800215004300086000Output Word Rate (Sps)-3 dB Filter Frequency (Hz)Instrumentation Amplifier Gainx64x32x16x8x4x2x17.5 1.942021222323232315 3.8820212222222222307.75192021222222226015.5192021212121211203118192021212121240621717181818181848012217171717171717960230161617171717171,920390161616161616163,840780131313131313135 V DIGITAL CHARACTERISTICS(VA+, VD+ = 5 V ±5%; VA-, DGND = 0 V; See Notes 2 and 17.)3 V DIGITAL CHARACTERISTICS(T A = 25 °C; VA+ = 5V ±5%; VD+ = 3.0V±10%; VA-, DGND = 0V; See Notes 2 and 17.)17.All measurements performed under static conditions.ParameterSymbol Min Typ Max Unit High-level Input Voltage All Pins Except SCLKSCLK V IH 0.6 VD+(VD+) - 0.45--VD+VD+V Low-level Input Voltage All Pins Except SCLKSCLK V IL 0.00.0-0.80.6V High-level Output Voltage A0 and A1, I out = -1.0 mASDO, I out = -5.0 mA V OH (VA+) - 1.0(VD+) - 1.0--V Low-level Output Voltage A0 and A1, I out = 1.0 mASDO, I out = 5.0 mAV OL --(VA-) + 0.40.4V Input Leakage Current I in -±1±10µA SDO Tri-State Leakage Current I OZ --±10µA Digital Output Pin CapacitanceC out-9-pFParameterSymbol Min Typ Max Unit High-level Input Voltage All Pins Except SCLKSCLK V IH 0.6 VD+(VD+) - 0.45-VD+VD+V Low-level Input Voltage All Pins Except SCLKSCLK V IL 0.00.0-0.80.6V High-level Output Voltage A0 and A1, I out = -1.0 mASDO, I out = -5.0 mA V OH (VA+) - 1.0(VD+) - 1.0--V Low-level Output Voltage A0 and A1, I out = 1.0 mASDO, I out = 5.0 mAV OL --(VA-) + 0.40.4V Input Leakage Current I in -±1±10µA SDO Tri-State Leakage Current I OZ --±10µA Digital Output Pin CapacitanceC out-9-pFDYNAMIC CHARACTERISTICS18.The ADCs use a Sinc 5 filter for the 3200 Sps and 3840 Sps output word rate (OWR) and a Sinc 5 filterfollowed by a Sinc 3 filter for the other OWRs. OWR sinc5 refers to the 3200 Sps (FRS = 1) or 3840 Sps (FRS = 0) word rate associated with the Sinc 5 filter.19.The single conversion mode only outputs fully settled conversions. See Table 1 for more details aboutsingle conversion mode timing. OWR SC is used here to designate the different conversion time associated with single conversions.20.The continuous conversion mode outputs every conversion. This means that the filter’s settling timewith a full scale step input in the continuous conversion mode is dictated by the OWR.ABSOLUTE MAXIMUM RATINGS(DGND = 0 V; See Note 21.)Notes:21.All voltages with respect to ground.22.VA+ and VA- must satisfy {(VA+) - (VA-)} ≤ +6.6 V.23.VD+ and VA- must satisfy {(VD+) - (VA-)} ≤ +7.5 V.24.Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pins.25.Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power supply pin is ±50 mA.26.Total power dissipation, including all input currents and output currents.WARNING:Operation at or beyond these limits may result in permanent damage to the device.Normal operation is not guaranteed at these extremes.ParameterSymbol Ratio Unit Modulator Sampling Ratef s MCLK/16Sps Filter Settling Time to 1/2 LSB (Full Scale Step Input)Single Conversion mode (Notes 18, 19, and 20)Continuous Conversion mode, OWR < 3200 Sps Continuous Conversion mode, OWR ≥ 3200 Spst s t s t s1/OWR SC5/OWR sinc5 + 3/OWR5/OWRs s sParameterSymbol Min Typ Max Unit DC Power Supplies(Notes 22 and 23)Positive Digital Positive Analog Negative Analog VD+VA+VA--0.3-0.3+0.3---+6.0+6.0-3.75V V V Input Current, Any Pin Except Supplies (Notes 24 and 25)I IN --±10mA Output Current I OUT--±25mA Power Dissipation (Note 26)PDN --500mW Analog Input Voltage VREF pins AIN PinsV INR V INA (VA-) -0.3(VA-) -0.3--(VA+) + 0.3(VA+) + 0.3V V Digital Input VoltageV IND -0.3-(VD+) + 0.3V Ambient Operating Temperature T A -40-85°C Storage Temperature T stg-65-150°CSWITCHING CHARACTERISTICS(VA+ = 2.5 V or 5 V ±5%; VA- = -2.5V±5% or 0 V; VD+ = 3.0 V ±10% or 5 V ±5%;DGND = 0 V; Levels: Logic 0 = 0 V, Logic 1 = VD+; C L = 50 pF; See Figures 1 and 2.)Notes:27.Device parameters are specified with a 4.9152 MHz clock.28.Specified using 10% and 90% points on waveform of interest. Output loaded with 50pF.29.Oscillator start-up time varies with crystal parameters. This specification does not apply when using anexternal clock source.ParameterSymbol Min Typ MaxUnitMaster Clock Frequency (Note 27)External Clock or Crystal OscillatorMCLK1 4.91525MHz Master Clock Duty Cycle 40-60%Rise Times(Note 28)Any Digital Input Except SCLKSCLKAny Digital Output t rise-----50 1.0100-µs µs ns Fall Times(Note 28)Any Digital Input Except SCLKSCLKAny Digital Output t fall-----50 1.0100-µs µs ns Start-upOscillator Start-up Time XTAL = 4.9152 MHz(Note 29)t ost-20-ms Serial Port Timing Serial Clock Frequency SCLK 0-2MHz Serial Clock Pulse Width High Pulse Width Lowt 1t 2250250----ns nsSDI Write TimingCS Enable to Valid Latch Clock t 350--ns Data Set-up Time prior to SCLK rising t 450--ns Data Hold Time After SCLK Rising t 5100--ns SCLK Falling Prior to CS Disable t 6100--nsSDO Read Timing CS to Data Validt 7--150ns SCLK Falling to New Data Bit t 8--150ns CS Rising to SDO Hi-Zt 9--150ns分销商库存信息:CIRRUS-LOGICCS5532-BSZR CS5534-BSZR CDB5532U。

士兰微SL库存型号推荐---赛矽电子何小姐

士兰微SL库存型号推荐SA7527(料管)士兰微SOP-8 1000SA1117BH-1.8TR 士兰微SOT-223 20000/箱 2500/盘SA1117BH-3.3TR 士兰微SOT-223 20000/箱 2500/盘SA1117BH-2.5TR 士兰微SOT-223 20000/箱 2500/盘SA1117BH-5.0TR 士兰微SOT-223 20000/箱 2500/盘SA1117BH-ADJTR 士兰微SOT-223 20000/箱 2500/盘SD4840P67K65 士兰微DIP-8 2000/盒SD4841P67K65 士兰微DIP-8 2000/盒SD4842P67K65 士兰微DIP-8 2000/盒SD4843P67K65 士兰微DIP-8 2000/盒SD45215 士兰微SOP-8 25000/箱 2500/盘SD4844P67K65 士兰微DIP-8 2000/盒SD4870TR 士兰微SOT23-6 3000/盘SC5272 士兰微TO-22OF 1000SC5262 士兰微TO-22OF 1000SD42522 士兰微SOP-8 2500/盘SD42525E 士兰微SOT89 2500/盘SA7527(盘装)士兰微SOP-8 2500/盘SDH6802 士兰微DIP-8 2000/盒SD6863 士兰微DIP-8 2000/盒SD6861P 士兰微DIP-8 2000/盒GB45215 士兰微SOP-8 25000/箱 2500/盘SD6834 士兰微DIP-8 2000/盒SD6832 士兰微DIP-8 2000/盒SD6864 士兰微DIP-8 2000/盒SD6953B 士兰微SOT-6 3000/盘WY0365 士兰微DIP-8 2000/盒SD45216 士兰微SOP-8 25000/箱 2500/盘SA1117BH-1.2TR 士兰微SOT-223 25000/箱 2500/盘SD6834G 士兰微DIP-8 2000/盒SD45214 士兰微SOP-8 25000/箱 2500/盘SD6835 士兰微DIP-8 2000/盒SD42527 士兰微SOP-8 2500/盘SD42560E 士兰微ESOP-8 2500/盘SC8113 士兰微TO-22OF 1000SD6834B 士兰微DIP-8 2000/盒SD7530S 士兰微SOP-8 2500/盘SD45217 士兰微SOP-8 2500SD6900 士兰微SOT-6 3000/盘SD4871 士兰微SOT-23-6 3000/盘SD6800 士兰微SOP-8 盘SD6901S 士兰微SOP-8 盘SD6902S 士兰微SOP-8 盘SA1117BH-1.5TR 士兰微SOT-223 2500/盘SA9801 士兰微SOP-20 100SD6857 士兰微SOP-8 3000SD6954 士兰微DIP-8 2000SD6830 士兰微DIP-8 2000SVD1N60B 士兰微TO-92 2000/盒SVD1N60DB 士兰微TO-92 2000/盒SVD2N60F 士兰微TO-22OF 5000/箱/ 1000/盒SVD2N65F 士兰微TO-22OF 5000/箱/ 1000/盒SVD4N60F 士兰微TO-22OF 5000/箱/ 1000/盒SVD4N65F 士兰微TO-22OF 5000/箱/ 1000/盒SVD7N65AF 士兰微TO-22OF 1000/盒SVD10N65F 士兰微TO-22OF 5000/箱/ 1000/盒SVD10N60F 士兰微TO-22OF 5000/箱/ 1000/盒SBD20C100T 士兰微TO-220T 5000/箱/ 1000/盒SBD20C100F 士兰微TO-22OF 5000/箱/ 1000/盒SVD1N60M 士兰微TO-251 24000/箱 4800/盒SVD1N60M(J)士兰微TO-251 4500/盒SVD12N65F 士兰微TO-22OF 5000/箱/ 1000/盒SVD12N60F 士兰微TO-22OF 5000/箱/ 1000/盒SVD2N60M 士兰微TO-251 24000/箱 4800/盒SVD2N60M(J) 士兰微TO-251 4500/盒SFR16S20T 士兰微TO-220T 5000/箱/ 1000/盒SBD10C100F 士兰微TO-22OF 5000/箱/ 1000/盒SBD10C150T 士兰微TO-220T 5000/箱/ 1000/盒SBD10C100T 士兰微TO-220T 5000/箱/ 1000/盒SVD5N60F 士兰微TO-22OF 5000/箱/ 1000/盒SFR20S20T 士兰微TO-220T 5000/箱/ 1000/盒SVF1N60N 士兰微TO-126 200/包SVF10N60F 士兰微TO-22OF 5000/箱/ 1000/盒SVD8N60F 士兰微TO-22OF 5000/箱/ 1000/盒SVF2N60F 士兰微TO-22OF 5000/箱/ 1000/盒SVF4N60D 士兰微TO-252 2500/盘SVF4N65F 士兰微TO-22OF 5000/箱/ 1000/盒SVF4N65M 士兰微TO-251 24000/箱 4800/盒SVF5N60F 士兰微TO-22OF 5000/箱/ 1000/盒SVF8N60F 士兰微TO-22OF 5000/箱/ 1000/盒SVF7N80F 士兰微TO-22OF 5000/箱/ 1000/盒SVF7N60F 士兰微TO-22OF 5000/箱/ 1000/盒SVF12N60F 士兰微TO-22OF 5000/箱/ 1000/盒SVF840F 士兰微TO-22OF 5000/箱/ 1000/盒SVF7N65F 士兰微TO-22OF 5000/箱/ 1000/盒SVF10N65F 士兰微TO-22OF 5000/箱/ 1000/盒SVF2N60MJ 士兰微TO-251 4500/盒SVF2N70M 士兰微TO-251 24000/箱 4800/盒SVF13N60AF 士兰微TO-22OF 1000/盒SVD2N60MJ 士兰微TO-251 4500/盒SVF12N65F 士兰微TO-22OF 5000/箱/ 1000/盒SVF2N60N 士兰微TO-126 3000/盒 200/包SVF5N60D 士兰微TO-252 2500/盘SVF13N50F 士兰微TO-22OF 5000/箱/ 1000/盒SVF4N70F 士兰微TO-22OF 5000/箱/ 1000/盒SVF2N60M 士兰微TO-251 24000/箱 4800/盒SVF9N90F 士兰微TO-22OF 5000/箱/ 1000/盒SVF4N90F 士兰微TO-, 22OF 5000/箱/ 1000/盒SVF2N65F 士兰微TO-22OF 5000/箱/ 1000/盒SVF4N65D 士兰微TO-252 2500/盘SVF830F 士兰微TO-22OF 5000/箱/ 1000/盒SBD20C45T 士兰微TO-220T 5000/箱/ 1000/盒SVF20N60F 士兰微TO-22OF 5000/箱/ 1000/盒SVF1N60B 士兰微TO-92 2000/盒SVD7N60F 士兰微TO-22OF 5000/箱/ 1000/盒SVF830T 士兰微TO-220F 5000/箱SVD830T 士兰微TO-220T 10SVF2N60D 士兰微TO-252 2500SVF3N80F 士兰微TO-220F 1000/盘SVF4N60F 士兰微TO-220F 1000SBD20C150T 士兰微TO-220T 1000/盒SVF4N65MJ 士兰微TO-251 4500/盒SVF4N65M(S) 士兰微TO-251 4500/盒SVF2N60M(S) 士兰微TO-251 4800PCS/盒SBD20C150F 士兰微TO-220F 1000SVD2N70M 士兰微TO-251 4500/盒SVF1N60D 士兰微TO-252 2500/盒SVF8N80F 士兰微TO-220F 1000/盒SBD10C200F 士兰微TO-220F 1000/盒SBD20C200F 士兰微TO-220F 1000/盒SVF1N60M(S) 士兰微TO-251 80/管SVF4N60EF 士兰微TO-220F 1000/盒SVF5N60MJ 士兰微TO-251 4500/盒SFR10S40T 士兰微TO-220 50 SBD20C45F 士兰微TO-220 1000/盒SA7527STR 士兰微SOP-8 2500/盘。

TM7715

16 bit 模数转换器一、概述TM7715TM7715 是应用于低频测量的 2/3 通道的模拟前端。

该器件可以接受直接来自传感器的低电平的输入信号，然后产生串行的数字输出。

利用 Σ-∆ 转换技术实现了 16 位无丢失代码性能。

选定的输入信号被送到一个基于模拟调制器的增益可编程专用前端。

片内数字滤波器处理调制器的输出信号。

通过片内控制寄存器可调节滤波器的截止点和输出更新速率，从而对数字滤波器的第一个陷波进行编程。

TM7715 只需 2.7~3.3V 或 4.75~5.25V 单电源。

TM7715 是单通道全差分模拟输入，带有一个差分基准输入。

当电源电压为 5V、基准电压为 2.5V 时，该器件都可将输入信号范围从 0~+20mV 到 0~+2.5V 的信号进行处理。

还可处理 ±20mV~±2.5V 的双极性输入信号，对于 TM7715 是以 AIN （-）输入端为参考点。

当电源电压为 3V、基准电压为 1.225V 时，可处理 0~+10mV 到 0~+1.225V 的单极性输入信号，它的双极性输入信号范围是±10mV 到±1.225V。

因此， TM7715 可以实现单通道系统所有信号的调理和转换。

TM7715 是用于智能系统、微控制器系统和基于 DSP 系统的理想产品。

其串行接口可配置为三线接口。

增益值、信号极性以及更新速率的选择可用串行输入口由软件来配置。

该器件还包括自校准和系统校准选项，以消除器件本身或系统的增益和偏移误差。

CMOS 结构确保器件具有极低功耗，掉电模式减少等待时的功耗至 20µW （典型值）。

TM7715 采用 16 脚塑料双列直插（DIP）和 16 脚宽体（0.3 英寸） SOIC 封装和 16 脚 TSSOP 封装。

二、特点TM7715：1 个全差分输入通道的 ADC 16 位无丢失代码 0.003%非线性可编程增益前端增益：1～128 三线串行接口有对模拟输入缓冲的能力 2.7～3.3V 或 4.75～5.25V 工作电压 3V 电压时，最大功耗为 1mW 等待电流的最大值为 8µA 16 脚 DIP、SOIC 和 TSSOP 封装©Titan Micro Electronics-1-16 bit 模数转换器三、功能方框图TM7715四、引脚排列与功能TM7715 的引脚排列©Titan Micro Electronics-2-16 bit 模数转换器五、引脚功能编号名称功能TM77151SCLK串行时钟，施密特逻辑输入。

Mellanox InfiniBand路由器SB7780和SB7880的产品介绍说明书

©2020 Mellanox Technologies. All rights reserved.†For illustration only. Actual products may vary.SB7780 and SB7880 InfiniBand routers enable new levels of subnets isolation and compute-to-storage connectivity, critical to large-scale and diverse data-centers.Scaling-Out Data Centers with EDR 100G InfiniBandHigh Performance Computing (HPC), Artificial Intelligence (AI), and Data-Intensive and Cloud infrastructures all leverage InfiniBand’s high data throughput, extremely low latency, and smart In-Network Computing acceleration engines to deliver world-leading application performance and scalability, while reducing operational costs and infrastructure complexity. Mellanox’s innovative In-Networking-based Scalable Hierarchical Aggregation and Reduction Protocol (SHARP)™ technology enables the acceleration of communications frameworks using embedded hardware, resulting in order of magnitude application and performance improvements.In cases where the separation between InfiniBand subnets and keeping connectivity to a central InfiniBand Storage are required, InfiniBand Routers are the ideal solution.Sustained Network PerformanceSB7780 / SB7880 InfiniBand routers are based on Switch-IB ® / Switch-IB ® 2 ASICs, respectively. They offer fully-flexible 36 EDR 100Gb/s ports that can be split among several different subnets. InfinBand routers bring two major enhancements to the Mellanox InfiniBand portfolio:•Increase resiliency by s plitting the data center’s network into several subnets; each subnet runs itsown subnet manager, effectively isolating each subnet from the others’ availability or instability •Enable multiple compute to storage connections while separately isolating login access to each compute subnetWorld-Class DesignSB7780 / SB7880 InfiniBand routers are elegantly designed for performance, serviceability, energy savings and high-availability. They come equipped with two highly efficient, 80 gold+ and energy star certified, power supplies.Their best-in-class design enables the EDR IB routers to support low power consumption, with ATIS weighted power consumption as low as 122W for a fully populated system. This means more power reduction if not all ports are used or fully utilized.SB7780 / SB7880 also have redundant power supplies (1+1) and their fans draw (N+1) both with air shutters for achieving maximal thermal protection.36-port Non-blocking Managed EDR 100Gb/s InfiniBand RoutersInfiniBand EDR 100Gb/s RoutersPRODUCT BRIEFSWITCH SYSTEM †© Copyright 2020. Mellanox Technologies. All rights reserved. Mellanox, Mellanox logo, MLNX-OS , Switch-IB, and UFM are registered trademarks of Mellanox Technologies, Ltd. Switch-IB, UFM and Unified Fabric Manager are trademarks of Mellanox Technologies, Ltd. All other trademarks are property of their respective owners.350 Oakmead Parkway, Suite 100, Sunnyvale, CA 94085Tel: 408-970-3400 • Fax: Mellanox SB7700 and SB7880 InfiniBand Routerspage 2ManagementThe InfiniBand router’s dual-core x86 CPU runs MLNX-OS ® software package, which delivers complete chassis management of the router’s firmware, power supplies, fans and ports. The router can also becoupled with Mellanox’s Unified Fabric Manager (UFM ®) platforms to manage scale-out InfiniBand computing environments.Revolutionizing data center management, the UFM family of products combine enhanced, real-time network telemetry with AI-poweredcyber intelligence and analytics. The UFM solutions minimize downtime by enabling system admins to quickly detect and respond to potential security threats and operational issues, and predict upcoming failures.Mellanox SB7780 / SB7880–19’’ rack mountable 1U chassis –36 QSFP28 non-blocking ports with aggregate data throughput up to 7Tb/s (EDR)Router Specifications–Compliant with IBTA 1.21 and 1.3 –9 virtual lanes: 8 data + 1 management–256 to 4Kbyte MTU–8X 48K entry linear forwarding databaseManagement Ports–100/1000Mb/s Ethernet ports –RS232 port over DB9–USB port –DHCP–Familiar Industry Standard CLI –Management over IPv6 –Management IP –SNMP v1,v2,v3 –Web UIFabric Management–Unified Fabric Manager (UFM™) AgentConnectors and Cabling–QSFP28 connectors–Passive copper or active fiber cables –Optical modulesIndicators–Per port status LED Link, Activity –System status LEDs: System, fans, power supplies –Port Error LED –Unit ID LEDPhysical Characteristics–Dimensions: 1.7’’ (43.6 mm) H x 16.85’’ (428mm) W x 27’’ (685.8mm) D –Weight: 11kg (24.2lb)Power Supply–Dual redundant slots –Hot plug operation –Input range:100-127 VAC, 200-240VAC–Frequency: 50-60Hz, single phase AC, 4.5A, 2.9ACooling–Front-to-rear or rear-to-front cooling option–Hot-swappable fan unitPower Consumption–Typical Power with Passive Cables (ATIS): 136WFEATURESSafety–CB –cTUVus –CE –CUEMC (Emissions)–CE –FCC–VCCI –ICES –RCMOperating Conditions–Temperature:–Operating 0ºC to 45ºC–Non-operating -40ºC to 70ºC–Humidity:–Operating 10% to 85% non-condensing–Non-operating 10% to 90% non-condensing–Altitude: Operating -60m to 3200mAcoustic–ISO 7779 –ETS 300 753Others–RoHS compliant –Rack-mountable, 1U –1-year warrantyCOMPLIANCETable 1 - Part Numbers and Descriptions*P 2C is connector side outlet; C 2P is connector side inlet.15-7858PB Rev 1.3。

ST778资料

1/11October 2002s1V TO 6V INPUT GUARANTEES START-UP UNDER LOADsMAXIMUM OUTPUT CURRENT OF 300mA (778OR 779ADJUSTED TO 3V)sLOAD FULLY DISCONNECTED IN SHUTDOWNs TYPICAL EFFICIENCY OF 82%sINTERNAL 1A POWER SWITCH AND SYNCHRONOUS RECTIFIERsADJUSTABLE CURRENT LIMIT ALLOWS LOW-COST INDUCTORSs SUPPLY CURRENT OF 270µA (NO LOAD)s SHUTDOWN SUPPLY CURRENT 20µA sPACKAGE AVAILABLE:DIP-8AND SO-8DESCRIPTIONThe ST777/778/779are dc-dc converters that step-up from low voltage inputs requiring only three external components,an inductor (typically 22µH)and two capacitors.The device include a Sinchronous Rectifier that eliminates the need for an external catch diode,and allows regulation even when the input is greater than the output.Unlike others step-up DC-DC converters the ST777/778/779’s Sinchronous Rectifier turns off in the shutdown mode,fully disconnecting the output from the source.This eliminates the current drain associated with conventional step-up converters when off or in shutdown.Supply current is 270µA under no load and only 20µA in stand by mode.ST777/778/779LOW VOLTAGE INPUT,3-3.3V/5V/ADJUSTABLE OUTPUT DC-DC CONVERTER WITH SYNCHRONOUS RECTIFIERV INV O22µH100µF100µFR LIMI LIM L XINOUT PGND SEL AGND12345678SHDN1.25VVREFSHUTDOWN CONTROLDELAY TIMERDELAY TIMERt OFFt ONSWITCH DRIVERACTIVE RECTIFIERRECTIFIER CONTROL1:NSCHEMATIC DIAGRAMST777/778/7792/11ABSOLUTE MAXIMUM RATINGSAbsolute Maximum Ratings are those values beyond which damage to the device may occur.Functional operation under these condition is not implied.ORDERING CODESCONNECTION DIAGRAMPIN CONNECTIONSTHERMAL DATASymbol ParameterValue Unit V CCDC Input Voltage to GND -0.3to +7V LXSwitch off Pin Voltage -0.3to +7V Switch on Pin Voltage 30sec short to IN or OUTOUT,SHDN Output,Shutdown Voltage -0.3to +7V AGND to PGNDAnalog and Power Ground -0.3to +0.3V FBFB Pin Voltage-0.3to (OUT+0.3)V P TOT Continuous Power Dissipation (at T A =85°C)DIP-8550mW Continuous Power Dissipation (at T A =85°C)SO-8344T STG Storage Temperature Range-40to 150°C T OPOperating Ambient Temperature Range0to 85°CTYPE DIP-8SO-8ST777ST777ACN ST777ACD ST778ST778ACN ST778ACD ST779ST779ACNST779ACDPin No.SYMBOL NAME AND FUNCTION1ILIM Sets switch current limit input.Connect to IN for 1A current limit.A resistor from ILIM to IN sets lower peak inductor currents.2IN Input from battery3AGND Analog ground.Not internally connected to PGND.4PGND Power ground.Must be low impedance;solder directly to ground plane or star ground.Connect to AGND,close to the device.5LX Collector of 1A NPN power switch and emitter of Sinchronous Rectifier PNP .6OUT Voltage Output.Connect filter capacitor close to pin.7SHDNShutdown input disables power supply when low.Also disconnets load from input.Threshold is set at V IN /2.8SEL/N.C./FB -Selection pin for 3/3.3V version (778);-Not internally connected for 5V version (777);-Feedback pin for adjustable version (779).Symbol ParameterDIP-8SO-8Unit R thj-ambThermal Resistance Junction-ambient100160°C/WST777/778/7793/11ELECTRICAL CHARACTERISTICS (V IN =2.5V,C I =22µF,C O =100µF,SHDN and ILIM connected to IN,AGND connected to PGND,T A =0to 85°C,unless otherwise specified.Typical values are referred at T A =25°C)Note 1:Output in regulation,V OUT =V OUT (nominal)± 4%.Note 2:At hight V IN to V OUT differentials,the maximum load current is limited by the maximum allowable power dissipation in the package.Note 3:Start-up guaranteed under these load conditions.Note 4:Minimum value is production tested.Maximum value is guaranteed by design and is not production tested.Note 5:In the ST779supply current depends on the resistor divider used to set the output voltage.Note 6:V OUT is set to a target value of +5V by 0.1%external feedback resistors.V OUT is measured to be 5V±2.5%to guarantee the error comparator trip point.Symbol Parameter Test ConditionsMin.Typ.Max.Unit V START Start up Voltage I LOAD <10mA,T A =25°C (Note 1)1V V IN(MAX)Maximum Input Voltage (Note 1,2)6V V OOutput Voltage ST777779(set to 5V),(Note 3)I LOAD ≤ 30mA,V IN = 1.1V to 5V or I LOAD ≤ 80mA,V IN = 1.8V to 5V or I LOAD ≤ 130mA,V IN = 2.4V to 5V 4.85.05.2VOutput Voltage ST778(Note 3)SEL=0VI LOAD ≤ 50mA,V IN =1.1V to 3.3V or I LOAD ≤ 210mA,V IN =1.8V to 3.3V or I LOAD ≤ 300mA,V IN =2.4V to 3.3V 3.17 3.30 3.43VSEL=OPENI LOAD ≤ 30mA,V IN =1.1V to 3V or I LOAD ≤ 210mA,V IN =1.8V to 3V or I LOAD ≤ 300mA,V IN =2.4V to 3V2.883.00 3.12VOutput Voltage Range ST779(Note 4)2.76.5V I IN No Load Supply Current I LOAD =0mA,(Switch ON)(Note 5)270µAI SHDN Shutdown Supply Current SHDN=0V,(Switch OFF)2035µA I IN SHDNShutdown Input Current SHDN =0to V IN 15100nA SHDN =V IN to 5V 1240µA υEfficiencyI LOAD =100mA 82%V IH Shutdown Input Threshold V IN =1V to 6VV IN /2+0.25V I LIMCurrent Limit1.0A I LIM TEMPCO Current Limit TemperatureCoefficient-0.3%/°C t OFFMIN Minimum Switch Off Time 1.2µst ONMAXMaximum Switch ON TimeV IN =2.5V 4.5V IN =1.8V 6.5V IN =1V15V CESAT NPN Switch saturation VoltageI SW =400mA 0.25VI SW =600mA 0.33I SW =1000mA0.5V CESAT NPN Rectifier Forward DropI SW =400mA 0.18V I SW =600mA 0.22I SW =1000mA0.4V FB Error Comparator Trip Point ST779,over operating inputvoltage (Note 6)1.23±2%V I FB FB Pin Bias Current ST779,V FB =1.3V 50nA I LXSwitch Off Leakage Current 0.1µA Rectifier Off Leakage Current0.1µAST777/778/7794/11TYPICAL APPLICATION CIRCUITAPPLICATIONS INFORMATIONR1and R2must be placed only in ST779applications to set the output voltage according to the following equation:V OUT =(1.23)[(R1+R2)/R2]and to simplify the resistor selection:R1=R2[(V OUT /1.23)-1]It is possible to use a wide range of values for R2(10K Ωto 50K Ω)with no significant loss of accuracy thanks to the very low FB input current.To have 1%error,the current through R2must be at least 100times FB’s bias current.When large values are used for the feedback resistors (R1>50K Ω),stray output impedance at FB can incidentally add "lag"to the feedback response,destabilizing the regulator and creating a larger ripple at the output.Lead lengths and circuit board traces at the FB node should be kept pensate the loop by adding a "lead"compensation capacitor (C3,100pF to 1nF)in parallel with R1.The typical value of the L1inductor is 22µH,enough for most applications.However,are also suitable values ranging from 10µF to 47µF with a saturation rating equal to or greater than the peak switch -current limit.Efficiency will be reduced if the inductor works near its saturation limit,while will be maximized using an inductor with a low DC resistance,preferably under 0.2Ω.Connecting ILIM to V IN the maximum LX current limit (1A)is set.If this maximum value is not required is possible to reduce it connecting a resistor between ILIM and V IN (See Figure 16to choose the right value).The current limit value is misured when the switch current through the inductor begins to flatten and does’nt coincide with the max short circuit current.Even if the device is designed to tolerate a short circuit without any damage,it is strictly recommended to avoid a continuos and durable short circuit of the output to GND.To achieve the best performances from switching power supply topology,particular care to layout drawing is needed,in order to minimize EMI and obtain low noise.Moreover,jitter free operation ensures the full device functionality.Wire lengths must be minimized,filter and by-pass capacitors must be low ESR type,placed as close as possible to the integrated circuit.Solder AGND and PGND pins directly to a ground plane.ST777/778/7795/11TYPICAL CHARACTERISTICS (unless otherwise specified T j =25°C,C I =22µF,C O =100µF)Figure 1:Output Voltage vs TemperatureFigure 2:Output Voltage vs Temperature Figure 3:Efficiency vs Temperature Figure 4:Efficiency vs Input VoltageFigure 5:Efficiency vs Output CurrentFigure 6:Efficiency vs Low OutputCurrentST777/778/7796/11Figure 7:No Load Supply Current vs Input VoltageFigure 8:No Load Supply Current vs Temperature Figure 9:Shutdown Input Threshold vs Input VoltageFigure 10:Minimum Switch Off Time vs TemperatureFigure 11:Maximum Switch ON Time vs TemperatureFigure 12:FB Pin Bias Current vsTemperatureST777/778/7797/11Figure 13:Error Comparator Trip Point vs TemperatureFigure 14:Maximum Output Current vs Input Voltage Figure 15:Maximum Output Current vs Input VoltageFigure 16:Peak Inductor Current vs Current-LimitResistorST777/778/7798/11Figure 17:Line TransientFigure 18:Load Transient Figure 19:Switching WaveformFigure 20:Switching WaveformPRINTED DEMOBOARD (Not in scale)VoutVinVout (5V)IoutST777/779Vin=2.5VIout=10m A to 130m AVoutIswVin=1.1V Iout=30mAVoutIswVin=2.5VIout=30mA元器件交易网ST777/778/779 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result fromits use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specificationsmentioned in this publication are subject to change without notice. This publication supersedes and replaces all informationpreviously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices orsystems without express written approval of STMicroelectronics.© The ST logo is a registered trademark of STMicroelectronics© 2002 STMicroelectronics - Printed in Italy - All Rights ReservedSTMicroelectronics GROUP OF COMPANIESAustralia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - MoroccoSingapore - Spain - Sweden - Switzerland - United Kingdom - United States.© 11/11。

ADE7753中文用户手册

除了 PGA，通道 1 还为 ADC 的满量程输入范围做选择。ADC 模拟输入的范围选择也是使用增益寄存器——见图 32。正如前面提到，最大差动输入电压为 0.5 V。但是，通过使用增益寄存器中的 3 和 4 位，最大的 ADC 输入的电压可以设置为 0.5 V、 0.25 V 或 0.125 V。这是通过调整 ADC 参考实现。——请参阅 ADE7753 参考电路部分。表 5 总结了在通道 1 上不同的 ADC 范围最大差动输入的信号级别和增益的选择。
ADE7753 的通道 2 上有一过零检测电路。这个过零点是用来产生一个外部的过零信号（ZX），它也可用于在校准模式 —— 请参阅基于 ADE7753 校准电表一节。过零信号还可用于启动 ADE7753 上的温度测量 —— 请参阅温度测量一节。图 40 展示了过零信号从 LPF1 输出中生成的方式。
桂林电子科技大学毕业设计（论文）报告用纸
第 2 页共 24 页
每个模拟输入通道有一个可编程增益放大器（PGA），增益可选择 1，2，4，8 和 16。增益选择是通过向增益寄存器写操作实现——见图 32。第 0 到 2 位是选择通道 1 的 PGA 的增益，在通道 2 中的 PGA 增益选择是由第 5 至第 7 位决定。图 31 显示了如何使用增益寄存器完成对通道 1 的增益选择。
桂林电子科技大学毕业设计Байду номын сангаас论文）报告用纸
第 6 页共 24 页
在中断状态寄存器中过零检测也驱动 ZX 标志位。ZX 标志位在电压波形上升和下降沿被设置为逻辑 0。它一直保持低电平直到状态寄存器被用复位读。如果中断使能寄存器对应的位设置为逻辑 1，在 IRQ 中断输出也会出现一有效的低电平。
当用复位(RSTSTATUS)读中断状态寄存器时，中断状态寄存器标志位以及 IRQ 中断输出将被重置为默认值。过零超时

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元器件交易网
MICROWAVE POWER GaAs FET MICROWAVE SEMICONDUCTOR
TIM7785-35SL
TECHNICAL DATA FEATURES
n LOW INTERMODULATION DISTORTION IM3=-45 dBc at Po= 35.0dBm, Single Carrier Level n HIGH POWER P1dB=45.5dBm at 7.7GHz to 8.5GHz n HIGH GAIN G1dB=6.0dB at 7.7GHz to 8.5GHz n BROAD BAND INTERNALLY MATCHED FET n HERMETICALLY SEALED PACKAGE
Rev. Nov. 2003
元器件交易网
TIM7785-35SL
ABSOLUTE MAXIMUM RATINGS
CHARACTERISTICS Drain-Source Voltage Gate-Source Voltage Drain Current Total Power Dissipation (Tc= 25 °C) Channel Temperature Storage
S21 ANG -157.88 153.1 105.53 58.534 10.528 -38.853 -89.791 MAG -26.718 -26.03 -25.415 -24.785 -24.184 -23.802 -23.776
S22 ANG 135.77 113.8 90.07 62.308 28.383 -11.132 -55.383 -6.814 -7.7217 -8.8479 -10.106 -11.394 -12.511 -13.44
TIM7785-35SL
TIM7785-35SL S-PARAMETERS (MAGN. and ANGLES)
VDS=10V, IDS=8.0A
f=7.5 to 8.7 GHz
7.7 7.5 8.5 8.3 8.1 7.9
7.9 8.1 8.3 8.7 8.5 8.7
7.5 7.7
FREQUENCY (GHz) 7.50 7.70 7.00 8.10 8.30 8.50 8.70 MAG
44
60 50
42
40
ηadd
40
30 20 10
34
36
38
40
Pin(dBm)
3
ηadd(%)
Pout
元器件交易网
TIM7785-35SL
Power Dissipation(PT) vs. Case Temperature(Tc)
120
100
PT(W)
80
60
40
20 0 40 80 120 160 200
u The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may results from its use, No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. The information contained herein is subject to change without prior notice. It is therefor advisable to contact TOSHIBA before proceeding with design of equipment incorporating this product.
( Ta= 25° C )
SYMBOL VDS VGS IDS PT Tch Tstg UNIT V V A W °C °C RATING 15 -5 26 115 175 -65 to +175
PACKAGE OUTLINE (2-16G1B)
0.7± 0.15 4 – C1.0 2.5 MIN. Unit in mm
RF PERFORMANCE SPECIFICATIONS
CHARACTERISTICS Output Power at 1dB Gain Compression Point Power Gain at 1dB Gain Compression Point Drain Current Gain Flatness Power Added Efficiency 3rd Order Intermodulation Distortion Drain Current SYMBOL P1dB G1dB IDS1 ∆G
( Ta= 25° C )
UNIT mS V A V °C/W MIN. -1.0 -5 TYP. 6500 -2.5 20 1.0 MAX. -4.0 26 1.3
gm
VGSoff IDSS VGSO Rth(c-c)
CONDITIONS VDS= 3V IDS= 10.5A VDS= 3V IDS= 140mA VDS= 3V VGS= 0V IGS= -420µA Channel to Case
Tc( ° C )
IM3 vs. Output Power Characteristics
-10
VDS=10V
-20
freq.=8.5GHz ∆f=5MHz
-30
IM3(dBc)
-40
-50
-60 30 32 34 36 38 40
Pout(dBm) @Single carrier level
4
元器件交易网
Pout(dBm)
VDS=10V
47
IDS≅ 8.0A Pin=39.5dBm
46
45
44
7.7
7.9
8.1
8.3
8.5
Frequency(GHz)
Output Power(Pout) vs. Input Power(Pin)
freq.=8.5GHz VDS=10V
46 80 70
Pout(dBm)
5
S11 ANG -58.883 -95.847 -125.79 -153.45 177.35 141.44 61.355 MAG -8.9814 -8.3276 -8.2456 -9.079 -11.201 -15.55 -23.587
S12 ANG -132.94 178.84 131.47 83.846 35.074 -15.135 -66.763 MAG 7.7466 7.6201 7.5867 7.6876 7.8387 7.9431 7.879e Test Po=35.0dBm
(Single Carrier Level)
dBc A °C
Channel Temperature Rise ∆Tch VDS X IDS X Rth(c-c) Recommended Gate Resistance(Rg): 28 Ω (Max.)
•
• Gate ‚ Source ƒ Drain
‚
‚
ƒ
20.4± 0.3 0.1 -0.05 24.5 MAX. 16.4 MAX.
+0.1
2.5 MIN.
2.6± 0.3
17.4± 0.4
8.0± 0.2
0.2 MAX.
1.4± 0.3
HANDLING PRECAUTIONS FOR PACKAGE MODEL
( Ta= 25° C )
UNIT dBm dB A dB % MIN. 45.0 5.0 -42 TYP. MAX. 45.5 6.0 8.0 33 -45 8.0 9.0 ±0.8 9.0 100
CONDITIONS
VDS=10V f = 7.7 to 8.5GHz
Soldering iron should be grounded and the operating time should not exceed 10 seconds at 260° C.
2
2.4± 0.3
5.5 MAX.
元器件交易网
TIM7785-35SL
RF PERFORMANCE Output Power (Pout) vs. Frequency
ELECTRICAL CHARACTERISTICS
CHARACTERISTICS Transconductance Pinch-off Voltage Saturated Drain Current Gate-Source Breakdown Voltage Thermal Resistance SYMBOL