74LVT573MTCX,74LVT573MTC,74LVT573MSAX,74LVT573SJX,74LVT573WM,74LVT573WMX, 规格书,Datasheet 资料
74HC573数据手册
© NXP B.V. 2012. All rights reserved.
2 of 21
NXP Semiconductors
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
D0
D1
D2
D3
Q0 19 Q1 18 Q2 17 3-STATE Q3 16 OUTPUTS Q4 15 Q5 14 Q6 13 Q7 12
mna809
74HC_HCT573
Product data sheet
All information provided in this document is subject to legal disclaimers.
3 of 21
NXP Semiconductors
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
5. Pinning information
5.1 Pinning
OE 1 D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9 GND 10
(1) The die substrate is attached to this pad using conductive die attach material. It can not be used as supply pin or input
Fig 6. Pin configuration DHVQFN20
Useful as input or output port for microprocessors and microcomputers 3-state non-inverting outputs for bus-oriented applications Common 3-state output enable input Multiple package options ESD protection:
74AHC573 74AHCT573 CMOS 高速透明储存器说明书
74AHC573; 74AHCT573Octal D-type transparant latch; 3-stateRev. 7 — 8 November 2011Product data sheet1. General descriptionThe 74AHC573; 74AHCT573 is a high-speed Si-gate CMOS device and is pin compatiblewith Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standardNo.7A.The 74AHC573; 74AHCT573 consists of eight D-type transparent latches featuringseparate D-type inputs for each latch and 3-state true outputs for bus orientedapplications. A latch enable input (LE) and an output enable input (OE) are common to alllatches.When pin LE is HIGH, data at the Dn inputs enters the latches. In this condition thelatches are transparent, i.e. a latch output will change state each time its correspondingDn input changes. When pin LE is LOW, the latches store the information that is presentat the Dn inputs, after a set-up time preceding the HIGH-to-LOW transition of LE.When pin OE is LOW, the contents of the 8latches are available at the outputs. Whenpin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OEinput does not affect the state of the latches.The 74AHC573; 74AHCT573 is functionally identical to the 74AHC373; 74AHCT373, buthas a different pin arrangement.2. Features and benefits⏹Balanced propagation delays⏹All inputs have a Schmitt trigger action⏹Common 3-state output enable input⏹Functionally identical to the 74AHC373; 74AHCT373⏹Inputs accept voltages higher than V CC⏹Input levels:◆For 74AHC573: CMOS input level◆For 74AHCT573: TTL input level⏹ESD protection:◆HBM EIA/JESD22-A114E exceeds 2000V◆MM EIA/JESD22-A115-A exceeds 200V◆CDM EIA/JESD22-C101C exceeds 1000V⏹Multiple package options⏹Specified from -40︒C to +85︒C and from -40︒C to +125︒C3. Ordering information4. Functional diagramTable 1.Ordering informationType numberPackageTemperature rangeNameDescriptionVersion74AHC57374AHC573D -40︒C to +125︒C SO20plastic small outline package; 20leads;body width 7.5mmSOT163-174AHC573PW -40︒C to +125︒C TSSOP20plastic thin shrink small outline package; 20leads; body width 4.4mmSOT360-174AHC573BQ-40︒C to +125︒CDHVQFN20plastic dual in-line compatible thermal enhanced very thin quad flat package no leads; 20 terminals; body 2.5⨯4.5⨯0.85mmSOT764-174AHCT57374AHCT573D -40︒C to +125︒C SO20plastic small outline package; 20leads; body width 7.5mmSOT163-174AHCT573PW -40︒C to +125︒C TSSOP20plastic thin shrink small outline package; 20leads; body width 4.4mmSOT360-174AHCT573BQ-40︒C to +125︒CDHVQFN20plastic dual in-line compatible thermal enhanced very thin quad flat package no leads; 20 terminals; body 2.5⨯4.5⨯0.85mmSOT764-15. Pinning information5.1Pinning5.2Pin descriptionTable 2.Pin descriptionSymbol Pin DescriptionOE1output enable input (active LOW) D0 to D72, 3, 4, 5, 6, 7, 8, 9data inputGND10ground (0V)LE11latch enable (active HIGH)Q0 to Q719, 18, 17, 16, 15, 14, 13, 12data outputV CC20supply voltage6. Functional description[1]H =HIGH voltage level;h =HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;L =LOW voltage level;l =LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;Z =high-impedance OFF-state.7. Limiting values[1]The input and output voltage ratings may be exceeded if the input and output current ratings are observed.[2]For SO20 packages: above 70︒C the value of P tot derates linearly at 8mW/K.For TSSOP20 packages: above 60︒C the value of P tot derates linearly at 5.5mW/K.For DHVQFN20 packages: above 60︒C the value of P tot derates linearly with 4.5mW/K.Table 3.Function table [1]Operating modeInput Internal latch Output OE LE Dn Qn Enable and read register (transparent mode)L H L L L H H H Latch and read registerL L l L L h H H Latch register and disable outputsHLl L Z hHZTable 4.Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).Voltages are referenced to GND (ground = 0V).Symbol Parameter Conditions Min Max Unit V CC supply voltage -0.5+7.0V V I input voltage-0.5+7.0V I IK input clamping current V I < -0.5V[1]-20-mA I OK output clamping current V O <-0.5V or V O >V CC +0.5V [1]-20+20mA I O output current V O = -0.5V to (V CC +0.5V)-25+25mA I CC supply current -+75mA I GND ground current -75-mA T stg storage temperature -65+150︒C P tottotal power dissipationT amb = -40 ︒C to +125︒C[2]-500mW8. Recommended operating conditions9. Static characteristicsTable 5.Operating conditions Symbol ParameterConditionsMinTypMaxUnit74AHC573V CC supply voltage 2.0 5.0 5.5V V I input voltage 0- 5.5V V O output voltage 0-V CC V T amb ambient temperature-40+25+125︒C ∆t/∆V input transition rise and fall rateV CC = 3.0 V to 3.6 V --100ns/V V CC = 4.5 V to 5.5 V--20ns/V74AHCT573V CC supply voltage 4.5 5.0 5.5V V I input voltage 0- 5.5V V O output voltage 0-V CC V T amb ambient temperature-40+25+125︒C ∆t/∆Vinput transition rise and fall rateV CC = 4.5 V to 5.5 V--20ns/VTable 6.Static characteristicsAt recommended operating conditions; voltages are referenced to GND (ground = 0V).Symbol Parameter Conditions25 ︒C -40︒C to +85 ︒C -40︒C to +125 ︒C UnitMin Typ Max Min Max Min Typ Max 74AHC573V IHHIGH-level input voltageV CC = 2.0 V 1.5-- 1.5- 1.5--V V CC = 3.0 V 2.1-- 2.1- 2.1--V V CC = 5.5 V3.85-- 3.85- 3.85--V V ILLOW-level input voltageV CC = 2.0 V --0.5-0.5--0.5V V CC = 3.0 V --0.9-0.9--0.9V V CC = 5.5 V-- 1.65- 1.65-- 1.65V V OHHIGH-level output voltage V I = V IH or V IL I O = -50μA; V CC =2.0 V1.92.0- 1.9- 1.9--V I O = -50μA; V CC =3.0 V 2.9 3.0- 2.9- 2.9--V I O = -50μA; V CC =4.5 V 4.4 4.5- 4.4- 4.4--V I O = -4.0mA; V CC =3.0 V 2.58-- 2.48- 2.40--V I O = -8.0mA; V CC =4.5 V3.94-- 3.80- 3.70--V V OLLOW-level output voltage V I = V IH or V IL I O = 50μA; V CC =2.0 V-00.1-0.1--0.1V I O = 50μA; V CC =3.0 V -00.1-0.1--0.1V I O = 50μA; V CC =4.5 V -00.1-0.1--0.1V I O = 4.0mA; V CC =3.0 V --0.36-0.44--0.55V I O = 8.0mA; V CC =4.5 V--0.36-0.44--0.55VI OZ OFF-stateoutput current V I=V IH or V IL;V O=V CC or GND;V CC=5.5V--±0.25-±2.5--±10.0μAI I input leakagecurrent V I=V CC or GND;V CC=0V to5.5V--0.1- 1.0-- 2.0μAI CC supply current V I=V CC or GND;I O=0A;V CC=5.5V-- 4.0-40--80μAC I inputcapacitanceV I=V CC or GND-310-10--10pFC O outputcapacitance-4-----10pF 74AHCT573V IH HIGH-levelinput voltageV CC = 4.5 V to 5.5 V 2.0-- 2.0- 2.0--VV IL LOW-levelinput voltageV CC = 4.5 V to 5.5 V--0.8-0.8--0.8VV OH HIGH-leveloutput voltage V I= V IH or V IL; V CC=4.5 VI O= -50μA 4.4 4.5- 4.4- 4.4--V I O= -8.0mA 3.94-- 3.80- 3.70--VV OL LOW-leveloutput voltage V I= V IH or V IL; V CC=4.5 VI O= 50μA-00.1-0.1--0.1V I O= 8.0mA--0.36-0.44--0.55VI OZ OFF-stateoutput current V I=V IH or V IL;V O=V CC or GND per inputpin; other inputs at V CC orGND; I O=0 A--±0.25-±2.5--±10.0μAI I input leakagecurrent V I=5.5 V or GND;V CC=0V to5.5V--0.1- 1.0-- 2.0μAI CC supply current V I=V CC or GND; I O = 0 A;V CC=5.5V-- 4.0-40--80μA∆I CC additionalsupply current per input pin;V I=V CC-2.1V; I O=0 A;other pins at V CC or GND;V CC=4.5V to5.5V-- 1.35- 1.5-- 1.5mAC I inputcapacitanceV I=V CC or GND-310-10--10pFC O outputcapacitance -4-----10pFTable 6.Static characteristics …continuedAt recommended operating conditions; voltages are referenced to GND (ground = 0V).Symbol Parameter Conditions25 ︒C-40︒C to+85 ︒C-40︒C to+125 ︒C UnitMin Typ Max Min Max Min Typ Max10. Dynamic characteristicsTable 7.Dynamic characteristicsVoltages are referenced to GND (ground = 0 V); for test circuit see Figure11.Symbol Parameter Conditions25 ︒C-40︒C to+85 ︒C-40︒C to+125 ︒C UnitMin Typ[1]Max Min Max Min Max74AHC573t pd propagationdelay Dn to Qn; see Figure7[2]V CC = 3.0 V to 3.6 VC L=15pF- 5.511.0 1.013.0 1.014.0nsC L=50pF-7.814.5 1.016.5 1.018.5ns V CC = 4.5 V to 5.5 VC L=15pF- 3.9 6.8 1.08.0 1.08.5nsC L=50pF- 5.58.8 1.010.0 1.011.0ns LE to Qn; see Figure8[2]V CC = 3.0 V to 3.6 VC L=15pF- 5.811.9 1.014.0 1.015.0nsC L=50pF-8.315.4 1.017.5 1.019.5ns V CC = 4.5 V to 5.5 VC L=15pF- 4.27.7 1.09.0 1.010.0nsC L=50pF- 5.99.7 1.011.0 1.012.5nst en enable time OE to Qn; see Figure9[3]V CC = 3.0 V to 3.6 VC L=15pF- 5.811.5 1.013.5 1.014.5nsC L=50pF-8.315.0 1.017.0 1.019.0nsV CC = 4.5 V to 5.5 VC L=15pF- 4.47.7 1.09.0 1.010.0nsC L=50pF- 6.39.7 1.011.0 1.012.5ns t dis disable time OE to Qn; see Figure9[4]V CC = 3.0 V to 3.6 VC L=15pF- 6.811.0 1.013.0 1.014.0nsC L=50pF-9.714.5 1.016.5 1.018.5nsV CC = 4.5 V to 5.5 VC L=15pF- 4.67.7 1.09.0 1.010.0nsC L=50pF-7.49.7 1.011.0 1.012.5ns t W pulse width LE HIGH; see Figure8V CC=3.0 V to 3.6 V 5.0-- 5.0- 5.0-nsV CC=4.5 V to 5.5 V 5.0-- 5.0- 5.0-ns t su set-up time Dn to LE; see Figure10V CC=3.0 V to 3.6 V 3.5-- 3.5- 3.5-nsV CC=4.5 V to 5.5 V 3.5-- 3.5- 3.5-ns[1]Typical values are measured at nominal supply voltage (V CC = 3.3V and V CC = 5.0V).[2]t pd is the same as t PHL and t PLH .[3]t en is the same as t PZH and t PZL .[4]t dis is the same as t PHZ and t PLZ .[5]C PD is used to determine the dynamic power dissipation (P D in μW).P D =C PD ⨯V CC 2⨯f i ⨯N +∑(C L ⨯V CC 2⨯f o )where:f i = input frequency in MHz;f o =output frequency in MHz;C L =output load capacitance in pF;V CC =supply voltage in V;N =number of inputs switching;∑(C L ⨯V CC 2⨯f o )=sum of the outputs.t hhold timeDn to LE; see Figure 10V CC =3.0 V to 3.6 V 1.5-- 1.5- 1.5-ns V CC =4.5 V to 5.5 V1.5-- 1.5- 1.5-ns C PDpower dissipation capacitancef i = 1 MHz;V I =GND to V CC[5]-12-----pF74AHCT573; V CC = 4.5 V to 5.5 V t pdpropagation delay Dn to Qn; see Figure 7[2]C L =15pF- 3.5 5.51 6.517.0ns C L =50pF- 4.97.518.519.5ns LE to Qn; see Figure 8[2]C L =15pF - 3.9 6.017.017.5ns C L =50pF- 5.58.519.5111.0ns t enenable timeOE to Qn; see Figure 9[3]C L =15pF - 4.1 6.517.518.5ns C L =50pF- 5.98.5110.0111.0ns t disdisable time OE to Qn; see Figure 9[4]C L =15pF - 4.5 6.517.518.5ns C L =50pF- 6.49.0110.0111.5ns t W pulse width LE HIGH; see Figure 8 5.0-- 5.0- 5.0-ns t su set-up time Dn to LE; see Figure 10 3.5-- 3.5- 3.5-ns t h hold time Dn to LE; see Figure 10 1.5-- 1.5- 1.5-ns C PDpower dissipation capacitancef i = 1 MHz;V I =GND to V CC[5]-18-----pFTable 7.Dynamic characteristics …continuedVoltages are referenced to GND (ground = 0 V); for test circuit see Figure 11.Symbol Parameter Conditions25 ︒C -40︒C to +85 ︒C -40︒C to +125 ︒C Unit MinTyp [1]Max Min Max Min Max11. WaveformsTable 8.Measurement pointsType Input OutputV M V M V X V Y74AHC5730.5⨯V CC0.5⨯V CC V OL + 0.3 V V OH- 0.3 V 74AHCT573 1.5 V0.5⨯V CC V OL + 0.3 V V OH- 0.3 VTable 9.Test dataType Input Load S1 positionV I t r, t f C L R L t PHL, t PLH t PZH, t PHZ t PZL, t PLZ 74AHC573V CC≤3.0ns15pF, 50pF1kΩopen GND V CC74AHCT573 3.0V≤3.0ns15pF, 50pF1kΩopen GND V CC12. Package outlineSO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1Fig 12.Package outline SOT163-1 (SO20)TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1Fig 13.Package outline SOT360-1 (TSSOP20)Fig 14.Package outline SOT764-1 (DHVQFN20)SOT764-1DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;20 terminals; body 2.5 x 4.5 x 0.85 mm13. AbbreviationsTable 10.AbbreviationsAcronym DescriptionCDM Charged Device ModelCMOS Complementary Metal-Oxide SemiconductorESD ElectroStatic DischargeHBM Human Body ModelMM Machine ModelTTL Transistor-Transistor Logic14. Revision historyTable 11.Revision historyDocument ID Release date Data sheet status Change notice Supersedes74AHC_AHCT573 v.720111108Product data sheet-74AHC_AHCT573 v.6 Modifications:•Legal pages updated.74AHC_AHCT573 v.620101125Product data sheet-74AHC_AHCT573 v.5 74AHC_AHCT573 v.520100325Product data sheet-74AHC_AHCT573 v.4 74AHC_AHCT573 v.420100303Product data sheet-74AHC_AHCT573 v.3 74AHC_AHCT573 v.320080424Product data sheet-74AHC_AHCT573 v.2 74AHC_AHCT573 v.220031208Product specification-74AHC_AHCT573 v.1 74AHC_AHCT573 v.119990927Product specification--15. Legal information15.1 Data sheet status[1]Please consult the most recently issued document before initiating or completing a design.[2]The term ‘short data sheet’ is explained in section “Definitions”.[3]The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product statusinformation is available on the Internet at URL .15.2 DefinitionsDraft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give anyrepresentations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia salesoffice. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia andcustomer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product isdeemed to offer functions and qualities beyond those described in the Product data sheet.15.3 DisclaimersLimited warranty and liability — Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.In no event shall Nexperia be liable for any indirect, incidental,punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia’s aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia.Right to make changes — Nexperia reserves the right to makechanges to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. 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Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperiaaccepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications andproducts planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.Nexperia does not accept any liability related to any default,damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications andthe products or of the application or use by customer’s third partycustomer(s). Nexperia does not accept any liability in this respect.Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.Terms and conditions of commercial sale — Nexperiaproducts are sold subject to the general terms and conditions of commercial sale, as published at /profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects toapplying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer.No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.Document status[1][2]Product status[3]DefinitionObjective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.Product [short] data sheet Production This document contains the product specification.Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified,the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use ofnon-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of theproduct for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’sown risk, and (c) customer fully indemnifies Nexperia for anyliability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’sstandard warranty and Nexperia’s product specifications.15.4 TrademarksNotice: All referenced brands, product names, service names and trademarks are the property of their respective owners.16. Contact informationFor more information, please visit: For sales office addresses, please send an email to: ***************************17. Contents1 General description. . . . . . . . . . . . . . . . . . . . . . 12 Features and benefits . . . . . . . . . . . . . . . . . . . . 13 Ordering information. . . . . . . . . . . . . . . . . . . . . 24 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 25 Pinning information. . . . . . . . . . . . . . . . . . . . . . 45.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 46 Functional description . . . . . . . . . . . . . . . . . . . 57 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 58 Recommended operating conditions. . . . . . . . 69 Static characteristics. . . . . . . . . . . . . . . . . . . . . 610 Dynamic characteristics . . . . . . . . . . . . . . . . . . 811 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1012 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 1313 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 1614 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 1615 Legal information. . . . . . . . . . . . . . . . . . . . . . . 1715.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 1715.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1715.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 1715.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 1816 Contact information. . . . . . . . . . . . . . . . . . . . . 1817 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19© Nexperia B.V. 2017. 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74系列中lvclvhcls等有什么区别
74系列中lvclvhcls等有什么区别74系列中lvc lv hc ls等有什么区别ABT高级双极CMOS技术ABTE/ETL高级双极CMOS技术增强收发逻辑AC/ACT高级CMOS逻辑AHC/AHCT高级高速CMOS逻辑ALB高级低电压BiCMOSALS高级低功耗肖特基逻辑ALVC高级低电压CMOS技术ALVT高级低电压BiCMOS技术AS高级肖特基逻辑AUC高级极低电压CMOS逻辑AUP高级极低功耗CMOS逻辑AVC高级很低电压CMOS逻辑BCT双极CMOS技术CB3Q 2.5V、3.3V低电压高带宽总线交换纵横逻辑CB3T 2.5V、3.3V低电压晶体管总线交换纵横逻辑CBT纵横技术CBT-C有2V下冲保护的5V总线交换纵横逻辑CBTLV低电压纵横技术逻辑CD4000CMOS逻辑4000系列F快速逻辑FB基底电极收发逻辑FCT高速CMOS技术GTL电子?收发逻辑GTLP电子?收发逻辑+HC/HCT高速CMOS逻辑HSTL高速收发逻辑LS低功耗肖特基逻辑LV低电压LV-A低电压CMOS技术LV-AT低电压CMOS技术并兼容TTL电平LVC低电压CMOS技术LVT低电压BiCMOS技术S肖特基逻辑SSTL抽头级联逻辑SSTU抽头级联极低电压逻辑SSTV/SSTVF抽头级联低电压逻辑TVC平移电压箝位逻辑这些逻辑电平对应的英文含义如下：S-Schottky LogicLS-Low-Power Schottky LogicCD4000-CMOS Logic4000AS-Advanced Schottky Logic74F-Fast LogicALS-Advanced Low-Power Schottky LogicHC/HCT-High-Speed CMOS LogicBCT-BiCMOS TechnologyAC/ACT-Advanced CMOS LogicFCT-Fast CMOS TechnologyABT-Advanced BiCMOS TechnologyLVT-Low-Voltage BiCMOS TechnologyLVC-Low Voltage CMOS TechnologyLV-Low-VoltageCBT-Crossbar TechnologyALVC-Advanced Low-Voltage CMOS Technology AHC/AHCT-Advanced High-Speed CMOSCBTLV-Low-Voltage Crossbar TechnologyALVT-Advanced Low-Voltage BiCMOS Technology AVC-Advanced Very-Low-Voltage CMOS Logic。
M74HCT573TTR,M74HCT573TTR,M74HCT573TTR,M74HCT573B1R,M74HCT573RM13TR, 规格书,Datasheet 资料
1/11July 2001sHIGH SPEED:t PD = 21ns (TYP .) at V CC = 4.5V sLOW POWER DISSIPATION:I CC = 4µA(MAX.) at T A =25°CsCOMPATIBLE WITH TTL OUTPUTS : V IH = 2V (MIN.) V IL = 0.8V (MAX)sBALANCED PROPAGATION DELAYS:t PLH ≅ t PHLsSYMMETRICAL OUTPUT IMPEDANCE:|I OH | = I OL = 6mA (MIN)sPIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573DESCRIPTIONThe M74HCT573 is an high speed CMOS OCTAL LATCH WITH 3-STATE OUTPUTS fabricated with silicon gate C 2MOS technology.This 8-BIT D-Type latches is controlled by a latch enable input (LE) and output enable input (OE).While the LE input is held at a high level, the Q outputs will follow the data input precisely. When the LE is taken low, the Q outputs will be latched precisely at the logic level of D input data.While the OE input is at low level, the eight outputs will be in a normal logic state (high or low logic level) and while OE is at high level the outputs will be in a high impedance state.The 3-State output configuration and the wide choice of outline make bus organized system simple.The M74HCT573 is designed to directly interface HSC 2MOS systems with TTL and NMOS components.All inputs are equipped with protection circuits against static discharge and transient excess voltage.M74HCT573OCTAL D-TYPE LATCHWITH 3 STATE OUTPUT NON INVERTINGPIN CONNECTION AND IEC LOGIC SYMBOLSORDER CODESPACKAGE TUBE T & RDIP M74HCT573B1R SOP M74HCT573M1RM74HCT573RM13TR TSSOPM74HCT573TTRM74HCT5732/11INPUT AND OUTPUT EQUIVALENT CIRCUITPIN DESCRIPTIONTRUTH TABLEX: Don’t CareZ: High Impedance(*): Q Outputs are latched at the time when the LE input is taken low logic level.LOGIC DIAGRAMPIN No SYMBOL NAME AND FUNCTION 1OE 3 State Output Enable Input (Active LOW)2, 3, 4, 5, 6, 7, 8, 9D0 to D7Data Inputs12, 13, 14, 15, 16, 17, 18, 19Q0 to Q73 State Latch Outputs11LE Latch Enable Input 10GND Ground (0V)20V CCPositive Supply VoltageINPUTSOUTPUTSOE LE D QH X X ZL L X NO CHANGE (*)L H L L LHHHM74HCT5733/11ABSOLUTE MAXIMUM RATINGSAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°CRECOMMENDED OPERATING CONDITIONSSymbol ParameterValue Unit V CC Supply Voltage -0.5 to +7V V I DC Input Voltage -0.5 to V CC + 0.5V V O DC Output Voltage -0.5 to V CC + 0.5V I IK DC Input Diode Current ± 20mA I OK DC Output Diode Current ± 20mA I O DC Output Current ± 35mA I CC or I GND DC V CC or Ground Current± 70mA P D Power Dissipation 500(*)mW T stg Storage Temperature -65 to +150°C T LLead Temperature (10 sec)300°CSymbol ParameterValue Unit V CC Supply Voltage 4.5 to 5.5V V I Input Voltage 0 to V CC V V O Output Voltage 0 to V CC V T op Operating Temperature-55 to 125°C t r , t fInput Rise and Fall Time (V CC = 4.5 to 5.5V)0 to 500nsM74HCT5734/11DC SPECIFICATIONSAC ELECTRICAL CHARACTERISTICS (C L = 50 pF, Input t r = t f = 6ns)SymbolParameterTest ConditionValue UnitV CC (V)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.Max.Min.Max.V IHHigh Level Input Voltage4.5 to5.5 2.02.02.0V V IL Low Level Input Voltage4.5 to5.50.80.80.8V V OH High Level Output Voltage4.5I O =-20 µA 4.4 4.5 4.4 4.4VI O =-6.0 mA 4.184.31 4.134.10V OL Low Level Output Voltage4.5I O =20 µA 0.00.10.10.1V I O =6.0 mA 0.170.260.330.40I I Input Leakage Current5.5V I = V CC or GND ± 0.1± 1± 1µA I OZ High Impedance Output Leakage Current5.5V I = V IH or V IL V O = V CC or GND ± 0.5± 5± 10µA I CC Quiescent Supply Current5.5V I = V CC or GND 44080µA ∆ I CCAdditional Worst Case Supply Current5.5Per Input pin V I = 0.5V or V I = 2.4V Other Inputs at V CC or GND2.02.93.0mASymbolParameterTest ConditionValue UnitV CC (V)C L (pF)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.Max.Min.Max.t TLH t THL Output TransitionTime4.5507121518ns t PLH t PHL Propagation DelayTime (LE - Q,Q) 4.55021334150ns 4.515025394959t PLH t PHL Propagation DelayTime (D - Q,Q) 4.55019303845ns 4.515023364554t PZL t PZH Output EnableTime 4.550R L = 1 K Ω19303845ns 4.515023364554t PLZ t PHZ Output DisableTime4.550R L = 1 K Ω18253138ns t W(L) t W(H)Minimum PulseWidth (LE) 4.5507151922ns t s Minimum Set-Up Time4.5504101315ns t hMinimum Hold Time4.550555nsM74HCT5735/11CAPACITIVE CHARACTERISTICS1) C PD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I CC(opr) = C PD x V CC x f IN + I CC /8 (per Flip Flop)TEST CIRCUITC L = 50pF/150pF or equivalent (includes jig and probe capacitance)R 1 = 1K Ω or equivalentR T = Z OUT of pulse generator (typically 50Ω)SymbolParameterTest ConditionValue UnitV CC (V)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.Max.Min.Max.C IN Input Capacitance5101010pF C OUT OutputCapacitance10pF C PDPower Dissipation Capacitance (note 1)51pF TESTSWITCH t PLH , t PHL Open t PZL , t PLZ V CC t PZH , t PHZGNDM74HCT5736/11WAVEFORM 1: LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn TO LE SETUP AND HOLD TIMES(f=1MHz; 50% duty cycle)M74HCT5737/11WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle)WAVEFORM 3: PROPAGATION DELAY TIMES(f=1MHz; 50% duty cycle)M74HCT573 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.© The ST logo is a registered trademark of STMicroelectronics© 2000 STMicroelectronics - Printed in Italy - All Rights ReservedSTMicroelectronics GROUP OF COMPANIESAustralia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - MoroccoSingapore - Spain - Sweden - Switzerland - United Kingdom© 11/11芯天下--/。
74HC_HCT573 三态锁存器
Octal D-type transparent latch; 3-state
Rev. 7 — 4 March 2016 Product data sheet
1. General description
The 74HC573; 74HCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
74LVC573APW-T中文资料
74LVC573AOctal D-type transparent latch with 5 V tolerantinputs/outputs; 3-stateRev. 04.00 — 18 May 2006Product data sheet1.General descriptionThe 74LVC573A consists of eight D-type transparent latches, featuring separate D-typeinputs for each latch and 3-state true outputs for bus-oriented applications. A LatchEnable (LE) input and an Output Enable (OE) input are common to all internal latches.When LE is HIGH, data at the Dn inputs enters the latches. In this condition, the latchesare transparent, that is, a latch output will change each time its corresponding D-inputchanges. When LE is LOW, the latches store the information that was present at theD-inputs one setup time preceding the HIGH-to-LOW transition of LE.When OE is LOW, the contents of the eight latches are available at the outputs. When OEis HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input doesnot affect the state of the latches.It is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to mostadvanced CMOS compatible TTL families.Inputs can be driven from either 3.3V or5V devices. When disabled, up to 5.5 V can beapplied to the outputs. This feature allows the use of these devices as translators in mixed3.3V or5V applications.The 74LVC573A is functionally identical to the 74LVC373A, but has a different pinarrangement.2.Features5 V tolerant inputs/outputs, for interfacing with 5V logicSupply voltage range from 1.2V to3.6VCMOS low power consumptionDirect interface with TTL levelsHigh-impedance when V CC = 0 VFlow-through pin-out architectureComplies with JEDEC standard JESD8-B/JESD36ESD protection:HBM JESD22-A114-C exceeds 2000VCDM JESD22-C101-C exceeds 1000VSpecified from −40°C to +85°C and −40°C to 125°C3.Ordering information4.Functional diagramTable 1:Ordering informationType numberPackage Temperature rangeNameDescriptionVersion74LVC573AD−40 °C to +125 °C SO20plastic small outline package; 20leads; body width 7.5mm SOT163-174LVC573ADB −40 °C to +125 °C SSOP20plastic shrink small outline package; 20leads; body width 5.3mmSOT339-174LVC573APW −40 °C to +125 °C TSSOP20plastic thin shrink small outline package; 20leads; body width 4.4mmSOT360-174LVC573ABQ −40 °C to +125 °C DHVQFN20plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20terminals; body 2.5×4.5×0.85mmSOT764-15.Pinning information5.1Pinning5.2Pin descriptionTable 2:Pin descriptionSymbol Pin DescriptionOE1output enable input (active LOW) D0 - D7 2 - 9data inputGND10ground (0 V)LE11latch enable input (active HIGH) Q7 - Q012 - 19data outputV CC20supply voltage6.Functional description[1]H = HIGH voltage levelh = HIGH voltage level one setup time prior to the HIGH-to-LOW LE transition L = LOW voltage levell = LOW voltage level one setup time prior to the HIGH-to-LOW LE transition Z = High-impedance OFF-state.7.Limiting values[1]The input and output voltage ratings may be exceeded if the input and output current ratings are observed.[2]For SO20 packages: above 70°C the value of P tot derates linearly with 8mW/K.For (T)SSOP20 packages: above 60°C the value of P tot derates linearly with 5.5mW/K.For DHVQFN20 packages: above 60°C the value of P tot derates linearly with 4.5mW/K.Table 3:Functional table [1]Operating modes Input Internal latch OutputOE LE Dn QnEnable and read register (transparent mode)L H L L L L H H H H Latch and read register L L l L L L L h H H Latch register and disable outputsH L l L Z HLhHZTable 4:Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).Symbol Parameter Conditions Min Max Unit V CC supply voltage −0.5+6.5V I IK input clamping current V I < 0-−50mA V I input voltage[1]−0.5+6.5V I OK output clamping current V O > V CC or V O < 0-±50mA V O output voltage [1]−0.5V CC + 0.5V I O output current V O = 0 to V CC-±50mA I CC supply current -+100mA I GND ground current -−100mA T stg storage temperature −65+150°C P tottotal power dissipationT amb = −40 °C to +125 °C[2]-500mW8.Recommended operating conditions9.Static characteristicsTable 5:Recommended operating conditions Symbol Parameter ConditionsMin Typ Max Unit V CC supply voltage 1.2- 3.6V V I input voltage 0- 5.5V V O output voltage output HIGH- or LOW-state 0-V CC V output 3-state 0- 5.5V T amb ambient temperature in free air−40-+125°C ∆t/∆Vinput transition riseand fall rateV CC = 1.65 V to 2.7 V 0-20ns/V V CC = 2.7 V to 3.6 V 0-10ns/VTable 6:Static characteristicsAt recommended operating conditions voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ [1]Max Unit T amb =−40 °C to +85°C V IHHIGH-level input voltageV CC = 1.2 V1.08--V V CC = 1.65 V to 1.95 V 0.65 × V CC --V V CC = 2.3 V to 2.7 V 1.7--V V CC = 2.7 V to 3.6 V2.0--V V ILLOW-level input voltageV CC = 1.2 V--0.12V V CC = 1.65 V to 1.95 V --0.35 × V CC VV CC = 2.3 V to 2.7 V --0.7V V CC = 2.7 V to 3.6 V--0.8V V OHHIGH-level output voltageV I =V IH or V ILI O =−100µA; V CC = 1.65 V to 3.6 V V CC −0.2V CC -V I O =−4mA; V CC = 1.65 V V CC −0.45--V I O =−8mA; V CC = 2.3 V V CC −0.5--V I O =−12mA; V CC = 2.7 V V CC −0.5--V I O =−18mA; V CC = 3.0 V V CC −0.6--V I O =−24mA; V CC = 3.0 VV CC −0.8--V V OLLOW-level output voltageV I =V IH or V ILI O =100µA; V CC = 1.65 V to 3.6 V --0.20V I O =4mA; V CC = 1.65 V --0.45V I O =8mA; V CC = 2.3 V --0.6V I O =12mA; V CC = 2.7 V --0.4V I O =24mA; V CC = 3.0 V--0.55V I I input leakage current V CC = 3.6 V; V I =5.5V or GND [2]-±0.1±5µA I OZ OFF-state output current V CC =3.6V;V I =V IH or V IL ; V O =5.5V or GND-0.1±10µA I OFFpower off leakage supplyV CC =0.0V;V I or V O =5.5V-0.1±10µA[1]All typical values are measured at V CC = 3.3 V (unless stated otherwise) and T amb =25°C.[2]The specified overdrive current at the data input forces the data input to the opposite logic input state.I CC supply currentV CC = 3.6 V; V I =V CC or GND; I O =0-0.110µA ∆I CC additional supply current per input pin V CC = 2.7 V to 3.6 V; V I =V CC −0.6V; I O =0-5500µA C I input capacitance V CC =0 V to 3.6V; V I = GND to V CC - 5.0-pF T amb =−40 °C to +125°CV IHHIGH-level input voltageV CC = 1.2 V1.08--V V CC = 1.65 V to 1.95 V 0.65 × V CC --V V CC = 2.3 V to 2.7 V 1.7--V V CC = 2.7 V to 3.6 V2.0--V V ILLOW-level input voltageV CC = 1.2 V--0.12V V CC = 1.65 V to 1.95 V --0.35 × V CC VV CC = 2.3 V to 2.7 V --0.7V V CC = 2.7 V to 3.6 V--0.8V V OHHIGH-level output voltageV I =V IH or V ILI O =−100µA; V CC = 1.65 V to 3.6 V V CC −0.3--V I O =−4mA; V CC = 1.65 V V CC −0.6--V I O =−8mA; V CC = 2.3 V V CC −0.65--V I O =−12mA; V CC = 2.7 V V CC −0.65--V I O =−18mA; V CC = 3.0 V V CC −0.75--V I O =−24mA; V CC = 3.0 VV CC −1--V V OLLOW-level output voltageV I =V IH or V ILI O =100µA; V CC = 1.65 V to 3.6 V --0.3V I O =4mA; V CC = 1.65 V --0.65V I O =8mA; V CC = 2.3 V --0.8V I O =12mA; V CC = 2.7 V --0.6V I O =24mA; V CC = 3.0 V--0.8V I I input leakage current V CC = 3.6 V; V I =5.5V or GND --±20µA I CC supply currentV CC = 3.6 V; V I =V CC or GND; I O =0--40µA ∆I CCadditional supply current per input pinV CC = 2.7 V to 3.6 V; V I =V CC −0.6V; I O =0--5000µATable 6:Static characteristics …continuedAt recommended operating conditions voltages are referenced to GND (ground = 0 V). Symbol Parameter ConditionsMin Typ [1]Max Unit10.Dynamic characteristicsTable 7:Dynamic characteristicsVoltages are referenced to GND (ground=0V). For test circuit see Figure11.Symbol Parameter Conditions Min Typ[1]Max Unit T amb=−40°C to+85 °Ct PHL, t PLH HIGH to LOW, LOW to HIGH propagation delayDn to Qn see Figure7V CC= 1.2 V-16.0-nsV CC= 1.65V to 1.95 V 1.97.814.8nsV CC= 2.3V to 2.7 V 1.3 4.17.7nsV CC= 2.7V 2.0 4.17.2nsV CC= 3.0V to3.6V 1.6 3.4 6.2ns LE to Qn see Figure8V CC= 1.2 V-16.0-nsV CC= 1.65V to 1.95 V 1.97.714.6nsV CC= 2.3V to 2.7 V 1.3 4.17.5nsV CC= 2.7V 1.7 3.77.0nsV CC= 3.0V to3.6V 1.6 3.4 6.3nst PZH, t PZL OFF-state to HIGH, OFF-state toLOW propagation delay OE to Qn see Figure9V CC= 1.2 V-18.0-ns V CC = 1.65 V to 1.95 V 1.57.516ns V CC = 2.3 V to 2.7 V 1.2 4.28.8ns V CC = 2.7 V 2.1 4.27.5ns V CC = 3.0 V to 3.6 V 1.5 3.47.0nst PHZ, t PLZ HIGH to OFF-state,LOW to OFF-state propagationdelay OE to Qn see Figure9V CC= 1.2 V-8.0-ns V CC = 1.65 V to 1.95 V0.4 3.38.1ns V CC = 2.3 V to 2.7 V0.3 1.8 4.6ns V CC = 2.7 V 1.8 3.0 5.2ns V CC = 3.0 V to 3.6 V 1.5 2.5 4.9nst W pulse width, LE HIGH see Figure8V CC = 1.65 V to 1.95 V8.0--nsV CC = 2.3 V to 2.7 V 4.0--nsV CC = 2.7 V 3.2--nsV CC = 3.0 V to 3.6 V 3.2 1.6-ns t su setup time, nD to nCP see Figure10V CC = 1.65 V to 1.95 V 5.0--nsV CC = 2.3 V to 2.7 V 3.7--nsV CC = 2.7 V 1.7--nsV CC = 3.0 V to 3.6 V 1.7--nst hhold time, Dn to LEsee Figure 10V CC = 1.65 V to 1.95 V 3.0--ns V CC = 2.3 V to 2.7 V 1.9--ns V CC = 2.7 V 1.5--ns V CC = 3.0 V to 3.6 V1.4--ns t sk(0)output skew timeV CC = 3.0 V to 3.6 V[2]--1.0nsT amb =−40°C to +125 °Ct PHL , t PLHHIGH to LOW, LOW to HIGH propagation delay Dn to Qnsee Figure 7V CC = 1.2 V---ns V CC = 1.65V to 1.95 V 1.9-18.5ns V CC = 2.3V to 2.7 V 1.3-10.0ns V CC = 2.7V 2.0-9.5ns V CC = 3.0V to 3.6V1.6-8.0nsLE to Qnsee Figure 8V CC = 1.2 V---ns V CC = 1.65V to 1.95 V 1.9-18.5ns V CC = 2.3V to 2.7 V 1.3-9.5ns V CC = 2.7V 1.7-9.0ns V CC = 3.0V to 3.6V1.6-8.0nst PZH , t PZLOFF-state to HIGH, OFF-state to LOW propagation delay OE to Qnsee Figure 9V CC = 1.2 V---ns V CC = 1.65 V to 1.95 V 1.5-20ns V CC = 2.3 V to 2.7 V 1.2-11ns V CC = 2.7 V 2.1-9.5ns V CC = 3.0 V to 3.6 V1.5-9.0nst PHZ , t PLZHIGH to OFF-state,LOW to OFF-state propagation delay OE to Qnsee Figure 9V CC = 1.2 V---ns V CC = 1.65 V to 1.95 V 0.4-10.5ns V CC = 2.3 V to 2.7 V 0.3- 6.0ns V CC = 2.7 V 1.8- 6.5ns V CC = 3.0 V to 3.6 V1.5- 6.5nst Wpulse width, LE HIGHsee Figure 8V CC = 1.65 V to 1.95 V 8.0--ns V CC = 2.3 V to 2.7 V 4.0--ns V CC = 2.7 V 3.2--ns V CC = 3.0 V to 3.6 V3.2--nsTable 7:Dynamic characteristics …continuedVoltages are referenced to GND (ground =0V). For test circuit see Figure 11.Symbol Parameter Conditions Min Typ [1]Max Unit[1]Typical values are measured at T amb =25°C and V CC = 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.[2]Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.[3]C PD is used to determine the dynamic power dissipation (P D in µW).P D =C PD ×V CC 2×f i ×N +Σ(C L ×V CC 2×f o )where:f i = input frequency in MHz,f o =output frequency in MHz,C L =output load capacitance in pF,V CC =supply voltage in V,N =number of inputs,Σ(C L ×V CC 2×f o )=sum of the outputs.11.AC waveformst susetup time, nD to nCPsee Figure 10V CC = 1.65 V to 1.95 V 5.0--ns V CC = 2.3 V to 2.7 V 3.7--ns V CC = 2.7 V 1.7--ns V CC = 3.0 V to 3.6 V1.7--ns t hhold time, Dn to LEsee Figure 10V CC = 1.65 V to 1.95 V 3.0--ns V CC = 2.3 V to 2.7 V 1.9--ns V CC = 2.7 V 1.5--ns V CC = 3.0 V to 3.6 V1.4--ns t sk(o)output skew timeV CC = 3.0 V to 3.6 V[2]--1.0nsT amb = 25 °C C PDpower dissipation capacitance per latch.V I = GND to V CC[3]V CC = 1.65 V to 1.95 V -7-pF V CC = 2.3 V to 2.7 V -10-pF V CC = 3.0 V to 3.6 V-13-pFTable 7:Dynamic characteristics …continuedVoltages are referenced to GND (ground =0V). For test circuit see Figure 11.Symbol ParameterConditions Min Typ [1]Max UnitTable 8:Test dataSupply voltage Input Load V EXTV I t r, t f C L R L t PLH, t PHL t PLZ, t PZL t PHZ, t PZH1.65V to1.95V V CC≤ 2 ns30pF 1 kΩopen 2 × V CC GND2.3V to2.7V V CC≤ 2 ns30pF500Ωopen 2 × V CC GND2.7V 2.7V≤ 2.5ns50pF500Ωopen6V GND12.Package outlineSO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1SOT764-1DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;20 terminals; body 2.5 x 4.5 x 0.85 mm13.Abbreviations14.Revision historyTable 9.AbbreviationsAcronym DescriptionCDM Charged Device ModelCMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model TTLTransistor Transistor LogicTable 10.Revision historyDocument ID Release date Data sheet status Change notice Supersedes 74LVC573A_4<tbd>Product data sheet-74LVC573A_3Modifications:•The format of this data sheet is redesigned to comply with the current presentation and information standard of Philips Semiconductors.•Table 4, Table 5, Table 6, Table 7 and Table 8: values added for lower voltage ranges.74LVC573A_3 (939775011938)20031003Product specification -74LVC573A_274LVC573A_2 (939775010494)20030526Product specification -74LVC573A_174LVC573A_1 (939775004513)19980729Product specification--15.Legal information15.1Data sheet status[1]Please consult the most recently issued document before initiating or completing a design. [2]The term ‘short data sheet’ is explained in section “Definitions”.[3]The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL .15.2DefinitionsDraft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Philips Semiconductors does not give any representations or warranties as to the accuracy or completeness ofinformation included herein and shall have no liability for the consequences of use of such information.Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Philips Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.15.3DisclaimersGeneral — Information in this document is believed to be accurate andreliable. However, Philips Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.Right to make changes — Philips Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.Suitability for use — Philips Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure ormalfunction of a Philips Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmentaldamage. Philips Semiconductors accepts no liability for inclusion and/or use of Philips Semiconductors products in such equipment or applications and therefore such inclusion and/or use is for the customer’s own risk.Applications — Applications that are described herein for any of theseproducts are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and andoperation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability.Terms and conditions of sale — Philips Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at /profile/terms , including thosepertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by PhilipsSemiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail.No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.15.4TrademarksNotice: All referenced brands, product names, service names and trademarks are the property of their respective owners.16.Contact informationFor additional information, please visit: For sales office addresses, send an email to: sales.addresses@Document status [1][2]Product status [3]DefinitionObjective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheetProductionThis document contains the product specification.17.Contents1General description. . . . . . . . . . . . . . . . . . . . . . 12Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Ordering information. . . . . . . . . . . . . . . . . . . . . 24Functional diagram . . . . . . . . . . . . . . . . . . . . . . 25Pinning information. . . . . . . . . . . . . . . . . . . . . . 45.1Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45.2Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 46Functional description . . . . . . . . . . . . . . . . . . . 57Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 58Recommended operating conditions. . . . . . . . 69Static characteristics. . . . . . . . . . . . . . . . . . . . . 610Dynamic characteristics. . . . . . . . . . . . . . . . . . 811AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 1012Package outline. . . . . . . . . . . . . . . . . . . . . . . . 1313Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 1714Revision history. . . . . . . . . . . . . . . . . . . . . . . . 1715Legal information. . . . . . . . . . . . . . . . . . . . . . . 1815.1Data sheet status . . . . . . . . . . . . . . . . . . . . . . 1815.2Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1815.3Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 1815.4Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 1816Contact information. . . . . . . . . . . . . . . . . . . . . 1817Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Please be aware that important notices concerning this document and the product(s)described herein, have been included in section ‘Legal information’.© Koninklijke Philips Electronics N.V.2006.All rights reserved.。
74ls573
首先说74LS373不是单片机，而是一个逻辑芯片，看下面：
74ls373是常用的地址锁存器芯片，它实质是一个是带三态缓冲输出的8D触发器，在单片机系统中为了扩展外部存储器，通常需要一块74ls373芯片。
<74ls373内部结构图> <74ls373引脚图>
(1).1脚是输出使能(OE),是低电平有效,当1脚是高电平时,不管输入3、4、7、8、13、14、17、18如何,也不管11脚(锁存控制端,G)如何,输出2(Q0)、5(Q1)、6(Q2)、9(Q3)、12(Q4)、15(Q5)、16(Q6)、19(Q7)全部呈现高阻状态(或者叫浮空状态);
(2).当1脚是低电平时,只要11脚(锁存控制端,G)上出现一个下降沿,输出2(Q0)、5(Q1)、6(Q2)、9(Q3)、12(Q4)、15(Q5)、16(Q6)、19(Q7)立即呈现输入脚3、4、7、8、13、14、17、18的状态.
锁存端LE 由高变低时，输出端8 位信息被锁存，直到LE 端再次有效。
当三态门使能信号OE为低电平时，三态门导通，允许Q0~Q7输出，OE为高电平时，输出悬空。
当74LS373用作地址锁存器时，应使OE为低电平，此时锁存使能端C为高电平时，输出Q0~Q7 状态与输入端D1~D7状态相同；当C发生负的跳变时，输入端D0~D7 数据锁入Q0~Q7。
51单片机的ALE信号可以直接与74LS373的C连接。
74ls573中文资料
74ls573中文资料三态总线驱动输出·置数全并行存取·缓冲控制输入·使能输入有改善抗扰度的滞后作用原理：74LS573 的八个锁存器都是透明的D 型锁存器，当使能（G）为高时，Q 输出将随数据（D）输入而变。
当使能为低时，输出将锁存在已建立的数据电平上。
输出控制不影响锁存器的内部工作，即老数据可以保持，甚至当输出被关闭时，新的数据也可以置入。
这种电路可以驱动大电容或低阻抗负载，可以直接与系统总线接口并驱动总线，而不需要外接口。
特别适用于缓冲寄存器，I/O 通道，双向总线驱动器和工作寄存器。
H=高电平 L=低电平×=不定 Z=高阻态QO=建立稳态输入条件前Q的电平引脚图及功能图Operating Conditions 操作条件Symbol 符号Parameter 参数DM74LS最小典型最大VCC Supply Voltage 电源电压 4.75 5 5.25VIH High Level Input Voltage输入高电平电压 2 - -VIL LOW Level Input Voltage 输入低电平电压- - 0.8IOH HIGH Level Input Current输入高电平电流- - −2.6IOL LOW Level Output Current低电平输出电流- - 24TA Free Air Operating Temperature工作温度0 - 70Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of th cannot be guaranteed. The device should not be operated at these limits. The parametri defined in the “Electrical Characteristics” table are not guaranteed at the absolute ratings. The “Recommended Operating Conditions” table will define the conditions fo device operation.Electrical Characteristics 直流电气特性Over recommended operating free air temperature range (unless otherwise noted)Symbol 符号Parameter 参数Conditions 条件最小典型最大单VI Input Clamp Voltage输入钳位电压VCC=最小, II=−18 mA - - −1.5VOH High Level OutputVoltage输出高电平电压VCC = 最小, IOH=最大,VIL = 最大2.73.4 -VOL Low Level OutputVoltage输出低电平电压VCC = 最小, IOL=最大- 0.35 0.5VIH = 最小- - -。
74lvxc3245mtcx原理
74LVXC3245MTCX原理1.概述本文档将介绍74LV XC3245M TC X芯片的原理、功能及使用方法。
该芯片是一种高集成度、高速驱动能力的双向总线转换器。
它具有诸多特点和应用场景，本文将详细讲解。
2. 74LVXC3245MTC X芯片的特点-双向总线转换器，能够实现逻辑电平的双向转换-低功耗设计，适用于电池供电系统-高速传输，最大传输速率可达100MH z-支持5V和3.3V之间的电平转换3.功能描述74LV XC3245MT CX芯片具有以下主要功能：3.1电平转换该芯片可以实现5V和3.3V之间的双向电平转换。
通过引脚的设置，可以将5V逻辑电平转换为3.3V逻辑电平，或者将3.3V逻辑电平转换为5V逻辑电平。
3.2双向传输该芯片支持双向数据传输，可以在两个总线之间进行数据的双向传输。
它能够实现将数据从一侧总线传输到另一侧总线，同时保持两侧总线的输入输出状态。
3.3高速传输74LV XC3245MT CX芯片具有高速传输的能力，最大传输速率可达100M Hz。
这使得它适用于高速数据传输的场景，如计算机总线、存储器接口等。
4.使用方法使用74LV XC3245MTC X芯片进行电平转换和双向传输的方法如下：1.设置引脚电平：根据需求，将DI R引脚设置为高电平或低电平，以确定数据传输的方向。
2.连接总线：将要进行转换的两个总线分别连接到A端和B端。
3.数据传输：通过控制DI R引脚的电平，实现双向数据的传输。
使用74LV XC3245MTC X芯片时需要注意以下事项：-确保供电电压符合芯片的规格要求，以避免损坏芯片或降低性能。
-使用正确的引脚连接方式，确保总线连接正确无误。
-在高速传输时，要保持信号线的稳定性，减少信号干扰。
5.应用场景74LV XC3245MT CX芯片广泛应用于以下场景：1.计算机总线：用于连接不同电平的总线，实现数据的双向传输和电平转换。
2.存储器接口：用于连接处理器和存储器，实现高速数据的传输。
74LV573A中文资料
74LV573A中⽂资料PACKAGING INFORMATIONOrderable Device Status (1)Package Type Package Drawing Pins Package Qty Eco Plan (2)Lead/Ball Finish MSL Peak Temp (3)SN74LV573ADBR ACTIVE SSOP DB 202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74LV573ADBRE4ACTIVE SSOPDB 202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74LV573ADGVR ACTIVE TVSOP DGV 202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74LV573ADGVRE4ACTIVE TVSOP DGV 202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74LV573ADW ACTIVE SOIC DW 2025Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74LV573ADWE4ACTIVE SOIC DW 2025Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74LV573ADWR ACTIVE SOIC DW 202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74LV573ADWRE4ACTIVE SOIC DW 202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74LV573AGQNRACTIVEBGA MI CROSTA R JUNI ORGQN201000TBDSNPBLevel-1-240C-UNLIMSN74LV573ANSR ACTIVE SO NS 202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74LV573ANSRE4ACTIVE SO NS 202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74LV573APW ACTIVE TSSOP PW 2070Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74LV573APWE4ACTIVE TSSOP PW 2070Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74LV573APWR ACTIVE TSSOP PW 202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74LV573APWRE4ACTIVE TSSOP PW 202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74LV573APWRG4ACTIVE TSSOP PW 202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74LV573APWT ACTIVE TSSOP PW 20250Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74LV573APWTE4ACTIVE TSSOP PW 20250Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74LV573ARGYR ACTIVE QFN RGY 201000Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR SN74LV573ARGYRG4ACTIVE QFN RGY 201000Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR SN74LV573AZQNRACTIVEBGA MI CROSTA R JUNI ORZQN201000Green (RoHS &no Sb/Br)SNAGCULevel-1-260C-UNLIM(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part ina new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan-The planned eco-friendly classification:Pb-Free(RoHS),Pb-Free(RoHS Exempt),or Green(RoHS&no Sb/Br)-please check /doc/c811093619.html/productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free(RoHS):TI's terms"Lead-Free"or"Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all6substances,including the requirement that lead not exceed0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free(RoHS Exempt):This component has a RoHS exemption for either1)lead-based flip-chip solder bumps used between the die and package,or2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free(RoHS compatible)as defined above.Green(RoHS&no Sb/Br):TI defines"Green"to mean Pb-Free(RoHS compatible),and free of Bromine(Br)andAntimony(Sb)based flame retardants(Br or Sb do not exceed0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.。
74LCX573WM资料
© 2005 Fairchild Semiconductor Corporation DS012405March 1995Revised March 200574LCX573 Low Voltage Octal Latch with 5V Tolerant Inputs and Outputs74LCX573Low Voltage Octal Latch with 5V Tolerant Inputs and OutputsGeneral DescriptionThe LCX573 is a high-speed octal latch with buffered com-mon Latch Enable (LE) and buffered common Output Enable (OE) inputs.The LCX573 is functionally identical to the LCX373 but has inputs and outputs on opposite sides.The LCX573 is designed for low voltage (3.3V or 2.5V)applications with capability of interfacing to a 5V signal environment. The LCX573 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation.Featuress 5V tolerant inputs and outputs s 2.3V–3.6V V CC specifications provided s 7.0 ns t PD max (V CC 3.3V), 10 P A I CC max s Power down high impedance inputs and outputs s Supports live insertion/withdrawal (Note 1)s r 24 mA output drive (V CC 3.0V)s Implements patented noise/EMI reduction circuitry s Latch-up performance exceeds JEDEC 78 conditions s ESD performance:Human body model ! 2000V Machine model ! 200Vs Leadless Pb-Free DQFN packageNote 1: To ensure the high-impedance state during power up or down, OE should be tied to V CC through a pull-up resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver.Ordering Code:Devices also available in T ape and Reel. Specify by appending the suffix letter “X ” to the ordering code.Pb-Free package per JEDEC J-STD-020B.Note 2: DQFN package available in Tape and Reel only.Note 3: “_NL ” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.Order Number Package Package DescriptionNumber 74LCX573WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LCX573SJ M20DPb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide74LCX573BQX (Preliminary)(Note 2)MLP020B Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDECMO-241, 2.5 x 4.5mm 74LCX573MSA MSA2020-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 74LCX573MTC MTC2020-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74LCX573MTCX_NL (Note 3)MTC20Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 274L C X 573Logic SymbolConnection DiagramsPin Assignments for SOIC, SOP, SSOP , TSSOPPad Assignments for DQFN(Top View)Pin DescriptionsTruth TableH HIGH Voltage L LOW Voltage Z High Impedance X ImmaterialO 0 Previous O 0 before HIGH-to-LOW transition of Latch EnableFunctional DescriptionThe LCX573 contains eight D-type latches with 3-STATE output buffers. When the Latch Enable (LE) input is HIGH,data on the D n inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches.Logic DiagramPlease note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.Pin Names DescriptionD 0–D 7Data Inputs LE Latch Enable InputOE 3-STATE Output Enable Input O 0–O 73-STATE Latch OutputsInputsOutputs OE LE D O n L H H H L H L L L L X O 0HXXZ74LCX573Absolute Maximum Ratings (Note 4)Recommended Operating Conditions (Note 6)Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-mended Operating Conditions ” table will define the conditions for actual device operation.Note 5: I O Absolute Maximum Rating must be observed.Note 6: Unused (inputs or I/O's) must be held HIGH or LOW. They may not float.DC Electrical CharacteristicsSymbol ParameterValueConditionsUnits V CC Supply Voltage 0.5 to 7.0V V I DC Input Voltage 0.5 to 7.0VV O DC Output Voltage 0.5 to 7.0Output in 3-STATEV 0.5 to V CC 0.5Output in HIGH or LOW State (Note 5)I IK DC Input Diode Current 50V I GND mA I OK DC Output Diode Current 50V O GND mA 50V O ! V CCI O DC Output Source/Sink Current r 50mA I CC DC Supply Current per Supply Pin r 100mA I GND DC Ground Current per Ground Pin r 100mAT STGStorage Temperature65 to 150q CSymbol ParameterMin Max Units V CC Supply Voltage Operating 2.0 3.6V Data Retention1.5 3.6V I Input Voltage 0 5.5V V O Output Voltage HIGH or LOW State0V CC V3-STATE5.5I OH /I OLOutput CurrentV CC 3.0V 3.6V r 24mAV CC 2.7V 3.0V r 12V CC 2.3V 2.7Vr 8T AFree-Air Operating Temperature4085q C 't/'VInput Edge Rate, V IN 0.8V 2.0V, V CC 3.0V10ns/VSymbol ParameterConditionsV CC T A 40q C to 85q C Units (V)Min MaxV IH HIGH Level Input Voltage 2.3 2.7 1.7V 2.7 3.6 2.0V IL LOW Level Input Voltage 2.3 2.70.7V2.73.60.8V OHHIGH Level Output VoltageI OH 100 P A 2.3 3.6V CC 0.2VI OH 8 mA 2.3 1.8I OH 12 mA 2.7 2.2I OH 18 mA 3.0 2.4I OH 24 mA3.0 2.2V OLLOW Level Output VoltageI OL 100 P A 2.3 3.60.2V I OL 8 mA 2.30.6I OL 12 mA 2.70.4I OL 16 mA 3.00.4I OL 24 mA3.00.55I I Input Leakage Current 0 d V I d 5.5V 2.3 3.6r 5.0P A I OZ 3-STATE Output Leakage 0 d V O d 5.5V 2.3 3.6r 5.0P A V I V IH or V IL I OFFPower-Off Leakage CurrentV I or V O 5.5V10P A 474L C X 573DC Electrical Characteristics (Continued)Note 7: Outputs disabled or 3-STATE only.AC Electrical CharacteristicsNote 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t OSHL ) or LOW-to-HIGH (t OSLH ).Dynamic Switching CharacteristicsCapacitanceSymbol ParameterConditionsV CC T A 40q C to 85q C Units (V)MinMax I CC Quiescent Supply Current V I V CC or GND2.33.610P A 3.6V d V I , V O d 5.5V (Note 7) 2.3 3.6r 10'I CCIncrease in I CC per InputV IH V CC 0.6V2.33.6500P ASymbolParameterT A 40q C to 85q C, R L 500 :UnitsV CC 3.3V r 0.3VV CC 2.7V V CC 2.5 r 0.2V C L 50pF C L 50pF C L 30pF MinMax Min Max Min Max t PHL Propagation Delay 1.58.0 1.59.0 1.59.6ns t PLH D n to O n1.58.0 1.59.0 1.59.6t PHL Propagation Delay 1.58.5 1.59.5 1.510.5ns t PLH LE to O n1.58.5 1.59.5 1.510.5t PZL Output Enable Time1.58.5 1.59.5 1.510.5ns t PZH 1.58.5 1.59.5 1.510.5t PLZ Output Disable Time 1.5 6.5 1.57.0 1.57.8ns t PHZ 1.5 6.51.57.01.57.8t S Setup Time, D n to LE 2.5 2.5 4.0ns t H Hold Time, D n to LE 1.5 1.5 2.0ns t W LE Pulse Width3.33.34.0ns t OSHL Output to Output Skew (Note 8) 1.0ns t OSLH1.0Symbol ParameterConditionsV CC T A 25q C Units (V)Typical V OLP Quiet Output Dynamic Peak V OL C L 50 pF, V IH 3.3V, V IL 0V 3.30.8V C L 30 pF, V IH 2.5V, V IL 0V 2.50.6V OLVQuiet Output Dynamic Valley V OLC L 50 pF, V IH 3.3V, V IL 0V 3.3 0.8VC L 30 pF, V IH 2.5V, V IL 0V2.50.6Symbol ParameterConditionsTypical Units C IN Input Capacitance V CC Open, V I 0V or V CC 7pF C OUT Output CapacitanceV CC 3.3V, V I 0V or V CC8pF C PDPower Dissipation CapacitanceV CC 3.3V, V I 0V or V CC , f 10 MHz25pF74LCX573AC LOADING and WAVEFORMS Generic for LCX FamilyFIGURE 1. AC Test Circuit (C L includes probe and jig capacitance)Waveform for Inverting and Non-Inverting FunctionsPropagation Delay. Pulse Width and t rec Waveforms3-STATE Output Low Enable andDisable Times for Logic3-STATE Output High Enable andDisable Times for LogicSetup Time, Hold Time and Recovery Time for Logict rise and t fallFIGURE 2. Waveforms(Input Characteristics; f =1MHz, t r = t f = 3ns)Test Switch t PLH , t PHL Opent PZL , t PLZ 6V at V CC 3.3 r 0.3V V CC x 2 at V CC 2.5 r 0.2Vt PZH ,t PHZGNDSymbol V CC3.3V r 0.3V2.7V 2.5V r 0.2V V mi 1.5V 1.5V V CC /2V mo 1.5V 1.5V V CC /2V x V OL 0.3V V OL 0.3V V OL 0.15V V yV OH 0.3VV OH 0.3VV OH 0.15V 674L C X 573Schematic DiagramGeneric for LCX Family74LCX573Tape and Reel SpecificationTape Format for DQFNTAPE DIMENSIONS inches (millimeters)REEL DIMENSIONS inches (millimeters)PackageTape Number Cavity Cover Tape DesignatorSection Cavities Status Status Leader (Start End)125 (typ)Empty Sealed BQXCarrier 3000Filled Sealed Trailer (Hub End)75 (typ)EmptySealedTape SizeA B C D N W1W212 mm13.00.0590.5120.795 2.1650.4880.724(330.0)(1.50)(13.00)(20.20)(55.00)(12.4)(18.4) 874L C X 573Physical Dimensionsinches (millimeters) unless otherwise noted20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" WidePackage Number M20B 74LCX573Physical Dimensions inches (millimeters) unless otherwise noted (Continued)Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm WidePackage Number M20D 1074L C X 573Physical Dimensionsinches (millimeters) unless otherwise noted (Continued)Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mmPackage Number MLP020B 74LCX573Physical Dimensions inches (millimeters) unless otherwise noted (Continued)20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm WidePackage Number MSA20 1274L C X 573 L o w V o l t a g e O c t a l L a t c h w i t h 5V T o l e r a n t I n p u t s a n d O u t p u t sPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm WidePackage Number MTC20Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICYFAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into thebody, or (b) support or sustain life, and (c) whose failureto perform when properly used in accordance withinstructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to theuser.2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or 。
74VHC573 Octal D-Type Latch with 3-STATE Outputs
74VHC573 Octal D-Type Latch with 3-STATE Outputs74VHC573 Octal D-Type Latch with 3-STATE OutputsLogic SymbolIEEE/IECTruth TableH = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High ImpedanceFunctional DescriptionThe VHC573 contains eight D-type latches with 3-STATE output buffers. When the Latch Enable (LE)input is HIGH, data on the D n inputs enters the latches.In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes.When LE is LOW the latches store the information that was present on the D inputs, a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode, but, this does not interfere with entering new data into the latches.Logic DiagramPlease note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.InputsOutputsOE LE D O n L H H H L H L L L L X O 0HXXZ74VHC573 Octal D-Type Latch with 3-STATE OutputsAbsolute Maximum RatingsStresses exceeding the absolute maximum ratings may damage the device. The device may not function or beoperable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.Recommended Operating Conditions (1)The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.Note:1.Unused inputs must be held HIGH or LOW. They may not float.Symbol ParameterRatingV CC Supply Voltage –0.5V to +7.0V V IN DC Input Voltage –0.5V to +7.0V V OUT DC Output Voltage –0.5V to V CC + 0.5VI IK Input Diode Current –20mA I OK Output Diode Current ±20mA I OUT DC Output Current ±25mA I CC DC V CC /GND Current ±75mAT STG Storage Temperature–65°C to +150°CT LLead Temperature (Soldering, 10 seconds)260°CSymbol ParameterRatingV CC Supply Voltage 2.0V to +5.5V V IN Input Voltage 0V to +5.5V V OUT Output Voltage 0V to V CCT OPR Operating Temperature –40°C to +85°C t r , t fInput Rise and Fall Time, V CC = 3.3V ± 0.3VV CC =5.0V ± 0.5V0ns/V ∼ 100ns/V 0ns/V ∼20ns/V74VHC573 Octal D-Type Latch with 3-STATE OutputsDC Electrical CharacteristicsNoise CharacteristicsNote:2.Parameter guaranteed by design.SymbolParameterV CC (V)Conditions T A = 25°CT A = –40°C to +85°CUnitsMin.Typ.Max.Min.Max. V IH HIGH Level Input Voltage2.0 1.50 1.50V3.0–5.50.7 x V CC0.7 x V CCV IL LOW Level Input Voltage 2.00.500.50V3.0–5.50.3 x V CC0.3 x V CCV OHHIGH Level Output Voltage2.0V IN = V IH or V ILI OH = –50µA 1.9 2.0 1.9V 3.0 2.9 3.0 2.94.5 4.44.54.43.0I OH = –4mA 2.58 2.484.5I OH = –8mA3.943.80V OLLOW Level Output Voltage2.0V IN = V IH or V ILI OL = 50µA 0.00.10.1V3.00.00.10.14.50.00.10.13.0I OL = 4mA 0.360.444.5I OL = 8mA0.360.44I OZ 3-STATE Output Off-State Current 5.5V IN = V IH or V IL , V OUT = V CC or GND ±0.25±2.5µA I IN Input Leakage Current0–5.5V IN = 5.5V or GND ±0.1±1.0 µA I CCQuiescent Supply Current5.5V IN = V CC or GND4.040.0µASymbolParameterV CC (V)ConditionsT A = 25°CUnitsTyp.LimitsV OLP (2) Quiet Output Maximum Dynamic V OL5.0C L= 50pF 0.9 1.2V V OLV (2)Quiet Output Minimum Dynamic V OL5.0C L = 50pF –0.8–1.0V V IHD (2)Minimum HIGH Level Dynamic Input Voltage 5.0C L = 50pF 3.5V V ILD (2)Maximum LOW Level Dynamic Input Voltage5.0C L = 50pF1.5V74VHC573 Octal D-Type Latch with 3-STATE OutputsAC Electrical CharacteristicsNotes:3.Parameter guaranteed by design. t OSLH = |t PLH max – t PLH min |; t OSHL = |t PHL max – t PHL min |4.C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation:I CC (Opr.) = C PD • V CC • f IN + I CC / 8 (per Latch). The total C PD when n pcs. of the Latch operates can be calculated by the equation: C PD (total) = 21 + 8n.AC Operating RequirementsSymbolParameterV CC (V)ConditionsT A = 25°CT A = –40°C to +85°CUnitsMin.Typ.Max.Min.Max.t PLH , t PHLPropagation Delay Time (LE to O n )3.3 ± 0.3C L = 15pF 7.611.9 1.014.0nsC L = 50pF 10.115.4 1.017.55.0 ± 0.5C L = 15pF 5.07.7 1.09.0C L = 50pF 6.59.7 1.011.0t PLH , t PHLPropagation Delay Time (D–O n )3.3 ± 0.3C L = 15pF 7.011.0 1.013.0nsC L = 50pF 9.514.5 1.016.55.0 ± 0.5C L = 15pF 4.5 6.8 1.08.0C L = 50pF6.08.8 1.010.0t PZL , t PZH3-STATE Output Enable Time3.3 ± 0.3R L = 1k ΩC L = 15pF 7.311.5 1.013.5nsC L = 50pF 9.815.0 1.017.05.0 ± 0.5C L = 15pF 5.27.7 1.09.0C L = 50pF6.79.7 1.011.0t PLZ , t PHZ3-STATE Output Disable Time3.3 ± 0.3R L = 1k ΩC L = 50pF 10.714.5 1.016.5ns 5.0 ± 0.5C L = 50pF 6.79.7 1.011.0t OSLH , t OSHL Output to OutputSkew3.3 ± 0.3(3)C L = 50pF 1.5 1.5ns 5.0 ± 0.5C L = 50pF1.01.0C IN Input Capacitance V CC = Open 41010pF C OUT Output Capacitance V CC = 5.0V6pF C PDPower Dissipation Capacitance(4)29pFSymbol Parameter V CC (V)T A = 25°C T A = –40°C to+85°CUnitsMin.Typ.Max.Min.Max.t w (H), t w (L)Minimum Pulse Width (LE)3.3 ± 0.3 5.0 5.0ns5.0 ± 0.55.0 5.0t S Minimum Setup Time 3.3 ± 0.3 3.5 3.5ns5.0 ± 0.5 3.5 3.5t HMinimum Hold Time3.3 ± 0.3 1.5 1.5ns 5.0 ± 0.51.51.5Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" WidePackage Number M20B74VHC573 Octal D-Type Latch with 3-STATE Outputs The™TinyBoost。
74HC573_74HCT573
74HC573/74HCT573（锁存器）
一、简介
74HC573/74HCT573是高速硅门CMOS工艺集成电路，兼容TTL（LSTTL），符合JED EC-7A标准，它将输入数据分别锁存在不同的锁存器上，三态门输出。
锁存器的输入使能端是LE，输出使能端是OE。
当LE端是高电平时，数据进入锁存器；当LE端是低电平时，锁存器保留数据。
当OE端是低电平时，8个锁存器的数据输出有效；当OE端是高电平时，输出端为高阻抗，OE端输入不会影响锁存器中的数据。
二、特点
z输入与输出接口分别置于封装两面，有利于与微处理器相接；
z输入输出接口可与微处理器或微机相接；
z三态门正相输出；
z总线驱动；
z采用DIP20或PLCC20封装形式。
三、内部框图
四、引脚功能。
74LVX573MTR,74LVX573TTR, 规格书,Datasheet 资料
1/13August 2004sHIGH SPEED:t PD =6.4ns (TYP.) at V CC = 3.3V s 5V TOLERANT INPUTSs POWER-DOWN PROTECTION ON INPUTS sINPUT VOLTAGE LEVEL:V IL = 0.8V, V IH = 2V at V CC =3V sLOW POWER DISSIPATION:I CC = 4 µA (MAX.) at T A =25°C sLOW NOISE:V OLP = 0.3V (TYP .) at V CC =3.3VsSYMMETRICAL OUTPUT IMPEDANCE:|I OH | = I OL = 4 mA (MIN) at V CC = 3V sBALANCED PROPAGATION DELAYS:t PLH ≅ t PHLsOPERATING VOLTAGE RANGE:V CC (OPR) = 2V to 3.6V (1.2V Data Retention)sPIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573sIMPROVED LATCH-UP IMMUNITYDESCRIPTIONThe 74LVX573 is a low voltage CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C 2MOS technology. It is ideal for low power, battery operated and low noise 3.3V applications.This 8 bit D-Type latch is controlled by a latch enable input (LE) and an output enable input (OE).While the LE input is held at a high level, the Q outputs will follow the data input precisely.When the LE is taken low, the Q outputs will be latched precisely at the logic level of D input data.While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state.Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage.This device can be used to interface 5V to 3V. It combines high speed performance with the true CMOS low power consumption.All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.74LVX573LOW VOLTAGE CMOS OCTAL D-TYPE LATCH (3-STATE NON INV.) WITH 5V TOLERANT INPUTSTable 1: Order CodesPACKAGE T & R SOP 74LVX573MTR TSSOP74LVX573TTR74LVX5732/13Figure 2: Input Equivalent CircuitTable 2: Pin DescriptionTable 3: Truth TableX : Don’t CareZ : High Impedance* : Q Outputs are Latched at the time when the LE INPUT is taken low logic levelFigure 3: Logic DiagramThis logic diagram has not be used to estimate propagation delaysPIN N°SYMBOL NAME AND FUNCTION 1OE 3 State Output Enable Input (Active LOW)2, 3, 4, 5, 6, 7, 8, 9D0 to D7 Data Inputs12, 13, 14, 15, 16, 17, 18, 19Q0 to Q73-State Latch Outputs11LE Latch Enable Input 10GND Ground (0V)20V CCPositive Supply VoltageINPUTSOUTPUTOE LE DQH X X Z L L X NOCHANGE*L H L L LHHH74LVX5733/13Table 4: Absolute Maximum RatingsAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not impliedTable 5: Recommended Operating Conditions1) Truth Table guaranteed: 1.2V to 3.6V 2) V IN from 0.8V to 2.0VTable 6: DC SpecificationsSymbol ParameterValue Unit V CC Supply Voltage -0.5 to +7.0V V I DC Input Voltage -0.5 to +7.0V V O DC Output Voltage -0.5 to V CC + 0.5V I IK DC Input Diode Current - 20mA I OK DC Output Diode Current ± 20mA I O DC Output Current ± 25mA I CC or I GND DC V CC or Ground Current± 50mA T stg Storage Temperature -65 to +150°C T LLead Temperature (10 sec)300°CSymbol ParameterValue Unit V CC Supply Voltage (note 1) 2 to 3.6V V I Input Voltage 0 to 5.5V V O Output Voltage 0 to V CC V T op Operating Temperature-55 to 125°C dt/dvInput Rise and Fall Time (note 2) (V CC = 3V)0 to 100ns/VSymbolParameterTest ConditionValue Unit V CC (V)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.Max.Min.Max.V IHHigh Level Input Voltage2.0 1.5 1.5 1.5V3.0 2.0 2.0 2.03.6 2.42.42.4V ILLow Level Input Voltage2.00.50.50.5V3.00.80.80.83.60.80.80.8V OHHigh Level Output Voltage2.0I O =-50 µA 1.9 2.0 1.9 1.9V3.0I O =-50 µA 2.9 3.02.9 2.93.0I O =-4 mA 2.582.482.4V OLLow Level Output Voltage2.0I O =50 µA 0.00.10.10.1V3.0I O =50 µA 0.00.10.10.13.0I O =4 mA 0.360.440.55I OZ High Impedance Output Leakage Current3.6V I = V IH or V IL V O = V CC or GND ±0.25± 2.5± 2.5µA I I Input Leakage Current 3.6V I = 5V or GND ± 0.1± 1± 1µA I CCQuiescent Supply Current3.6V I = V CC or GND44040µA74LVX5734/13Table 7: Dynamic Switching Characteristics1) Worst case package.2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V ILD ), 0V to threshold (V IHD ), f=1MHz.Table 8: AC Electrical Characteristics (Input t r = t f = 3ns)1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-ing in the same direction, either HIGH or LOW 2) Parameter guaranteed by design (*) Voltage range is 3.3V ± 0.3VSymbolParameterTest ConditionValue UnitV CC (V)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.Max.Min.Max.V OLP Dynamic Low Voltage Quiet Output (note 1, 2) 3.3C L = 50 pF0.30.8VV OLV -0.8-0.3V IHD Dynamic High Voltage Input (note 1, 3) 3.32.0V ILDDynamic Low Voltage Input (note 1, 3)3.30.8SymbolParameterTest ConditionValue UnitV CC (V)C L (pF)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.Max.Min.Max.t PLH t PHLPropagation Delay Time LE to Q2.7158.215.6 1.018.5 1.018.5ns2.75010.719.1 1.022.0 1.022.03.3(*)15 6.410.1 1.012.0 1.012.03.3(*)508.913.6 1.015.5 1.015.5t PLH t PHLPropagation Delay Time D to Q2.7157.614.5 1.017.5 1.017.5ns2.75010.118.0 1.021.0 1.021.03.3(*)15 5.99.3 1.011.0 1.011.03.3(*)508.412.8 1.014.5 1.014.5t PZL t PZHOutput Enable Time2.7157.815.0 1.018.5 1.018.5ns2.75010.318.5 1.022.0 1.022.03.3(*)15 6.19.7 1.012.0 1.012.03.3(*)508.613.2 1.015.5 1.015.5t PLZ t PHZ Output Disable Time2.75012.119.1 1.022.0 1.022.0ns3.3(*)5010.113.6 1.015.5 1.015.5t W LE pulse Width, HIGH2.750 6.57.57.5ns 3.3(*)50 5.0 5.0 5.0t S Setup Time D to LE HIGH or LOW 2.750 5.0 5.0 5.0ns 3.3(*)50 3.5 3.5 3.5t hHold Time D to LEHIGH or LOW 2.750 1.5 1.5 1.5ns 3.3(*)50 1.5 1.5 1.5t OSLH t OSHLOutput to Output Skew Time (note1,2)2.7500.5 1.0 1.5 1.5ns3.3(*)500.5 1.01.51.574LVX5735/13Table 9: Capacitive Characteristics1) C PD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I CC(opr) = C PD x V CC x f IN + I CC /8 (per circuit)Figure 4: Test CircuitC L =15/50pF or equivalent (includes jig and probe capacitance)R L = R1 = 1K Ω or equivalentR T = Z OUT of pulse generator (typically 50Ω)SymbolParameterTest ConditionValue UnitV CC (V)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.Max.Min.Max.C IN Input Capacitance 3.34101010pF C OUT OutputCapacitance3.36pF C PDPower Dissipation Capacitance (note 1)3.3f IN = 10MHz29pF TESTSWITCH t PLH , t PHL Opent PZL , t PLZ V CC t PZH , t PHZGND74LVX573Figure 5: Waveform - LE To Qn Propagation Delays, Le Minimun Pulse Width, Dn To LE Setup And Hold Times (f=1MHz; 50% duty cycle)Figure 6: Waveform - Output Enable And Disable Times (f=1MHz; 50% duty cycle)74LVX573 Figure 7: Waveform - Propagation Delay Time (f=1MHz; 50% duty cycle)7/1374LVX5738/13DIM.mm.inchMIN.TYP MAX.MIN.TYP.MAX.A 2.35 2.650.0930.104 A10.10.300.0040.012 B0.330.510.0130.020 C0.230.320.0090.013 D12.6013.000.4960.512 E7.47.60.2910.299 e 1.270.050H10.0010.650.3940.419 h0.250.750.0100.030 L0.4 1.270.0160.050 k0°8°0°8°ddd0.1000.004SO-20 MECHANICAL DATA0016022D74LVX5739/13DIM.mm.inchMIN.TYPMAX.MIN.TYP.MAX.A 1.20.047A10.050.150.0020.0040.006A20.81 1.050.0310.0390.041b 0.190.300.0070.012c 0.090.200.0040.0079D 6.4 6.5 6.60.2520.2560.260E 6.2 6.4 6.60.2440.2520.260E1 4.34.4 4.480.1690.1730.176e 0.65 BSC0.0256 BSCK 0˚8˚0˚8˚L0.450.600.750.0180.0240.030TSSOP20 MECHANICAL DATAcEbA2AE1D1PIN 1 IDENTIFICATIONA1LK e0087225C74LVX573Tape & Reel SO-20 MECHANICAL DATAmm.inch DIM.MIN.TYP MAX.MIN.TYP.MAX.A33012.992 C12.813.20.5040.519 D20.20.795N60 2.362T30.4 1.197 Ao10.8110.4250.433 Bo13.213.40.5200.528 Ko 3.1 3.30.1220.130 Po 3.9 4.10.1530.161 P11.912.10.4680.47610/1374LVX573 Tape & Reel TSSOP20 MECHANICAL DATAmm.inchDIM.MIN.TYP MAX.MIN.TYP.MAX.A33012.992C12.813.20.5040.519D20.20.795N60 2.362T22.40.882Ao 6.870.2680.276Bo 6.97.10.2720.280Ko 1.7 1.90.0670.075Po 3.9 4.10.1530.161P11.912.10.4680.47611/1374LVX573Table 10: Revision HistoryDate Revision Description of Changes 27-Aug-20044Ordering Codes Revision - pag. 1.12/1374LVX573 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is grantedby implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are notauthorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.The ST logo is a registered trademark of STMicroelectronicsAll other names are the property of their respective owners© 2004 STMicroelectronics - All Rights ReservedSTMicroelectronics group of companiesAustralia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America13/13。
HD74LVC573AT资料
HD74LVC573AOctal D-type Transparent Latches with 3-state OutputsADE-205-116B(Z)3rd EditionDecember 1996 DescriptionThe HD74LVC573A has eight D type latches with three state outputs in a 20 pin package. When the latch enable input is high, the Q outputs will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. Low voltage and high speed operation is suitable at the battery drive product (note type personal computer) and low power consumption extends the life of a battery for long time operation.Features•V CC = 2.0 V to 5.5 V•All inputs V IH (Max.) = 5.5 V (@V CC = 0 V to 5.5 V)•All outputs V OUT (Max.) = 5.5 V (@V CC = 0 V or output off state)•Typical V OL ground bounce < 0.8 V (@V CC = 3.3 V, Ta = 25°C)•Typical V OH undershoot > 2.0 V (@V CC = 3.3 V, Ta = 25°C)•High output current ±24 mA (@V CC = 3.0 V to 5.5 V)HD74LVC573ARev.3, Dec. 1996, page 2 of 11Function TableInputsOC LE D Output Q L H H H L H L L L L X Q 0H XXZH :High level L :Low level X :ImmaterialZ :High impedanceQ 0 :Level of Q before the indicated steady input conditions were established.Pin ArrangementHD74LVC573ARev.3, Dec. 1996, page 3 of 11Absolute Maximum RatingsItemSymbol Ratings Unit ConditionsSupply voltage V CC –0.5 to 6.0V Input diode current I IK –50mA V I = –0.5 V Input voltage V I –0.5 to 6.0V Output diode current I OK –50mA V O = –0.5 V 50mA V O = V CC +0.5 V Output voltage V O –0.5 to V CC +0.5V Output "H" or "L"–0.5 to 6.0V Output "Z" or V CC :OFF Output current I O±50mA V CC , GND current / pin I CC or I GND 100mA Storage temperatureTstg–65 to +150°CNote:The absolute maximum ratings are values which must not individually be exceeded, and furthermore,no two of which may be realized at the same time.Recommended Operating ConditionsItemSymbol Ratings Unit Conditions Supply voltage V CC 1.5 to 5.5V Data hold 2.0 to 5.5V At operation Input / output voltageV I 0 to 5.5V OC , LE, D V O0 to V CC V Output "H" or "L"0 to 5.5V Output "Z" or V CC :OFFOperating temperature Ta –40 to 85°C Output currentI OH –12mA V CC = 2.7 V –24*2mA V CC = 3.0 V to 5.5 V I OL12mA V CC = 2.7 V 24*2mA V CC = 3.0 V to 5.5 V Input rise / fall time *1t r , t f10ns/VNotes: 1.This item guarantees maximum limit when one input switches.Waveform : Refer to test circuit of switching characteristics.2.duty cycle ≤ 50%HD74LVC573ARev.3, Dec. 1996, page 4 of 11Electrical CharacteristicsTa = –40 to 85°CItem Symbol V CC (V)Min Max Unit Test Conditions Input voltageV IH 2.7 to 3.6 2.0—V 4.5 to 5.5V CC ×0.7—V V IL2.7 to3.6—0.8V 4.5 to 5.5—V CC ×0.3V Output voltageV OH2.7 to 5.5V CC –0.2—V I OH = –100 µA 2.7 2.2—V I OH = –12 mA3.0 2.4—V 3.0 2.2—V I OH = –24 mA4.53.8—V V OL2.7 to 5.5—0.2V I OL = 100 µA 2.7—0.4V I OL = 12 mA3.0—0.55V I OL = 24 mA4.5—0.55V Input currentI IN 0 to 5.5—±5.0µA V IN = 5.5 V or GND Off state output current I OZ 2.7 to 5.5—±5.0µA V IN = V CC , GNDV OUT = 5.5 V or GND Output leak currentI OFF0—20µA V IN / V OUT = 5.5 V Quiescent supply current I CC2.7 to3.6—±10µA V IN / V OUT = 3.6 to 5.5 V 2.7 to 5.5—10µA V IN = V CC or GND∆I CC3.0 to 3.6—500µAV IN = one input at(V CC –0.6)V,other inputs at V CC or GNDHD74LVC573ARev.3, Dec. 1996, page 5 of 11Switching CharacteristicsTa = –40 to 85°CItemSymbol V CC (V)Min Typ Max Unit From (Input)To (Output)Propagation delay timet PLH 2.7——9.0ns DQt PHL 3.3±0.3 1.5—8.0ns 5.0±0.5—— 6.5ns t PLH 2.7——9.5ns LEQt PHL3.3±0.3 1.5—8.5ns 5.0±0.5——7.0ns Output enable timet ZH 2.7——9.5ns OCQt ZL3.3±0.3 1.5—8.5ns 5.0±0.5——7.0ns Output disable timet HZ 2.7——8.5ns OCQt LZ3.3±0.3 1.5—7.5ns 5.0±0.5—— 6.5ns Setup timet su2.7 2.0——ns3.3±0.3 2.0——ns 5.0±0.52.0——ns Hold timet h2.7 1.5——ns3.3±0.3 1.5——ns 5.0±0.51.5——ns Pulse widtht w2.73.3——ns 3.3±0.3 3.3——ns 5.0±0.53.3——ns Between output pins skew *1t OSLH 2.7———ns t OSHL3.3±0.3—— 1.0ns 5.0±0.5—— 1.0ns Input capacitance C IN 2.7— 3.0—pF Output capacitance C O2.7—15.0—pFNote:1.This parameter is characterized but not tested.tos LH = | t PLHm - t PLHn |, tos HL = | t PHLm - t PHLn |HD74LVC573ATest CircuitWaveforms – 1Rev.3, Dec. 1996, page 6 of 11HD74LVC573A Waveforms – 2Waveforms – 3Rev.3, Dec. 1996, page 7 of 11HD74LVC573A Waveforms – 4Rev.3, Dec. 1996, page 8 of 11HD74LVC573A Package DimensionsRev.3, Dec. 1996, page 9 of 11HD74LVC573ARev.3, Dec. 1996, page 10 of 11HD74LVC573ARev.3, Dec. 1996, page 11 of 11Disclaimer1.Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,copyright, trademark, or other intellectual property rights for information contained in this document.Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.2.Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use.3.Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,traffic, safety equipment or medical equipment for life support.4.Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installationconditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product.5.This product is not designed to be radiation resistant.6.No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi.7.Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products.Sales OfficesHitachi, Ltd.Semiconductor & Integrated Circuits.Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109Copyright Hitachi, Ltd., 2000. All rights reserved. Printed in Japan.Hitachi Asia Ltd. Hitachi Tower16 Collyer Quay #20-00, Singapore 049318Tel : <65>-538-6533/538-8577 Fax : <65>-538-6933/538-3877URL : .sg URLNorthAmerica : /Europe : /hel/ecg Asia : Japan : http://www.hitachi.co.jp/Sicd/indx.htmHitachi Asia Ltd.(Taipei Branch Office)4/F, No. 167, Tun Hwa North Road, Hung-Kuo Building, Taipei (105), Taiwan Tel : <886>-(2)-2718-3666 Fax : <886>-(2)-2718-8180 Telex : 23222 HAS-TPURL : Hitachi Asia (Hong Kong) Ltd.Group III (Electronic Components) 7/F., North Tower, World Finance Centre,Harbour City, Canton Road Tsim Sha Tsui, Kowloon, Hong KongTel : <852>-(2)-735-9218 Fax : <852>-(2)-730-0281URL : Hitachi Europe Ltd.Electronic Components Group.Whitebrook ParkLower Cookham Road MaidenheadBerkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000Fax: <44> (1628) 585160Hitachi Europe GmbHElectronic Components Group Dornacher Stra ße 3D-85622 Feldkirchen, Munich GermanyTel: <49> (89) 9 9180-0Fax: <49> (89) 9 29 30 00Hitachi Semiconductor (America) Inc.179 East Tasman Drive,San Jose,CA 95134 Tel: <1> (408) 433-1990Fax: <1>(408) 433-0223For further information write to:Colophon 2.0。
74ls573工作原理
74ls573工作原理Title: Understanding the Working Principle of 74LS573The 74LS573 is a 3-state octal D-type latch with three-state outputs. It is designed to operate with low power consumption and high speed, making it a popular choice in various digital circuits.74LS573是一个具有三态输出的3态8位D型锁存器。
它设计用于低功耗和高速操作，因此在各种数字电路中备受欢迎。
The latch function of the 74LS573 allows it to store and retain data even when the input signals change. This is achieved through the use of internal latches that capture the data on the rising edge of the latch enable (LE) input.74LS573的锁存功能使其能够在输入信号改变时存储和保留数据。
这是通过内部锁存器实现的，这些锁存器在锁存使能（LE）输入的上升沿捕获数据。
When the LE input is high, the data present on the D inputs is latched and appears on the Q outputs. Conversely, when LE is low, the Q outputs are in a high-impedance state, effectively disconnecting them from the internal circuitry.当LE输入为高电平时，D输入上的数据被锁存并出现在Q输出上。
74CH573锁存器的功能
174CH573锁存器的功能74HC573和74LS373原理一样，8数据锁存器。
主要用于数码管、按键等等的控制。
74HC573有20个脚，数据的进和出没有逻辑关系，这个芯片主要是看高电压激活还是低电压激活：1是低电压激活芯片2~9脚是数据的输入脚从D0到D710脚是接地11脚是高电压激活芯片12~19脚是数据的输出脚1.真值表74HC573真值表,意思如下：第一行/第二行：当OE＝0、LE＝1时，输出端数据等于输入端数据； 第三行：当OE＝0、LE＝0时，输出端保持不变；第四行：当OE＝1是无论Dn、LE为何，输出端为高阻态；2. 高阻态就是输出既不是高电平，也不是低电平，而是高阻抗的状态；在这种状态下，可以多个芯片并联输出；但是，这些芯片中只能有一个处于非高阻态状态，否则会将芯片烧毁。
高阻态的概念在RS232和RS422通讯中还可以用到。
3. 数据锁存当输入的数据消失时，在芯片的输出端,数据仍然保持；这个概念在并行数据扩展中经常使用到。
4. 数据缓冲加强驱动能力：74LS244/74LS245/74LS373/74LS573都具备数据缓冲的能力。
OE：output_enable，输出使能；LE：latch_enable，数据锁存使能，atch是锁存的意思； Dn：第n路输入数据； On：第n路输出数据；74HC573波形图,在实际应用的时候是这样做的：a． OE＝0；b．先将数据从单片机的口线上输出到Dn； c．再将LE从0->1->0 ；d．这时，你所需要输出的数据就锁存在On上了，输入的数据在变化也影响不到输出的数据了；实际上,单片机现在在忙着干别的事情，串行通信、扫描键盘……单片机的资源有限啊。
在单片机按照RAM方式进行并行数据的扩展时,使用movx @dptr, A这条指令时，这些时序是由单片机来实现的。
后面的表格中还有需要时间的参数，你不需要去管它，因为这些参数都是几十ns 级别的，对于单片机在12M下的每个指令周期最小是1us的情况下，完全可以实现；如果是你自己来实现这个逻辑，类似的指令如下：MOV P0,A //将数据输出到并行数据端口 CLR LESETB LECLR LE ; //上面三条指令完成LE的波形从0->1->0的变化74LS573跟74LS373逻辑上完全一样,只不过是管脚定义不一样,数据输入和输出端.。
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74LVT573, 74LVTH573 — Low Voltage Octal Transparent Latch with 3-STATE OutputsLow Voltage Octal Transparent Latch with 3-STATE OutputsFeatures■ Input and output interface capability to systems at 5V V CC■Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH573), also available without bushold feature (74LVT573) ■ Live insertion/extraction permitted■ Power Up/Down high impedance provides glitch-free bus loading■ Outputs source/sink –32mA/+64mA■ Functionally compatible with the 74 series 573 ■ Latch-up performance exceeds 500mA ■ESD performance:– Human-body model > 2000V – Machine model > 200V– Charged-device model > 1000VGeneral DescriptionThe LVT573 and LVTH573 consist of eight latches with 3-STATE outputs for bus organized system applica-tions. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state.The LVTH573 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs.These octal latches are designed for low-voltage (3.3V)V CC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT573 and LVTH573 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation.Ordering InformationDevice also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.All packages are lead free per JEDEC: J-STD-020B standard.Order NumberPackage NumberPackage Description74LVT573WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVT573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide74LVT573MSA MSA2020-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 74LVT573MTC MTC2020-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide74LVTH573WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVTH573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide74LVTH573MSA MSA2020-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 74LVTH573MTCMTC2020-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm WidePin DescriptionFunctional DescriptionThe LVT573 and LVTH573 contain eight D-type latches with 3-STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the D n inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D-type input changes. When LE is LOW, the latches store the infor-mation that was present on the D-type inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard out-puts are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.IEEE/IECTruth TableH = HIGH Voltage LevelL = LOW Voltage LevelZ = High ImpedanceX = ImmaterialO0= Previous O0 before HIGH to LOW transition of Latch EnablePin Names DescriptionD0–D7Data InputsLE Latch Enable InputOE Output Enable InputO0–O73-STATE Latch OutputsInputs OutputsLE OE D n O nX H X ZH L L LH L H HL L X O074LVT573, 74LVTH573 — Low Voltage Octal Transparent Latch with 3-STATE Outputs74LVT573, 74LVTH573 — Low Voltage Octal Transparent Latch with 3-STATE Outputs Please note that this diagram is provided only for the understanding of logic operations and should not be used toestimate propagation delays.74LVT573, 74LVTH573 — Low Voltage Octal Transparent Latch with 3-STATE OutputsNote:1.I O Absolute Maximum Rating must be observed.Recommended Operating ConditionsThe Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.V CC Supply Voltage –0.5V to +4.6V V I DC Input Voltage –0.5V to +7.0V V ODC Output Voltage Output in 3-STATE–0.5V to +7.0V Output in HIGH or LOW State (1)–0.5V to +7.0VI IK DC Input Diode Current, V I < GND –50mA I OK DC Output Diode Current, V O < GND –50mA I ODC Output Current, V O > V CC Output at HIGH State 64mA Output at LOW State128mA I CC DC Supply Current per Supply Pin ±64mA I GND DC Ground Current per Ground Pin ±128mAT STGStorage Temperature–65°C to +150°CSymbolParameter MinMaxUnitsV CC Supply Voltage 2.7 3.6V V I Input Voltage5.5V I OH HIGH-Level Output Current –32mA I OL LOW-Level Output Current 64mA T A Free-Air Operating Temperature–4085°C ∆ t / ∆ VInput Edge Rate, V IN = 0.8V–2.0V , V CC =3.0V10ns/VNotes:2.All typical values are at V CC=3.3V, T A= 25°C.3.Applies to bushold versions only (74LVTH573).V O≥ V CC – 0.1VV IL Input LOW Voltage 2.7–3.60.8V V OH Output HIGH Voltage 2.7–3.6I OH= –100µA V CC – 0.2 V2.7I OH= –8mA 2.43.0I OH= –32mA 2.0V OL Output LOW Voltage 2.7I OL= 100µA 0.2VI OL= 24mA0.53.0I OL= 16mA 0.4I OL= 32mA0.5I OL= 64mA 0.55I I(HOLD)(3)Bushold Input MinimumDrive 3.0V I= 0.8V75µAV I= 2.0V –75I I(OD)(3)Bushold Input Over-DriveCurrent to Change State 3.0(4)500µA(5)–500I I Input Current 3.6V I= 5.5V10µAControl Pins 3.6V I= 0V or V CC±1Data Pins 3.6V I= 0V–5V I= V CC 1I OFF Power Off Leakage Current 00V ≤ V I or V O≤ 5.5V±100µAI PU/PD Power up/down 3-STATEOutput Current 0–1.5V O= 0.5V to 3.0V,V I= GND or V CC±100µAI OZL3-STATE Output LeakageCurrent3.6V O= 0.5V–5 µAI OZH3-STATE Output LeakageCurrent3.6V O= 3.0V5µAI OZH+3-STATE Output LeakageCurrent3.6V CC< V O≤ 5.5V 10µAI CCH Power Supply Current 3.6Outputs HIGH0.19mA I CCL Power Supply Current 3.6Outputs LOW5mA I CCZ Power Supply Current 3.6Outputs Disabled 0.19mA I CCZ+Power Supply Current 3.6V CC≤ V O≤ 5.5V,Outputs Disabled0.19mA∆I CC Increase in Power SupplyCurrent(6)3.6One Input at V CC – 0.6V,Other Inputs at V CC orGND0.2mA74LVT573, 74LVTH573 — Low Voltage Octal Transparent Latch with 3-STATE Outputs10.Skew is defined as the absolute value of the difference between the actual propagation delay for any twoseparate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t OSHL) or LOW-to-HIGH (t OSLH).Capacitance(11)Symbol Parameter Conditions Typical UnitsC IN Input Capacitance V CC= Open, V I= 0V or V CC4pFC OUT Output Capacitance V CC= 3.0V, V O= 0V or V CC6pF Note:Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" WidePackage drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products.Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:/packaging/Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm WidePackage drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify orFigure 3. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm WidePackage drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,Figure 4. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm WidePackage drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner©1999 Fairchild Semiconductor Corporation 74LVT573, 74LVTH573 Rev. 1.7.011subsidiaries,and is not intended to be an exhaustive list of all such trademarks.ACEx ®Build it Now™CorePLUS™CROSSVOLT ™CTL™Current Transfer Logic™EcoSPARK ®EZSWITCH™*™®Fairchild ®Fairchild Semiconductor ®FACT Quiet Series™FACT ®FAST ®FastvCore™FlashWriter ®*FPS™FRFET ®Global Power Resource SM Green FPS™Green FPS™e-Series™GTO™i-Lo ™IntelliMAX™ISOPLANAR™MegaBuck™MICROCOUPLER™MicroFET™MicroPak™MillerDrive™Motion-SPM™OPTOLOGIC ®OPTOPLANAR ®®PDP-SPM™Power220®POWEREDGE ®Power-SPM™PowerTrench ®Programmable Active Droop™QFET ®QS™QT Optoelectronics™Quiet Series™RapidConfigure™SMART START™SPM ®STEALTH™SuperFET™SuperSOT™-3SuperSOT™-6SuperSOT™-8SupreMOS™SyncFET™®The Power Franchise ®TinyBoost™TinyBuck™TinyLogic ®TINYOPTO™TinyPower™TinyPWM™TinyWire™µSerDes™UHC ®Ultra FRFET™UniFET™VCX™*EZSWITCH™and FlashWriter ®are trademarks of System General Corporation,used under license by Fairchild Semiconductor.DISCLAIMERFAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY,FUNCTION,OR DESIGN.FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS,NOR THE RIGHTS OF OTHERS.THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS,SPECIFICALLY THE WARRANTY THEREIN,WHICH COVERS THESE PRODUCTS.LIFE SUPPORT POLICYFAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.As used herein:1.Life support devices or systems are devices or systems which,(a)are intended for surgical implant into the body or (b)support or sustain life,and (c)whose failure to perform when properly used in accordance with instructions for use provided in the labeling,can be reasonably expected to result in a significant injury of the user.2.A critical component in any component of a life support,device,or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,or to affect its safety or effectiveness.PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status DefinitionAdvance InformationFormative or In DesignThis datasheet contains the design specifications for productdevelopment.Specifications may change in any manner without notice.Preliminary First ProductionThis datasheet contains preliminary data;supplementary data will be published at a later date.Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design.74LVT573, 74LVTH573 — Low Voltage Octal Transparent Latch with 3-STATE Outputs芯天下--/。