semiconductormanufacturingtechnology

Can do : oxidation, diffusion, deposition, anneals, and alloy
Pressure controller
Exhaust
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Figure 9.3
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by Michael Quirk and Julian Serda
Model of Typical Wafer Flow in a Sub-Micron CMOS IC Fab
Wafer Start Unpatterned
Wafer
Completed Wafer
Wafer Fabrication (front-end)
Thin Films
Polish
Diffusion
2. Give an overview of the six major process areas and the sort/test area in the wafer fab.
3. For each of the 14 CMOS manufacturing steps, describe its primary purpose.
p-well
1
p- Epitaxial layer
p+ Silicon substrate
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Photolithography Bay in a Sub-micron Wafer Fab
Yellow fluorescent: do not affect photoresist
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Photo 9.1
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by Michael Quirk and Julian Serda
Figure 9.6
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Thin Film Metallization Bay
Photo courtesy of Advanced Micro Devices
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
oxide
Ionized oxygen gas oxide
Oxide Etch
Photoresist Strip
oxygen gate oxide
Oxidation (Gate oxide)
Dopant gas Silane gas polysilicon
Ionized CCl4 gas oxide
Passivation layer ILD-6
14
Bonding pad metal
M-4 13
M-3
ILD-5 ILD-4
12
M-2
11
ILD-3 ILD-2
M-1 10
Via
9
ILD-1
8 LI metal
Poly gate 5 3
LI oxide
n+ 2
p+
4
Байду номын сангаасp+
STI
n+
n+
6
p+
7
n-well
Semiconductor Manufacturing Technology
Michael Quirk & Julian Serda © October 2001 by Prentice Hall
Chapter 9
IC Fabrication Process Overview
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1. Twin-well Implants 2. Shallow Trench Isolation 3. Gate Structure 4. Lightly Doped Drain Implants 5. Sidewall Spacer 6. Source/Drain Implants 7. Contact Formation 8. Local Interconnect 9. Interlayer Dielectric to Via-1 10. First Metal Layer 11. Second ILD to Via-2 12. Second Metal Layer to Via-3 13. Metal-3 to Pad Etch 14. Parametric Testing
Photo courtesy of Advanced Micro Devices
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Photo 9.3
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CMOS Manufacturing Steps
Etchant gas entering gas inlet
Electromagnetic field
Free electron
e-
e-
λ
Ion sheath
e-
+ Chamber wall
Positive ion
R
Radical chemical
Vacuum line
High-frequency energy
Simplified Schematic of a Photolithography Processing Module
Load Station
Vapor Prime
Resist Develop- Edge-Bead
Coat
Rinse Removal Transfer Station
Wafer Stepper (Alignment/Exposure System)
Metal contacts
dS rGaiDn
Metal Deposition and
Etch
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CMOS Process Flow
• Overview of Areas in a Wafer Fab
– Diffusion – Photolithography – Etch – Ion Implant – Thin Films – Polish
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Figure 9.4
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by Michael Quirk and Julian Serda
Simplified Schematic of Dry Plasma Etcher
Gas distribution baffle Anode electrode
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by Michael Quirk and Julian Serda
Objectives
After studying the material in this chapter, you will be able to:
1. Draw a diagram showing how a typical wafer flows in a sub-micron CMOS IC fab.
Temperature controller
Thermocouple measurements
Quartz tube
Gas flow controller
Process gas
Temperaturesetting voltages
Heater 1 Heater 2 Heater 3
Three-zone Heating Elements
Wafer Cassettes
Wafer Transfer System
Soft Bake
Cool Plate
Cool Plate
Hard Bake
Note: wafers flow from photolithography into only two other areas: etch and ion implant
Mask-Wafer
Exposed
Coating Alignment and Exposure Photoresist
oxide
Photoresist Develop
RRFFPPoowweerr
RF Power RF Power
resist poly gate
Ionized CF4 gas photoresist
Lighter ions
Mass resolving slit Acceleration column
Beamline tube
Process chamber
Heavy ions
Graphite
Scanning disk
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by Michael Quirk and Julian Serda
4. Discuss the key process and equipment used in each CMOS manufacturing step.
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Photo
Etch
Test/Sort
Implant
6 major production areas
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Figure 9.2
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by Michael Quirk and Julian Serda
Diffusion: Simplified Schematic of HighTemperature Furnace
Polysilicon Deposition
Polysilicon Mask and Etch
Scanning ion beam
silicon nitride
Contact holes
G
ox S
D
G SD
top nitride S GD
S GD
Ion Implantation
Active
Nitride
Major Fabrication Steps in MOS Process Flow
oxygen
Silicon dioxide
Silicon substrate
Oxidation (Field oxide)
photoresist
UV light
Mask
exposed photoresist
Photoresist
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Heat lamps
Figure 9.7
Wafer Susceptor
Exhaust
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Polish Bay in a Sub-micron Wafer Fab
Photo 9.2
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Simplified Schematics of CVD Processing System
Process chamber
Gas inlet
Capacitivecoupled RF input
Chemical vapor deposition
CVD cluster tool
Contact
Regions
Deposition
Etch
Used with permission from Advanced Micro Devices
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Figure 9.1
• CMOS Manufacturing Steps • Parametric Testing • 6~8 weeks involve 350-step
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Figure 9.5
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by Michael Quirk and Julian Serda
Simplified Schematic of Ion Implanter
Gas cabinet Ion source Filament Plasma
Extraction assembly Analyzing magnet Ion beam
RF coax cable Photon
Glow discharge (plasma) Vacuum gauge Wafer
Cathode electrode
Flow of byproducts and process gases
Exhaust to vacuum pump
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