时序电路的设计 计数器

using the ’163 as a modulo-11 counter (用4位二进制计数器74x163实现模11计数器)
—— m<2n
清零法
S0 S1 S2 S3 S4
计数到1010时， S15
S5
利用同步清零端
S14
S6
强制为0000。
电路?
S13
S7
S12 S11 S10 S9 S8
using the ’163 as a modulo-11 counter
清零法
—— m<2n 情况
计数到1010时， CLK
利用同步清零端
强制为0000。
Q0
Q1
思考：
Q2
如果是74x161
Q3
（异步清零）
可以这样连接吗？
—— 利用1011状态异步清零，会出现“毛刺”
Modulo-m counter
• This circuit uses a NAND gate to detect state 10 and force the next state to 0. Notice that only a 2-input gate is used to detect state 10 (binary 1010).
a free-running ’163 can be used as a divide-by-2, -4, -8, or -16 counter, by ignoring any unnecessary high-order output bits.
Other MSI counters
• 1bit BCD counter • 74x160 Synchronous clear 、 • 74x162 Asynchronous clear
8.4.3 MSI Counters and Applications
4位二进制计数器74x163
74x163的功能表
CLK CLR_L LD_L ENP ENT 工作状态
0 1 1 1 1
同步清零 0 同步置数 1 0 1 保持 1 0 保持,RCO=0 1 1 1 计数
74x161异步清零
called decade counters.
• the QD and QC outputs have one-tenth of the CLK frequency, they do not have a 50% duty cycle, and the QC output.
Other MSI counters
G2B Y2 Y3
SRC0 A
Y4 Y5
SRC1 B
Y6
SRC2 C
Y7
SDATA
如何控制地址端自动 P7 轮流选择输出Y0～Y7
—— application of the counter
Timing diagram for a modulo-8 binary counter and decoder,
general, to detect state N in a binary counter that counts from 0 to N, we need to AND only the state bits that are 1 in the binary encoding of N.
• 74x169---up/down counter
UP/DN = 1
counts up （升序）
UP/DN = 0
counts down（降序）
UP/DN
Enable inputs
ripple carry out
Active-low
74x138
P0
EN1 G1 Y0
EN2_L G2A Y1
P1
EN3_L
8- bit register
CLK
More better way 。。。 Ring counter
Modulo-m counter
• Use SSI device
—— Clocked Synchronous State-Machine Design
• Use MSI counter
—— using n bit binary counter as a modulo-m counter
• Although a 4-input gate would normally be used to detect the condition CNT10 = Q3 × Q2’ × Q1 × Q0’, the 2-input gate takes advantage of the fact that no other state in the normal counting sequence of 0–10 has Q3 = 1 and Q1 = 1. In
showing decoding glitches.
0 1 2 3 4 5 6 7 0 12
若在一次状态转移中有2位或多位计数位同时变化， 译码器输出端可能会产生“尖峰脉冲” —— 功能性冒险
A modulo-8 binary counter and decoder with glitch-free (无尖峰)outputs.
in two cases：
Although mth<e2n’163 is a modulo-16 counter, it
can 16
be by
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count in a CLR_L or
modulus less than LD_L input to
shorten the normal counting sequence.
QA QB QC QD
0 1 2 3 4 5 6 7 8 90
74x160、74x162
• the counting sequence is modified to go to state 0 after state 9. In other words, these are modulo-10 counters, sometimes
Connections for the 74X163 to operate in a free-running mode(P715) 74x163工作于自由运行模式时的接线方法
A free running divide-by-16 counter
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0