先进芯片封装知识介绍

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WLCSP
• Why WLCSP?
– Smallest package size: WLCSP have the smallest package size against die size. So it has widely use in mobile devices.
– High electrical performance: because of the short and thick trace routing in RDL, it gives high SI and reduced IR drop.
▼ SO Family
▼ QFP Family
▼ BGA Family
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Package Development Trend
▼ CSP Family
▼ Memory Card
▼ SiP Module
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3D Package
3D Package
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DDDD2234 DDDD3242
PoP QFN
Functional Integration
Multi Chip Stack
2 Chip Stack Flip Chip & Wirebond
3 S-CSP
3S-PBGA Stacked-SiP
4SS-SCSP
5SCSP
Ultra thin Stack
Top epoxy Under-fill
Wafer Thinning
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Fine Process Control
• Top Package Attach • Die Attach • etc
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▼ PiP – W/B PiP and FC PiP
Memory PKG
Digital
Spacer Analog
PiP
Analog Memory PKG
Flip chip
Substrate
Inner PKG
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WB PIP
FIlnipnecr hPKipG
FC PIP
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WLCSP & Flip Chip Package
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WLCSP
• What is WLCSP?
WLCSP(Wafer Level Chip Scale Packaging), is not same as traditional packaging method (dicing packaging testing, package size is at least 20% increased compared to die size). WLCSP is packaging and testing on wafer base, and dicing later. So the package size is exactly same as bare die size. WLCSP can make ultra small package size, and high electrical performance because of the short interconnection.
– High thermal performance: since there is no plastic or ceramic molding cap, heat from die can easily spread out.
– Low cost: no need substrate, only one time testing.
A 3D package (System in Package, Chip Stack MCM, etc.) contains two or more chips (integrated circuits) stacked vertically so that they occupy less space. In most 3D packages, the stacked chips are wired together along their edges. This edge wiring slightly increases the length and width of the package and usually requires an extra “interposer” layer between the chips. In some new 3D packages, through-silicon via replace edge wiring by creating vertical connections through the body of the chips. The resulting package has no added length or thickness.
• Potable Digital Gadget
– Cellular Phone, Digital Still Camera, Potable Game Unit
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▼ Why PiP?
PiP
✓Easy system integration ✓Flexible memory configuration ✓100% memory KGD ✓Thinner package than POP ✓High IO interconnection than POP ✓Small footprint in CSP format
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WLCSP
• Process Flow of WLCSP
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▼ Process Flow of WLCSP
WLCSP
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Flip Chip Package
(PI)-EHS2-FCBGA
(Passive Integrated Exposed 2 pieces of Heat Sink Flip Chip BGA)
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▼ PiP Core Technology
Optimized Package Design
M I
S B
L3 L2 D2 BL2
L1 BL1 D1
UF
PiP
Material for High Reliability Based on Low Warpage
ISM Flip Chip
Through Mold Via
Top view
Bottom view
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▼ Process Flow of TMV PoP
Ball Placement on top surface Die Bond
Mold (Under Full optional)
PoP
Laser drilling
Stacked Die
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FOW materil
Wire Top die
Bottom die 8
TSV
▼ TSV (Through Silicon Via)
A through-silicon via (TSV) is a vertical electrical connection (via) passing completely through a silicon wafer or die. TSV technology is important in creating 3D packages and 3D integrated circuits.
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▼ PoP Core Technology
Low Loop Wire
PoP
Pin Gate Mold
Wafer Thinning
PS-vfBGA PS-etCSP
Package Stacking
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PoP
▼ Amkor’s TMV™ PoP
▼ Allows for warpage reduction by utilizing fully-molded structure ▲ More compatible with substrate thickness reduction
▼ Provides fine pitch top package interface with thru mold via ▼ Improved board level reliability ▼ Larger die size / package size ratio ▼ Compatible with flip chip, wire bond, or stacked die configurations ▼ Cost effective compared to alternative next generation solutions
Ball Placement on bottom
Singulation Final Visual Inspection
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Base M’tl
Thermal effect
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PiP
Epoxy
spacer
Memory die Analog die Digital die
• Digital(Btm die) + Analog(Middle die) + Memory(Top pkg)
FS-CSP1
FS-CSP2
FS-BGA
2 Chip Stack Wirebond