CPU实验报告

C23,C12,C0 00001001
12
memory←MBR, CAR←CAR+1
C11,C0 00000801
13
MAR←PC，CAR←0
C10,C2 00000404
20 (LOAD)
MAR←MBR7-0,PC←PC+1,
CAR←CAR+1
C5,C6,C0 00000061
21
MBR←memory , CAR←CAR+1
DIV
C19
Shift ACC to left
SHIFTL
C20
ACC←NOTBR
NOT
C21
ACC←ACC or BR
OR
C22
ACC←ACC and BR
AND
C23
WE=1
Memory write
Address(Hex)
Micro-instructions
Control Signals
0 (FETCH)
93
ACC←ACC and BR, CAR←CAR+1
C22,C0
94
MAR←PC，CAR←0
C10,C2 00000404
A0(OR)
MAR←MBR7-0 ,PC←PC+1,
CAR←CAR+1
C5,C6,C0 00000061
A1
MBR←memory, CAR←CAR+1
C3,C0 00000009
84
MAR←PC , CAR←0
C10,C2 00000404
90(AND)
MAR←MBR7-0, PC←PC+1,
CAR←CAR+1
C5,C6,C0 00000061
91
MBR←memory, CAR←CAR+1
C3,C0 00000009
92
BR←MBR, CAR←CAR+1
C7,C0 00000081
CAR←CAR+1
C16,C6,C0 00020041
C1
MAR←PC, CAR←0
C10,C2 00000404
D0(SHIFTL)
ACC←ACC<<1, PC←PC+1,
CAR←CAR+1
C19,C6,C0 02000041
D1
MAR←PC, CAR←0
C10,C2 00000404
E0 (DIV)
Read RAM
C4
IR←MBR(15..8)
MBR into IR
C5
MAR←MBR[7..0]
MBR into MAR
C6
PC←PC+1
Increase PC
C7
BR←MBR
MBR into BR
C8
ACC←0
reset_ACC
C9
ACC←ACC+BR
ADD
C10
MAR←PC
PC into MAR
44
MAR←PC, CAR←0
C10,C2 00000404
50(JUMPEZ)
(IF flag=1) PC←PC+1, CAR←CAR+1
C6,C0 00000041
51
CAR←0 ,MAR←PC
C10,C2 00000404
52
(IF flag =0) PC←MBR7-0, CAR←CAR+1
C13,C0 00004001
A2
BR←MBR, CAR←CAR+1
C7,C0 00000081
A3
ACC←ACC or BR, CAR←CAR+1
C21,C0 08000001
A4
MAR←PC, CAR←0
C10,C2 00000404
B0(NOT)
MAR←MBR7-0 ,PC←PC+1,
CAR←CAR+1
C5,C6,C0 00000061
C11
memory←MBR
RAM _write
C12
MBR←ACC
ACC into MBR
C13
PC←MBR
MBR into PC
C14
PC←0
Reset_PC
C15
ACC←ACC-BR
SUB
C16
Shift ACC to right
SHIFTR
C17
MRACC←ACC*BR
MPY
C18
DRACC←ACC/BR
MAR←MBR7-0 ,PC←PC+1,
CAR←CAR+1
C5,C6,C0 00000061
E1
MBR←memory, CAR←CAR+1
C3,C0 00000009
E2
BR←MBR , CAR←CAR+1
C7,C0 00000081
E3
ACC←ACC/BR
C18,C0 00040001
E4
MAR←PC , CAR←0
MAR←MBR7-0 ,PC←PC+1,
CAR←CAR+1
C5,C6,C0 00000061
81
MBR←memory, CAR←CAR+1
C3,C0 00000009
82
BR←MBR , CAR←CAR+1
C7,C0 00000081
83
MR←ACC*BR(H), CAR←CAR+1
C17,C0 00040001
53
CAR←0 ,MAR←PC
C10,C2 00000404
60(JMP)
PC←MBR7-0, CAR←CAR+1
C13,C0 00004001
61
CAR←0 ,MAR←PC
C10,C2 00000404
70(HALT)
ACC←0, CAR←0 ,PC←0
C8,C14,C2 00008104
80 (MPY)
B1
MBR←memory, CAR←CAR+1
C3,C0 00000009
B2
BR←MBR, CAR←CAR+1
C7,C0 00000081
B3
ACC←notBR, CAR←CAR+1
C20,C0 04000001
B4
MAR←PC, CAR←0
C10,C2 00000404
C0(SHIFTR)
ACC←ACC>>1, PC←PC+1,
MBR←memory，CAR←CAR+1
C3,C0 00000009
1
IR←MBR15-8，CAR←CAR+1
C4,C0 00000011
2
CAR←**
C1 00000002
10(STORE)
MAR←MBR7-0,PC←PC+1,
CAR←CAR+1
C5,C6,C0 00000061
11
MBR←ACC, CAR←CAR+1,WE=1
40 (SUB)
MAR←MBR7-0, PC←PC+1,
CAwk.baidu.com←CAR+1
C5,C6,C0 00000061
41
MBR←memory, CAR←CAR+1
C3,C0 00000009
42
BR←MBR, CAR←CAR+1
C7,C0 00000081
43
ACC←ACC-BR, CAR←CAR+1
C15,C0 00010001
CAR←CAR+1
C5,C6,C0 00000061
31
MBR←memory, CAR←CAR+1
C3,C0 00000009
32
BR←MBR, CAR←CAR+1
C7,C0 00000081
33
ACC←ACC+BR, CAR←CAR+1
C9,C0 00000201
34
MAR←PC, CAR←0
C10,C2 00000404
C10,C2 00000404
C3,C0 00000009
22
ACC←0, BR←MBR, CAR←CAR+1
C8,C7,C0 00000181
23
ACC←ACC+BR, CAR←CAR+1
C9,C0 00000201
24
MAR←PC, CAR←0
C10,C2 00000404
30(ADD)
MAR←MBR7-0, PC←PC+1,
Bit in read-only control memory
(Bit of ROM)
Micro-operation
Control signal name
C0
CAR←CAR+1
Increase CAR
C1
CAR←**
Control addressing
C2
CAR←0
Reset CAR
C3
MBR←memory