4点流水线结构的FFT
相关主题
- 1、下载文档前请自行甄别文档内容的完整性，平台不提供额外的编辑、内容补充、找答案等附加服务。
- 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
- 3、如文档侵犯您的权益，请联系客服反馈,我们会尽快为您处理(人工客服工作时间：9:00-18:30)。
-1-
E__MONEY_FFT_fБайду номын сангаасt4
2012年10月28日星期日 22:32
else next_state_fft4<=IDLE; end ST1: begin wfta4out_valid_temp<=0; x0<=wfta4in_data;//输入第1个x(0) if(wfta4in_valid==1) next_state_fft4<=ST2; else next_state_fft4<=ST1; end ST2: begin wfta4out_valid_temp<=0; x1<=wfta4in_data;//输入第1个x(1) if(wfta4in_valid==1) next_state_fft4<=ST3; else next_state_fft4<=ST2; end ST3: begin wfta4out_valid_temp<=0; x2<=wfta4in_data;//输入第1个x(2) a1<={x0[15:8]+x2[15:8],x0[7:0]+x2[7:0]}; a2<={x0[15:8]-x2[15:8],x0[7:0]-x2[7:0]}; if(wfta4in_valid==1) next_state_fft4<=ST4; else next_state_fft4<=ST3; end ST4: begin wfta4out_valid_temp<=0; x3<=wfta4in_data;//输入第1个x(3) a3<={x1[15:8]+x3[15:8],x1[7:0]+x3[7:0]}; a4<={x1[15:8]-x3[15:8],x1[7:0]-x3[7:0]}; if(wfta4in_valid==1) next_state_fft4<=ST5; else next_state_fft4<=ST4; end ST5: begin x0<=wfta4in_data;//输入第2个x(0) wfta4out_valid_temp<=1; wfta4out_data_temp<={a1[15:8]+a3[15:8],a1[7:0]+a3[7:0]};//输出X(0)=c1 c3<={a1[15:8]-a3[15:8],a1[7:0]-a3[7:0]}; if(wfta4in_valid==1) next_state_fft4<=ST6; else next_state_fft4<=ST5; end ST6:
E__MONEY_FFT_fft4
2012年10月28日星期日 22:32
module fft4( input clk_fft4, input reset, input wfta4in_valid, input [15:0]wfta4in_data, output wfta4out_valid, output [15:0]wfta4out_data ); reg reg reg reg reg [15:0]x0,x1,x2,x3; [15:0]c3,c4; [15:0]a1,a2,a3,a4; [15:0]wfta4out_data_temp; wfta4out_valid_temp;
-3-
//状态标记 reg [8:0]state_fft4; reg [8:0]next_state_fft4; localparam IDLE=9'b000000001; localparam ST1=9'b000000010; localparam ST2=9'b000000100; localparam ST3=9'b000001000; localparam ST4=9'b000010000; localparam ST5=9'b000100000; localparam ST6=9'b001000000; localparam ST7=9'b010000000; localparam ST8=9'b100000000; /*reg [3:0]state_fft4; reg [3:0]next_state_fft4; localparam IDLE=3'd0; localparam ST1=4'd1; localparam ST2=4'd2; localparam ST3=4'd3; localparam ST4=4'd4; localparam ST5=4'd5; localparam ST6=4'd6; localparam ST7=4'd7; localparam ST8=4'd8; */ //次态计算 always @(posedge clk_fft4,posedge reset) if(reset==1) state_fft4<=IDLE; else state_fft4<=next_state_fft4; //状态机控制逻辑 always @(*) case(state_fft4) IDLE: begin wfta4out_valid_temp<=0; if(wfta4in_valid==1) next_state_fft4<=ST1;
-2-
E__MONEY_FFT_fft4
2012年10月28日星期日 22:32
begin x1<=wfta4in_data;//输入第2个x(1) wfta4out_data_temp<={a2[15:8]+a4[15:8],a2[7:0]+a4[7:0]};//输出X(1) c4<={a2[15:8]-a4[15:8],a2[7:0]-a4[7:0]}; wfta4out_valid_temp<=1; if(wfta4in_valid==1) next_state_fft4<=ST7; else next_state_fft4<=ST6; end ST7: begin x2<=wfta4in_data;//输入第2个x(2) a1<={x0[15:8]+x2[15:8],x0[7:0]+x2[7:0]}; a2<={x0[15:8]-x2[15:8],x0[7:0]-x2[7:0]}; wfta4out_valid_temp<=1; wfta4out_data_temp<=c3;//输出X(2) if(wfta4in_valid==1) next_state_fft4<=ST8; else next_state_fft4<=ST7; end ST8: begin x3<=wfta4in_data;//输入第2个x(3) a3<={x1[15:8]+x3[15:8],x1[7:0]+x3[7:0]}; a2<={x1[15:8]-x3[15:8],x1[7:0]-x3[7:0]}; wfta4out_valid_temp<=1; wfta4out_data_temp<=c4;//输出X(3) if(wfta4in_valid==1) next_state_fft4<=ST5; else next_state_fft4<=ST8; end default next_state_fft4<=IDLE; endcase assign wfta4out_valid=wfta4out_valid_temp; assign wfta4out_data=wfta4out_data_temp; endmodule
E__MONEY_FFT_fБайду номын сангаасt4
2012年10月28日星期日 22:32
else next_state_fft4<=IDLE; end ST1: begin wfta4out_valid_temp<=0; x0<=wfta4in_data;//输入第1个x(0) if(wfta4in_valid==1) next_state_fft4<=ST2; else next_state_fft4<=ST1; end ST2: begin wfta4out_valid_temp<=0; x1<=wfta4in_data;//输入第1个x(1) if(wfta4in_valid==1) next_state_fft4<=ST3; else next_state_fft4<=ST2; end ST3: begin wfta4out_valid_temp<=0; x2<=wfta4in_data;//输入第1个x(2) a1<={x0[15:8]+x2[15:8],x0[7:0]+x2[7:0]}; a2<={x0[15:8]-x2[15:8],x0[7:0]-x2[7:0]}; if(wfta4in_valid==1) next_state_fft4<=ST4; else next_state_fft4<=ST3; end ST4: begin wfta4out_valid_temp<=0; x3<=wfta4in_data;//输入第1个x(3) a3<={x1[15:8]+x3[15:8],x1[7:0]+x3[7:0]}; a4<={x1[15:8]-x3[15:8],x1[7:0]-x3[7:0]}; if(wfta4in_valid==1) next_state_fft4<=ST5; else next_state_fft4<=ST4; end ST5: begin x0<=wfta4in_data;//输入第2个x(0) wfta4out_valid_temp<=1; wfta4out_data_temp<={a1[15:8]+a3[15:8],a1[7:0]+a3[7:0]};//输出X(0)=c1 c3<={a1[15:8]-a3[15:8],a1[7:0]-a3[7:0]}; if(wfta4in_valid==1) next_state_fft4<=ST6; else next_state_fft4<=ST5; end ST6:
E__MONEY_FFT_fft4
2012年10月28日星期日 22:32
module fft4( input clk_fft4, input reset, input wfta4in_valid, input [15:0]wfta4in_data, output wfta4out_valid, output [15:0]wfta4out_data ); reg reg reg reg reg [15:0]x0,x1,x2,x3; [15:0]c3,c4; [15:0]a1,a2,a3,a4; [15:0]wfta4out_data_temp; wfta4out_valid_temp;
-3-
//状态标记 reg [8:0]state_fft4; reg [8:0]next_state_fft4; localparam IDLE=9'b000000001; localparam ST1=9'b000000010; localparam ST2=9'b000000100; localparam ST3=9'b000001000; localparam ST4=9'b000010000; localparam ST5=9'b000100000; localparam ST6=9'b001000000; localparam ST7=9'b010000000; localparam ST8=9'b100000000; /*reg [3:0]state_fft4; reg [3:0]next_state_fft4; localparam IDLE=3'd0; localparam ST1=4'd1; localparam ST2=4'd2; localparam ST3=4'd3; localparam ST4=4'd4; localparam ST5=4'd5; localparam ST6=4'd6; localparam ST7=4'd7; localparam ST8=4'd8; */ //次态计算 always @(posedge clk_fft4,posedge reset) if(reset==1) state_fft4<=IDLE; else state_fft4<=next_state_fft4; //状态机控制逻辑 always @(*) case(state_fft4) IDLE: begin wfta4out_valid_temp<=0; if(wfta4in_valid==1) next_state_fft4<=ST1;
-2-
E__MONEY_FFT_fft4
2012年10月28日星期日 22:32
begin x1<=wfta4in_data;//输入第2个x(1) wfta4out_data_temp<={a2[15:8]+a4[15:8],a2[7:0]+a4[7:0]};//输出X(1) c4<={a2[15:8]-a4[15:8],a2[7:0]-a4[7:0]}; wfta4out_valid_temp<=1; if(wfta4in_valid==1) next_state_fft4<=ST7; else next_state_fft4<=ST6; end ST7: begin x2<=wfta4in_data;//输入第2个x(2) a1<={x0[15:8]+x2[15:8],x0[7:0]+x2[7:0]}; a2<={x0[15:8]-x2[15:8],x0[7:0]-x2[7:0]}; wfta4out_valid_temp<=1; wfta4out_data_temp<=c3;//输出X(2) if(wfta4in_valid==1) next_state_fft4<=ST8; else next_state_fft4<=ST7; end ST8: begin x3<=wfta4in_data;//输入第2个x(3) a3<={x1[15:8]+x3[15:8],x1[7:0]+x3[7:0]}; a2<={x1[15:8]-x3[15:8],x1[7:0]-x3[7:0]}; wfta4out_valid_temp<=1; wfta4out_data_temp<=c4;//输出X(3) if(wfta4in_valid==1) next_state_fft4<=ST5; else next_state_fft4<=ST8; end default next_state_fft4<=IDLE; endcase assign wfta4out_valid=wfta4out_valid_temp; assign wfta4out_data=wfta4out_data_temp; endmodule