如何读懂时序图

/itangcle
CPE/EE 421
Microcomputers
WEEK #10
Interpreting the Timing Diagram
如何读懂时序图
The 68000 Read Cycle
2 Alan Clements
3 Actual behavior of a D flip - f lop
Timing Diagram of a Simple Flip - F lop
Idealized form of the timing diagram
Data hold time
Data setup time Max time for output to become valid after clock
4 An alternative form of the timing diagram
General form of the timing diagram
A memory access begins in clock
state S0 and ends in state S7
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The most important parameter
of the clock is the duration of a cycle, t C YC.
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Address Timing
地址时序
•We are interested in when the 68000 generates a new address for use in the current memory access
我们感兴趣的是当6800芯片能够生成一个新的地址供当前的内存访问
•The next slide shows the relationship between the new address and the state of the 68000 ’s clock
下面展示的是新的地址跟6800芯片时钟的
关系
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1: S0在没有初始化的时候，地址总线总是包涵新的地址。

2： S1这个状态说明一个新的地址可以供内存访问
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Address Timing
地址时序
• Let’s look at the sequence of events that govern the timing of the address bus 让我们看看事件发生的顺序,管理时间的地址总线 • The “old” address is removed in state S0 旧的地址已经从S0中移除
• The address bus is floated for a short time, and the CPU puts out a new address in state S1
地址要先存在一小段时间后，CPU 才能把心的地址状态写入S1中12
The old address is removed in clock state S0 and the address bus floated
t C LA V
The designer is interested in the point at which the address first becomes valid. This point is t C LA V seconds after the falling edge of S0.
Address and Address Strobe
地址跟地址选通
•We are interested in the relationship between the time at which the address is valid and the time at which the address strobe, AS*, is asserted
我们感兴趣的事在地址总线能够访问时，地址选通是否有效。

•When AS* is active-low it indicates that the
上图说明：1：当地址有效的时候把AS 低电平信号.
当地址要改变前，要把AS变成高电We now look at the timing of the clock, the address, and the address strobe
从上面的时序图可以看出到，时钟脉冲，地址信号，片选脉冲；3者的关系。

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AS* goes low in clock state S2
The Data Strobes 数据选通•The 68000 has two data strobes LDS* and UDS*. These select the lower byte or the upper byte of a word during a memory access
6800芯片有两个数据选通信号LDS（低）和UDS（高）.内存通过选择LDS和UDS来访问数据。

•To keep things simple, we will use a single data strobe, DS* 为了让事情看起来简单，我们只要选通DS就可以了。

（DS的高8位是UDS低8位是LDS）
•The timing of DS* in a read cycle is the same as the address strobe, AS*
DS的读数据跟AS读地址的时序是一样的。

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The data strobe, is asserted
at the same time as AS*
in a read cycle
During a read cycle the memory provides 20
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Analyzing the Timing Diagram
分析时序图
• We are going to redraw the timing diagram to remove clutter
让我们从头到脚分析这个时序图让头脑不那么乱
• We aren’t interested in the signal paths
themselves, only in the relationship between the signals 我们不能单单从一条信号线来分析了，我们得从整体上来分析。

据选通)和数据在读周期
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在地址开始有效的时候，内存就可以访问数据了。

在地址可访问，内存可以接收数据的时间是t acc 秒。

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Calculating the Access Time
计算访问时间
• We need to calculate the memory’s access time 我们必须计算内存的访问时间
• By knowing the access time, we can use the appropriate memory component 通过了解访问时间，我们可以适当使用内存
• Equally, if we select a given memory component, we can calculate whether its access time is adequate for a particular system 同样,如果我们选择一个特定内存组件,我们可以计算出它的访问时间是否足够用来在一个特定的系统
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在t DICL 后，数据必须有效。

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我们知道在地址和数据可以访问的时候之间的时间是t acc 秒
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地址数据在t CLA V 后能被访问
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在地址有效，从S0到S6结束，数据就别俘获了。

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Timing Example
•68000 clock 8 MHz t CYC = 125 ns •68000 CPU t CLA V = 70 ns
•68000 CPU t DICL = 15 ns
•What is the minimum t acc?
•3 t CYC = t CLA V + t acc + t DICL
•375 = 70 + t acc + 15
•t acc = 290 ns
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