字符叠加芯片MB90092手册中文版

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欧姆网9102B Handheld Spectrum Analyzer商品说明书

9102 Handheld Spectrum Analyzer SpecificationsSpecifications apply for 9102B series devices with serial number 0604001 and higher without the 9151 Frequency Extension 7.5 GHz.General dataDisplay (TFT)Size 6.5''Brightness 300 cdResolution 640 x 480, 256 coloursMeasurement result points 2 x 501Power supplyDC voltage, external 11 to 15 V / max. 28 WChangeable Internal battery Li-Ion2.0 h min.Operating time, battery fully charged, fullbrightness, TG onMemoryType Flash DiskCapacity (set-ups and traces) 257Dimensions (W x H x D)355 x 190 x 91 [mm]WeightWith battery and Tracking Generator 3.2 kg (7 lbs)Power supply only 0.32 kg (0.7 lbs)Environmental conditions (unless otherwise specified)MIL-PRF28800F class 2Operating temperature 0 to +45 °CRel. humidity (non-condensing) 80%Storage temperature -10 to + 50 °CConnectorsRF in Connector type N (female), impedance 50 ohmSerial interface For software updates and remote controlSpeed 57.6 kbit/sLAN (TCP/IP) For software updates and remote controlSpeed 10 Mbit/sStandard deliveries9102 Handheld Spectrum Analyzer incl. power supply (90 to 240 V/50 to 60 Hz), crossover Ethernet communication cable, 9100 Data Exchange Software (1 license, user's guide on CD) and getting started manualFrequencyFrequency rangeMeasurement range 100 kHz to 4 GHzResolution 1 kHzSweep timeSpan > 10 kHz 1 ms to 250 sSpan = 0 Hz 1 ms to 250 sResolution bandwidth (RBW)RBW (-3 dB) range 100 Hz to 1 MHz (RBW selection manual or automatic) Video bandwidth (VBW)VBW range (-3 dB) 10 Hz to 1 MHz (VBW selection manual or automatic)SSB noise< -80 dBc/Hz (f = 2 GHz, Δf = 100 kHz, RBW = 10 kHz, VBW = 1 kHz)AmplitudeMeasurement rangeAveraged noise floor to 20 dBmDisplay unitsdBm, dBµV, dBmV, dBV, dBDisplayed average noise level (DANL) (RBW = 100 Hz, attenuation = 0 dB)10 to 1000 MHz < -127 dBm,typ.-130 dBm 1000 to 4000 MHz < -130 dBm,typ.-135 dBm Input attenuationSetting range 0(10) to 50 dB Attenuation steps 10 dB Dynamic rangeRange > 70 dB Max. measurable input level (attenuation = 40 dB) 20 dBm Min. measurable input level -130 dBm Level accuracy10 to 3600 MHz ±1 dBRF input match (1 to 4000 MHz, input attenuation = 10 dB)VSWR < 1.6, typ. < 1.5 Return loss < -12 dB Spurious responseImage rejection (f = 1 GHz) > 80 dBLO breakthrough (attenuation = 10 dB) < -77 dBm Spurious level (attenuation = 0 dB) < -90 dBm Intermodulation-free range> 63 dB (input level -30 dBm, f1 = 990 MHz, f2 = 992 MHz)FunctionsDetector & sweepDetector types pos./neg. peak, pos. peak, neg. peak, sampleSweep processing actual, average, max. hold, min. holdTraceMax. displayed traces 2Trace points 2 x 501(Two independent traces are available, min. hold, max.hold at the same time)Trace functions A+B ? A, A-B ? A,trace offset, copy a>b, copy b>aMarkerMax. markers 6Delta markers 5Marker functions max. peak, next peakTransfer functions M ? centre frequency, M ? ref. level, M ? f stepLimit checkLimit functions upper, lower, upper and lowerPower measurementMeasurement functions Channel Power, ACPR, OBWDefault systems GSM, WCDMA, DECT, WLANDemodulationAM/FM on marker/permanent/on multi marker9102 Handheld Spectrum Analyzer with 9151 Frequency Extension 7.5 GHz SpecificationsFrequency rangeMeasurement range 100 kHz to 7.5 GHzSSB noise< –80 dBc/Hz (f = 5.7 GHz, ?f = 100 kHz, RBW = 10 kHz, VBW = 1 kHz)Displayed average noise level (DANL) (RBW = 100 Hz, attenuation = 0 dB)10 MHz to 4 GHz < –119 dBm, typ. –121 dBm 4 GHz to 7 GHz < –120 dBm, typ. –123 dBm 7 to 7.5 GHz < –113 dBmDynamic rangeRange (5.000 GHz / 5.001 GHz) > 70 dBMax. measurable input level20 dBm(attenuation = 40 dB)Min. measurable input level (<4 GHz) –119 dBmMin. measurable input level (4 GHz to 7 GHz) –120 dBmMin. measurable input level (7 GHz to 7.5 GHz)–112dBm(attenuation = 0 dB)RF input match (input attenuation = 10 dB)VSWR (100 MHz to 4 GHz) < 1.6VSWR (4 GHz to 6 GHz) < 2.0 VSWR (6 GHz to 7.5 GHz) < 2.3 Return loss (100 MHz to 4 GHz) < –15 dB Return loss (4 GHz to 6 GHz) < –9 dB Return loss (6 GHz to 7.5 GHz) < –7 dB Spurious responseImage rejection (f = 6.7 GHz) ) > 60 dB Spurious level (100 kHz to 4 GHz) < –90 dBm< –83 dBm Spurious level (4 GHz to 7.5 GHz)(attenuation = 0 dB)< –57 dBm LO leakage (7.7 GHz)(attenuation = 10 dB)。

基于MB90092的视频字符叠加器的设计

２２ＭＢ０９叠加电路．９０２
Ｓ — 主输控｛全Ｃ横人制＿．ＬＸ抽ｒ＿型鱼
一
视信频号
输＾同步信号
ＣＬ８一
— — —
＿＿Ｊ
］
』
．
输入
Ｍ９０２Ｂ０９有两种同步方式：当外部有视频信号输入时，它采用提取的外部同步信号，工作在外部同步模式；当外部没有视频信号输入时，此时也相应的没有同步信号可以提取，９０２内部可通过Ｅ与ＸＭＢ０９ＸＳＳ之间所接的晶体（此处接入１．３Ｍ晶体，频信号为ＰＬ制）７７４视Ａ自行产生同步信号，直接输出只含叠加字符的视频信号，在监视器上显示不同背景颜色、不同字符颜色的视频信号，此为内同步模式。ＭＢ０９与ＡＲ９０２Ｍ只有３条通信线：Ｉ串行数据输入）ＣＫ（ＳＮ（，Ｌ串行Ｓ时钟）ｓ片选信号），（ｃ。２３制单元及字库电路＿控本设计中控制单元除了要对Ｍ９０２Ｂ０９进行控制外，还需要提供更新字库的功能。由于字库容量比较大，而普通单片机的寻址空间不够，无法完成整个字库的烧写，能满足要求，不因此这里采用一块ＡＭ微Ｒ
引言
、
随着视频监控系统应用的普及，安全防护的要求也在不断提高，单纯的视频画面监控已经不能满足现代监控的需要。现在很多用户要求监视的画面中能带有与之相关的各种信息，比如监控的地点、时间、监控的状态信息及一些实时更新的数据等。本文设计了一种能在视频画面中任意位置叠加任意字符和图形的视频字符叠加系统。它可以方便的接收外部数据并把相关的信息叠加到视频画面中，监视信息和画面一目了然，能应用在对监控性能要求较高的场合，比如储物仓库、超市、银行和高速公路收费站等。１系统设计．１１．原理及设计思路为了向视频信号中叠加所需字符信息，先要处理的就是视频信首号和叠加字符的同步问题，也就是保证经视频信号提取电路分离出的行与场信号对于所需叠加的字符信号的同步，然后再使这两种不同的信号叠加起来后在同一幅画面中显示出来。传统的方法是通过自己用分立器件搭建各部分核心电路，此种方法实现起来比较复杂而且系统的整体性能会因为引人了过多的分立元件而降低。还有一种方法是使用专用的集成芯片来实现，优点是实现电路简单，其使用的元器件少，系统稳定性强，本系统采用后者实现。１９０２要功能特点．ＭＢ０９主２ＭＢ０９是日本富士公司推出的一款ＯＤ专用集成芯片，用该９０２Ｓ使芯片可以向视频画面中叠加各种文字及图像信息。该芯片叠加目标信息时需使用外部字库芯片，因此其相应的提供有外挂字库的接口，它能支持多达１Ｍｂｔ的外部存储空间的访问，６ｉｓ用户可以自己向字库芯片中烧入自己所需叠加的任意点阵字符或图像等。ＭＢ０９９０２内部结构模块如图１所示。

基于MB90092的字符叠加系统设计

保障视频信号的清晰输出。图１所示是该视频叠
加系统的硬件结构框图。阻输ｆ步号颁同信分离
ｌ
这种方案的优点是元件数量少。电路简单容易实
现。系统稳定性好。
Ｉ — Ｌｌ１ｌＩＭｇ８
ＥＨＹ０７ＸＳＮＤ０】Ａ［８［１
统的通用性和实用性，本文选择ＭＢｏ９来实现９０２
间、日期、提示语或图形标志等。为此，本文给
出了一般的低成本、高可靠视频叠加系统的设计方案
字符叠加系统。
２硬件设计
１视频叠加系统原理
２１总体结构．ＯＳＯ — ｃｅｎＤｓｌｙＤｆｎＳｒｅ — ｉａ）是视频叠加的英ｐ
维普资讯
第９卷
期２７第９０年月ｏ９
婚墓缔痢
Ｖ１Ｎ．ｏｏ．９９
Ｓｐ０７ｅ．２０
基于ＭＢ０９的字符叠加系统设计９０２
王天玉
（同济大学中德学院，上海
摘
２０９）００２
要：介绍了基于专用视频叠加芯片ＭＢ０９实现字符叠加的系统结构及外围电路实现原９０２
— ＶＩＮ
Ｄ０】［７
Ａ［１】０８字库芯片Ｗ２ＣＯＯ９４
ＣＥ
视频叠加芯片
毋９０２０９
Ｐ１１ＣＳ
通过比较两种方案的优劣。本设计采用第二种方案来实现视频叠加。而第二种方案在芯片选型上又有两种不同的芯片可供选择。一种是芯片

ANALOG DEVICES AD9520-0 中文数据手册

12路LVPECL/24路CMOS输出时钟发生器，集成2.8 GHz VCO AD9520-0
特性低相位噪声锁相环(PLL) 片内VCO调谐范围：2.53 GHz至2.95 GHz 支持最高2.4 GHz的外部3.3 V/5 V VCO/VCXO 1路差分或2路单端参考输入支持最高250 MHz的CMOS、LVDS或LVPECL参考参考输入接受16.67 MHz至33.3 MHz晶振可选参考时钟倍频器参考监控功能自动和手动参考切换/保持模式，支持可选的恢复式/非恢复式切换参考间无毛刺切换从保持模式自动恢复可选数字或模拟锁定检测可选零延迟工作 12路1.6 GHz LVPECL输出分为4组每组3路输出，具有一个带相位延迟的1至32分频器加性输出抖动低至225 fs rms 分组输出的通道间偏斜：<16 ps 可以将每路LVPECL输出配置为2路CMOS输出(fOUT ≤ 250 MHz) 上电时所有输出自动同步可以根据需要手动同步多路输出 SPI和I²C兼容型串行控制端口 64引脚LFCSP封装非易失性EEPROM存储配置设置
DIV/Φ
DIV/Φ
DIV/Φ
图1
AD9520串行接口支持SPI和I2C®端口。封装内EEPROM可以通过串行接口进行编程，存储用于上电和芯片复位的用户定义寄存器设置。 AD9520具有12路LVPECL输出，分为四组。任何一路1.6 GHz LVPECL输出都可以重新配置为两路250 MHz CMOS输出。每组输出具有一个分频器，其分频比(从1至32)和相位(粗调延迟)均可以设置。 AD9520提供64引脚LFCSP封装，可以采用3.3 V单电源供电。外部VCO的工作电压最高可达5.5 V。独立的输出驱动器电源可以为2.375 V至3.465 V。 AD9520的额定工作温度范围为−40°C至+85°C标准工业温度范围。

高频耦合防弹芯片数据手册说明书

High Isolation, Silicon SPDT,Nonrefective Switch, 9 kHz to 13.0 GHz Data Sheet HMC1118Rev. 0Document FeedbackInformation furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, N orwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved. Technical Support FEATURESNonreflective 50 Ω designPositive control: 0 V/3.3 VLow insertion loss: 0.68 dB at 8.0 GHzHigh isolation: 48 dB at 8.0 GHzHigh power handling35 dBm through path27 dBm terminated pathHigh linearity1 dB compression (P1dB): 37 dBm typicalInput third-order intercept (IIP3): 62 dBm typicalESD rating: 2 kV human body model (HBM)3 mm × 3 mm, 16-lead LFCSP packageNo low frequency spuriousSettling time (0.05 dB margin of final RF OUT): 7.5 μs APPLICATIONSTest instrumentationMicrowave radios and very small aperture terminals (VSATs) Military radios, radars, and electronic counter measures (ECMs) Fiber optics and broadband telecommunicationsFUNCTIONAL BLOCK DIAGRAMGNDGNDRFCGNDNDNDF1ND12961-1Figure 1.GENERAL DESCRIPTIONThe HMC1118 is a general-purpose, broadband, nonreflective single-pole, double-throw (SPDT) switch in a LFCSP surface mount package. Covering the 9 kHz to 13.0 GHz range, the switch offers high isolation and low insertion loss. The switch features >48 dB isolation, 0.68 dB insertion loss up to 8.0 GHz, and a 7.5 μs settling time of 0.05 dB margin of final RF OUT. The switch operates using positive control voltage logic lines of +3.3 V and 0 V and requires +3.3 V and −2.5 V supplies. The HMC1118 can cover the same operating frequency range with a single positive supply voltage applied and the negative supply voltage (V SS) tied to ground and still maintaining good power handling performance. The HMC1118 is packaged in a 3 mm × 3 mm, surface mount LFCSP package.HMC1118Data SheetRev. 0 | Page 2 of 11TABLE OF CONTENTSFeatures .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Electrical Specifications ............................................................... 3 Digital Control Voltages .............................................................. 4 Bias and Supply Current .............................................................. 4 Absolute Maximum Ratings ............................................................ 5 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions ..............................6 Interface Schematics .....................................................................6 Typical Performance Characteristics ..............................................7 Insertion Loss, Return Loss, and Isolation ................................7 Input Compression Point and Input Third-Order Intercept ...8 Theory of Operation .........................................................................9 Applications Information .............................................................. 10 Evaluation PCB ........................................................................... 10 Outline Dimensions ....................................................................... 11 Ordering Guide .. (11)REVISION HISTORY10/15—Revision 0: Initial VersionData Sheet HMC1118 SPECIFICATIONSELECTRICAL SPECIFICATIONSV CTRL = 0 V/3.3 V dc, V DD = LS = 3.3 V dc, V SS = −2.5 V dc, T A = 25°C, 50 Ω system, unless otherwise specified.Table 1.Parameter Test Conditions/Comments Min Typ Max Unit INSERTION LOSS9 kHz to 3.0 GHz 0.5 1.0 dB9 kHz to 8.0 GHz 0.68 1.1 dB9 kHz to 10.0 GHz 0.7 1.3 dB9 kHz to 13.0 GHz 1.3 2.0 dB ISOLATION RFC TO RF1/RF2 (WORST CASE)9 kHz to 3.0 GHz 40 50 dB9 kHz to 8.0 GHz 42 48 dB9 kHz to 10.0 GHz 28 35 dB9 kHz to 13.0 GHz 18 25 dB RETURN LOSSOn State 9 kHz to 3.0 GHz 26 dB9 kHz to 8.0 GHz 22 dB9 kHz to 13.0 GHz 9 dB Off State 9 kHz to 3.0 GHz 26 dB9 kHz to 8.0 GHz 14 dB9 kHz to 13.0 GHz 5 dB RADIO FREQUENCY (RF) SETTLING TIME50% V CTRL to 0.05 dB margin of final RF OUT7.5 µs50% V CTRL to 0.1 dB margin of final RF OUT 6 µs SWITCHING SPEEDt RISE/t FALL10%/90% RF 0.85 µst ON/t OFF50% V CTRL to 10%/90% RF 2.7 µs INPUT POWER 1 MHz to 13.0 GHz1 dB Compression (P1dB) 35 37 dBm 0.1 dB Compression (P0.1dB) 35 dBm INPUT THIRD-ORDER INTERCEPT (IIP3) Two-tone input power = 14 dBm at each tone, 1 MHz to 13.0 GHz 62 dBm RECOMMENDED OPERATING CONDITIONS1Positive Supply Voltage (V DD) 3.0 3.6 V Negative Supply Voltage (V SS) −2.75 −2.25 V Control Voltage (V CTRL) Range 0 V DD V Logic Select (LS) Voltage Range 0 V DD V RF Input Power V DD/V CTRL = 3.3 V, V SS = −2.5 V, T A = 85°C, frequency = 2 GHzThrough Path 35 dBm Termination Path 27 dBm Hot Switch Power Level V DD = 3.3 V, T A = 85°C, frequency = 2 GHz 27 dBm Case Temperature Range (T CASE) −40 +85 °C1 These are the recommended values for these parameters.Rev. 0 | Page 3 of 11HMC1118 Data SheetDIGITAL CONTROL VOLTAGESV DD = 3.3 V ± 10%, V SS = −2.5 V ± 10%, T CASE = −40°C to +85°C, unless otherwise specified.Table 2.Parameter Symbol Min Typ Max Unit Test Condition/CommentsINPUT CONTROL VOLTAGE <1 µA typicalLow V IL−0.3 +0.8 VHigh V IH 2.0 V DD + 0.3 VBIAS AND SUPPLY CURRENTTable 3.Parameter Symbol Min Typ Max UnitSUPPLY CURRENTV DD = 3.3 V I DD20 200 µAV SS = −2.5 V I SS0.5 10 µARev. 0 | Page 4 of 11Data SheetHMC1118Rev. 0 | Page 5 of 11ABSOLUTE MAXIMUM RATINGSTable 4.ParameterRatingPositive Supply Voltage (V DD ) Range −0.3 V to +3.7 V dc Negative Supply Voltage (V SS ) Range −2.8 V to +0.3 V Control Voltage (V CTRL ) Range −0.3 V to V DD + 0.3 V Logic Select (LS) Voltage Range−0.3 V to V DD + 0.3 V RF Input Power 1 (V DD /V CTRL = 3.3 V, V SS = −2.5 V, T A = 85°C, Frequency = 2 GHz) See Figure 2 to Figure 4 Through Path 37 dBm Termination Path28 dBm Hot Switch Power Level (V DD = 3.3 V,T A = 85°C, Frequency = 2 GHz) 30 dBm Storage Temperature Range−65°C to +150°C Maximum Reflow Temperature (MSL3 Rating) 260°C Channel Temperature135°C Thermal Resistance (Channel to Package Bottom)Through Path 116°C/W Terminated Path100°C/W ESD Sensitivity (HBM), Class 22 kV1For recommended operating conditions, see Table 1.Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.4–24–20–16–12–8–40010987654321P O W E R (d B )FREQUENCY (GHz)12961-002Figure 2. Power Derating Through Path4–24–20–16–12–8–400.010.11101001000P O W E R (d B )FREQUENCY (MHz)12961-004Figure 3. Power Derating Through Path (Low Frequency Detail)4–24–20–16–12–8–400.010.1110100100010000P O W E R (d B )FREQUENCY (MHz)12961-003Figure 4. Power Derating for Hot Switching PowerESD CAUTIONHMC1118Data SheetRev. 0 | Page 6 of 11PIN CONFIGURATION AND FUNCTION DESCRIPTIONSDD CTRL SSG N DG N DR F 2G N D G N DG N DR F 1G N D12961-005NOTES1. THE EXPOSED PAD MUST BE CONNECTED TO THE RF/DC GROUND OF THE PRINTED CIRCUIT BOARD (PCB).Figure 5. Pin ConfigurationTable 5. Pin Function DescriptionsPin No.MnemonicDescription1, 2, 4 to 6, 8, 13, 15, 16GNDGround. The package bottom has an exposed metal pad that must connect to the printed circuit board (PCB) RF/dc ground. See Figure 6 for the GND interface schematic.3 RFC RF Common Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required ifthe RF line potential is not equal to 0 V dc.7 RF2 RF2 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RFline potential is not equal to 0 V dc.14 RF1 RF1 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RFline potential is not equal to 0 V dc.9 V SS Negative Supply Voltage Pin. 10 V CTRL Control Input Pin. See Table 1, Table 2, and Table 6. 11 LS Logic Select Input Pin. See Table 1, Table 2, and Table 6. 12 V DD Positive Supply Voltage Pin. EPADExposed Pad. The exposed pad must be connected to the RF/dc ground of the printed circuit board (PCB).Table 6. Truth TableControl InputSignal Path StateLS V CTRL RFC to RF1RFC to RF2High L ow On Off High High Off On ow L owOff On ow HighOnOffINTERFACE SCHEMATICSGND12961-006Figure 6. GND Interface SchematicV12961-007V CTRLFigure 7. V CTRL Interface SchematicV 12961-008LSFigure 8. LS Interface SchematicData SheetHMC1118Rev. 0 | Page 7 of 11TYPICAL PERFORMANCE CHARACTERISTICSINSERTION LOSS, RETURN LOSS, AND ISOLATION–4–3–2–12468101214I N S E R T I O N L O S S (d B )FREQUENCY (GHz)12961-009Figure 9. Insertion Loss vs. Frequency–50–40–30–20–10024********R E T U R N L O S S (d B )FREQUENCY (GHz)12961-011Figure 10. Return Loss vs. Frequency0–90–80–70–60–50–40–30–20–102468101214I S O L A T I O N (d B )FREQUENCY (GHz)12961-010Figure 11. Isolation Between RFC and the RF1 and RF2 Ports vs. Frequency0–100–90–80–70–60–50–40–30–20–1002468101214I S O L A T I O N (d B )FREQUENCY (GHz)12961-012Figure 12. Isolation Between RF1 and RF2 Ports vs. FrequencyHMC1118Data SheetRev. 0 | Page 8 of 11INPUT COMPRESSION POINT AND INPUT THIRD-ORDER INTERCEPT4028303234363813121110987654321I N P U T C O M P R E S S I O N (d B m )FREQUENCY (GHz)12961-013Figure 13. 0.1 dB and 1 dB Compression Point vs. Frequency40283032343638013121110987654321I N P U T C O M P R E S S I O N (d B m )FREQUENCY (GHz)12961-014Figure 14. 1 dB Input Compression Point vs. Frequency over Temperature6545505560012108642I N P U T I P 3 (d B m )FREQUENCY (GHz)12961-015Figure 15. Input Third-Order Intercept (IIP3) Point vs. Frequency overTemperature 401015202530350.010.11101001000I N P U T C O M P R E S S I O N (d B m )FREQUENCY (MHz)12961-016Figure 16. 0.1 dB and 1 dB Input Compression Point vs. Frequency(Low Frequency Detail)401015202530350.010.11101001000I N P U T C O M P R E S S I O N (d B m )FREQUENCY (MHz)12961-017Figure 17. 1 dB Input Compression Point vs. Frequency over Temperature(Low Frequency Detail)65605550450.11101001000I N P U T I P 3 (d B m )FREQUENCY (MHz)12961-018Figure 18. Input Third-Order Intercept (IIP3) Point vs. Frequency overTemperature (Low Frequency Detail)Data SheetHMC1118Rev. 0 | Page 9 of 11THEORY OF OPERATIONThe HMC1118 requires a positive supply voltage applied to the V DD pin and a negative supply voltage applied to the V SS pin. Bypassing capacitors are recommended on the supply lines to minimize RF coupling. The HMC1118 can operate with a single positive supply voltage applied to the V DD pin and the negative voltage input pin (V SS ) connected to ground; however, some performance degradations in the input power compression and third-order intercept can occur.The HMC1118 is controlled via two digital control voltages applied to the V CTRL pin and the LS pin. A small value bypassing capacitor is recommended on these digital signal lines to improve the RF signal isolation.The HMC1118 is internally matched to 50 Ω at the RF input port (RFC) and the RF output ports (RF1 and RF2); therefore, no external matching components are required. The RF1 and RF2 pins are dc-coupled, and dc blocking capacitors are required on the RF paths if the RF potential is not equal to a common-mode voltage of 0 V . The design is bidirectional; the input and outputs are interchangeable.The ideal power-up sequence is as follows:1. Power up GND.2. Power up V DD and V SS . The relative order is not important.3. Power up the digital control inputs. The relative order ofthe logic control inputs is not important. Powering the digital control inputs before the V DD supply can inadvertently forward bias and damage the internal ESD protection structures.4. Power up the RF input. The logic select (LS) allows the user to define the control input logic sequence for the RF path selections. With the LS pin set to logic high, the RFC to RF1 path turns on when V CTRL is logic low, and the RFC to RF2 path turns on when V CTRL is logic high. With LS set to logic low, the RFC to RF1 path turns on when V CTRL is logic high, and the RFC to RF2 path turns on when V CTRL is logic low.Depending on the logic level applied to the LS and V CTRL pins, one RF output port (for example, RF1) is set to on mode, by which an insertion loss path provides the input to the output. The other RF output port (for example, RF2) is then set to off mode, by which the output is isolated from the input. When the RF output port (RF1 or RF2) is in isolation mode, internally terminate it to 50 Ω, and the port absorbs the applied RF signal (see Table 7).Table 7. Switch Mode OperationDigital Control Inputs Signal ModeLS V CTRL RFC to RF1 RFC to RF2 High LowOn mode. A low insertion loss path from the RFC port to the RF1 port.Off mode. The RF2 port is isolation from the RFC port andinternally terminated to a 50 Ω load to absorb the applied RF signals.High HighOff mode. The RF1 port is isolation from the RFC port and internally terminated to a 50 Ω load to absorb the applied RF signals.On mode. A low insertion loss path from the RFC port to the RF2 port. Low LowOff mode. The RF1 port is isolation from the RFC port and internally terminated to a 50 Ω load to absorb the applied RF signals.On mode. A low insertion loss path from the RFC port to the RF2 port. Low HighOn mode. A low insertion loss path from the RFC port to the RF1 port.Off mode. The RF2 port is isolation from the RFC port andinternally terminated to a 50 Ω load to absorb the applied RF signals.HMC1118Data SheetRev. 0 | Page 10 of 11APPLICATIONS INFORMATIONEVALUATION PCBGenerate the evaluation PCB used in this application with proper RF circuit design techniques. Signal lines at the RF port must have 50 Ω impedance, and the package ground leads and backside ground slug must be connected directly to the ground plane similarly to what is shown in Figure 19. The evaluation board shown in Figure 19 is available from Analog Devices, Inc. upon request.12961-019Figure 19. EV1HMC1118LP3D Evaluation PCBTable 8. Bill of Materials for the EV1HMC1118LP3D Evaluation Board 1Item Description Manufacturer 2J1 to J3 PC mount SMA RF connectors TP1 to TP5 Through-hole hold mount test points C1, C5 100 pF capacitors, 0402 packageU1 HMC1118 SPDT switch Analog Devices, Inc.PCB 600-01012-00-1 evaluation PCB, Rogers 4350 circuit board materialEV1HMC1118LP3D , Analog Devices, Inc.11 Reference this number to order the full evaluation PCB.2The blank cells in the manufacturer column are left blank intentionally for they are user-selectable.Product OverviewOnlineDocumentation Design ResourcesDiscussionSample & BuyData SheetHMC1118Rev. 0 | Page 11 of 11OUTLINE DIMENSIONS0.080.95FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONSSECTION OF THIS DATA SHEET.01-08-2015-A000000*COMPLIANT WITH JEDEC STANDARDS MO-220-VEED-4WITH THE EXCEPTION OF PACKAGE EDGE TO LEAD EDGE.Figure 20. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]3 mm × 3 mm Body, Very Very Thin Quad(CP-16-38)Dimensions shown in millimeters1 HMC1118LP3DE and HMC1118LP3DETR are RoHS-Compliant Parts.2See the Absolute Maximum Ratings section. 3XXXX is the 4-digit lot number.©2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12961-0-10/15(0)。

基于MB90092型专用字符叠加电路的视频监控系统的设计与实现

人员希望所看到的是得到验证的真实图像．论时无
再显示，从而检测出被监控方高科技人员随意拆动监控头系统的行为，有效防止了因信号传输线路被
随意改动而导致伪图像的引入。本系统能在一些要求较高且监视背
态伪随机符号的方法防止系统在运行时监控头被拆
卸。一旦线路被拆动，主监控端给出的确认标识将不
便使用人员知道该图像信息以何种方式来自何处及
与之相关的信息，时间，区徽标，时数据显示如地实在屏幕上。但是对于监控人员而言。控端遭到攻监击是一个值得担心的问题。因此，技术方案和增改善强安全性是对目前状况提出的一种迫切要求。监控
ｔｅｅａｔｅｓｏｇｐｅｅｎｒｍｏｅｃｎｒｌｌＯｗｉｅｇａａｔｅ．ｈｘｃｎｓｆｉｅａｐａｄｏｅｔｏｔＯｍｌｂｕｒｎｅｄｍａｒｏｌ
Ｋｅｗｏｄ：Ｂ０９；ｖｄｏｃａａｔｒｓｐｒｍｐｓｔｎ；ｍｏｉｒｓｓｅ；ｄｓｇｙｒｓＭ９０２ｉｅｈｒｃｅｕｅｉｏｉｏｉｎｔｙｔｍｏｅｉｎ
ａｙｆｏｏｕｐｓｔｃｆｈｇ —ｅｈｐｒｏｓｏｈｅｍｉａｒｎｒｄｃｄ。Ｕｓｎｈｓｍｅｈｄ，ｗａｍｎｐｒｏｅａｔｋｏｉｈｔｃｅｓｎｎｔｅｔｒｎｌａｅｉｔｕｅｒａｏｉｇｔｉｔｏ
１引言
随着监控现场的扩展和探头数量增多。在监控端的图像显示系统中，常需要接收外部数据并把经相关的信息实时地连同图像显示在监控屏幕上，以

MB90092 寄存器BIT的含义

Command 3 (VRAM Write Control)FIL : VRAM fill controlFIL = 0:Do not fill VRAM.FIL = 1: Fill VRAM.Command 5 (Screen Control 2)KID : Halftone controlKID = 0 : Perform normal display, disabling halftone display.APC : APC controlAPC = 1 : Turn the APC function ONGYZ : Main screen line enlargement controlBH2 to BH0 : Color phase control Color phase offset 45 degreesW3 to W0 : Main screen line spacing controlCommand 7 (Main Screen Vertical Display Position Control)EC : Sync signal output controlLP : Simple NTSC/PAL controlLP = 0 : Normal operationLP = 1 : Simple NTSC/PAL operationFO : Color phase signal（FSCO pin）output controlY5 to Y0 : Main screen vertical display position control (in dot units)Command 8 (Main Screen Horizontal Display Position Control)SC : Sync signal input control bitSC = 1 : Set the EXHSYN pin as a horizontal sync signal input and the EXVSYN pin as a vertical sync signal input.FC : Sync signal input 3 s filter controlX5 to X0 : Main screen horizontal display position controlCommand 9 (Kanji Font Display Control)GRM : Main screen display mode controlGRM = 0 : Display the main screen in normal mode.The main screen can display only normal characters.The character background color can be set for each character Command 10 (Color Control)RB : Main screen solid-fill background display controlBK : Main screen blink display controlCC : Main screen character color/monochrome controlBC : Main screen character background color/monochrome control(Main screen graphic color/monochrome control)UC : Screen background color/monochrome controlUG, UR, UB : Screen background colorCommand 4 (Screen Control 1)IE : Internal/external synchronization controlIN : Interlaced/noninterlaced display controlEB : Screen background display controlEO : Field controlCM : Color/monochrome display controlZM : Zoom-in controlNP : NTSC/PAL controlNP = 0: Output display signals using the NTSC system.NP = 1: Output display signals using the PAL system.P2, P0 : Pattern background controlDC : Display controlDC = 1: Enable display output operation.Command 0 (VRAM Address Setting)VSL : VRAM write controlRA8 to RA5 : VRAM row address setting (00 to B H)CA4 to CA0 : VRAM column address setting (00 to 17H)Main Screen Sharacter Control Data Write (If VSL = 0 in Command 0)Command 1-1 (Main screen character control data setting 1)Command 2-1 (Main screen character control data setting 2)(MD), MC to M0 : Character codeAT : Specify character attribute display.CG, CR, CB : Character colorsBG, BR, BB : Character background colors(GR) : Specify normal character/graphic character display(BS) : Specify shaded background display.Writing Sub-screen Line Control Data (When Command 0:VSL = 1, CA0 = 0)Set sub-screen line control data.Command 1-2 (Sub-screen line control data setting 1)Command 2-2 (Sub-screen line control data setting 2)SMD to SM0 : Sub-screen line first character codeSDC : Sub-screen line output controlSGR : Sub-screen line character display controlSCG to SCB : Sub-screen line character colors (when SGR = 0)SCG : Sub-screen line graphic color transparency control (when SGR = 1)SCR, SCB : Sub-screen line graphic color phase control (when SGR = 1)Main Screen Line Control Data Write (If VSL = 1 and CA0 = 1in Command 0)This command sets the line control data of the main screen.Command 1-3 (Main screen line control data setting 1)Command 2-3 (Main screen line control data setting 2)OF1, OF0 : Character color phase controlPC : Shaded pattern background color/monochrome controlPG, PR, PB : Shaded pattern background colorG2, G1, G0 : Character size controlSOC : Output priority controlVD : Video signal output controlDG : Digital signal output controlKC : Line background color/monochrome controlKG, KR, KB : Line background colorCommand 11 (Sub-Screen Control)SG2 to SG0 : Sub-screen configuration controlSCC : Sub-screen character color/monochrome controlSBC : Sub-screen character background color/monochrome controlSGC : Sub-screen graphic color/monochrome controlSBG, SBR, SBB : Sub-screen pattern background colorCommand 12 (Sub-Screen Vertical Position Control) SGA : Sub-screen full-screen mode controlSY7 to SY0 : Sub-screen vertical display positionCommand 13 (Sub-Screen Horizontal Position Control) SX8 to SX0 : Sub-screen horizontal display position。

基于MB90092的电梯楼层显示器设计

实现了将电梯当前所处楼层相关信息动态实时叠加至视频信号的功能，时还能检测视频信号的有无，而便于保安监控人员及时同从
处理有关情况。应用结果表明，系统运行稳定可靠、该编程简单、可维护性和可扩充性都较强。关键词：智能电磁干扰
状态；
⑨ 可以设置１１～２个字符的电梯名称； ⑩ 自带国标一、二级汉字库。
１电梯楼层显示器的总体方案
电梯楼层显示器采用双Ａ８Ｓ２单片机作为主Ｔ９５
要控制芯片，与ＭＢ０９、Ｍ１８、Ｍ２Ｆ８Ｂ９０２Ｌ８１Ａ９００、
和粤铭徐支影高嵩索勋胡ｊ｝ｌ
（长春理工大学电子信息工程学院，吉林长春１０２）３０２
摘
要：介绍了基于Ｍ９０２型专用视频字符叠加芯片的电梯楼层显示器的硬件与软件设计，合双Ａ８Ｓ２核心的单片机系统，Ｂ０９结Ｔ９５
中图分类号：Ｔ２７Ｐ７
可靠性
Ａ８Ｓ２频信号Ｔ９５视
动态实时
安保监控
文献标志码：Ｂ
Ａｂｔａｔ：ＨａｄｒｎｏｔｒｅｉｎｏｉｔｒｙｍｏｉｏｎｉｐａａｅｎＭＢ９０２，ｔｅｄｄｃｔｄＩｔｘｎｒｐｉｖｒａｄＩｓｒｃｒｗａｅａｄｓｆｗａｅｄｓｇｆａｌｓｏｅｎｔｒｇｄｓｌｙｂｓｄｏｔｆｉ０９ｈｅｉａｅＣｅｔａｄｇａｈｃｏｅｌｌＣ

290 Series Waveform Generators说明书

290 Series Waveform GeneratorsArbitrary WaveformsWaveforms The maximum arbitrary waveform size is 1 M points. Up to 500 user-definedwaveforms may be stored on the removable memory card. Arbitrarywaveforms can be defined by front panel editing controls, by downloading ofwaveform data via RS-232,USB or GPIB, or by writing directly to theremovable memory card using the USB card reader/writer connected to aPC.Waveform memory 1 M points. Minimum waveform size is 8 points.Vertical resolution 12 bitsSample clock range 100 mHz to 100 MHzResolution 4 digitsAccuracy ± 1 digit of settingOutput filter Selectable between 40 MHz Elliptic, 20 MHz Bessel or noneSequence Up to 1024 waveforms may be linked. Each waveform can have a loopcount of up to 32,768. A sequence of waveforms can be looped up to1,048,575 times or run continuously.Noise function Digital noise generated by a 35-bit linear feedback register clocked at 100MHz. User’s external filter defines bandwidth and responseStandard WaveformsWaveforms Sine, square, triangle, DC, positive ramp, negative ramp, sin(x)/x, pulse,pulse train, cosine, haversine and havercosineSine, Cosine, Haversine, HavercosineRange 0.1 mHz to 40 MHzResolution 0.1 mHz or 10 digitsAccuracy Better than 10 ppm for 1 yearTemperature stability Typically < 1 ppm/°COutput level 5 mV to 20 V p-p from 50 ΩHarmonic distortion < 0.15 % THD to 100 kHz; < –60 dBc to 20 kHz, < –50 dBc to 1 MHz, < –40dBc to 10 MHz, < –30 dBc to 40 MHzNon-harmonic spurii < –60 dBc to 1 MHz, < –60 dBc + 6 dB/octave 1 MHz to 40 MHzSquareRange 1 mHz to 50 MHzResolution 1 mHz (4 digits)Accuracy ± 1 digit of settingOutput level 5 mV to 20 V p-p from 50 ΩRise and fall times < 8 nsTriangleRange 0.1 mHz to 500 kHzResolution 0.1 mHz or 10 digitsAccuracy Better than 10 ppm for 1 yearOutput level 5 mV to 20 V p-p from 50 Ω, linearity error: < 0.1 % to 30 kHzRamps and Sin(x)/xRange 0.1 mHz to 500 kHzResolution 0.1 mHz or 10 digitsAccuracy Better than 10 ppm for 1 yearOutput level 5 mV to 20 V p-p from 50 ΩLinearity error < 0.1 % to 30 kHzPulse and Pulse TrainOutput level 5 mV to 20 V p-p from 50 ΩRise and fall times < 8 nsPeriod Range: 40 ns to 100 s; Resolution: 4-digits; Accuracy: ± 1 digit of setting Delay Range: –99.9 s to + 99.99 s; Resolution: 0.001 % of period or 10 nsWidth Range: 10 ns to 99.99 s; Resolution: 0.001 % of period or 10 nsTrains of up to 10 pulses may be specified, each having independently defined width, delay and level. The baseline voltage is separately defined and the sequence repetition rate is set by the pulse train period.Operating ModesContinuous Waveform runs continuouslyTriggered Burst Each active edge of the trigger signal will produce one burst of thewaveformCarrier waveforms All standard and arbitraryMax. carrier frequency The smaller of 2.5 MHz or the maximum for the selected waveform. 100Msamples/s for ARB or Sequence.Number of Cycles 1 to 1048575Trigger rep. rate 0.005 Hz to 100 kHz internal, dc to 1 MHz externalTrigger source Internal from keyboard or trigger generator. External from TRIG IN orremote interface.Start/stop phase ± 360 ° settable with 0.1 ° resolution, subject to waveform frequency andtypeGated Waveform will run while the Gate signal is true and stop while false Carrier waveforms All standard and arbitraryMax. carrier frequency The smaller of 2.5 MHz or the maximum for the selected waveform. 80Msamples/s for ARB or Sequence.Trigger rate 0.005 Hz to 100 kHz internal, dc to 1 MHz externalGate signal source Internal from keyboard or trigger generator. External from TRIG IN orremote interface.Start/stop phase ± 360 ° settable with 0.1 ° resolution, subject to waveform frequency andtypeSweep Capability provided for both standard and arbitrary waveforms.Arbitrary waveforms are expanded or condensed to exactly 4096points and DDS techniques are used to perform the sweep.Carrier waveforms All standard and arbitrary except pulse, pulse train and sequence. Sweepmode: Linear or logarithmic, continuous or triggered.Sweep direction Up, down, up/down or down/upSweep range 1 mHz to 40 MHz in one range. Phase continuous. Independent setting ofstart/stop frequency.Sweep time 1 ms to 999 s (3 digit resolution)Marker Variable during sweep.Sweep trig. Source The sweep may be free run or triggered from the following sources:Manually from keyboard. Externally from TRIG IN input or remote interface. Sweep hold Sweep can be held and restarted by HOLD keyTone Switching Capability provided for both standard and arbitrary waveforms.Arbitrary waveforms are expanded or condensed to exactly 4096points and DDS techniques used to allow instantaneous frequencyswitching.Carrier waveforms All waveforms bar pulse, pulse train, sequenceFrequency list Up to 16 frequencies from 1 mHz to 40 MHzTrigger rep. rate 0.005 Hz to 100 kHz internal, dc to 1 MHz external. Usable repetition rateand waveform frequency depend on the tone switching mode.Source Internal from keyboard or trigger generator. External from TRIG IN orremote interface.Tone switching modesGated The tone is output while the trigger signal is true and stopped, at the end ofthe current waveform cycle, while the trigger signal is false. The next tone isoutput when the trigger signal is true again.Triggered The tone is output when the trigger signal goes true and the next tone isoutput, at the end of the current waveform cycle, when the trigger signalgoes true again.FSK The tone is output when the trigger signal goes true and the next tone isoutput, immediately, when the trigger signal goes true again.External Amplitude ModulationCarrier frequency Entire range for selected waveformCarrier waveforms All standard and arbitrary waveformsModulation source Modulation socketFrequency range DC to 500 kHzSignal range Approx. 1 V pk-pk for 100 % level change at maximum outputExternal Signal SummingCarrier frequency Entire range for selected waveformCarrier waveforms All standard and arbitrary waveformsSum source Sum socketFrequency range DC to 16 MHzSignal range Approximately 2 Vpk-pk input for 20 Vpk-pk output.Trigger GeneratorSource Internal source 0.005 Hz to 100 kHz squarewave adjustable in 10 us steps.3 digit resolution. Available for external use from the SYNC OUT socket. Main Outputs – One for each channelOutput impedance 50 ΩAmplitude 5 mV to 20 V pk-pk open circuit (2.5 mV to 10 V pk-pk into 50 Ω. Amplitudecan be specified open circuit (Hi Z) or into an assumed load of 50 Ωor 60 Ω,in Vpk-pk, Vrms or dBm.Ampl. accuracy Better than 2 % ± 1 mV at 1 kHz into 50 Ω.Ampl. flatness ± 0.2 dB to 1 MHz; ± 0.4 dB to 40 MHzDC offset range ± 10 V. DC offset plus signal peak limited to ± 10 V from 50 Ω. Offset accuracy Typically within ± 3 % ± 10 mV, unattenuatedResolution 3 digits or 1 mV for both Amplitude and DC OffsetSync Out – One for each channel Multifunction output user definable or automatically selected to be any of the following:Waveform sync (All waveforms) A square wave with 50 % duty cycle at the main waveform frequency, or a pulse coincident with the first few points of an arbitrary waveform.Position markers (Arbitrary only) Any point(s) on the waveform may have associated marker bit(s) set high or lowBurst done Produces a pulse coincident with the last cycle of a burstSequence sync Produces a pulse coincident with the end of a waveform sequenceTrigger Selects the current trigger signal. Useful for synchronising burst or gatedsignals.Sweep sync Outputs a pulse at the start of sweep to synchronise an oscilloscope orrecorder. Can additionally output a sweep marker.Phase lock out Used to phase lock two generators. Produces a positive edge at the 0ophase point.Output signal level Logic level of < 0.8 V to > 3 V for all outputs except Sweep Sync. SweepSync is a 3-level waveform.Trig InFrequency range DC to 1 MHzSignal range Threshold nominally TTL level; max. input ± 10 VMin. rulse width 50 ns for Trigger and Gate modes; 50 µs for Sweep modeInput impedance 10 kΩModulation InFrequency range DC to 500 kHzSignal range VCA: Approximately 1 Vpk-pk for 100 % level change at maximum outputSCM: Approximately ± 1 Vpk for maximum outputInput impedance Typically 1 kΩSum InFrequency range DC to 30 MHz (291) DC to 16 MHz (292/294)Signal range Approximately 2 Vpk-pk input for 20 Vpk-pk outputInput impedance Typically 1 kΩHold Holds an arbitrary waveform at its current position. A TTL low level or switchclosure causes the waveform to stop at the current position and wait until aTTL high level or switch opening which allows the waveform to continue.The front panel MAN/HOLD key or remote command may also be used tocontrol the Hold function.Input impedance 10 kΩRef Clock In/OutSet to input Input for an external 10 MHz reference clock. TTL/CMOS threshold level. Set to output Buffered version of the internal 10 MHz clock. Output levels nominally 1 Vand 4 V from 50 Ω.Set to phase lock Used together with SYNC OUT on a master and the TRIG IN on a slave tosynchronize (phase lock) two generators ARB Clock InFrequency Range DC to 50 MHzMax. input voltage + 5 V, -1 VInter-Channel OperationInter-Channel Modulation The waveform from any channel may be used to Amplitude Modulate (AM) or Suppressed Carrier Modulate (SCM) the next channel. Alternatively any number of channels may be Modulated (AM or SCM) with the signal at the MODULATION input socket.Carrier frequency Entire range for selected waveformCarrier waveforms All standard and arbitrary waveformsModulation types AM: Double sideband with carrierSCM: Double sideband suppressed carrierModulation source Internal from the previous channel. External from Modulation input socket.The external modulation signal may be applied to any number of channelssimultaneouslyFrequency range DC to > 100 kHzInternal AM depth 0 % to 105 %Internal AM resolution 1 %Carrier Suppression(SCM)> 40 dBExternal modulation signal range VCA: Approximately 1 V pk-pk for 100 % level change at maximum output SCM: Approximately ± 1 Vpk for max. outputInter-Channel Analogue Summing Waveform Summing sums the waveform from any channel into the next channel. Alternatively any number of channels may be summed with the signal at the SUM input socket.Carrier frequency Entire range for selected waveformCarrier waveforms All standard and arbitrary waveformsSum source Internal from the previous channel. External from SUM IN socket. Frequency range DC to > 16 MHzExt. signal range Approx. 5 Vpk-pk input for 20 Vpk-pk outputInter-Channel Phase Locking Two or more channels may be phase locked together. Each locked channel may be assigned a phase angle relative to the other locked channels. Arbitrary waveforms and waveform sequences may be phase locked but certain constraints apply to waveform lengths and clock frequency ratios.With one channel assigned as the Master and other channels as Slaves a frequency change on the master will be repeated on each slave thus allowing multiphase waveforms at the same frequency to be easily generated. DDS waveforms are those with 7 digits of frequency setting resolution, while Non-DDS waveforms have 4 digits.Phase resolution DDS waveforms: 0.1 degreeNon-DDS waveforms 0.1 degree or 360 degrees/number of points whichever is the greater Phase error < ± 10 ns all waveforms.Inter-Channel Triggering Any channel can be triggered by the previous or next channel. The previous/next connections can be used to ‘daisy chain’ a trigger signal from a ‘start’ channel, through a number of channels in the ‘chain’ to an ‘end’ channel.Each channel receives the trigger out signal from the previous (or next) channel, and drives its selected trigger out to the next (orprevious) channel. The ‘end’ channel trigger out can be set up to drivethe ‘start’ channel, closing the loop.In this way, complex and versatile interchannel trigger schemes maybe set up. Each channel can have its trigger out and its outputwaveform set up independently. Trigger out may be selected fromWaveform End, Position Markers, Sequence Sync or Burst Done.Using the scheme above it is possible to create a sequence of up to 64waveform segments, each channel producing up to 16 segments andall channels being summed to produce the complete waveform at theoutput of channel 4.The signals from the REF IN/OUT socket and the SYNC OUT socketcan be used to phase lock two instruments where more than 4channels are required.InterfacesRS-232 Variable Baud rate, 9600 Baud maximumIEEE488 Conforms with IEEE488.2USB Conforms with USB 1.1General SpecificationsDisplay 20 character x 4 row alphanumeric LCDData entry Keyboard selection of mode, waveform etc.; value entry by numeric keys orby rotary control.Memory card Removable memory card conforming to the Compact Flash memory cardstandard. Sizes from 32 MB to 1 GB can be used.Stored settings Up to 500 complete instrument set-ups may be stored and recalled from thememory card. Up to 500 arbitrary waveforms can also be storedindependent of the instrument settings.Size 130 mm (3U) high; 335 mm long; 350 mm wide (292/294), 212 mm wide(291)Weight 292/294: 7.2 kg (16 lb); 291: 4.1 kg (9 lb)Power 110 to 120 V or 100 V nominal 50/60/400 Hz; 220 to 240 V nominal, 50/60Hz. Voltage adjustable internally; operating range ± 10 % of nominal; 60 VAmax. Installation Category II.ComplianceOperating range +5 °C to 40 °C, 20 to 80 % RHStorage range –20 °C to +60 °CEnvironmental Indoor use at altitudes to 200 m, Pollution Degree 2Safety Complies with EN61010-1EMC Complies with EN61326Instrument drivers Labview and LabWindows CVI drivers are either supplied with theinstrument or are available via your local Fluke OfficeSupplied Items IEC Mains Lead. Printed manual (partly multi-language), multi-languagemanual on CD, Waveform Manager Plus software, compact Flash memorycard, compact Flash card reader/writer (USB connection to PC)Options 19-inch rack mounting kit。

基于OSD控制器MB90092的一种视频安全通信系统设计

第２９卷第６期
２００９年１２月
苏
州
大
学
学
报（工
科
版）
Ｖ１２Ｎｏ６ｏ．９．Ｄｅ．Ｏ９ｃ２Ｏ
ＪＲＮＡＬＯＦＳＨＯＵＵＮＩＯＵＵＺＶＥＲＳＴＥＮＧＩＩＹ（ＮＥＥＲＩＮＧＣＩＳＥＮＣＥＥＤＩＩＴＯＮ）
２１电源时钟模块．
电路工作电压为５Ｃ，ＶＤ由稳压芯片Ｌ８５提供。时钟模块由频率为１ＭＨ和１．３ＭＨ的两无源７０２ｚ７７４４ｚ晶振组成，分别为微控制模块主芯片Ａ８Ｃ１以及字符叠加模块主芯片ＭＢ０９Ｔ９５９０２提供工作时钟频率。
２２视频信号同步分离模块．
视频信号来自监控现场的监控摄像头，占用带宽为６５ｚ除图像信号外，其．ＭＨ，还包括行场同步信号、消隐信号、脉冲信号及前后均衡脉冲等，槽以消隐电平为零电平基准点。行、同步脉冲是字符显示的基准，场所以输入的视频信号先经同步分离电路分离出行场同步脉冲。视频同步分离器采用Ｎｔｎｌｅｃｎｕｔ公ａｉａＳｍｉｄｃｏｏｏｒ
全性能要求较高的场合，物馆、行、如博银海关以及公司仓库等。
１系统工作原理
视频字符叠加技术是指在视频上附着图形或字符信号，从而在屏幕的特定位置上与图像信号进行同时显
示，这项技术是应用电视技术中的一个重要领域，应用电视系统中发挥着重要的作用，在现将其用于视频监控系统，得视频监控、使通信更为安全可靠。如图１所示，系统在监控摄像头处附加电路，用伪随机序列编本采码显示各种类型的图形或字符，而远程监控中心也采用与之相对应的伪随机序列编码来检测各种类型的图形

MB90092芯片在成像测井字符叠加中的应用

Ｍ９０２以很方便的把这些相关信息通过应用Ｂ０９可
文字叠加到视频图像中．
ＭＢ０９９０２由串行输入控制电路、ＴＡＰＬ信ＮＳ／Ａ
号发生器电路、显示存储器ＶＡＲＭ控制电路、显示
１ＭＢ０９９０２简介
ＭＢ０９９０２是一款专用的视频字符叠加芯片，
硬件各部分的功能描述如下：
１）视频同步分离：用Ｌ８１４同步分离器利Ｍ１８］Ｅ
计时，把相应的时间通过字符叠加到视频信号中输出，录测井时间，记以便对测井资料存档．３）字符叠加：９０２是该系统的核心，ＭＢ０９接
［］ＦＪＳ公司．Ｎ—ＣＲＥＩＰＡＯＴＯＬＲ１ＵＩＵＯＳＥＮＤＳＬＹＣＮＲＬＥ
始化控制也是该系统软件控制的主要工作，面下
介绍根据Ｍ９０２的时序图对其发送数据和命令Ｂ０９
以及对其寄存器的设置．
［］刘艳滢，２李桂菊，田睿，等．基于ＭＢ０９９０２的实时图像显示系统的设计［］长春理工大学学报，０４２Ｊ．２０，７
（）４９．１：９ —６
中利用８Ｃ１的通用ＩＯ口模拟串行通信，９５／利用
软件来实现模拟ＳＩ式进行通信，括串行时Ｐ方包钟、串行数据输入／出及片选信号．输２）寄存器的设置：寄存器的设置主要包括：对同步方式、频制式、符大小、视字字符的颜色和背

9602FMQB资料

Connection Diagram
Dual-In-Line Package
TL F 6611 – 1
Order Number 9602DMQB 9602FMQB or DM9602N See NS Package Number J16A N16E or W16A
Function Table
Pin No’s A HxL H X B L LxH X CLR H H L Trigger Trigger Reset Operation
b 65 C to a 150 C
Note The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation
24 04 0 45 60
b1 6 b1 6 b 1 24 b 1 41 b 25 b 35
VOL
V mA
IIH IIL
mA
IOS ICC
Short Circuit Output Current Supply Current

基于MB90092的ROV系统视频叠加器设计

基于MB90092的ROV系统视频叠加器设计【摘要】本文介绍了基于MB90092型专用视频叠加芯片在ROV（有缆无人遥控潜水器）系统视频叠加器的硬件与软件设计，通过以STM32为核心的单片机系统和ROV控制计算机实现了将ROV相关信息动态实时叠加到ROV水下视频信号的功能，从而方便了ROV驾驶人员通过视频监控了解ROV作业状态。

通过记录ROV系统水下作业视频，回放时便于了解ROV作业时的相关状态信息。

应用结果表明，该字符叠加器运行可靠，可操作性和可维护性都比较强，可在海底可视化勘查方面广泛应用。

【关键词】ROV;水下视频;字符叠加;MB900921.前言随着水下作业需求的高速发展，ROV系统作为一种重要的开发海洋的方法和技术手段被广泛应用，而ROV的视频系统作为水下机器人的“眼睛”至关重要，为方便ROV操作人员通过监控视频获取更多ROV信息，单纯的视频监控画面不能满足ROV操控人员对ROV的操控需要。

作业人员需要水下视频监控画面里带有与ROV作业相关的各种信息，比如ROV的艏向、深度、高度、位置和事件等状态信息，因此将ROV的相关状态信息叠加到视频非常必要。

本文设计了一种基于MB90092芯片的视频字符叠加器，它可以方便的接收ROV主控计算机发送的数据并把相关信息叠加到视频画面中任意指定位置，ROV本体在水下的视频监视画面和状态信息一目了然，极大的方便了ROV作业人员的操控和ROV作业信息的记录保存。

2.系统设计2.1 MB90092主要功能特点MB90092 是日本富士通公司推出的一款OSD专用集成芯片，使用该芯片可以向视频画面中叠加各种文字信息。

该芯片叠加目标信息时需使用外部字库芯片，因此其相应的提供有外挂字库的接口，它能支持多达16Mbits 的外部存储空间的访问，用户可以自己向字库芯片中烧入自己所需叠加的任意点阵字符或图像等。

此外，MB90092可提供双屏显示功能，主屏和子屏可单独或重叠显示;字符大小有标准、双倍宽、双倍高、双倍宽×双倍高、四倍宽×双倍高等多种模式;字符可设置8种不同的颜色和8种背景色;显示位置可任意设置成水平方向和垂直方向，同时可设定行距;支持复合视频信号和Y/C分离视频信号输入。

pcm2900数据手册

BurrĆBrown Productsfrom TexasInstrumentsFEATURESAPPLICATIONSDESCRIPTIONPCM2900PCM2902SLES035E–MARCH2007–REVISED MARCH2008 STEREO AUDIO CODEC WITH USB INTERFACE,SINGLE-ENDED ANALOG INPUT/OUTPUT AND S/PDIF–Pass-Band Ripple=±0.1dB•PCM2900:Without S/PDIF–Stop-Band Attenuation=–43dB•PCM2902:With S/PDIF–Single-Ended Voltage Output•On-Chip USB Interface:–Analog LPF Included –With Full-Speed Transceivers•Multifunctions:–Fully Compliant With USB1.1Specification–Human Interface Device(HID)Volume±Control and Mute Control –Certified by USB-IF–Suspend Flag–Partially Programmable Descriptors(1)•Package:28-Pin SSOP–USB Adaptive Mode for Playback–USB Asynchronous Mode for Record–Bus Powered•USB Audio Speaker•16-Bit Delta-Sigma ADC and DAC•USB Headset•Sampling Rate:•USB Monitor–DAC:32,44.1,48kHz•USB Audio Interface Box–ADC:8,11.025,16,22.05,32,44.1,48kHz•On-Chip Clock Generator With Single12-MHzClock Source The PCM2900/2902is Texas Instruments'single-chip •Single Power Supply:5V Typical(V BUS)USB stereo audio codec with USB-compliantfull-speed protocol controller and S/PDIF(only •Stereo ADCPCM2902).The USB protocol controller works with –Analog Performance at V BUS=5V no software code,but the USB descriptors can be–THD+N=0.01%modified in some areas(e.g.,vendor ID/product ID).The PCM2900/2902employs SpAct™architecture,–SNR=89dBTI's unique system that recovers the audio clock from –Dynamic Range=89dB USB packet data.On-chip analog PLLs with SpAct–Decimation Digital Filter architecture enable playback and record with lowclock jitter and with independent playback and record –Pass-Band Ripple=±0.05dBsampling rates.–Stop-Band Attenuation=65dB–Single-Ended Voltage Input–Antialiasing Filter Included–Digital LCF Included•Stereo DAC–Analog Performance at V BUS=5V–THD+N=0.005%–SNR=96dB–Dynamic Range=93dB–Oversampling Digital Filter(1)The descriptor can be modified by changing a mask.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.SpAct is a trademark of Texas Instruments.System Two,Audio Precision are trademarks of Audio Precision,Inc.All other trademarks are the property of their respective owners.PRODUCTION DATA information is current as of publication date.Copyright©2007–2008,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasABSOLUTE MAXIMUM RATINGSPCM2900PCM2902SLES035E–MARCH 2007–REVISED MARCH 2008This integrated circuit can be damaged by ESD.Texas Instruments recommends that all integrated circuits be handled with appropriate precautions.Failure to observe proper handling and installation procedures can cause damage.ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.PACKAGING ORDERING INFORMATIONPCM2900SPECIFIED PACKAGE PACKAGE ORDERING TRANSPORT PRODUCTPACKAGE-LEADTEMPERATUREDESIGNATORMARKING NUMBER (1)MEDIARANGE PCM2900E Rails PCM2900E SSOP-2828DB–25°C to 85°CPCM2900EPCM2900E/2KTape and reel(1)Models with a slash (/)are available only in tape and reel in the quantities indicated (e.g.,/2K indicates 2000devices per reel).Ordering 2000pieces of PCM2900E/2K gets a single 2000-piece tape and reel.PCM2902SPECIFIED PACKAGE PACKAGE ORDERING TRANSPORT PRODUCTPACKAGE-LEADTEMPERATUREDESIGNATORMARKING NUMBER (1)MEDIARANGE PCM2902E Rails PCM2902E SSOP-2828DB–25°C to 85°CPCM2902EPCM2902E/2KTape and reel(1)Models with a slash (/)are available only in tape and reel in the quantities indicated (e.g.,/2K indicates 2000devices per reel).Ordering 2000pieces of PCM2902E/2K gets a single 2000-piece tape and reel.over operating free-air temperature range (unless otherwise noted)(1)PCM2900/PCM2902UNIT V BUSSupply voltage–0.3to 6.5V Ground voltage differences,AGNDC,AGNDP,AGNDX,DGND,DGNDU ±0.1V SEL0,SEL1,TEST0(DIN)(2)–0.3to 6.5V Digital input voltage D+,D–,HID0,HID1,HID2,XTI,XTO,TEST1(DOUT)(2),SSPND –0.3to (V DDI +0.3)<4V V IN L,V IN R,V COM ,V OUT R,V OUT L –0.3to (V CCCI +0.3)<4V Analog input voltageV CCCI ,V CCP1I ,V CCP2I ,V CCXI ,V DDI–0.3to 4V Input current (any pins except supplies)±10mA Ambient temperature under bias–40to 125°C T stg Storage temperature –55to 150°C T JJunction temperature 150°C Lead temperature (soldering)260°C,5s Package temperature (IR reflow,peak)250°C(1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)():PCM29022Submit Documentation Feedback Copyright ©2007–2008,Texas Instruments IncorporatedELECTRICAL CHARACTERISTICSPCM2900PCM2902 SLES035E–MARCH2007–REVISED MARCH2008all specifications at T A=25°C,V BUS=5V,f S=44.1kHz,f IN=1kHz,16-bit data,unless otherwise notedPCM2900E,PCM2902EPARAMETER TEST CONDITIONS UNITMIN TYP MAXDIGITAL INPUT/OUTPUTHost interface Apply USB Revision1.1,full speedAudio data format USB isochronous data formatINPUT LOGICD+,D–2 3.3XTI,HID0,HID1,and2.523.3High-level input HID2V IH VDC voltageSEL0,SEL12 5.25DIN,PCM2902 2.52 5.25D+,D–0.8XTI,HID0,HID1,and0.9Low-level input HID2V IL VDC voltageSEL0,SEL10.8DIN,PCM29020.9D+,D–,XTI,SEL0,±10SEL1High-level inputI IH V IN=3.3VµAvoltage HID0,HID1,and HID25080DIN,PCM290265100D+,D–,XTI,SEL0,±10SEL1Low-level inputI IL V IN=0VµAvoltage HID0,HID1,and HID2±10DIN,PCM2902±10 OUTPUT LOGICD+,D– 2.8High-level outputV OH DOUT,PCM2902I OH=–4mA 2.8VDC voltageSSPND I OH=–2mA 2.8D+,D–0.3 Low-level outputV OL DOUT,PCM2902I OL=4mA0.5VDC voltageSSPND I OL=2mA0.5CLOCK FREQUENCYInput clock frequency,XTI11.9941212.008MHz ADC CHARACTERISTICSResolution8,16bits Audio data channel1,2channelCopyright©2007–2008,Texas Instruments Incorporated Submit Documentation Feedback3ELECTRICAL CHARACTERISTICSPCM2900PCM2902SLES035E–MARCH 2007–REVISED MARCH 2008all specifications at T A =25°C,V BUS =5V,f S =44.1kHz,f IN =1kHz,16-bit data,unless otherwise notedPCM2900E,PCM2902E PARAMETERTEST CONDITIONSUNITMINTYPMAXCLOCK FREQUENCY 8,11.025,16,22.05,32,44.1,f SSampling frequencykHz48DC ACCURACY%of Gain mismatch,channel-to-channel ±1±5FSR %of Gain error ±2±10FSR %of Bipolar zero error±0FSRDYNAMIC PERFORMANCE (1)V CCCI =3.67V,V IN =–0.5dB (2)0.01%0.02%THD+NTotal harmonic distortion plus noise V IN =–0.5dB (3)0.1%V IN =–60dB 5%Dynamic rangeA-weighted 8189dB SNRSignal-to-noise ratio A-weighted8189dB Channel separation8085dBANALOG INPUTInput voltage 0.6V CCCI V p-p Center voltage 0.5V CCCIV Input impedance30k Ω–3dB 150kHz Antialiasing filter frequency responsef IN =20kHz–0.08dBDIGITAL FILTER PERFORMANCEPass band 0.454f SHz Stop band 0.583f SHz Pass-band ripple ±0.05dB Stop-band attenuation65dB t dDelay time17.4/f S s LCF frequency response–3dB0.078f SMHzDAC CHARACTERISTICSResolution 8,16bits Audio data channel1,2channelCLOCK FREQUENCY f S Sampling frequency32,44.1,48kHz(1)f IN =1kHz,using a System Two™audio measurement system by Audio Precision™in the RMS mode with 20-kHz LPF,400-Hz HPF in calculation.(2)Using external voltage regulator for V CCCI (as shown in Figure 36and Figure 37,using with REG103xA-A)(3)Using internal voltage regulator for V CCCI (as shown in Figure 38Figure 39)4Submit Documentation Feedback Copyright ©2007–2008,Texas Instruments IncorporatedELECTRICAL CHARACTERISTICSPCM2900PCM2902 SLES035E–MARCH2007–REVISED MARCH2008all specifications at T A=25°C,V BUS=5V,f S=44.1kHz,f IN=1kHz,16-bit data,unless otherwise notedPCM2900E,PCM2902EPARAMETER TEST CONDITIONS UNITMIN TYP MAXDC ACCURACY%of Gain mismatch channel-to-channel±1±5FSR%of Gain error±2±10FSR%of Bipolar zero error±2FSR DYNAMIC PERFORMANCE(1)V OUT=0dB0.005%0.016%THD+N Total harmonic distortion plus noiseV OUT=–60dB3% Dynamic range EIAJ,A-weighted8793dB SNR Signal-to-noise ratio EIAJ,A-weighted9096dB Channel separation8692dB ANALOG OUTPUTV O Output voltage0.6V CCCI V p-p Center voltage0.5V CCCI VLoad impedance AC coupling10kΩ–3dB250kHz LPF frequency responsef=20kHz–0.03dB Digital filter performancePass band0.445f S HzStop band0.555f S HzPass-band ripple±0.1dBStop-band attenuation–43dBt d Delay time14.3f S s POWER SUPPLY REQUIREMENTSV BUS Voltage range 4.355 5.25VDCADC,DAC operation5667mA Supply currentSuspend mode(2)210µAADC,DAC operation280352P D Power dissipation mWSuspend mode(2) 1.05Internal power supply V CCCI,V CCP1I,V CCP2I,3.25 3.35 3.5VDCvoltage V CCXI,and V DDITEMPERATURE RANGEOperation temperature–2585°CθJA Thermal resistance100°C/W(1)f OUT=1kHz,using a System Two audio measurement system by Audio Precision in the RMS mode with20-kHz LPF,400-Hz HPF.(2)Under USB suspend stateCopyright©2007–2008,Texas Instruments Incorporated Submit Documentation Feedback5 PIN ASSIGNMENTS1 2 3 4 5 6 7 8 9 10 11 12 13 1428 27 26 25 24 23 22 21 20 19 18 17 16 15D+D–VBUS DGNDUHID0HID1HID2SEL0SEL1VCCCI AGNDCV LINV RINVCOMSSPNDTEST0VCCXIAGNDXXTOVCCP2IDGNDVCCP1IV LOUTXTITEST1VDDIAGNDPV ROUTPCM2900(Top View)12345678910111213142827262524232221201918171615D+D–VBUSDGNDUHID0HID1HID2SEL0SEL1VCCCIAGNDCV LINV RINVCOMSSPNDDINVCCXIAGNDXXTOVCCP2IDGNDVCCP1IV LOUTXTIDOUTVDDIAGNDPV ROUTP0007-06PCM2902(Top View)PCM2900PCM2902SLES035E–MARCH2007–REVISED MARCH20086Submit Documentation Feedback Copyright©2007–2008,Texas Instruments IncorporatedPCM2900PCM2902SLES035E–MARCH2007–REVISED MARCH2008 PCM2900TERMINAL FUNCTIONSTERMINALI/O DESCRIPTIONNAME NO.AGNDC11–Analog ground for codecAGNDP18–Analog ground for PLLAGNDX22–Analog ground for oscillatorD–2I/O USB differential input/output minus(1)D+1I/O USB differential input/output plus(1)DGND26–Digital groundDGNDU4–Digital ground for USB transceiverHID05I HID key state input(mute),active-high(2)HID16I HID key state input(volume up),active-high(2)HID27I HID key state input(volume down),active-high(2)SEL08I Must be set to high(3)SEL19I Must be set to high(3)SSPND28O Suspend flag,active-low(Low:suspend,High:operational)TEST024I Test pin,must be connected to GNDTEST125O Test pin,must be left openV BUS3–Connect to USB power(V BUS)V CCCI10–Internal analog power supply for codec(4)V CCP1I17–Internal analog power supply for PLL(4)V CCP2I19–Internal analog power supply for PLL(4)V CCXI23–Internal analog power supply for oscillator(4)V COM14–Common for ADC/DAC(V CCCI/2)(4)V DDI27–Internal digital power supply(4)V IN L12I ADC analog input for L-channelV IN R13I ADC analog input for R-channelV OUT L16O DAC analog output for L-channelV OUT R15O DAC analog output for R-channelXTI21I Crystal oscillator input(5)XTO20O Crystal oscillator output(1)LV-TTL level(2) 3.3-V CMOS-level input with internal pulldown.This pin informs the PC of serviceable control signals such as mute,volume up,orvolume down,which have no connection with the internal DAC or ADC directly.See the Interface#3and End-Points sections.(3)TTL Schmitt trigger,5-V tolerant(4)Connect a decoupling capacitor to GND.(5) 3.3-V CMOS-level inputCopyright©2007–2008,Texas Instruments Incorporated Submit Documentation Feedback7PCM2900PCM2902SLES035E–MARCH 2007–REVISED MARCH 2008PCM2902TERMINAL FUNCTIONSTERMINAL I/O DESCRIPTIONNAME NO.AGNDC 11–Analog ground for codec AGNDP 18–Analog ground for PLL AGNDX 22–Analog ground for oscillatorD–2I/O USB differential input/output minus (1)D+1I/O USB differential input/output plus (1)DGND 26–Digital groundDGNDU 4–Digital ground for USB transceiver DIN 24I S/PDIF input (2)DOUT 25O S/PDIF outputHID05I HID key state input (mute),active high (3)HID16I HID key state input (volume up),active high (3)HID27I HID key state input (volume down),active high (3)SEL08I Must be set to high (4)SEL19I Must be set to high (4)SSPND 28O Suspend flag,active-low (Low:suspend,High:operational)V BUS 3–Connect to USB power (V BUS )V CCCI 10–Internal analog power supply for codec (5)V CCP1I 17–Internal analog power supply for PLL (5)V CCP2I 19–Internal analog power supply for PLL (5)V CCXI 23–Internal analog power supply for oscillator (5)V COM 14–Common for ADC/DAC (V CCCI /2)(5)V DDI 27–Internal digital power supply V IN L 12I ADC analog input for L-channel V IN R 13I ADC analog input for R-channel V OUT L 16O DAC analog output for L-channel V OUT R 15O DAC analog output for R-channel XTI 21I Crystal oscillator input (6)XTO 20OCrystal oscillator output(1)LV-TTL level(2) 3.3-V CMOS-level input with internal pulldown,5-V tolerant(3) 3.3-V CMOS-level input with internal pulldown.This pin informs the PC of serviceable control signals such as mute,volume up,or volume down,which have no connection with the internal DAC or ADC directly.See the Interface #3and End-Points sections.(4)TTL Schmitt trigger,5-V tolerant(5)Connect a decoupling capacitor to GND.(6)3.3-V CMOS-level input8Submit Documentation Feedback Copyright ©2007–2008,Texas Instruments IncorporatedPCM2900FUNCTIONAL BLOCK DIAGRAMSSPNDTEST1V LIN V RIN V COMV LOUT V ROUT XTIXTOD+D–SEL0SEL1HID0HID1HID2V BUSV CCCIV CCP1IV CCP2IV CCXIV DDIDGNDUDGNDAGNDXAGNDPAGNDCB0238-01TEST0PCM2900PCM2902SLES035E–MARCH 2007–REVISED MARCH 2008Copyright ©2007–2008,Texas Instruments Incorporated Submit Documentation Feedback 9PCM2902FUNCTIONAL BLOCK DIAGRAMSSPNDDIN V LIN V RIN V COMV LOUT V ROUT DOUT XTIXTOD+D–SEL0SEL1HID0HID1HID2V BUSV CCCIV CCP1IV CCP2IV CCXIV DDIDGNDUDGNDAGNDXAGNDPAGNDCB0239-01PCM2900PCM2902SLES035E–MARCH 2007–REVISED MARCH 200810Submit Documentation Feedback Copyright ©2007–2008,Texas Instruments IncorporatedPCM2900/2902DIAGRAM OF ANALOG FRONT-END(RIGHT CHANNEL)S0011-06TYPICAL CHARACTERISTICSADC7580859095−50−250255075100T A − Free-Air Temperature − °CD y n a m i c R a n g e a n d S N R − d BG0020.0030.0040.0050.0060.0070.0080.0090.010−50−250255075100T A − Free-Air Temperature − °CT H D +N − T o t a l H a r m o n i c D i st o r t i o n + N o i s e − %G0010.0030.0040.0050.0060.0070.0080.0090.0104.04.55.0 5.5V BUS − Supply Voltage − VT H D +N −T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %G00375808590954.04.55.0 5.5V BUS − Supply Voltage − VD y n a m i c R a n g e a n dS N R − d BG004SLES035E–MARCH 2007–REVISED MARCH 2008All specifications at T A =25°C,V BUS =5V,f S =44.1kHz,f in =1kHz,16-bit data,using REG 103xA-A,unless otherwise notedTOTAL HARMONIC DISTORTION +NOISE at –0.5dBDYNAMIC RANGE and SNRvsvsFREE-AIR TEMPERATUREFREE-AIR TEMPERATUREFigure 1.Figure 2.TOTAL HARMONIC DISTORTION +NOISE at –0.5dBDYNAMIC RANGE and SNRvsvsSUPPLY VOLTAGESUPPLY VOLTAGEFigure 3.Figure 4.75808590953035404550f S − Sampling Frequency − kHzD y n a m i c R a n g e a n d S N R − d BG006f S − Sampling Frequency − kHzG005DAC909192939495969798−50−250255075100T A − Free-Air Temperature − °CD y n a m i c R a n g e a n d S N R − d BG0080.0030.0040.0050.0060.0070.008−50−250255075100T A − Free-Air Temperature − °CT H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %G007TYPICAL CHARACTERISTICS (continued)All specifications at T A =25°C,V BUS =5V,f S =44.1kHz,f in =1kHz,16-bit data,using REG 103xA-A,unless otherwise notedTOTAL HARMONIC DISTORTION +NOISE at –0.5dBDYNAMIC RANGE AND SNRvsvsSAMPLING FREQUENCYFigure 5.Figure 6.TOTAL HARMONIC DISTORTION +NOISE at 0dBDYNAMIC RANGE AND SNRvsvsFREE-AIR TEMPERATUREFREE-AIR TEMPERATUREFigure 7.Figure 8.9091929394959697984.04.55.0 5.5V BUS − Supply Voltage − VD y n a m i c R a n g e a n d S N R − d BG0100.0030.0040.0050.0060.0070.0084.04.55.0 5.5V BUS − Supply Voltage − VT H D +N − T o t a lH a r m o n i c D i s t o r t i o n + N o i s e − %G0099091929394959697983035404550f S − Sampling Frequency − kHzD y n a m i c R a n g e a n d S N R − d BG0120.0030.0040.0050.0060.0070.0083035404550f S − Sampling Frequency − kHzT H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %G011SLES035E–MARCH 2007–REVISED MARCH 2008TYPICAL CHARACTERISTICS (continued)All specifications at T A =25°C,V BUS =5V,f S =44.1kHz,f in =1kHz,16-bit data,using REG 103xA-A,unless otherwise notedTOTAL HARMONIC DISTORTION +NOISE at 0dBDYNAMIC RANGE AND SNRvsvsSUPPLY VOLTAGESUPPLY VOLTAGEFigure 9.Figure 10.TOTAL HARMONIC DISTORTION +NOISE at 0dBDYNAMIC RANGE AND SNRvsvsSAMPLING FREQUENCYSAMPLING FREQUENCYFigure 11.Figure 12.SUPPLY CURRENT0.200.220.240.260.280.304.004.25 4.50 4.755.00 5.255.50V BUS − Supply Voltage − V203040506070G013I C C − O p e r a t i o n a l S u p p l y C u r r e n t − m AI C C − S u s p e n d S u p p l y C u r r e n t − m A2030405060703035404550f S − Sampling Frequency − kHz I C C − O p e r a t i o n a l Su p p l y C u r r e n t − m AG0140.100.150.200.250.300.350.40−40−20020406080100T A − Free-Air Temperature − °CI C C − S u s p e n d S u p p l y C u r r e n t − mAG015TYPICAL CHARACTERISTICS (continued)All specifications at T A =25°C,V BUS =5V,f S =44.1kHz,f in =1kHz,16-bit data,using REG 103xA-A,unless otherwise notedOPERATIONAL AND SUSPEND SUPPLY CURRENTvsSUPPLY VOLTAGEFigure 13.OPERATIONAL SUPPLY CURRENTSUSPEND SUPPLY CURRENTvsvsSAMPLING FREQUENCYFREE-AIR TEMPERATUREFigure 14.Figure 15.ADC DIGITAL DECIMATION FILTER FREQUENCY RESPONSEFrequency [y f S ]A m p l i t u d e − d BG016Frequency [y f S ]0.00.20.40.60.8 1.0A m p l i t u d e − dBG017Frequency [y f S ]−20−16−12−8−40.460.480.500.520.54A m p l i t u d e − d BG019Frequency [y f S ]0.00.10.20.30.40.5A m p l i t u d e − d BG018SLES035E–MARCH 2007–REVISED MARCH 2008TYPICAL CHARACTERISTICS (continued)All specifications at T A =25°C,V BUS =5V,f S =44.1kHz,f in =1kHz,16-bit data,unless otherwise notedOVERALL CHARACTERISTICSSTOP-BAND ATTENUATIONFigure 16.Figure 17.PASS-BAND RIPPLETRANSITION-BAND RESPONSEFigure 18.Figure 19.ADC DIGITAL HIGH-PASS FILTER FREQUENCY RESPONSEFrequency [y f S /1000]0.00.10.20.30.4A m p l i t u d e − dBG020Frequency [y f S /1000]−1.0−0.8−0.6−0.4−0.201234A m p l i t u d e − d BG021ADC ANALOG ANTIALIASING FILTER FREQUENCY RESPONSEf − Frequency − kHzA m p l i t u d e − d B0.011101000.1G023f − Frequency − kHzA m p l i t u d e − d B11001k 10k10G022TYPICAL CHARACTERISTICS (continued)All specifications at T A =25°C,V BUS =5V,f S =44.1kHz,f in =1kHz,16-bit data,unless otherwise notedSTOP-BAND CHARACTERISTICSPASS-BAND CHARACTERISTICSFigure 20.Figure 21.STOP-BAND CHARACTERISTICSPASS-BAND CHARACTERISTICSFigure 22.Figure 23.DAC DIGITAL INTERPOLATION FILTER FREQUENCY RESPONSEFrequency [y f S ]A m p l i t u d e − dBG024Frequency [y f S ]−0.8−0.6−0.4−0.20.20.00.10.20.30.40.5A m p l i t u d e − d BG025Frequency [y f S ]−20−18−16−14−12−10−8−6−4−200.460.470.480.490.500.510.520.530.54A m p l i t u d e − d BG026SLES035E–MARCH 2007–REVISED MARCH 2008TYPICAL CHARACTERISTICS (continued)All specifications at T A =25°C,V BUS =5V,f S =44.1kHz,f in =1kHz,16-bit data,unless otherwise notedSTOP-BAND ATTENUATIONPASS-BAND RIPPLEFigure 24.Figure 25.TRANSITION-BAND RESPONSEFigure 26.DAC ANALOG FIR FILTER FREQUENCY RESPONSE−50−40−30−20−100Frequency [y f S ]A m p l i t u d e − dBG027−0.8−0.6−0.4−0.20.20.00.10.20.30.40.5Frequency [y f S ]A m p l i t u d e − d BG028DAC ANALOG LOW-PASS FILTER FREQUENCY RESPONSEf − Frequency − kHzA m p l i t u d e − d B0.011101000.1G030f − Frequency − kHzA m p l i t u d e − d B11001k 10k10G029TYPICAL CHARACTERISTICS (continued)All specifications at T A =25°C,V BUS =5V,f S =44.1kHz,f in =1kHz,16-bit data,unless otherwise notedSTOP-BAND CHARACTERISTICSPASS-BAND CHARACTERISTICSFigure 27.Figure 28.STOP-BAND CHARACTERISTICSPASS-BAND CHARACTERISTICSFigure 29.Figure 30.SLES035E–MARCH2007–REVISED MARCH2008USB INTERFACEControl data and audio data are transferred to the PCM2900/2902via D+(pin1)and D–(pin2).All data to/from the PCM2900/2902is transferred at full speed.The device descriptor contains the information described in Table1.The device descriptor can be modified on request;contact a Texas Instruments representative for details.Table1.Device DescriptionUSB revision 1.1compliantDevice class0x00(device-defined interface level)Device subclass0x00(not specified)Device protocol0x00(not specified)Max packet size for end-point08bytesVendor ID0x08BB(default value,can be modified)Product ID0x2900/0x2902(default value,can be modified)Device release number 1.0(0x0100)Number of configurations1Vendor strings String#1(see Table3)Product strings String#2(see Table3)Serial number Not supportedThe configuration descriptor contains the information described in Table2.The configuration descriptor can be modified on request;contact a Texas Instruments representative for details.Table2.Configuration DescriptorInterface Four interfaces0x80(Bus powered,no remotePower attributewakeup)0x32(100mA.Default value,can beMax powermodified)The string descriptor contains the information described in Table3.The string descriptor can be modified on request;contact a Texas Instruments representative for details.Table3.String Descriptor#00x0409#1Burr-Brown from TI(default value,can be modified)#2USB audio codec(default value,can be modified)DEVICE CONFIGURATIONFigure31illustrates the USB audio function topology.The PCM2900/2902has four interfaces.Each interface is constructed by alternative settings.M0024-03Interface #0Figure B Audio Function TopologyInterface #0is defined as the control interface.Alternative setting #0is the only possible setting for interface #0.Alternative setting #0describes the standard audio control interface.A terminal constructs the audio control interface.The PCM2900/2902has five terminals as follows:•Input terminal (IT #1)for isochronous-out stream •Output terminal (OT #2)for audio analog output •Feature unit (FU #3)for DAC digital attenuator •Input terminal (IT #4)for audio analog input•Output terminal (OT #5)for isochronous-in streamInput terminal #1is defined as USB stream (terminal type 0x0101).Input terminal #1can accept 2-channel audio streams constructed by left and right channels.Output terminal #2is defined as a speaker (terminal type 0x0301).Input terminal #4is defined as a microphone (terminal type 0x0201).Output terminal #5is defined as a USB stream (terminal type 0x0101).Output terminal #5can generate 2-channel audio streams constructed by left and right channels.Feature unit #3supports the following sound control features.•Volume control •Mute controlThe built-in digital volume controller can be manipulated by an audio class specific request from 0dB to -64dBInterface #1Interface #2Interface #3SLES035E–MARCH 2007–REVISED MARCH 2008in 1-dB steps.Changes are made by incrementing or decrementing by one step (1dB)for every 1/f S time interval until the volume level has reached the requested value.Each channel can be set for different values.The master volume control is not supported.A request to the master volume is stalled and ignored.The built-in digital mute controller can be manipulated by audio class specific request.A master mute control request is acceptable.A request to an individual channel is stalled and ignored.Interface #1is the audio streaming data-out interface.Interface #1has the following seven alternative settings.Alternative setting #0is the zero bandwidth setting.All other alternative settings are operational settings.ALTERNATIVE TRANSFER SAMPLING RATEDATA FORMATSETTINGMODE(kHz)00Zero Bandwidth0116bit Stereo 2s complement (PCM)Adaptive 32,44.1,480216bit Mono 2s complement (PCM)Adaptive 32,44.1,48038bit Stereo 2s complement (PCM)Adaptive 32,44.1,48048bit Mono 2s complement (PCM)Adaptive 32,44.1,48058bit Stereo Offset binary (PCM8)Adaptive 32,44.1,48068bitMonoOffset binary (PCM8)Adaptive32,44.1,48Interface #2is the audio streaming data-in the interface.Interface #2has the following 19alternative settings.Alternative setting #0is the zero bandwidth setting.All other alternative settings are operational settings.ALTERNATIVE TRANSFER SAMPLING RATEDATA FORMATSETTINGMODE(kHz)00Zero Bandwidth0116bit Stereo 2s complement (PCM)Asynchronous 480216bit Mono 2s complement (PCM)Asynchronous 480316bit Stereo 2s complement (PCM)Asynchronous 44.10416bit Mono 2s complement (PCM)Asynchronous 44.10516bit Stereo 2s complement (PCM)Asynchronous 320616bit Mono 2s complement (PCM)Asynchronous 320716bit Stereo 2s complement (PCM)Asynchronous 22.050816bit Mono 2s complement (PCM)Asynchronous 22.050916bit Stereo 2s complement (PCM)Asynchronous 160A 16bit Mono 2s complement (PCM)Asynchronous 160B 8bit Stereo 2s complement (PCM)Asynchronous 160C 8bit Mono 2s complement (PCM)Asynchronous 160D 8bit Stereo 2s complement (PCM)Asynchronous 80E 8bit Mono 2s complement (PCM)Asynchronous 80F 16bit Stereo 2s complement (PCM)Synchronous 11.0251016bit Mono 2s complement (PCM)Synchronous 11.025118bit Stereo 2s complement (PCM)Synchronous 11.025128bitMono2s complement (PCM)Synchronous11.025Interface #3is the interrupt data-in interface.Alternative setting #0is the only possible setting for interface #3.Interface #3constructs the HID consumer control device and reports the following three key statuses.•Mute (0xE209)•Volume up (0xE909)•Volume down (0xEA09)。

在屏显示芯片MB90092的原理及应用

收稿日期：０７０ — ９２０－８２
２内部结构及工作原理
ＭＢ０９含有ｌ个内部模块，其内部结构模９０２２块框图如图１示。其中串行输入控制模块用于所
３电手元器件焘用２０．Ｗ＇ｅｄｃＯ０８Ｗ．￣ｎ３Ｗｃ
人ＭＢ０９。９０２
◇ 芯片内建上电复位电路，因此，使用时须
先清除上电复位，芯片才能工作，这样可避免出
ＭＢ０９的主要性能特点如下：９０２
现意想不到的结果。 ◇ 芯片封装采用８引脚的ＱＰ０Ｆ封装形式。体积很小。
维普资讯
第２８第３１卷年月０期ｏ３ｏ
姆霹缔厕
Ｖ１ｏｏ１Ｎ．．３０
Ｍａ．２ｏｒｏ８
３控制命令功能
ＭＢ０９共有１条控制命令，其中命令１９ｏ２４和命令２又分为三种。下面是命令功能介绍：命令０ＲＭ地址控制。ＭＢ０９的字符显：ＶＡ９０２示存储器（ＲＭ）包括主屏字符控制ＲＭ、子ＶＡＡ
屏行控制ＲＭ和主屏行控制ＲＭ。用于控制ＡＡ
ＲＭ三种不同的功能并使命令１Ａ和命令２有三种各不同的格式，命令０于选择ＶＡ用ＲＭ的地址；命令１１ — ：主屏字符控制１：命令２１ — ：主屏字符控制２。命令１１ — 用 — 和２１于对主屏字符控制ＲＭ进行写入，它们可为主屏Ａ

基于MB90092的视频字符叠加系统的设计

ｃｐＢ９０９２．ｃｈｉＭ０Ｂｅａｕｓｏｉｅｆｔｓａｄｖａｎｔｇｓｃａｓｇｏａｄｔａｅｓｕｈｏｄａｐａｂｉｔｙ，ｌｃｎｓｕｔｉｎ，ｌｃｔｌｉｏｗｏｍｐｏｏｗｏｓａｎＳｏｄＯｎ，ｉｉｓｔｗｉｄｅｌａｐｙｐｌｌｄｎｅｉａｃｕａｌｒｔｉｅｅａｔｐａｃｃ —ｔｃｈｉｎｇ．
ＭＹｇＣｈｇａＯｎｅｎＧｕｎｇａｗｅｉＦｅＸｉｇａｎｇａｏｎｇ
（西安工业大学电子信息工程学院，陕西西安
７０３）１０２
（ｃｏｌｏｌｃｒｎｃＩｆｒａｉｎＥｇｎｅｉｇｉｎＴｃｎｌｇｃｌＵｉｅｓｔ，Ｓａｘｉｎ７０３）ＳｈｏｆＥｅｔｏｉｎｏｍｔｏｎｉｅｒｎ，Ｘ ’ａｅｈｏｏｉａｎｖｒｉｙｈｎｉＸ ’ａ１０２
图一是该视频叠加系统的硬件结构框图。
式来自何处，以及对应图像的其他相关信息，如当前的站址
号、ｕＩ、实时数据及状态信息显示到屏幕上。针对目前大－＇，Ｈｊ－］
部分显示系统均采用分立元器件，结构复杂，不易于维护等
２２字符叠加模块Ｍ９０２．Ｂ０９［Ｍ９０２Ｂ０９是通用的字符叠加集成电路，具有视频信号发
生器、显示存储器（ＲＭ和字形存储器接口，只需少量外部ＶＡ）
缺点，本文提出采用富士通公司的字符叠加芯片Ｍ９０２，Ｂ０９
不仅软件编程简单，全中文显示，而且还可以设置子菜单（用副屏显示）把更多的信息实时叠加显示在屏幕上。

Carlin Combustion 90524A Triple Limit Control说明书

T ech support 800-989-2275FunctionsCarlin’s 90524A can be operated as either a triple limit control or a cold-start• control, determined by the setting of the LOW LIMIT adjustment.Triple limit operation (LOW LIMIT on): Provides adjustable high limit set-• ting and maintains an adjustable minimum temperature in the boiler (low limit setting) while in stand-by (no space heating call); used for tankless heater applications. (See Figure 3 , page 4.)Cold-start operation (LOW LIMIT off): Provides adjustable high limit set-• ting and low temperature protection (delays circulator start until the boiler is heated above the fixed minimum temperature setpoint); used to prevent condensation in the boiler on cold start. (See Figure 4 , page 4.)The 90524A provides input from zone controllers or relays (ZR contact) and• output to enable circulators (C1 contact) or zone controllers (ZC contact). The gas valve/burner output is on the B1 terminal. Call for heat input is on the T-T terminals.SpecificationsCarlin’s Model 90524A microprocessor-operated temperature controls are• described below.Refer to separate product listing sheets for pre-defined models, or request• a control to meet your specifications, within the available ranges listedbelow.InstructionsFrontRear(size reduced)Easy-wire terminal strip Microprocessor-operated(Processor coordinates operation and diagnostic)Easy remote sense(Electronic sensor, wired to control)Self-checking program(Control locks out on diagnostic failure)Diagnostic/status LED’s(LED’s indicate power, call for heat, and lockout)SMC technology on burner relay(lockout when welded contact sensed)Carlin part number MN90524AM Rev. 01/19/09– 2 –adjusts Low Limit differential when in triple limit operation) — when in OFF position, default high and low limit differentials are used8 Hidden reset button9Low limit adjustment (set to OFF for cold-start operation)10 High limit setpoint adjustment4109567RearModel 90524A Triple limit or cold-start control — InstructionsCarlin part number MN90524AM Rev. 01/19/09– 3 –Where appliance instructions differ from this manual, follow the appliance instructions.Model 90524A diagnostic LED’s90524A controls have three LED’s, as explained below. See following pages for operating sequence and LED behavior.ConfigurationsControl kits — 90524A controls mount to a standard 4x4 J-box, supplied• with the control. Mount the box directly to a well (new or existing) with hardware supplied, or panel mount. See Figure 2 for dimensions.Well kits — Wells for 90524A sensors are available in the sizes shown• in Figure 2. Well kits include sensor mounting hardware designed to hold sensor securely in position.Sensors — Sensors are available in single configurations.• Mounting the 90524AFigure 2 DefinitionsHigh limit Shut-off temperature during space heating (call for heat atT-T or ZR).Setpoint is adjustable at lower front center of control.• Differential is fixed when in triple limit operation (LOW • LIMIT on).Differential is adjustable on back of control when in cold • start operation (LOW LIMIT set to OFF).Low limit Temperature maintained during stand-by (no call for heatat T-T or ZR) when in triple limit operation (LOW LIMIT on).The setpoint for the low limit (minimum temperature in • the boiler during standby) is adjustable with the lower left adjustment.The differential for low limit is adjustable with the adjust-• ment on the back of the control.The circulator output at C1 is activated only when • the temperature in the boiler is above the low limit setting.Low temp Boiler condensation protection setting when in cold-startoperation (LOW LIMIT set to OFF).This setting is fixed.• The differential is fixed.• The circulator outputs are disabled until the boiler tem-• perature rises above the low temp setting.Model 90524A Triple limit or cold-start control — InstructionsCarlin part number MN90524AM Rev. 01/19/09– 4 –Where appliance instructions differ from this manual, follow the appliance instructions.Equivalent circuit diagram — Figure 3 Triple limit operation(LOW LIMIT on)Triple limit operation — Setup & adjustmentSet low limit setpoint on front of control (item 9, page 2). Set low limit differential• at the adjustment potentiometer on the back of the control (item 7, page 2). The differential range is shown on the control label. Rotate the potentiometer fully counterclockwise for minimum setting, fully clockwise for maximum setting.Set high limit setpoint on front of control (item 10, page 2). High limit differential• is fixed.Triple limit sequence of operationBurner turns ON when sensor temp is below the high limit (minus high limit differential) — AND — sensor temp is below low limit setting (minus low limit differential) OR there is a call for heat atT-T or ZR.Burner turns OFF when sensor temp is above high limit setting — OR — when sensor temp is above the low limit AND there is nocall for heat at T-T or ZR.Circulator turns ON when sensor temp is at or above low limit —AND — there is a call for heat at T-T.Circulator turns OFF when the sensor temp goes below the low limit setting (minus the low limit differential) — OR — there is nocall for heat at T-T.[ Zone feed (terminal ZC) turns ON when sensor temp is at or abovethe low limit.[Zone feed (terminal ZC) turn OFF when sensor temp goes below the low limit setting (minus the low limit differential).Equivalent circuit diagram — Figure 4 Cold-start operation(LOW LIMIT set to OFF)Cold-start operation — Setup & adjustmentSet low limit adjust on front of control to OFF (item 9, page 2). This activates the• low temp setting. Low temp and its differential are fixed settings.Set high limit setpoint on front of control (item 10, page 2). Set high limit differential• at the adjustment potentiometer on back of the control (item 7, page 2).Cold start sequence of operationBurner turns ON when sensor temp is below the high limit (minus high limit differential) — AND — there is a call for heat at T-T orZR.Burner turns OFF when sensor temp is above high limit setting —OR — there is no call for heat at T-T or ZR.Circulator turns ON when sensor temp is at or above low temp —AND — there is a call for heat at T-T.Circulator turns OFF when the sensor temp goes below the low temp setting (minus the low temp differential) — OR — there isno call for heat at T-T.[ Zone feed (terminal ZC) turns ON when sensor temp is at or abovethe low temp.[Zone feed (terminal ZC) turn OFF when sensor temp goes below the low temp setting (minus the low temp differential).Model 90524A Triple limit or cold-start control — InstructionsCarlin part number MN90524AM Rev. 01/19/09– 5 –Where appliance instructions differ from this manual, follow the appliance instructions.Typical — Figure 5 Triple limit operation (LOW LIMIT ON) — Multi-zone controller, zoning with zone valvesModel 90524A Triple limit or cold-start control — InstructionsCarlin part number MN90524AM Rev. 01/19/09– 6 –Where appliance instructions differ from this manual, follow the appliance instructions.Typical — Figure 6 Triple limit operation (LOW LIMIT ON) — Multi-zone controller, zoning with circulatorsModel 90524A Triple limit or cold-start control — InstructionsCarlin part number MN90524AM Rev. 01/19/09– 7 –Where appliance instructions differ from this manual, follow the appliance instructions.Typical — Figure 7 Cold-start operation (LOW LIMIT OFF) — Delays circulator until boiler has heated above LOW TEMP settingModel 90524A Microprocessor Temperature Controls — Data sheet©Copyright 2008 — Carlin Combustion Technology, Inc.Carlin part number MN90524AM Rev. 01/19/09。

900MHz系统控制逻辑 IF板维修手册说明书

MAINTENANCE MANUALORION™900 MHz SYSTEM CONTROL LOGIC/IF BOARDCMC-682/CMF-138NDESCRIPTIONThe System Control Logic/IF circuit board combines func-tions of receive circuit 1st IF, 2nd IF, audio detection, audio signal processing and system control on one circuit board. As an option, an additional circuit board can be plugged into this board to provide AEGIS™ (digital encryption system). Pro-gramming and personality information is stored in FLASH and EEPROM memory on the logic/IF board. The audio speaker amplifier is also part of the same board.Electrical interfaces are achieved between this board and the Control Unit (LCC), synthesizer, RF PA (APC) and the O ption and R emote C ontrol C onnector (ORCC) on the rear of the assembled radio.All radio control signals originate or terminate on the con-trol logic/IF board. Two microcomputers share the processing load. Control signals are connected through a high speed digi-tal link with the control unit, either through the LCC or ORCC connectors, making possible either front or remote control for the radio. The same link also makes possible dual radio or dual control head configuration. An RS-232 compat-ible digital link is available at the ORCC interface, to facilitate programming or Radio Data Interface to Mobile Digital termi-nals.This circuit board also generates Type 99, Channel Guard, GE-Star and DTMF signals if so programmed.The System Control Logic/IF board consists of the follow-ing control logic, IF and audio circuits (see figures 1 & 2).Printed in U.S.A. LBI-39057Copyright© May 1994, Ericsson GE Mobile Communications Inc.Figure 1 - Logic Section Block Diagram Figure 2 - IF Section Block DiagramLBI-390571SYSTEM CONTROL LOGIC (CMC-682)•CMOS Microprocessor (IC701, IC702)•Custom CMOS ASIC Chip (IC703)•Address Decoder (IC704)•RS-485 (IC705)•RS-232 (IC706)•Flash EEPROM (IC707)•EEPROM (IC708)•CMOS SRAM (IC709)•CMOS Inverters (IC711)•Silicon Serial Number (IC712)•TTL Inverters (IC713)IF (CMF-138)•Custom CMOS ASP Chip (IC601)•Operational Amplifier (IC602, IC603)•Audio Amplifier (IC604)• 5 V olt Regulator (IC606, IC607)•9 V olt Regulator (IC605, IC608, IC609)•Reset Circuit (IC610)•Bilateral Switch (IC611, IC612)CIRCUIT ANALYSISLOGIC SECTION (CMC-682) MicrocomputerThe main microcomputer circuit in the ORION radio con-sist of microprocessor IC701, EEPROM IC708, Flash EEPROM IC707, RAM IC709 and custom ASIC IC703. This circuitry runs at a 9.8304 MHz rate determined by crystal X701 and controls the radio through a second microprocessor IC702. This second microprocessor runs at a 4.9152 MHz rate. The 4.9152 MHz rate is determined by ASIC IC703.•Controlling the ASIC, FLASH EEPROM and RAM•Loading data to the frequency synthesizer•Fetching and processing the PTT, monitor, channel, selection and volume control•Controlling the audio circuit (processor)•Decoding the squelch•Encoding/Decoding the Channel Guard and DigitalChannel Guard•Controlling the loading interface for the radio data(channel number and signaling)FLASH EEPROM (IC707)This memory contains the software to control the micro-processor. This Flash EEPROM has a storage capacity of 256kx 8 bits.CMOS SRAM (IC709)This SCRATCH RAM has a storage capacity of 32k x 8bits. The memory is available for variables, buffers, etc.EEPROM (IC708)This EEPROM has a storage capacity of 8k x 8 bits. Thememory contains the user configurable parameters that must bemaintained through a power cycle. This personality controlsvarious functions of the radio. The personality data is enteredfrom outside the radio through the ORCC connector to the mi-croprocessor and then to the EEPROM. The data mainly con-sists of the following:•Channel Frequency Data•CG/DCG Data•Tx Power, Tx Modulation Data•Squelch Data•Display Data, etc.APPLICATION OF SPECIFIC INTEGRATEDCIRCUITSASIC (IC703)The ASIC is basically a chip that integrates many miscella-neous functions. The chip provides functions as follows:•MODEM•Watch Dog Timer•Clock Control•Interrupt Control•Address Decode etc.Voltage Regulators (IC606, IC607) (IC605,IC608, IC609)V oltage regulators IC606 and IC607 each generate a 5Vdc for the Control Board. V oltage regulators IC605, IC608and IC609 each generate a 9 Vdc for the Control Board andV oice Guard Adapter Module.Audio Amplifier (IC604)The audio amplifier is located between the audio proces-sor and the speaker. Amplifier IC604 amplifies the outputsignal of the ASP (IC601) to the level adequate for drivingthe speaker.Audio Signal Processor (ASP ) (IC601)The audio processor consists of a one-chip IC accommo-dating almost all of the audio functions. The audio functionsare under control of the microcomputer in compliance withthe function of the radio unit. The functions of the audioprocessor are as follows:•Rx Audio Processor with Tone Reject Filter,De-emphasis and Programmable Attenuator.•Data Limiting•CG/DCG filtering and limiting•Noise Squelch filtering and detecting•8 bits D/A Converter with sample and hold•Tx Audio Processor with microphone amplifier,pre-emphasis, deviation limiter, summingamplifier,post limiter filter and programmableattenuator•Data signal filtering•Two 6 bits programmable divider for clock and alerttoneAll of these functions are made up of switched capaci-tor filters, amplifiers and timing logic. The timing forthis logic is derive from the 4.9152 MHz clock gener-ator (ASIC).RS-485 (IC705)This is a high speed differential TRI-STATE bus/linetransceiver designed to meet the requirements of EIA stand-ard RS-485 specification. The IC705 is located between theRadio Unit and the Control Unit.RS-232 (IC706This IC consists of line drivers/receivers designed tomeet the requirements of EIA standard RS -232 specifica-tions. The IC706 is located between the radio unit and theORCC to drive external data terminal devices.Reset Circuit (IC610)This is an active low reset IC which includes a delay timegenerating circuit. Delay time can be set up by externally us-ing a capacitor and a resistor. The function of this IC is to ac-curately reset the system after detecting voltage at the timeof switching power on and instantaneous power off.Option and Remote Control Connector(ORCC)The ORCC is located on the rear of the radio and is usedfor options and accessories when Control Unit and RadioUnit are directly attached and for remote control in all otherconfigurations. The ORCC allows various kinds of externalequipment connections to be made. External equipment con-necting signals are as follows:LBI-39057 2IF SECTION (CMF-138)1st IFThe 82.2 MHz 1st IF output signal is coupled from the out-put of the first mixer circuit, located on the Synthesizer/Re-ceiver/IF board, through 30-pin connector P501-1 and capacitor C501 to the source input of buffer amplifier J unction F ield E ffect T ransistors (JFET) TR501 and TR502. This input can be monitored at test point TP1. The output of TR501 and TR502 is coupled through inductor L502 to 4-pole crystal band-pass filter FL501. The highly-selective crystal filters FL501-1 and FL502-2 provide the first part of receiver IF se-lectivity. The output of the filters is coupled through the imped-ance matching network consisting of inductor L502 and capacitors C504 and C505 to the base of 1st IF amplifier tran-sistor TR503. The crystal filter output of FL501 is applied to the base of 1st IF amplifier transistor TR503. This amplified signal is taken from the collector of TR503 through an imped-ance matching network consisting inductor L505, capacitor C506 and resistor R507 that matches the amplifier output to the input of 4-pole crystal filters FL502-1 and FL502-2 which provides the second part of receiver IF selectivity. The output of the crystal filters is coupled through an impedance-matching network consisting of inductor L507, capacitor C508, resistor R508 and coupling capacitor C509 to the base of 2nd IF ampli-fier transistor TR505.2nd MixerThe 82.2 MHz IF input is applied to transistor TR505 and mixed with a 82.655 MHz frequency supplied by a crystal os-cillator circuit consisting of X501 and oscillator transistor TR504. Variable inductor L521 sets the frequency of the oscil-lator circuit. This signal can be monitored at test point TP5.2nd IF And DetectorThe output of the 2nd mixer is coupled to the input of 4-pole ceramic filter FL503 which provides 455 kHz 2nd IF se-lectivity. The 455 kHz IF output of ceramic filter FL503 iscoupled to Pin 3 of Limiter/FM Detector IC501. The IF signalis amplified internal to IC501 then applied to 4-pole ceramicfilter FL504 which provides additional 455 kHz IF selectivity(Refer to IC DATA for IC501). The output of the 455 kHz filteris applied to IC501, Pin 7. The 2nd IF signal is amplified andlimited internal to IC501. Inductor L523 shifts the IF signal by90° and applies it to the internal FM detector. The FM detectorcompares the shifted IF signal to the internal IF signal to re-cover the audio modulation. The audio output of the opera-tional amplifier internal to IC501 is applied the input of bufferamplifier IC502-2. The AUDIO output of IC502-2 is applied tothe System Control Logic circuit. This signal can be monitoredat test point TP4. The output on Pin 12 of IC501 is applied tothe input of amplifier buffer IC502-1. The output of IC502-1provides a Receiver Signal Strength Indicator (RSSI) signalalso sent to the System Control Logic circuit. This signal canbe monitored at test point TP3.9 V olt RegulatorThe 9-volt regulator circuit powers the IF circuits of CMF-138 and consists of regulator IC503 and filter capacitors C570,C571 C572 and C573. An input voltage of +13.8 Vdc is ap-plied to the input of IC503. This input is monitored at testpoint TP2.IC DATALINEAR, IF AMPLIFIER/DETECTOR IC501LINEAR, DUAL OPERATIONAL AMPLIFIER IC502LINEAR, POSITIVE VOLTAGE REGULATOR IC503LBI-390573IC DATAAUDIO SIGNAL PROCESSOR IC601LINEAR AUDIO AMPLIFIER IC602, IC603AUDIO FREQUENCY POWER AMPLIFIER IC604LINEAR: POSITIVE VOLTAGE REGULATOR IC605, IC609LINEAR: POSITIVE VOLTAGE REGULATOR IC606LINEAR: POSITIVE VOLTAGE REGULATOR IC607LBI-390574IC DATARESET CIRCUIT IC610BILATERAL SWITCH IC611, IC612CENTRAL PROCESSING UNIT IC701CENTRAL PROCESSING UNIT U702ASIC IC703LINEAR: POSITIVE VOLTAGE REGULATOR IC608LBI-390575IC DATARS-485 DRIVER/RECEIVER IC706RS-232 DRIVER/RECEIVER IC706FLASH MEMORY IC707EEPROM IC708RAM IC709PARTS LISTIC DATASILICON SERIAL NUMBER IC712INVERTER IC713INVERTER IC711SYSTEM CONTROL LOGIC/IF/AUDIO BOARDLOGIC SECTIONCMC-682SYMBOLPART NUMBER DESCRIPTIONNOTE: Parts listed are for reference only. Refer to Service Section for serviceable parts.------------ CAP ACITORS ---------------C601 Ceramic: 0.01 µF ±10% 50 VDC, tempcoef ±15%.C602Ceramic: 1 µF +80%/-20% 16 VDCW,temp coef +22%/-82%.C603Ceramic: 220 pF ±5% 50 VDCW, temp coef 0±30 PPM/°C.C604 Ceramic: 0.1 µF +80%/-20% 25 VDCW.C605 Ceramic: 0.01 µF ±10% 50 VDC, tempcoef ±15%.C606C607thru C609Ceramic: 0.1 µF +80%/-20% 25 VDCW,temp coef +22%/-82%.C610 T antalum: 1 µF ±20% 16 VDCW.C611Ceramic: 0.1 µF +80%/-20% 25 VDCW,temp coef +22%/-82%.C612 T antalum: 3.3 µF ±20% 16 VDCW.C613 T antalum: 1 µF ±20% 16 VDCW.C614T antalum: 0.33 µF ±20% 35 VDCW.C615Ceramic: 100 pF ±5% 50 VDCW, temp coef 0±30 PPM/°C.C616Ceramic: 1 µF +80%/-20% 16 VDCW,temp coef +22%/-82%.C617T antalum: 0.33 µF ±20% 35 VDCW.C618Ceramic: 0.1 µF +80%/-20% 25 VDCW,temp coef +22%/-82%.C621 and C622Ceramic: 0.1 µF +80%/-20% 25 VDCW,temp coef +22%/-82%.C623 T antalum: 22 µF ±20% 16 VDCW.C624Ceramic: 0.1 µF +80%/-20% 25 VDCW,temp coef +22%/-82%.C625T antalum: 1 µF ±20% 16 VDCW. C626Ceramic: 0.1 µF +80%/-20% 25 VDCW,temp coef +22%/-82%.C627 T antalum: 22 µF ±20% 16 VDCW.C628and C629Ceramic: 0.1 µF +80%/-20% 25 VDCW,temp coef +22%/-82%.C630 T antalum: 22 µF ±20% 16 VDCW.C631and C632Ceramic: 0.1 µF +80%/-20% 25 VDCW,temp coef +22%/-82%.C633 T antalum: 22 µF ±20% 16 VDCW.C634thru C637Ceramic: 0.1 µF +80%/-20% 25 VDCW,temp coef +22%/-82%.C638Ceramic: 220 pF ±5% 50 VDCW, temp coef 0±30 PPM/°C.SYMBOLPART NUMBERDESCRIPTIONC639 Electrolytic: 47 µF ±20% 25 VDCW.C640 Ceramic: 0.1 µF +80%/-20% 25 VDCW,temp coef +22%/-82%.C641 and C642Electrolytic: 22 µF ±20% 16 VDCW.C643 Ceramic: 0.1 µF +80%/-20% 25 VDCW,temp coef +22%/-82%.C644 Electrolytic: 10 µF ±20% 25 VDCW.C645 Ceramic: 1 µF +80%/-20% 25 VDCW,temp coef +22%/-82%.C646Ceramic: 1000 pF +80%/-20% 50VDCW temp coef +22%/-82%.C647 Ceramic: 0.1 µF +80%/-20% 25 VDCW,temp coef +22%/-82%.C649and C650Electrolytic: 22 µF ±20% 16 VDCW.C651and C652Ceramic: 0.47 µF +80%/-20% 25 VDCW temp coef +30%/-80%.C653and C654T antalum: 2.2 µF ±20% 16 VDCW.C655and C656Electrolytic: 10 µF ±20% 25 VDCW.C657and C658Ceramic: 0.047 µF +80%/-20% 50VDCW temp coef +22%/-82%.C659and C660T antalum: 1 µF ±20% 16 VDCW.C661thru C664Ceramic: 0.1 µF +80%/-20% 25 VDCW,temp coef +22%/-82%.C665and C666Ceramic: 0.1 µF ±10% 25 VDCW, temp coef ±15%.C667T antalum: 1 µF ±20% 16 VDCW.C670 Ceramic: 3300 pF ±10% 50 VDCW,temp coef ±15%.C701thru C706Ceramic: 0.1 µF +80%/-20% 25 VDCW,temp coef +22%/-82%.C707Ceramic: 47 pF ±5% 50 VDCW, temp coef 0±30 PPM/°C.C708and C709Ceramic: 12 pF 20.25 pF 50 VDCW,temp coef 0±30 PPM/°C.C710Ceramic: 47 pF ±5% 50 VDCW, temp coef 0±30 PPM/°C.C711 Ceramic: 0.1 µF +80%/-20% 25 VDCW,temp coef +22%/-82%.C712and C713Ceramic: 100 pF ±5% 50 VDCW, temp coef 0±30 PPM/°C.C714 Ceramic: 0.1 µF +80%/-20% 25 VDCW,temp coef +22%/-82%.C715thru C719T antalum: 1 µF ±20% 16 VDCW.C720thru C722Ceramic: 0.1 µF +80%/-20% 25 VDCW,temp coef +22%/-82%.C726and C727Ceramic: 0.1 µF +80%/-20% 25 VDCW,temp coef +22%/-82%.*COMPONENTS ADDED, DELETED OR CHANGED BY PRODUCTION CHANGESLBI-390577PARTS LISTSYMBOL PART NUMBERDESCRIPTIONIC708EEPROM: sim to HIT ACHI HN58C66FP .IC709 RAM: sim to SONY CXK58257AM.IC711Inverter: sim to MOTOROLA MC74HC04.IC712Silicon Serial Number: sim to DALLAS DS2400.IC713Inverter: sim to HIT ACHI HD74LS04FP .---------------------JACKS---------------------J701Connector: 18 pins.J702 and J703Connector: 24 pins.J704Connector: 4 pins.J706Connector: 10 pins. J707Connector: 13 pins.J708Connector: 5 pins.K601Relay: sim to T AKAMIZAWA JY9H-K.------------------RESISTORS-----------------R601 Metal film: 27k ohms ±5% 100 VDCW 1/16W.R602 Metal film: 56K ohms ±5% 100 VDCW 1/16W.R603 Metal film: 120k ohms ±5% 100 VDCW 1/16W.R604Metal film: 220K ohms ±5% 100 VDCW 1/16W.R605Metal film: 470K ohms ±5% 100 VDCW 1/16W.R606Metal film: 56K ohms ±5% 100 VDCW 1/16W.R607Metal film: 150K ohms ±5% 100 VDCW 1/16W.R608and R609 Metal film: 22k ohms ±5% 100 VDCW 1/16W.R610and R611Metal film: 10k ohms ±5% 100 VDCW 1/16W.R612and R613Metal film: 39k ohms ±5% 100 VDCW 1/16W.R614 Metal film: 4.7K ohms ±5% 100 VDCW 1/16W.R615 Metal film: 100K ohms ±5% 100 VDCW 1/16W.R616 Metal film: 470K ohms ±5% 100 VDCW 1/16W.R617 Metal film: 3.3 M ±10% 200 VDCW 1/10W.R618and R619Metal film: 100k ohms ±5% 100 VDCW 1/16W.R620 Metal film: 47K ohms ±5% 100 VDCW 1/16W.R621Metal film: 22k ohms ±5% 100 VDCW 1/16W.R622 thru R624 Metal film: 56K ohms ±5% 100 VDCW 1/16W.R625Metal film: 10k ohms ±5% 100 VDCW 1/16W.SYMBOL PART NUMBERDESCRIPTIONC728thru C743Ceramic: 100 pF ±5% 50 VDCW, temp coef 0±30 PPM/°C.C744and C745Ceramic: 0.1 µF +80%/-20% 25 VDCW,temp coef +22%/-82%.C746Ceramic: 1000 pF ±10% 50 VDCW, temp coef ±15%.-----------------------DIODES----------------------CD601and CD602POWER Supply rectification diode: sim to SANKEN SFPM-64V .CD603Zener 900mW 22 V: sim to Hitachi HZF22. CD604 Silicon fast recovery (2 diodes in series):sim to TOSHIBA ISS300.CD701thru CD705Silicon fast recovery (2 diodes in series):sim to TOSHIBA ISS302.CD709and CD710Silicon fast recovery (2 diodes in series):sim to TOSHIBA ISS302.CD711Silicon fast recovery (2 diodes in series):sim to TOSHIBA ISS300.CD712 Zener 900mW 22 V: sim to Hitachi HZF12.CD713and CD714 Silicon fast recovery (2 diodes in series):sim to TOSHIBA ISS302.CX701and CX702EMI Filter.F601Fuse, 5A.-----INTEGRA TED CIRCUITS-----IC601 Audio Signal PROCESSOR.IC602and IC603Linear Audio Amplifier: sim to NJRC 3403.PC1230H2.IC604 AF Power Amplifier: sim to NEC PC2500H.IC605 Linear Positive Voltage Regulator: sim to NJRC NJM78L09UA.IC606 Linear: Positive Voltage Regulator; sim to MOTOROLA MC7805CT .IC607 Linear: Positive Voltage Regulator; sim to SANYO L78M05T .IC608 Linear: Positive Voltage Regulator; sim to SANYO L78M09T .IC609 Linear Positive Voltage Regulator: sim to NJRC NJM78L09UA.IC610 Reset Circuit: sim to MITSUMI PST575.IC611and IC612Bilateral Switch: sim to TOSHIBA TC4S66F .IC701CPU: sim to HIT ACHI HD6475328F .IC702 CPU: sim to HIT ACHI HD6473308RF .IC703 ASIC: sim to TOSHIBA TC24SC090AF . IC704 DECODER: Sim to MOTOROLA MC74HC139.IC705 RS485 Driver/Receiver: sim to NS AS75176.IC706 RS232 Driver/Receiver: sim to MAXIM MA232EWE.IC707FLASH MEMORY: sim to INTEL N28F020.SYMBOL PART NUMBERDESCRIPTIONR627Metal film: 150k ohms ±5% 100 VDCW 1/16W.R628and R629Metal film: 100K ohms ±5% 100 VDCW 1/16W.R630 Metal film: 3.3M ohms ±10% 200 VDCW 1/10W.R631Metal film: 47k ohms ±5% 100 VDCW 1/16W.R632Metal film: 100K ohms ±5% 100 VDCW 1/16W.R633 Metal film: 22k ohms ±5% 100 VDCW 1/16W.R634Metal film: 1M ohms ±5% 100 VDCW 1/16W.R635Metal film: 6.8k ohms ±5% 100 VDCW 1/16W.R636thru R639Metal film: 10k ohms ±5% 100 VDCW 1/16W.R640 Metal film: 3.3k ohms ±5% 100 VDCW 1/16W.R641Metal film: 10k ohms ±5% 100 VDCW 1/16W.R642 Metal film: 22k ohms ±5% 100 VDCW 1/16W.R643and R644Metal film: 22 ohms ±5% 100 VDCW 1/16W.R645and R646Metal film: 1.0k ohms ±5% 100 VDCW 1/16W.R647 Metal film: 8.2k ohms ±5% 100 VDCW 1/16W.R648 Metal film: 10k ohms ±5% 100 VDCW 1/16W.R649 Metal film: 1M ohms ±5% 100 VDCW 1/16W.R650and R651Metal film: 680 ohms ±5% 100 VDCW 1/16W.R652 Metal film: 100K ohms ±5% 100 VDCW 1/16W.R653 Metal film: 15K ohms ±5% 100 VDCW 1/16W.R654 Metal film: 15K ohms ±5% 100 VDCW 1/16W.R655Metal film: 56k ohms ±5% 100 VDCW 1/16W.R656Metal film: 1.0k ohms ±5% 100 VDCW 1/16W.R657Carbon film: 560 ohms ±5% 200 VDCW 1/4W.R701thru R703Metal film: 100 ohms ±5% 100 VDCW 1/16W.R704 Metal film: 68k ohms ±5% 100 VDCW 1/16W.R705Metal film: 100 ohms ±5% 100 VDCW 1/16W.R706and R707Metal film: 1.0k ohms ±5% 100 VDCW 1/16W.R709and R710Metal film: 100 ohms ±5% 100 VDCW 1/16W.R718 Metal film: 4.7k ohms ±5% 100 VDCW 1/16W.SYMBOL PART NUMBERDESCRIPTIONR719Metal film: 100k ohms ±5% 100 VDCW 1/16W.R720 Metal film: 10k ohms ±5% 100 VDCW 1/16W.R721Metal film: 47k ohms ±5% 100 VDCW 1/16W.R724and R725Metal film: 2.7K ohms ±5% 100 VDCW 1/16W.R726 Metal film: 1M ohms ±5% 100 VDCW 1/16W.R729and R730Metal film: 0 ohms.R732 Metal film: 0 ohms.R733 Metal film: 4.7K ohms ±5% 100 VDCW 1/16W.R734 Metal film: 1.0k ohms ±5% 100 VDCW 1/16W.R735 Metal film: 4.7K ohms ±5% 100 VDCW 1/16W.R736 Metal film: 6.8K ohms ±5% 100 VDCW 1/16W.R737thru R740Metal film: 10k ohms ±5% 100 VDCW 1/16W.R741 Metal film: 27k ohms ±5% 100 VDCW 1/16W.R742and R743Metal film: 4.7K ohms ±5% 100 VDCW 1/16W.R744and R745Metal film: 470 ohms ±5% 100 VDCW 1/10W.R747 Metal film: 0 ohms.R748Metal film: 10K ohms ±5% 100 VDCW 1/16W.R749 Metal film: 100K ohms ±5% 100 VDCW 1/16W.R750and R751Metal film: 22k ohms ±5% 100 VDCW 1/16W.R752and R753Metal film: 10k ohms ±5% 100 VDCW 1/16W.SW601Slide Switch.SW701Slide Switch.--------------TRANSISTORS---------------TR602T ransistor NPN: sim to SANYO 2SC3398.TR603T ransistor NPN: sim to NEC 2SD596 .TR701T ransistor NPN: sim to TOSHIBA RN2301.TR702thru TR712FET: sim to NEC 2SK1582.TR713and TR714T ransistor NPN: sim to TOSHIBA 2SC2859 .TR715and TR716T ransistor NPN: sim to NEC 2SC3736.------------------CRYST AL---------------------X701Crystal: 9.8304 MHz CP12A..LBI-390578PARTS LIST900 MHz SYSTEM CONTROL LOGIC/IF BOARDIF SECTIONCMF-138NSYMBOL PART NUMBER DESCRIPTION---------------CAP ACITORS----------------C501NOTE: Parts listedare for referenceonly. Refer toService Sectionfor serviceableparts.Ceramic: 1000 pF ±10% 50 VDCW temp coef ±15%.C502Ceramic: 5 pF ±0.25 pF 50 VDCW tempcoef 0±60 PPM.C503Ceramic: 3 pF ±0.25 pF 50 VDCW tempcoef 0±250 PPM.C504Ceramic: 7 pF ±0.5 pF 50 VDCW temp coef0±60 PPM.C505Ceramic: 6 pF ±0.5 pF 50 VDCW temp coef0±60 PPM.C506Ceramic: 5 pF ±0.25 pF 50 VDCW tempcoef 0±60 PPM.C507Ceramic: 3 pF ±0.25 pF 50 VDCW tempcoef 0±250 PPM.C508Ceramic: 5 pF ±0.25 pF 50 VDCW tempcoef 0±60 PPM.C509 thru C512Ceramic: 1000 pF ±10% 50 VDCW temp coef ±15%.C513Ceramic: 3 pF ±0.25 pF 50 VDCW tempcoef 0±250 PPM.C514Ceramic: 0.75 pF ±0.25 pF 50 VDCWtemp coef 0±250 PPM.C515 and C516Ceramic: 1000 pF ±10% 50 VDCW temp coef ±15%.C521Ceramic: 1000 pF ±10% 50 VDCW tempcoef ±15%.C522 and C523Ceramic: 0.1F ±10% 25 VDCW temp coef ±15%.C524Ceramic: 1000 pF ±10% 50 VDCW tempcoef ±15%.C525Ceramic: 15 pF ±5% 50 VDCW temp coef0±60 PPM.C526Ceramic: 1000 pF ±10% 50 VDCW tempcoef ±15%.C527Ceramic: 33 pF ±5% 50 VDCW temp coef0±60 PPM.C528Ceramic: 15 pF ±5% 50 VDCW temp coef0±60 PPM.C529Ceramic: 1000 pF ±10% 50 VDCW tempcoef ±15%.C530Ceramic: 0.01F ±10% 50 VDCW temp coef±15%.C531Ceramic: 1 pF ±0.25 pF 50 VDCW tempcoef 0±250 PPM.C553Ceramic: 0.01F ±10% 50 VDCW temp coef±15%.C554 thru C556Ceramic: 0.1F ±10% 25 VDCW temp coef ±15%.C557Ceramic: 15 pF ±5% 50 VDCW temp coef0±60 PPM.C558 and C559Ceramic: 0.1F ±10% 25 VDCW temp coef±15%.SYMBOL PART NUMBER DESCRIPTIONC560Ceramic: 1000 pF ±10% 50 VDCW tempcoef ±15%.C561thruC565Ceramic: 0.1F ±10% 25 VDCW temp coef±15%.C567Electrolytic: 10F ±20% 16 VDCW.C571andC572Ceramic: 0.1F ±10% 25 VDCW temp coef±15%.C573Electrolytic: 10F ±20% 16 VDCW.------------------FIL TERS------------------FL501andFL502Crystal Filter: 82.2 MHz.FL503Ceramic: Filter: 455 kHz.FL504Ceramic: Filter: 455 kHz.-------INTEGRA TED CIRCUITS--------IC501Linear, IF Amplifier Detector; sim toTOSHIBA T A31132F.IC502Linear, Dual OP AMP; sim to NJRCNJM3404IC503Linear, Positive Voltage Regulator; sim toNJRC NJM78L09UA.-----------------CONNECTORS------------------P501Connector: 30 Pins.-------------------COILS---------------------L501Coil: RF 1 H ±20%.L502Coil: RF.L503Coil: RF.L504andL505Coil: RF.L506Coil: RF.L507Coil: RF.L521Coil: RF.L522Coil: RF 0.22 H ±10%.L523Coil: RF.-----------------RESISTORS ----------------R501Metal film: 82 ohms ±5% 100 VDCW.1/10W.R502Metal film: 18 ohms ±5% 100 VDCW.1/10W.R503Metal film: 3.3K ohms ±5% 100 VDCW.1/16W.R505Metal film: 150K ohms ±5% 100 VDCW,1/16W.R506Metal film: 330 ohms ±5% 100 VDCW,1/16W.R507Metal film: 6.8K ohms ±5% 100 VDCW,1/16W.R508Metal film: 5.6K ohms ±5% 100 VDCW,1/16W.R509Metal film: 220 ohms 5% 100 VDCW,1/16W.*COMPONENTS ADDED, DELETED OR CHANGED BY PRODUCTION CHANGES SYMBOL PART NUMBER DESCRIPTIONR510Metal film: 5.8K ohms ±5% 100 VDCW,1/16W.R511Metal film: 330 ohms ±5% 100 VDCW,1/16W.R521Metal film: 15K ohms ±5% 100 VDCW,1/16W.R522Metal film: 4.7K ohms ±5% 100 VDCW,1/16W.R523Metal film: 1.8K ohms ±5% 100 VDCW,1/16W.R524Metal film: 100 ohms ±5% 100 VDCW,1/16W.R525Metal film: 33 ohms ±5% 100 VDCW,1/16W.R526Metal film: 1K ohms ±5% 100 VDCW,1/16W.R527Metal film: 4.7K ohms ±5% 100 VDCW,1/16W.R528Metal film: 10K ohms ±5% 100 VDCW,1/16W.R529Metal film: 1K ohms ±5% 100 VDCW,1/16W.R530Metal film: 10K ohms ±5% 100 VDCW,1/16W.R531Metal film: 100 ohms ±5% 100 VDCW,1/16W.R552Metal film: 1.8K ohms ±5% 100 VDCW,1/16W.R556andR557Metal film: 1.5K ohms ±5% 100 VDCW,1/16W.R559Metal film: 820 ohms ±5% 100 VDCW,1/16W.R560Metal film: 18K ohms ±5% 100 VDCW,1/16W.R562Metal film: 10K ohms ±5% 100 VDCW,1/16W.R563Metal film: 12K ohms ±5% 100 VDCW,1/16W.R564Metal film: 1.2K ohms ±5% 100 VDCW,1/16W.R565Metal film: 10K ohms ±5% 100 VDCW,1/16W.R566Metal film: 0 ohms, 1/16W.RV501Variable: 10K ohms.-----------TRANSISTORS----------TR501andTR502aN-Channel, field effect 2SK1577.TR503Silicon, NPN; sim to NEC 2SC2223.TR504andTR505Silicon, NPN; sim to HIT ACHI 2SC2620.----------------CRYST ALS-------------X501Quartz crystal: 82.655 MHz.XS501AandXS501BCrystal Socket.LBI-390579OUTLINE DIAGRAMSystem Control Logic/IF/Audio BoardSOLDER SIDE COMPONENT SIDELBI-39057LBI-39057SCHEMATIC DIAGRAMLOGIC (CMC-682)SYSTEM CONTROL(CC00-CMC-682 2/2)LOGIC (CMC-682) SYSTEM CONTROL(DD00-CMC-682 1/2)IF(CMF-138)(DD00-CMF-138)。

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屏幕显示控制的专用标准产品CMOS屏幕显示控制芯片——MB900921.描述MB90092是用于显示控制视频中的文字和图像的视频显示控制芯片，内部集成了显示内存(VRAM)、外挂字库接口和视频信号发生器，其外部只需连接少量的电子元件就可以显示汉字和图形。

MB90092提供两种屏幕叠加方法，分别称为“主屏”和“副屏”，二者可单独或相互重叠出现在监视器上。

主屏由12行24个字符组成，允许设置每个字符的数据。

副屏由12行24个字符组成或最多达到16行24个字符。

数据不仅可以在前期配置的每行中被设置，也可以集中地在后期配置的整个屏幕中被设置。

MB90092所支持的字符为24×32点阵的普通字符和8×32点阵的图形字符，这些字符单元可以任意八种不同的颜色显示。

如果主屏中只有图形字符，则有192×384个像素点，在同样的情况下，副屏有192×384个像素点或256×512个像素点。

（实际显示屏由水平方向的像素点的时钟频率和电视系统垂直方向的一定光栅数决定。

）MB90092把RAM作为字库内存，能够显示自由图形。

MB90092总共能够使用16384种类型的字符，包括普通字符和图形字符。

它能够控制外部16M bits的字库内存。

对于视频信号的输出，MB90092具有合成视频信号，Y/C分离视频信号，RGB数字信号输出引脚。

MB90092还具有视频信号输入引脚，允许重叠显示任意一种复合视频信号和Y/C分离视频信号。

2.封装80个引脚的PQFP封装3.特性3.1主屏显示•屏幕显示能力：24字符×12行（达到288字符）•字符点配置：24×32点（每个字符）•字符类型：16384种字符（当使用16M比特的外部时钟）•字符大小：标准，双宽度，双高度，双宽度×双高度，四倍宽度×双高度（每行可设置）•显示位置控制：水平显示位置：1/3字符单元设置垂直显示位置：光栅单元设置行空间控制：光栅单元设置（0~15光栅）•显示优先级控制：副屏显示控制优先级的能力3.2副屏显示屏幕显示位置：可设置的水平和垂直为2个点单元•普通屏幕模式：屏幕显示能力：32字符×12行（达到384字符）56×384点（仅限图形字符）（实际显示屏幕由电视系统和点时钟频率决定）。

普通字符/图形字符显示每行可供选择。

（每行的头显示字符对于是特定的。

）•全屏模式：屏幕显示能力：32字符×16行（达到512字符）256×512点（仅限图形字符）（实际显示屏幕由电视系统和点时钟频率决定）。

•虚拟屏幕显示能力：模式A：32字符×16行，256×512点模式B：512字符×32行，4096×1024点3.3屏幕背景显示屏幕背景颜色：8种颜色•模拟输入复合视频信号输入Y/C分离视频信号输入•模拟输出复合视频信号输出Y/C分离视频信号输出3.4数字输出G(绿色)，R(红色)和B(蓝色)输出VOC(字符)输出，VOB(字符+背景)输出字符，字符背景，行背景和屏幕背景都可以8种颜色显示3.5内部同步控制(视频信号产生器)内部信号产生支持NTSC和PAL制系统隔行/逐行扫描显示选择3.6外部同步控制分离同步信号输入/复合同步信号输入选择3.7外部接口8-bit 串行输入（3个信号输入引脚）芯片选择:/CS串行时钟：SCLK串行数据：SIN3.8封装QFP-803.9其他内部开机复位电路4.引脚分布5.组成框图6.绝对最大额定值7.电气特性7.1直流特性7.1.1 VOUT 信号输出7.1.2 YOUT 信号输出7.1.3 COUT信号输出7.2交流特性7.2.1串行输入时序7.2.2垂直和水平同步信号输入时序7.2.3复位信号输入时序7.2.4地址数据保持时序7.2.5 TSC输入时，地址和READ信号延时时序图7.3时钟定时规范7.4开机复位规范7.5电源ON/OFF时序7.6上电复位取消时序8.典型电路这是一个标准的电路实例，用来对输入视频信号或从外面输入到内部所生成的视频信号叠加字符。

其构成随着系统和部件不同而不同。

9.显示控制命令7654321076543210010000VSL RA 8RA 70RA 6RA 5RA 4CA3CA 2CA 1CA 0VRAM 地址控制1—110001M A M B A T 0CG CR CB M C BG(GR)BG(BS)BB(M D)主屏字符控制12—110010M 9M 8M 70M 6M 5M 4M 3M 2M 1M 0主屏字符控制21—210001SM A SM B 00SCG SCR SCB SM C SGR SDC SM D 副屏行控制12—210010SM 9SM 8SM 70SM 6SM 5SM 4SM 3SM 2SM 1SM 0副屏行控制21—310001OF1OF000000PC PG PR PB 主屏行控制12—310010G2G1G00SOC VD DG KC KG KR KB 主屏行控制2310011FIL 0000000000VRAM 写控制410100IE IN EB 0EO CM ZM NP P2P0DC 屏幕控制1510101KID A PC GYZ 0BH2BH1BH0W 3W 2W 1W 0屏幕控制2610110G2G1G00SOC VD DG N3N2N1N0主屏行控制3710111EC LP FO 00Y5Y4Y3Y2Y1Y0主屏垂直位置控制811000SC 0FC 00X5X4X3X2X1X0主屏水平位置控制91100100GRM 00000000汉字字体显示控制101101000RB 0BK CC BC UC UG UR UB 颜色控制1111011SG2SG1SG000SCC SBC SGC SBG SBR SBB 副屏控制1211100SGA 0SY70SY6SY5SY4SY3SY2SY1SY0副屏垂直位置控制13111010SX8SX70SX6SX5SX4SX3SX2SX1SX0副屏水平位置控制1411110———0———————（保留)1511111——————————（保留)第一个字节第二个字节命令代码/数据数据命令号功能9.1命令0(VRAM 地址设置)[命令格式]第一字节第二字节[描述]VSL :VRAM写控制RA8 ~ RA5：VRAM 行地址设置(00 ~ BH)CA4 ~ CA0：VRAM 列地址设置(00 ~ 17H )9.1.1在正常模式下 (命令9: GRM = 0)MC ~ M0：设置一个字符代码0000H~1FFFH之间可以设置指定的字符代码。

多达8192个不同的字符都可以使用。

AT：指定字符显示属性。

AT = 0：指定正常显示。

AT = 1：指定属性显示。

固体填充背景（当命令10：RB = 1）闪烁（当命令10：BK = 1）阴影背景（当命令1：BS = 1）注：如果阴影背景显示和固体填充背景显示或闪烁显示都被指定,那么阴影背景显示设置的优先级高于其他设置。

CG，CG，CR：字符颜色BG，BR，BB：字符背景颜色9.1.2在扩展图形模式（命令9：GRM= 1）MD~M0：设置字符代码。

0000H~3FFFH之间可以设置指定的字符代码。

多达16384个不同的字符都可以使用。

AT：指定字符属性显示。

AT = 0：指定正常显示。

AT =1：属性变换显示开。

GR：指定普通字符/图形字符显示。

GR =0：指定字符显示正常。

字符由24水平点×32垂直点GR =1：指定图形字符显示字符由8个水平点×32垂直点构成（每个点可设置颜色）注意：不允许BS =1。

BS：指定阴影背景显示。

BS = 0：指定是正常显示。

BS =1：指定阴影背景显示。

AT = 0时设置的字符显示为阴影背景。

AT = 1时设置的字符显示为反向视频中的阴影背景9.2命令1和2(VRAM数据设置1和2)[命令格式]9.2.1命令1-1(主屏字符控制参数设置1)第一字节第二字节9.2.2命令2-1(主屏字符控制参数设置2)第一字节第二字节[描述](MD), MC ~M0 : 字符代码AT : 指定字符显示属性。

CG, CR, CB : 字符颜色。

BG, BR, BB : 字符背景颜色。

(GR) : 指定正常字符/图形字符显示。

(BS) : 指定阴影背景显示。

（1）在正常字符显示模式（GR= 0）CG，CR，CB：字符颜色（2）在图形字符的显示模式（GR= 1）CG：图形颜色透明度控制CG =0：正常显示CG =1：透明显示此设置将以透明显示替换“黑色”的图形颜色显示。

CR，CB：图形颜色相位控制这些位控制着视频信号输出的颜色相位（VOUT引脚和COUT引脚输出）。

9.2.3写副屏行控制参数（当命令0：VSL= 1，CA0= 0）设置副屏行控制参数。

[命令格式]命令1-2(副屏行控制参数设置1)第一字节第二字节命令2-2(副屏行控制参数设置2)第一字节第二字节[描述]SMD ~SM0：副屏行的第一个字符代码SDC：副屏行输出控制SDC=0：关闭副屏行显示输出。

SDC= 1：允许副屏行显示输出。

SGR：副屏行字符显示控制SGR =0：显示正常字符。

SGR =1：显示图形字符。

（1）在副屏行的正常字符显示模式（SGR= 0）SCG ~SCB：副屏行字符颜色（2）在副屏行的图形字符显示模式（SGR= 1）SCG：副屏行图形颜色的透明度控制SCG= 0：正常显示SCG=1：透明显示此设置将以透明显示替换“黑色”的图形颜色显示。

SCR，SCB：副屏行图形的颜色相位控制这些位控制着视频信号输出的颜色相位（VOUT引脚和COUT引脚输出）。

9.2.4写主屏控制参数（当命令0：VSL= 1，CA0= 1）[命令格式]命令1-3(主屏行控制参数设置1)第一字节第二字节命令2-3(主屏行控制参数设置2)第一字节第二字节[描述]OF1，OF0：字符颜色相位控制PC：阴影图案背景彩色/单色控制（只适用于扩展图形模式）PC = 0：显示彩色视频信号输出的阴影图案背景。

PC= 1：显示单色视频信号输出的阴影图案背景。

PG，PB，PR：阴影图案背景颜色（仅在扩展图形模式）G2 ~ G0：字符大小SOC：输出优先级控制SOC = 0：将显示优先级设为主屏。

该设定主屏显示在副屏的顶部。

SOC =1：将显示优先级设为副屏。